CN117637764A

CN117637764A - Semiconductor device, display device including the same, and method of manufacturing the semiconductor device

Info

Publication number: CN117637764A
Application number: CN202311103919.9A
Authority: CN
Inventors: 崔基埈
Original assignee: LX Semicon Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2022-08-31
Filing date: 2023-08-30
Publication date: 2024-03-01

Abstract

Disclosed herein are a semiconductor device, a display device including the same, and a method of manufacturing the semiconductor device. The semiconductor device includes: a 1 st medium voltage element disposed in the substrate and configured to receive a first level medium voltage; a 2 nd medium voltage element disposed in the substrate and configured to receive a second level medium voltage greater than the first level medium voltage; and a deep well provided in the substrate so as to surround the 1 st medium voltage element and the 2 nd medium voltage element, wherein the 2 nd medium voltage element includes: a 2-1 nd intermediate voltage well, the 2-1 nd intermediate voltage well being doped with a first type dopant; and a 2-2 nd intermediate pressure well, the 2-2 nd intermediate pressure well being doped with a second type of dopant different from the first type of dopant.

Description

Semiconductor device, display device including the same, and method of manufacturing the semiconductor device

Technical Field

The present disclosure relates to a semiconductor device including a 1 st medium voltage element and a 2 nd medium voltage element, a display driving device including the semiconductor device, and a method for manufacturing the semiconductor device.

Background

With the rapid development of the semiconductor industry, several generations of semiconductor devices have been produced such that each generation has smaller and more complex circuits than its previous generation. During the evolution of Integrated Circuits (ICs), functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. Such scaling down processes generally provide benefits by improving production efficiency and reducing associated costs. However, these benefits also increase the complexity of the semiconductor device and its manufacturing process.

Disclosure of Invention

It is an object of the present disclosure to provide a semiconductor device including a 1 st medium voltage element and a 2 nd medium voltage element, wherein the 2 nd medium voltage element includes two well regions respectively doped with different types of dopants to achieve electrical characteristics, thereby reducing an area size of a circuit including the 2 nd medium voltage element, and to provide a display driving device including the semiconductor device and a method for manufacturing the semiconductor device.

A semiconductor device according to an embodiment of the present disclosure includes: a 1 st medium voltage element disposed in the substrate and configured to receive a first level medium voltage; a 2 nd medium voltage element disposed in the substrate and configured to receive a second level medium voltage greater than the first level medium voltage; and a deep well provided in the substrate so as to surround the 1 st medium voltage element and the 2 nd medium voltage element, wherein the 2 nd medium voltage element includes: a 2-1 nd intermediate voltage well, the 2-1 nd intermediate voltage well being doped with a first type dopant; and a 2-2 nd intermediate pressure well, the 2-2 nd intermediate pressure well being doped with a second type of dopant different from the first type of dopant.

In the semiconductor device, the display driving device including the semiconductor device, and the method for manufacturing the semiconductor device according to the present disclosure, the semiconductor device may include a 2 nd medium voltage element realizing electrical characteristics. Therefore, the area size of the circuit including the 2 nd medium voltage element is reduced. In addition, the 2 nd medium voltage element may be formed using the manufacturing process of the 1 st medium voltage element. Therefore, the manufacturing cost of the semiconductor device including the 1 st medium voltage element and the 2 nd medium voltage element can be reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to describe the principles of the disclosure. In the drawings:

fig. 1 is a diagram illustrating a display device to which a display driving device according to an embodiment of the present disclosure is applied.

Fig. 2 is a block diagram of a display driving apparatus according to an embodiment of the present disclosure.

Fig. 3 is a cross-sectional view of a 1 st middling element according to an embodiment of the disclosure.

Fig. 4 is a cross-sectional view of a 2 nd medium voltage component according to one embodiment of the present disclosure.

Fig. 5 is a flowchart of a method for manufacturing a 1 st medium voltage element and a 2 nd medium voltage element according to one embodiment of the present disclosure.

Fig. 6A to 6E are diagrams of intermediate structures corresponding to intermediate steps of a method for manufacturing a 1 st medium voltage element and a 2 nd medium voltage element according to one embodiment of the present disclosure.

Detailed Description

The advantages and features of the present disclosure and methods of accomplishing the same will become apparent by reference to the embodiments described in detail below with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but may be implemented in various forms. Accordingly, these embodiments are set forth merely to complete the disclosure and to fully inform the scope of the disclosure to those ordinarily skilled in the art to which the disclosure pertains, and the disclosure is limited only by the scope of the claims.

For simplicity and clarity of illustration, elements in the figures have not necessarily been drawn to scale. The same reference numbers in different drawings identify the same or similar elements and thus perform similar functions. In addition, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it is understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure. Examples of the various embodiments are further illustrated and described below. It will be understood that the description herein is not intended to limit the claims to the particular embodiments described. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing embodiments of the present disclosure are exemplary, and the present disclosure is not limited thereto. Like reference numerals refer to like elements throughout.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including" and "having," when used in this specification, specify the presence of stated features, integers, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. For example, the expression "at least one of" when preceding a list of elements may modify the entire list of elements and may not modify the elements in the list. In the interpretation of numerical values, errors or tolerances may occur even when they are not explicitly described.

In addition, it will also be understood that when a first element or layer is referred to as being "on" a second element or layer, it can be directly on the second element or be indirectly on the second element with a third element or layer disposed between the first and second elements or layers. It will be understood that when an element or layer is referred to as being "connected" or "coupled" to another element or layer, it can be directly on, connected or coupled to the other element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

Further, as used herein, when a layer, film, region, plate, etc. is disposed "on" or "on top of" another layer, film, region, plate, etc., the former may directly contact the latter, or yet another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc., is disposed directly on "or" top "another layer, film, region, plate, etc., the former directly contacts the latter, and no further layer, film, region, plate, etc., is disposed between the former and the latter. Further, as used herein, when a layer, film, region, plate, etc. is disposed "under" or "under" another layer, film, region, plate, etc., the former may directly contact the latter, or yet another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc., is disposed "under" or "under" another layer, film, region, plate, etc., the former is in direct contact with the latter, and no further layer, film, region, plate, etc., is disposed between the former and the latter.

In the description of a temporal relationship, for example, a temporal precedent relationship (such as "after", "subsequent", "preceding", etc.) between two events, another event may occur between them unless indicated "directly after … …", "directly after … …", or "directly before … …".

When a particular embodiment may be implemented differently, the functions or operations specified in the particular block may occur in a different order than that specified in the flowchart. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending upon the functionality or acts involved.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, a first element, first component, first region, first layer, or first section discussed below could be termed a second element, second component, second region, second layer, or second section without departing from the spirit and scope of the present disclosure.

Features of various embodiments of the present disclosure may be combined with one another, in part or in whole, and may be technically associated with one another or operated with one another. Embodiments may be implemented independently of each other and together in association.

In interpreting the values, unless there is a separate explicit description of the values, the values are to be construed as including error ranges.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, "implementations," "examples," "aspects," and the like are not to be construed as making any aspect or design described more advantageous or advantageous over other aspects or designs.

Furthermore, the term "or" means "inclusive or" rather than "exclusive or". That is, unless otherwise indicated or clear from the context, the expression "x uses a or b" means any of the naturally inclusive permutations.

The terminology used in the following description is selected as being general and common in the relevant art. However, other terms besides these terms may exist depending on the development and/or variation of the technology, practices, preferences of the skilled artisan, and the like. Therefore, the terms used in the following description should not be construed as limiting the technical idea, but should be construed as examples of terms used to describe the embodiments.

Furthermore, in particular cases, the applicant may arbitrarily select terms, and in such cases, the detailed meanings thereof will be described in the corresponding description section. Accordingly, the terms used in the following description should be understood not only based on the names of the terms but also based on the meanings of the terms and the contents of the entire detailed description.

Hereinafter, a display device including a display driving device according to an embodiment of the present disclosure will be described in detail with reference to fig. 1.

The display device 50 according to the present disclosure includes a display panel 60, a power supply 65, and an external system 80. Further, the display device 50 according to the present disclosure includes the display driving device 10.

The display panel 60 may be implemented as an organic light emitting panel in which an organic light emitting element is formed, or may be implemented as a liquid crystal panel in which liquid crystal is formed. That is, the display panel 60 applied to the present disclosure may be applied to all types of currently used panels. Accordingly, the display device according to the present disclosure may be implemented as an organic light emitting display device, a liquid crystal display device, or other various types of display devices. However, in the following description, for convenience of description, an example in which the display device according to the present disclosure is implemented as a liquid crystal display device will be described.

When the display panel 60 is a liquid crystal panel, on a lower glass substrate of the display panel 60, a plurality of data lines DL1 to DLd, a plurality of gate lines GL1 to GLg crossing the data lines DL1 to DLd, a plurality of thin film transistors TFT formed at intersections of the plurality of data lines DL1 to DLd and the plurality of gate lines GL1 to GLg, respectively, a plurality of pixel electrodes for charging a data voltage to a pixel, and a common electrode for driving a liquid crystal filled in a liquid crystal layer together with the pixel electrodes may be formed. Due to the structure in which the plurality of data lines DL1 to DLd and the plurality of gate lines GL1 to GLg cross each other, the pixels are arranged in a matrix form.

The black matrix BM and the color filters are formed on the upper glass substrate of the display panel 60. The liquid crystal may be filled between the lower glass substrate and the upper glass substrate.

The liquid crystal mode applied to the display panel 60 of the present disclosure may include not only a TN mode, a VA mode, an IPS mode, and an FFS mode, but also any kind of liquid crystal mode. Further, the display device 50 according to the present disclosure may be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, or a reflective liquid crystal display device.

The display panel 60 displays an image in response to the gate signal and the source signal output from the display driving apparatus 10.

The power supply 65 is mounted on the main board 90 and supplies voltages for driving the display panel 60, the display driving apparatus 10, and the external system 80 thereto. In this regard, various circuit elements may be mounted on the motherboard 90 in addition to the power supply 65.

The power supply 65 generates a voltage based on a driving voltage of each circuit included in the display driving apparatus 10 and supplies the voltage to each circuit. In this regard, the driving voltage of each circuit of the display driving apparatus 10 may include a first level voltage, a first level medium voltage, a second level medium voltage, and a first level high voltage. The first level voltage means a low voltage. Each of the first level medium voltage and the second level medium voltage may be a medium voltage greater than a low voltage. The second level medium voltage may be a medium voltage greater than the first level medium voltage. The first level high voltage means a high voltage greater than the second level medium voltage. For example, the low pressure may be in the range of 0.9V to 2.2V, the medium pressure may be in the range of 6V to 11V, and the high pressure may be 12V or higher. Accordingly, the first level voltage may be in a range of 0.9V to 2.2V, each of the first level medium voltage and the second level medium voltage may be in a range of 6V to 11V, and the first level high voltage may be 12V or higher.

Further, the power supply 65 supplies power for driving the display panel 60 to the display panel 60 so that the display panel 60 can operate.

The display driving apparatus 10 may be configured to include a timing control circuit 110 provided in the display panel 60 for controlling the gate driver circuit 120 and the data driver circuit 130 provided in the display panel 60, the gate driver circuit 120 for controlling signals input to the gate lines GL1 to GLg, and the data driver circuit 130 for controlling signals input to the data lines DL1 to DLd.

In this regard, in fig. 1, the display driving apparatus 10 is illustrated as being mounted on a display panel 60. However, this is only an example, and the display driving apparatus 10 may be separated from the display panel 60 and may be mounted on a separate board.

Further, the timing control circuit 110, the gate driver circuit 120, and the data driver circuit 130 constituting the display driving device 10 may constitute a single semiconductor device, or may be respectively composed of separate semiconductor devices.

Hereinafter, a display driving apparatus according to an embodiment of the present disclosure will be described in detail with reference to fig. 2. Fig. 2 is a diagram showing each circuit constituting a display driving device according to one embodiment of the present disclosure.

As shown in fig. 2, the timing control circuit 110 supplies a gate control signal GCS to the gate driver circuit 120 to control the gate driver circuit 120. Specifically, the timing control circuit 110 receives the first image data and the timing signal from the external system 80, generates a gate control signal GCS for controlling the gate driver circuit 120 based on the timing signal, and generates a data control signal DCS for controlling the data driver circuit 130.

In one embodiment, the timing control circuit 110 may generate the gate control signal GCS including the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, and the like.

In one embodiment, the timing control circuit 110 may generate the data control signal DCS including the source start pulse SSP, the source sampling clock SSC, the source output enable signal SOE, and the like.

The timing control circuit 110 transmits a gate control signal GCS to the gate driver circuit 120 and a data control signal DCS to the data driver circuit 130.

The timing control circuit 110 aligns the first image data received from the external system 80. Specifically, the timing control circuit 110 aligns the first image DATA so as to match the structure and characteristics of the display panel 60 to generate the second image DATA.

The timing control circuit 110 transmits the second image DATA to the DATA driver circuit 130.

The gate driver circuit 120 outputs a gate signal synchronized with the source signal generated from the data driver circuit 130 to the gate lines GL1 to GLg according to the timing signal generated from the timing control circuit 110. Specifically, the gate driver circuit 120 outputs a gate signal synchronized with the source signal to the gate lines GL1 to GLg according to the gate start pulse, the gate shift clock, and the gate output enable signal generated from the timing control circuit 110.

The gate driver circuit 120 includes a gate shift register circuit, a gate level shifter circuit, and the like. In this regard, the gate shift register circuit may be directly formed on the TFT array substrate of the display panel 60 in a GIP (gate in panel) process. In this case, the gate driver circuit 120 supplies a gate start pulse and a gate shift clock signal to a gate shift register circuit formed on the TFT array substrate in a GIP manner.

The DATA driver circuit 130 converts the second image DATA into a source signal according to the timing signal generated from the timing control circuit 110. Specifically, the data driver circuit 130 converts the second image data into a source signal according to the source start pulse, the source sampling clock, and the source output enable signal. The data driver circuit 130 outputs a source signal corresponding to one horizontal line to the data lines DL1 to DLd at each horizontal period in which a gate signal is supplied to the gate lines GL1 to GLg.

In this regard, the DATA driver circuit 130 receives a gamma voltage from a gamma voltage generator (not shown), and may convert the second image DATA into a source signal using the gamma voltage. For this purpose, as shown in fig. 2, the data driver circuit 130 includes a shift register circuit 210, a latch circuit 220, a level shifter circuit 230, a digital-to-analog converter circuit 240, and an output buffer circuit 250.

The shift register circuit 210 receives a source start pulse and a source sampling clock from the timing control circuit 110, sequentially shifts the source start pulse according to the source sampling clock to output a sampling signal. The shift register circuit 210 transfers a sampling signal to the latch circuit 220.

The latch circuit 220 sequentially samples and latches the second image data in a predetermined unit according to the sampling signal. The latch circuit 220 transfers the latched second image data to the level shifter circuit 230.

The level shifter circuit 230 amplifies the level of the latched second image data. Specifically, the level shifter circuit 230 amplifies the level of the second image data to a level that can be handled by the digital-to-analog converter circuit 240. The level shifter circuit 230 transfers the level-amplified second image data to the digital-to-analog converter circuit 240.

The digital-to-analog converter circuit 240 converts the second image data into an analog source signal. The digital-to-analog converter circuit 240 transmits the source signal as an analog signal to the output buffer circuit 250.

The output buffer circuit 250 outputs source signals to the data lines DL1 to DLd. Specifically, the output buffer circuit 250 buffers the source signal according to the source output enable signal generated from the timing control circuit 110 and outputs the buffered source signal to the data lines DL1 to DLd.

In this regard, each of the shift register circuit 210 and the latch circuit 220 may receive a first level low voltage, for example, as a low voltage. Each of the level shifter circuit 230 and the digital-to-analog converter circuit 240 may receive the first level medium voltage or the second level medium voltage as the medium voltage. That is, each of the shift register circuit 210 and the latch circuit 220 may include a low voltage element LV for receiving a first level low voltage as a low voltage. At least one of the level shifter circuit 230 and the digital-to-analog converter circuit 240 may include a 1 st medium voltage element MV1 or a 2 nd medium voltage element MV2 for receiving the first level medium voltage or the second level medium voltage as the medium voltage. Further, at least one of the level shifter circuit 230, the digital-to-analog converter circuit 240, and the output buffer circuit 250 may include a high voltage element HV for receiving a first level high voltage as a high voltage.

According to one embodiment of the present disclosure, the 2 nd medium voltage element MV2 included in at least one of the level shifter circuit 230 and the digital-to-analog converter circuit 240 may include: the 2-1 medium voltage wells MV2_well1 and the 2-2 medium voltage wells MV2_well2, which are doped with different types of dopants and have different widths, respectively; a 2-1 nd midvoltage drift region MV2_LDD1 disposed between the 2-1 nd midvoltage well MV2_well1 and the 2 nd midvoltage source region MV2_S; and a 2-2 nd medium voltage drift region MV2_LDD2 disposed between the 2-2 nd medium voltage well MV2_well2 and the 2 nd medium voltage drain region MV2_D. Thus, the 2 nd medium voltage element MV2 may operate in response to receiving a second level medium voltage that is greater than the first level medium voltage. Accordingly, a separate element that operates in response to receiving the second level medium voltage higher than the first level medium voltage may be omitted, and thus, the area size of the circuit including the 2 nd medium voltage element MV2 may be reduced.

Hereinafter, a semiconductor device according to one embodiment of the present disclosure will be described in detail with reference to fig. 3 and 4.

Fig. 3 is a cross-sectional view of a 1 st middling element according to an embodiment of the disclosure. Fig. 4 is a cross-sectional view of a 2 nd medium voltage component according to one embodiment of the present disclosure.

As described above, the semiconductor device according to one embodiment of the present disclosure may include the 1 st medium voltage element MV1 for receiving the medium voltage of the first level and the 2 nd medium voltage element MV2 for receiving the medium voltage of the second level higher than the first level.

Referring to fig. 3 and 4, the 1 st and 2 nd medium voltage elements MV1 and MV2 may be positioned on the substrate 100.

The substrate 100 may include an elemental semiconductor such as silicon, germanium, and/or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; or an alloy semiconductor such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP and/or other suitable materials. The substrate 100 may be composed of a single material layer having a uniform composition. Alternatively, the substrate 100 may include multiple material layers of similar or different composition suitable for use in IC device fabrication. For example, the substrate 100 may include a silicon-on-insulator (SOI) having a silicon oxide layer and a silicon layer formed on the silicon oxide layer. Alternatively, the substrate 100 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof.

The substrate 100 may be doped with an n-type dopant or a p-type dopant, and thus may contain an n-type dopant or a p-type dopant.

In addition, the substrate 100 includes various doped regions disposed within the substrate 100 or on the substrate 100. Each of the doped regions may be doped with an n-type dopant such as phosphorus or arsenic and/or with a dopant such as boron or BF, depending on design requirements ₂ And the like. Furthermore, each of the doped regions may have an N-well structure such as a deep N-well (DNW), a P-well structure such as a deep P-well (DPW), or a double-well structure. Each of the doped regions may be formed via implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

According to one embodiment of the present disclosure, the 1 st medium voltage element MV1 may operate in response to receiving a first level medium voltage that is greater than the first level low voltage. The 2 nd medium voltage element MV2 may operate in response to receiving a second level medium voltage that is greater than the first level medium voltage.

The substrate 100 includes isolation structures STI within the substrate 100 to electrically isolate the elements from each other. To this end, isolation structures STI may be disposed between the elements so as to define a region in which each element is disposed. The isolation structures STI may be implemented as shallow trench isolation (STI: shallow trench isolation) structures.

The isolation structures STI may comprise a different dielectric material than the substrate 100. For example, the isolation structures STI may be made of dielectric materials including silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, other suitable dielectric materials, or any combination thereof.

In the 1 st medium voltage device MV1, as shown in fig. 3, the substrate 100 includes 1 st medium voltage wells mv1_well, 1 st-1 st medium voltage drift regions mv1_ldd1, 1 st-2 nd medium voltage drift regions mv1_ldd2, 1 st medium voltage source regions mv1_s, and 1 st medium voltage drain regions mv1_d doped with n-type dopants or p-type dopants, respectively, according to one embodiment of the present disclosure.

As shown in fig. 3, the 1 st pressure well mv1_well may be a region doped with the same type of dopant as the dopant doped into the deep well region in the deep well region. Specifically, the voltage well mv1_well in 1 may be a region in the deep N-well DNW doped with an N-type dopant as a first type dopant at a concentration different from that of the deep N-well doped with the N-type dopant as the first type dopant. However, the present disclosure is not limited thereto. The voltage well mv1_well in 1 may be a region in the deep P-well region doped with the same type of dopant as the dopant doped into the deep P-well region. Specifically, the 1 st medium voltage well mv1_well may be a region in the deep P-well DPW doped with a P-type dopant as the second type dopant at a concentration different from that of the deep P-well doped with the P-type dopant as the second type dopant.

Furthermore, according to one embodiment of the present disclosure, the 1 st medium pressure well mv1_well and the 2-1 nd medium pressure well mv2_well1 may be formed using one mask, and thus may be doped with the same dopant at substantially the same concentration. That is, the 1 st medium voltage well mv1_well and the 2-1 nd medium voltage well mv2_well1 may be doped with the first type dopant at the first well concentration. Accordingly, a separate mask for forming each of the 1 st and 2-1 nd pressure wells mv1_well and mv2_well1 is not required, thereby reducing the manufacturing cost of the semiconductor device.

Each of the 1 st-1 medium voltage drift region mv1_ldd1 and the 1 st-2 medium voltage drift region mv1_ldd2 may be present in the 1 st medium voltage well mv1_well doped with a first type dopant, but may be doped with a second type dopant different from the first type dopant. For example, when the 1 st medium voltage well mv1_well is a region doped with an n-type dopant as a first type dopant, each of the 1 st-1 medium voltage drift region mv1_ldd1 and the 1 st-2 medium voltage drift region mv1_ldd2 may be doped with a p-type dopant as a second type dopant. However, the present disclosure is not limited thereto. When the 1 st medium voltage well mv1_well is a region doped with a p-type dopant as the second type dopant, each of the 1 st-1 medium voltage drift region mv1_ldd1 and the 1 st-2 medium voltage drift region mv1_ldd2 may be a region doped with an n-type dopant.

The 1 st medium voltage source region mv1_s may be a region doped with the same type of dopant as the type of dopant doped into the 1 st medium voltage drift region mv1_ldd1. The 1 st medium voltage drain region mv1_d may be a region doped with the same type of dopant as the type of dopant doped into the 1 st-2 medium voltage drift region mv1_ldd2. The 1 st medium voltage source region mv1_s may be a region doped with a second type dopant and may be present in the 1 st-1 st medium voltage drift region mv1_ldd1 doped with the second type dopant. The 1 st medium voltage drain region mv1_d may be a region doped with a second type dopant and may be present in the 1 st-2 nd medium voltage drift region mv1_ldd2 doped with the second type dopant. For example, when each of the 1 st medium voltage drift region mv1_ldd1 and the 1 st medium voltage drift region mv1_ldd2 is doped with a p-type conductor, each of the 1 st medium voltage source region mv1_s and the 1 st medium voltage drain region mv1_d may be a region doped with a p-type dopant.

A 1 st medium voltage gate dielectric layer mv1_gox may be stacked on the substrate 100 so as to partially overlap each of the 1 st medium voltage drift region mv1_ldd1 and the 1 st medium voltage drift region mv1_ldd2.

The 1 st medium voltage gate dielectric layer mv1_gox may be made of an oxide such as silicon oxide, a nitride such as silicon nitride, or a high dielectric constant (high k) dielectric material, or may include an oxide such as silicon oxide, a nitride such as silicon nitride, or a high dielectric constant (high k) dielectric material. When the 1 st medium voltage gate dielectric layer mv1_gox is laminated in a high-k gate process (high-k metal gate: HKMG), the 1 st medium voltage gate dielectric layer mv1_gox may be made of or include a high-k dielectric material. For example, the high-k dielectric material may include hafnium oxide, lanthanum oxide, other suitable materials, or combinations thereof. Further, the 1 st medium voltage gate dielectric layer mv1_gox may have a structure in which a plurality of layers are stacked, wherein the plurality of layers may be made of materials having different dielectric constants.

The 1 st medium voltage gate electrode mv1_g is laminated on the 1 st medium voltage gate dielectric layer mv1_gox. The 1 st medium voltage gate electrode mv1_g may be made of, for example, titanium nitride, tantalum nitride, titanium, tantalum, tungsten, aluminum, copper, other suitable conductive metal materials, or any combination thereof, or may include titanium nitride, tantalum nitride, titanium, tantalum, tungsten, aluminum, copper, other suitable conductive metal materials, or any combination thereof. Alternatively, the 1 st medium voltage gate electrode mv1_g may be made of, or may include, polysilicon, intrinsic polysilicon, doped polysilicon, or any combination thereof. Further, the 1 st voltage gate electrode mv1_g may have a structure in which a plurality of layers are stacked, wherein the plurality of layers may be made of metal materials of different conductivity types.

Further, although not shown, the 1 st medium voltage element MV1 may further include a diffusion barrier layer or a work function layer. The diffusion barrier layer may be made of TiN (titanium nitride), which may be doped with or undoped silicon. The work function layer may determine a work function of a single gate, and may include at least one layer or a plurality of layers made of different materials.

Referring to fig. 4, in the 2 nd medium voltage device MV2, the substrate 100 includes 2-1 nd medium voltage wells mv2_well1, 2-2 nd medium voltage wells mv2_well2, 2-1 nd medium voltage drift regions mv2_ldd1, 2-2 nd medium voltage drift regions mv2_ldd2, 2 nd medium voltage source regions mv2_s, and 2 nd medium voltage drain regions mv2_d doped with n-type dopants or p-type dopants, respectively.

As shown in fig. 4, the 2-1 nd and 2-2 nd medium voltage wells mv2_well1 and mv2_well2 may be formed in a deep N-well DNW doped with an N-type dopant as a first type dopant doped into the substrate 100. However, the present disclosure is not limited thereto, and the 2-1 nd and 2-2 nd medium voltage wells mv2_well1 and mv2_well2 may be formed in the deep P-well of the substrate 100, and in this case, the first type dopant is a P-type dopant.

According to one embodiment of the present disclosure, the 2-1 nd and 2-2 nd medium voltage wells mv2_well1 and mv2_well2 may be doped with different types of dopants. Specifically, the 2-1 medium voltage well mv2_well1 may be a region doped with a first type of dopant, and the 2-2 medium voltage well mv2_well2 may be a region doped with a second type of dopant different from the first type of dopant. For example, as shown in fig. 4, the voltage well mv2_well1 in 2-1 may be a region doped with an n-type dopant as the first type dopant. The 2-2 nd medium voltage well mv2_well2 may be a region doped with a p-type dopant as the second type dopant.

According to one embodiment of the present disclosure, the 2-1 nd medium pressure well mv2_well1 may have a width greater than the width of the 2-2 nd medium pressure well mv2_well 2. Specifically, the first width WL1 of the 2-1 medium voltage well mv2_well1 may be defined as a distance between a boundary between the isolation structure STI and the 2-1 medium voltage well mv2_well1 and a boundary between the 2-1 medium voltage wells mv2_well1 and 2-2 medium voltage wells mv2_well 2. The second width WL2 of the 2-2 nd medium voltage well mv2_well2 may be defined as the distance between the boundary between the 2-2 nd medium voltage well mv2_well2 and the 2-1 nd medium voltage well mv2_well1 and the boundary between the isolation structure STI and the 2-2 nd medium voltage well mv2_well 2. As shown in fig. 4, the first width WL1 of the 2-1 th medium voltage well mv2_well1 may be greater than the second width WL2 of the 2-2 nd medium voltage well mv2_well2 (WL 1> WL 2).

Further, according to one embodiment of the present disclosure, the 2-1 th middling pressure well mv2_well1 disposed between the 2-1 th middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2 may have a width greater than that of the 2-2 nd middling pressure well mv2_well2 disposed between the 2-1 nd middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2. Specifically, the third width WL3 of the 2-1 th midvoltage well mv2_well1 disposed between the 2-1 st midvoltage drift region mv2_ldd1 and the 2-2 nd midvoltage drift region mv2_ldd2 may be defined as a distance from a boundary between the 2-1 st midvoltage drift region mv2_ldd1 and the 2-1 nd midvoltage well mv2_well1 to a boundary between the 2-1 nd midvoltage well mv2_well1 and the 2-2 nd midvoltage well mv2_well 2. The fourth width WL4 of the 2-2 nd medium voltage well mv2_well2 disposed between the 2-1 nd medium voltage drift region mv2_ldd1 and the 2-2 nd medium voltage drift region mv2_ldd2 may be defined as a distance from a boundary between the 2-1 nd medium voltage well mv2_well1 and the 2-2 nd medium voltage well mv2_well2 to a boundary between the 2-2 nd medium voltage drift region mv2_ldd2 and the 2-2 nd medium voltage well mv2_well 2. The third width WL3 of the 2-1 th middling pressure well mv2_well1 disposed between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2 may be greater than the fourth width WL4 of the 2-2 nd middling pressure well mv2_well2 disposed between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2 (WL 3> WL 4). In this regard, the third width WL3 of the 2-1 th middling pressure well mv2_well1 disposed between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2 may be in the range of 0.6 to 0.8 times the distance between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2. The fourth width WL4 of the 2-2 nd midvoltage well mv2_well2 disposed between the 2-1 nd midvoltage drift region mv2_ldd1 and the 2-2 nd midvoltage drift region mv2_ldd2 may have a value of 0.3 μm or less.

Thus, the 2 nd medium voltage element MV2 according to one embodiment of the present disclosure may operate without a separate element even when receiving the second level medium voltage greater than the first level medium voltage. Therefore, a smaller area can be used to perform the function of the 2 nd medium voltage element MV 2.

According to one embodiment of the present disclosure, the 2-1 nd medium voltage well mv2_well1 and the 1 st medium voltage well mv1_well may be formed simultaneously and may be doped with the same dopant at substantially the same concentration. For example, the 1 st and 2-1 nd well mv1_well and mv2_well1 may be doped with an n-type dopant at a first well concentration. However, the present disclosure is not limited thereto, and the 1 st and 2-1 nd medium voltage wells mv1_well and mv2_well1 may be doped with a p-type dopant at the first well concentration.

The 2-1 nd medium voltage drift region mv2_ldd1 may be a region doped with a different type of dopant from the type of dopant doped into the 2-1 nd medium voltage well mv2_well 1. That is, the 2-1 nd medium voltage drift region mv2_ldd1 may be a region doped with a second type dopant different from the first type dopant and may be present in the 2-1 nd medium voltage well mv2_well1 doped with the first type dopant. For example, when the 2-1 th medium voltage well Mc2_well 1 is a region doped with an n-type dopant, the 2-1 nd medium voltage drift region Mc2_ldd1 may be a region doped with a p-type dopant. However, the present disclosure is not limited thereto, and when the 2-1 th medium voltage well mv2_well1 is a region doped with a p-type dopant, the 2-1 th medium voltage drift region mv2_ldd1 may be a region doped with an n-type dopant.

The 2-2 nd medium voltage drift region mv2_ldd2 may be a region doped with the same type of dopant as the type of dopant doped into the 2-2 nd medium voltage well mv2_well 2. That is, the 2-2 nd medium voltage drift region mv2_ldd2 may be a region doped with a second type dopant and may be disposed in the 2-2 nd medium voltage well mv2_well2 doped with the second type dopant. In this regard, the 2-2 nd medium voltage drift region mv2_ldd2 may be a region doped at a concentration different from that at which the 2-2 nd medium voltage well mv2_well2 is doped. For example, when the 2-2 nd medium voltage well mv2_well2 is a region doped with a p-type dopant, the 2-2 nd medium voltage drift region mv2_ldd2 may be a region doped with a p-type dopant. However, the present disclosure is not limited thereto. When the 2-2 nd medium voltage well mv2_well2 is a region doped with an n-type dopant, the 2-2 nd medium voltage drift region mv2_ldd2 may be a region doped with an n-type dopant.

The 2 nd medium voltage device MV2 according to one embodiment of the present disclosure includes a 2-1 nd medium voltage drift region mv2_ldd1 disposed between the 2-1 nd medium voltage well mv2_well1 and the 2 nd medium voltage source region mv2_s, and a 2-2 nd medium voltage drift region mv2_ldd2 disposed between the 2-2 nd medium voltage well mv2_well2 and the 2 nd medium voltage drain region mv2_d. Thus, the 2 nd medium voltage element MV2 may operate in response to receiving a second level medium voltage that is greater than the first level medium voltage.

The 2 nd middle voltage source region mv2_s may be a region doped with the same type of dopant as the type of dopant doped into the 2-1 nd middle voltage drift region mv2_ldd1 and may be disposed in the 2-1 nd middle voltage drift region mv2_ldd1. That is, the 2 nd medium voltage source region mv2_s may be a region doped with the second type dopant and may be disposed in the 2-1 nd medium voltage drift region mv2_ldd1 doped with the second type dopant. For example, when the 2-1 nd medium voltage drift region mv2_ldd1 is a region doped with a p-type dopant, the 2 nd medium voltage source region mv2_s may be a region disposed in the 2-1 nd medium voltage drift region mv2_ldd1 and doped with a p-type dopant. However, the present disclosure is not limited thereto. When the 2-1 nd medium voltage drift region mv2_ldd1 is a region doped with an n-type dopant, the 2 nd medium voltage source region mv2_s may be doped with an n-type dopant and may be disposed in the 2-1 nd medium voltage drift region mv2_ldd1.

The 2 nd medium voltage drain region mv2_d may be a region doped with the same type of dopant as the type of dopant doped into the 2 nd medium voltage drift region mv2_ldd2. That is, the 2 nd medium voltage drain region mv2_d may be a region doped with the second type dopant and may be disposed in the 2 nd-2 medium voltage drift region mv2_ldd2 doped with the second type dopant. For example, when the 2-2 nd medium voltage drift region mv2_ldd2 is a region doped with a p-type dopant, the 2 nd medium voltage drain region mv2_d may be a region doped with a p-type dopant and may be disposed in the 2-2 nd medium voltage drift region mv2_ldd2. However, the present disclosure is not limited thereto. When the 2-2 nd medium voltage drift region mv2_ldd2 is a region doped with an n-type dopant, the 2 nd medium voltage drain region mv2_d may be a region doped with an n-type dopant and may be disposed in the 2-2 nd medium voltage drift region mv2_ldd2.

A 2 nd midgate dielectric layer mv2_gox may be stacked on the substrate 100 so as to partially overlap each of the 2-1 nd middrift region mv2_ldd1 and the 2-2 nd middrift region mv2_ldd2.

The 2 nd medium voltage gate dielectric layer mv2_gox may be made of, or may include, an oxide such as silicon oxide, a nitride such as silicon nitride, a high-k dielectric material, and the like. When the 2 nd medium voltage gate dielectric layer mv2_gox is laminated in a high k gate process (high k metal gate: HKMG), the 2 nd medium voltage gate dielectric layer mv2_gox may be made of a high k dielectric material. For example, the high-k dielectric material may include hafnium oxide, lanthanum oxide, other suitable materials, or combinations thereof. Further, the 2 nd medium voltage gate dielectric layer mv2_gox may have a structure in which a plurality of layers are stacked, wherein the layers may be respectively made of materials having different dielectric constants.

The 2 nd medium voltage gate electrode mv2_g is laminated on the 2 nd medium voltage gate dielectric layer mv2_gox. The 2 nd medium voltage gate electrode mv2_g may be made of, for example, titanium nitride, tantalum nitride, titanium, tantalum, tungsten, aluminum, copper, other suitable conductive metal materials, or any combination thereof, or may include titanium nitride, tantalum nitride, titanium, tantalum, tungsten, aluminum, copper, other suitable conductive metal materials, or any combination thereof. Alternatively, the 2 nd medium voltage gate electrode mv2_g may be made of, or may include, polysilicon, intrinsic polysilicon, doped polysilicon, or any combination thereof. Further, the 2 nd middle voltage gate electrode mv2_g may have a structure in which a plurality of layers are stacked, wherein the plurality of layers may be made of metal materials of different conductivity types.

The 2 nd medium voltage gate electrode mv2_g covers the exposed portion of the top surface of the 2-1 nd medium voltage well mv2_well1 and the exposed portion of the top surface of the 2-2 nd medium voltage well mv2_well 2. Accordingly, the region where the 2 nd middle voltage gate electrode mv2_g and the 2-1 nd middle voltage well mv2_well1 overlap each other may have a length greater than or equal to the aforementioned third width WL 3. The region where the 2 nd medium voltage gate electrode mv2_g and the 2 nd medium voltage well mv2_well2 overlap each other may have a length greater than or equal to the aforementioned fourth width WL 4. That is, therefore, the length of the region where the 2 nd medium voltage gate electrode mv2_g and the 2-1 nd medium voltage well mv2_well1 overlap each other may be greater than the length of the region where the 2 nd medium voltage gate electrode mv2_g and the 2-2 nd medium voltage well mv2_well2 overlap each other. Further, although not shown, the 2 nd medium voltage element MV2 may further include a diffusion barrier layer or a work function layer. The diffusion barrier layer may be made of TiN (titanium nitride), which may be doped with or undoped silicon. The work function layer may determine the work function of a single gate and may include at least one layer or multiple layers made of different materials.

A method for manufacturing a semiconductor device according to one embodiment of the present disclosure is described in detail with reference to fig. 5 to 6E.

Fig. 5 is a flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. Fig. 6A to 6E are diagrams of intermediate structures corresponding to intermediate steps of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

Referring to fig. 5 and 6A, first, in S511, a 1 st well mv1_well and a 2-1 nd well mv2_well1 are formed in the substrate 100. Specifically, as shown in fig. 6A, in the substrate 100, each of the region in which the 1 st medium voltage element MV1 is to be formed and the region in which the 2 nd medium voltage element MV2 is to be formed is doped with a first type dopant that is an n-type dopant or a p-type dopant. Thus, the 1 st medium pressure well MV1_well and the 2-1 nd medium pressure well MV2_well1 are formed. In this regard, the 1 st medium pressure well mv1_well and the 2-1 nd medium pressure well mv2_well1 may be formed by an ion implantation process using a mask.

According to one embodiment of the present disclosure, the 1 st and 2 nd medium voltage elements MV1 and MV2 may be formed in one substrate 100. In particular, the 1 st well mv1_well and the 2-1 nd well mv2_well1 may be formed simultaneously in the same process using one mask. Thus, a separate mask for each of the pressure wells mv1_well in 1 and mv2_well1 in 2-1 is not required. Therefore, the manufacturing cost of the semiconductor device can be reduced.

According to one embodiment of the present disclosure, the 1 st medium voltage well mv1_well and the 2-1 nd medium voltage well mv2_well1 may be doped with the same dopant at substantially the same concentration. That is, the 1 st medium voltage well mv1_well and the 2-1 nd medium voltage well mv2_well1 may be doped with the first type dopant at the first well concentration.

Furthermore, according to one embodiment of the present disclosure, the 1 st medium voltage well mv1_well and the 2-1 nd medium voltage well mv2_well1 may be doped with the same type of dopant as the dopant doped in the deep well region and may be disposed in the deep well region. For example, the 1 st and 2-1 nd medium voltage wells mv1_well and mv2_well1 may be doped with N-type dopants and may be disposed in a deep N-well doped with N-type dopants. That is, the 1 st and 2-1 nd medium voltage wells mv1_well and mv2_well1 may be doped with the first type dopant and may be disposed in the deep well doped with the first type dopant. In this regard, the 1 st and 2-1 nd well mv1_well and the 2 nd well mv2_well1 may be doped at different concentrations.

Then, in S512, a 2-2 nd medium voltage well mv2_well2 is formed in the substrate 100. Specifically, as shown in fig. 6B, the other side of the substrate 100 (different from the side of the substrate 100 where the 2-1 nd intermediate voltage well mv2_well1 has been formed) around the center of the region where the 2 nd intermediate voltage element MV2 is to be formed is doped with a second type dopant, so that the 2-2 nd intermediate voltage well mv2_well2 is formed. In this regard, the 2-2 nd medium voltage well mv2_well2 may be formed by an ion implantation process using a mask. According to one embodiment of the present disclosure, the 1 st medium voltage element MV1, the 2 nd medium voltage element MV2, and other elements may be formed in one substrate 100. In particular, although not shown, one mask is used to form the 2-2 medium voltage well mv2_well2 using wells of other elements. Thus, separate masks for each of the 2-2 medium voltage wells mv2_well2 and the wells of the other elements are not required. Therefore, the manufacturing cost of the semiconductor device can be reduced.

According to one embodiment of the present disclosure, the 2-2 nd medium voltage well mv2_well2 may be a region disposed in the deep well region and doped with a different type of dopant from the type of dopant doped into the deep well region. For example, the 2-2 medium voltage well mv2_well2 may be a region doped with a p-type dopant and disposed in a deep N-well doped with an N-type dopant. That is, the 2-2 nd medium voltage well mv2_well2 may be a region doped with a second type dopant different from the first type dopant and disposed in the deep well doped with the first type dopant.

According to one embodiment of the present disclosure, the 2-1 nd medium pressure well mv2_well1 may be formed to have a width greater than that of the 2-2 nd medium pressure well mv2_well 2. Specifically, the first width WL1 of the 2-1 medium voltage well mv2_well1 may be defined as a distance between a boundary between the isolation structure STI and the 2-1 medium voltage well mv2_well1 and a boundary between the 2-1 medium voltage wells mv2_well1 and 2-2 medium voltage wells mv2_well 2. The second width WL2 of the 2-2 nd medium voltage well mv2_well2 may be defined as the distance between the boundary between the 2-2 nd medium voltage well mv2_well2 and the 2-1 nd medium voltage well mv2_well1 and the boundary between the isolation structure STI and the 2-2 nd medium voltage well mv2_well 2. As shown in fig. 6B, the first width WL1 of the voltage well mv2_well1 in 2-1 may be larger than the second width WL2 of the voltage well mv2_well2 in 2-2 (WL 1> WL 2).

However, although the drawings show that the 1 st medium pressure well mv1_well and the 2-1 nd medium pressure well mv2_well1 are formed, and then the 2-2 nd medium pressure well mv2_well2 is formed, the order of the processes is not limited thereto. Alternatively, the 2-2 nd medium pressure well MV2_well2 may be formed, and then the 1 st medium pressure well MV1_well and the 2-1 nd medium pressure well MV2_well1 may be formed.

Subsequently, in S521, the drift regions mv1_ldd1 and mv1_ldd2 of the 1 st medium voltage element MV1 and the drift regions mv2_ldd1 and mv2_ldd2 of the 2 nd medium voltage element MV2 are formed in the substrate 100. Specifically, as shown in fig. 6C, the 1-1 st medium voltage drift region mv1_ldd1 and the 1-2 nd medium voltage drift region mv1_ldd2 may be formed in the 1 st medium voltage well mv1_well by implanting a low concentration of dopant into the 1 st medium voltage well mv1_well so as to be spaced apart from each other while the middle region of the 1 st medium voltage well mv1_well is disposed between the 1-1 st medium voltage drift region mv1_ldd1 and the 1-2 st medium voltage drift region mv1_ldd2. The 2-1 nd medium voltage drift region mv2_ldd1 may be formed in the 2-1 nd medium voltage well mv2_well1 by implanting a low concentration dopant into the 2-1 nd medium voltage well mv2_well1 in the substrate 100 so as to be spaced apart from the 2-2 nd medium voltage well mv2_well 2. The 2-2 nd medium voltage drift region mv2_ldd2 may be formed in the 2-2 nd medium voltage well mv2_well2 by implanting a low concentration dopant into the 2-2 nd medium voltage well mv2_well2 in the substrate 100 so as to be spaced apart from the 2-1 nd medium voltage well mv2_well1.

According to one embodiment of the present disclosure, the 1 st and 2 nd medium voltage elements MV1 and MV2 may be formed in one substrate 100. In particular, the 1-1 st medium voltage drift region MV1_LDD1, the 1-2 nd medium voltage drift region MV1_LDD2, the 2-1 st medium voltage drift regions MV2_LDD1 and the 2-2 nd medium voltage drift regions MV2_LDD2 may be formed using one mask. Thus, a separate mask for the same is not required. Therefore, the manufacturing cost of the semiconductor device can be reduced.

According to one embodiment of the present disclosure, the 1-1 st medium voltage drift region mv1_ldd1 and the 1-2 st medium voltage drift region mv1_ldd2 may be doped with a different type of dopant than the type of dopant doped into the 1 st medium voltage well mv1_well. The 2-1 th medium voltage drift region mv2_ldd1 may be doped with a different type of dopant than the type of dopant doped into the 2-1 nd medium voltage well mv2_well 1. Conversely, the 2-2 medium voltage drift region mv2_ldd2 may be a region doped with the same type of dopant as the type of dopant doped into the 2-2 medium voltage well mv2_well 2. That is, the 1 st and 2-1 nd well Mc1_well and Mc2_well 1 may be doped with a first type dopant. The 1-1 th medium voltage drift region MV1_LDD1, the 1-2 nd medium voltage drift region MV1_LDD2, and the 2-1 st medium voltage drift region MV2_LDD1 may be doped with a second type dopant. The 2-2 nd medium voltage well mv2_well2 may be doped with a second type dopant. The 2-2 medium voltage drift region mv2_ldd2 may be a region doped with a second type dopant.

According to one embodiment of the present disclosure, the 2-1 th midvoltage well mv2_well1 disposed between the 2-1 st midvoltage drift region mv2_ldd1 and the 2-2 nd midvoltage drift region mv2_ldd2 may have a width greater than that of the 2-2 nd midvoltage well mv2_well2 disposed between the 2-1 nd midvoltage drift region mv2_ldd1 and the 2-2 nd midvoltage drift region mv2_ldd2. Specifically, the third width WL3 of the 2-1 th midvoltage well mv2_well1 disposed between the 2-1 st midvoltage drift region mv2_ldd1 and the 2-2 nd midvoltage drift region mv2_ldd2 may be defined as a distance from a boundary between the 2-1 st midvoltage drift region mv2_ldd1 and the 2-1 nd midvoltage well mv2_well1 to a boundary between the 2-1 nd midvoltage well mv2_well1 and the 2-2 nd midvoltage well mv2_well 2. The fourth width WL4 of the 2-2 nd medium voltage well mv2_well2 disposed between the 2-1 nd medium voltage drift region mv2_ldd1 and the 2-2 nd medium voltage drift region mv2_ldd2 may be defined as a distance from a boundary between the 2-1 nd medium voltage well mv2_well1 and the 2-2 nd medium voltage well mv2_well2 to a boundary between the 2-2 nd medium voltage drift region mv2_ldd2 and the 2-2 nd medium voltage well mv2_well 2. The third width WL3 of the 2-1 th middling pressure well mv2_well1 disposed between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2 may be greater than the fourth width WL4 of the 2-2 nd middling pressure well mv2_well2 disposed between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2 (WL 3> WL 4). In this regard, the third width WL3 of the 2-1 th middling pressure well mv2_well1 disposed between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2 may be in the range of 0.6 to 0.8 times the distance between the 2-1 st middling pressure drift region mv2_ldd1 and the 2-2 nd middling pressure drift region mv2_ldd2. The fourth width WL4 of the 2-2 nd midvoltage well mv2_well2 disposed between the 2-1 nd midvoltage drift region mv2_ldd1 and the 2-2 nd midvoltage drift region mv2_ldd2 may have a value of 0.3 μm or less.

Then, in S531, the 1 st medium voltage source region mv1_s and 1 st medium voltage drain region mv1_d and the 2 nd medium voltage source region mv2_s and 2 nd medium voltage drain region mv2_d are formed. Specifically, the 1 st medium voltage source region mv1_s, the 1 st medium voltage drain region mv1_d, the 2 nd medium voltage source region mv2_s, and the 2 nd medium voltage drain region mv2_d are formed by implanting a second type dopant. As shown in fig. 6D, the 1 st medium voltage source region mv1_s and the 1 st medium voltage drain region mv1_d may be formed by implanting a high concentration of a second type dopant into the 1 st medium voltage drift region mv1_ldd1 and the 1 st medium voltage drift region mv1_ldd2, respectively. The 2 nd medium voltage source region mv2_s and the 2 nd medium voltage drain region mv2_d may be formed by implanting a high concentration of a second type dopant into the 2-1 nd medium voltage drift region mv2_ldd1 and the 2-2 nd medium voltage drift region mv2_ldd2, respectively.

According to one embodiment of the present disclosure, the 1 st and 2 nd medium voltage elements MV1 and MV2 may be formed in one substrate 100. The 1 st middle voltage source region mv1_s, the 1 st middle voltage drain region mv1_d, the 2 nd middle voltage source region mv2_s, and the 2 nd middle voltage drain region mv2_d may be simultaneously formed in one substrate 100 in the same process.

Subsequently, in S541, the gate dielectric layers mv1_gox and mv2_gox and the gate electrodes mv1_g and mv2_g of the 1 st medium voltage element MV1 and the 2 nd medium voltage element MV2 are sequentially stacked, respectively. Specifically, as shown in fig. 6E, a 1 st medium voltage gate dielectric layer mv1_gox is laminated on the substrate 100 so as to partially overlap each of the 1 st medium voltage drift region mv1_ldd1 and the 1 st medium voltage drift region mv1_ldd2. The 1 st medium voltage gate electrode mv1_g is laminated on the 1 st medium voltage gate dielectric layer mv1_gox. Further, a 2 nd medium voltage gate dielectric layer mv2_gox is laminated on the substrate 100 so as to partially overlap each of the 2-1 nd medium voltage drift region mv2_ldd1 and the 2-2 nd medium voltage drift region mv2_ldd2. The 2 nd medium voltage gate electrode mv2_g is laminated on the 2 nd medium voltage gate dielectric layer mv2_gox.

According to one embodiment of the present disclosure, the 1 st and 2 nd medium voltage elements MV1 and MV2 may be formed in one substrate 100. The gate dielectric layers mv1_gox and mv2_gox and the gate electrodes mv1_g and mv2_g of the 1 st and 2 nd medium voltage devices mv1 and mv2, respectively, may be simultaneously formed on one substrate 100 in the same process.

Those skilled in the art to which the present disclosure pertains will appreciate that the present disclosure as described above may be practiced in other specific forms without changing its technical idea or essential features.

It should therefore be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the appended claims, rather than the foregoing detailed description, and should be construed to cover all modifications or variations that may come within the meaning and range of the following claims and equivalents thereof.

The present application claims the benefit of korean patent application No.2022-0109914 filed on month 8 and 31 of 2022, which is hereby incorporated by reference as if fully set forth herein.

Claims

1. A semiconductor device, the semiconductor device comprising:

a 1 st medium voltage element disposed in the substrate and configured to receive a first level medium voltage;

A 2 nd medium voltage element disposed in the substrate and configured to receive a second level medium voltage greater than the first level medium voltage; and

a deep well provided in the substrate so as to surround the 1 st medium voltage element and the 2 nd medium voltage element,

wherein the 2 nd medium voltage element comprises:

a 2-1 nd medium voltage well, the 2-1 nd medium voltage well being doped with a first type dopant; and

a 2-2 nd medium voltage well, said 2-2 nd medium voltage well being doped with a second type of dopant different from said first type of dopant.

2. The semiconductor device of claim 1, wherein the 1 st medium voltage element comprises a 1 st medium voltage well doped with the first type dopant.

3. The semiconductor device of claim 2, wherein the 1 st and 2-1 nd well are doped with the first type dopant at a first well concentration.

4. The semiconductor device of claim 1, wherein a first width of the 2-1 th medium voltage well is greater than a second width of the 2-2 nd medium voltage well.

5. The semiconductor device according to claim 1, wherein the 2 nd medium voltage element further comprises:

a 2-1 th medium voltage drift region, the 2-1 nd medium voltage drift region being doped with the second type dopant; and

A 2-2 nd medium voltage drift region, said 2-2 nd medium voltage drift region being doped with said second type dopant.

6. The semiconductor device of claim 5, wherein a third width of the 2-1 th middling pressure well disposed between the 2-1 st middling pressure drift region and the 2-2 nd middling pressure drift region is greater than a fourth width of the 2-2 nd middling pressure well disposed between the 2-1 st middling pressure drift region and the 2-2 nd middling pressure drift region.

7. The semiconductor device of claim 5, wherein a third width of the 2-1 th medium voltage well disposed between the 2-1 st medium voltage drift region and the 2-2 nd medium voltage drift region is in a range of 0.6 to 0.8 times a distance between the 2-1 st medium voltage drift region and the 2-2 nd medium voltage drift region.

8. A display device, the display device comprising:

a display panel for displaying an image through at least one pixel connected to the gate line and the data line; and

a display driving device, the display driving device comprising:

a timing control circuit configured to output a strobe control signal and a data control signal using a signal input from an external system;

A gate driver circuit configured to output a gate signal to the gate line using the gate control signal; and

a data driver circuit configured to output a source signal to the data line using the data control signal; and

a power supply for supplying power to the display panel and the display driving device,

wherein the data driver circuit includes:

wherein the 2 nd medium voltage element comprises:

9. A method for manufacturing a semiconductor device, the method comprising the steps of:

Forming a deep well in a substrate;

forming a 1 st medium pressure well and a 2-1 nd medium pressure well;

forming a 2-2 medium pressure well;

forming a 1 st medium voltage drift part and a 2-1 nd medium voltage drift part;

forming a 2-2 medium voltage drift part;

forming a 1 st medium voltage source electrode, a 1 st medium voltage drain electrode, a 2 nd medium voltage source electrode and a 2 nd medium voltage drain electrode; and

the 1 st medium voltage gate dielectric layer, the 1 st medium voltage gate electrode, the 2 nd medium voltage gate dielectric layer, and the 2 nd medium voltage gate electrode are laminated.

10. The method of claim 9, wherein the 1 st and 2-1 nd well are formed using a single mask.