CN117636993A - Memory device and method for detecting faulty memory cells thereof - Google Patents

Abstract

Memory devices and methods for detecting defective memory cells thereof are provided. The memory device includes: a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to: controlling input/output operations of the memory cell array. When a memory defect detection command is received from the memory controller, the word line defect detection circuit is configured to generate a fault flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to: the fault flag and the fault row address corresponding to the fault flag are sent to the memory controller.

Description

Memory device and method for detecting faulty memory cells thereof

The present application claims priority to korean patent application No. 10-2022-0110531 filed on 1 month 2022 at 9 and korean patent application No. 10-2022-0167045 filed on 2 month 2022 at 12, which disclosure is incorporated herein by reference in its entirety.

Technical Field

Embodiments of the present disclosure relate to memory devices included in memory systems, and more particularly, to methods of operating memory devices to detect defective memory cells of the memory devices.

Background

Semiconductor memory devices may be generally divided into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. Volatile semiconductor memory devices may have relatively fast read speeds and write speeds, but when power is not supplied to the volatile semiconductor memory devices, the volatile semiconductor memory devices may lose data stored therein. In contrast, even if power supply is interrupted, information stored in the nonvolatile semiconductor memory device does not disappear. Therefore, a nonvolatile semiconductor memory device is used to store information that must be maintained regardless of whether power is supplied thereto.

A representative example of volatile memory is Dynamic Random Access Memory (DRAM). Memory cells of a volatile memory device (e.g., DRAM) may include, for example, one NMOS transistor that acts as a switch and one capacitor that stores charge (data). The binary information "1" or "0" may correspond to the presence or absence of charge in a capacitor stored in the memory cell, i.e., the terminal voltage of the cell capacitor is high or low. The memory cells may be connected to word lines or bit lines. The bit line may be connected to a sense amplifier. The sense amplifier may sense data stored in the memory cell through the bit line based on a voltage applied to the word line.

In general, a memory controller may perform an operation of detecting an error in a memory cell included in a volatile memory and an operation of recovering the memory cell in which the error was detected. The memory controller may determine whether the memory cell has an error by writing dummy data into the memory cell included in the volatile memory, reading the stored dummy data, and comparing the read dummy data with reference data. However, in this method, since the time for detecting the defective memory cell may include a time for writing dummy data into the defective memory cell and a time for reading stored dummy data, the memory controller may require a lot of time to detect the defective memory cell.

Disclosure of Invention

Embodiments of the present disclosure provide a memory device configured to detect defects in memory cells based on leakage current of a word line without a write operation or a read operation of the memory device, and a method for detecting a defective or defective memory cell of the memory device.

According to an embodiment of the present disclosure, a memory device includes: a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to: controlling input/output operations of the memory cell array. The word line defect detection circuit is configured to provide an input voltage to a selected word line of the plurality of word lines in response to receiving a memory defect detection command from the memory controller, and to generate a fault flag based on a difference between a voltage of the selected word line and a reference voltage, and the control logic is configured to send the fault flag and a fault row address corresponding to the fault flag to the memory controller in response to receiving a mode register read command from the memory controller.

According to an embodiment, the memory device may further comprise: a first mode register configured to store a fault flag, and a second mode register configured to store a fault row address.

According to an embodiment, the word line defect detection circuit may be configured to: when the voltage of the selected word line is less than or equal to the reference voltage, storing a first failure flag in a first mode register, and may be configured to: when the voltage of the selected word line exceeds the reference voltage, a second fault flag is stored in the first mode register.

According to an embodiment, the control logic may be configured to: when the first failure flag is stored in the first mode register, the failed row address is stored in the second mode register.

According to an embodiment, the control logic may be configured to: when the second fail flag is stored in the first mode register, the fail row address is not stored.

According to an embodiment, the control logic may be configured to: when a first mode register read command is received, either the first failure flag or the second failure flag stored in the first mode register is sent to the memory controller.

According to an embodiment, when the second mode register read command is received after the first failure flag is sent in response to the first mode register read command, the control logic may be configured to: the failed row address stored in the second mode register is sent to the memory controller.

According to an embodiment, when the failed row address is greater than a certain size, the control logic may be configured to: in response to a third mode register read command received after the second mode register read command is received, an additional failed row address is sent to the memory controller.

According to an embodiment, when the first failure flag is stored in the first mode register, the control logic may be configured to: a write operation of the failed row address associated with the second mode register is performed internally, regardless of a command from the memory controller.

According to an embodiment, the mode register read command may be received after the memory defect detection command is received and after a certain time has elapsed, and the specified time may be based on a time required for a write operation of the failed row address.

According to an embodiment of the present disclosure, a method of detecting a failed memory cell of a memory device includes: the method includes receiving a memory defect detection command from a memory controller, generating a fail flag based on a difference between a voltage of a selected word line among a plurality of word lines of the memory device and a reference voltage in response to the memory defect detection command, storing the fail flag in a first mode register of the memory device, and storing a fail row address corresponding to the fail flag in a second mode register of the memory device.

According to an embodiment, the method of detecting a faulty memory cell may further comprise: a first mode register read command is received from the memory controller and a failure flag stored in the first mode register is sent to the memory controller in response to the first mode register read command.

According to an embodiment, the method of detecting a faulty memory cell may further comprise: when the fail flag indicates a word line failure, a second mode register read command is received from the memory controller and a failed row address stored in the second mode register is sent to the memory controller in response to the second mode register read command.

According to an embodiment, the step of generating the fault flag may comprise: a first fault flag is generated when the voltage of the selected word line is less than or equal to the reference voltage, and a second fault flag is generated when the voltage of the selected word line exceeds the reference voltage.

According to an embodiment, the step of storing the faulty row address in the second mode register may comprise: the failed row address is stored when a first failure flag is stored in the first mode register, and the failed row address is not stored when a second failure flag is stored in the first mode register.

According to an embodiment of the present disclosure, a memory system includes: a memory device comprising a plurality of memory cells, and a memory controller configured to: controlling input/output operations of the memory device. The memory device is configured to: in response to receiving a memory defect detection command from the memory controller, performing a defect detection operation of the plurality of memory cells and configured to: a fault flag indicating current leakage of one or more word lines electrically connected to the plurality of memory cells is generated by a defect detection operation. The memory controller is configured to: a fail flag or a fail row address corresponding to the fail flag from the memory device in response to a mode register read command is received, and the mode register read command is transmitted after a memory defect detection command and after a certain time has elapsed.

According to an embodiment, a memory device may be configured to: based on the memory defect detection command, one of the word lines is selected, and when the voltage of the selected word line is less than or equal to the reference voltage, a first failure flag is stored in the first mode register, and when the voltage of the selected word line exceeds the reference voltage, a second failure flag is stored in the first mode register, and when the first failure flag is stored in the first mode register, a failure row address is stored in the second mode register.

According to an embodiment, a memory device may be configured to: when the first mode register read command is received, either the first failure flag or the second failure flag is sent, and the memory controller may be configured to: when the first failure flag is received in response to the first mode register read command, a second mode register read command is sent.

According to an embodiment, a memory device may be configured to: when a second mode register read command is received, a failed row address is sent.

According to an embodiment, a memory controller may restore a failed memory cell of a memory device based on a failed row address by mapping a logical address mapped to the failed row address to a physical address corresponding to a dummy memory cell.

Drawings

The detailed description of each of the figures is provided to facilitate a more complete understanding of the drawings referenced in the detailed description of the present disclosure.

FIG. 1 is a block diagram illustrating a memory system according to some embodiments.

Fig. 2 is a block diagram illustrating the memory device of fig. 1.

FIG. 3 is a block diagram illustrating the memory system of FIG. 1 performing a memory defect detection operation in accordance with some embodiments.

Fig. 4 is a diagram illustrating, by way of example, the word line defect detection of fig. 3 in accordance with some embodiments.

FIG. 5 is a timing diagram illustrating a memory defect detection operation of the memory system of FIG. 3, according to some embodiments.

FIG. 6 is a flow diagram illustrating a memory defect detection operation of the memory system of FIG. 3, according to some embodiments.

FIG. 7 is a timing diagram illustrating a memory defect identification operation of the memory system of FIG. 3, according to some embodiments.

FIG. 8 is a flow diagram illustrating a memory defect identification operation of the memory system of FIG. 3, according to some embodiments.

FIG. 9 is a timing diagram illustrating a memory defect detection operation of the memory system of FIG. 3, according to some embodiments.

FIG. 10 is a flow chart illustrating a memory defect detection and recovery operation of the memory system of FIG. 3, according to some embodiments.

Fig. 11 is a diagram illustrating a mobile system according to some embodiments.

Detailed Description

Hereinafter, embodiments of the present disclosure may be described in detail and clearly to the extent that those skilled in the art easily implement the present disclosure. The terms "comprising" and/or "including," when used herein, mean that there are stated elements, but not excluding the presence of additional elements. The term "and/or" includes any and all combinations of one or more of the associated listed items.

Further, hereinafter, DRAM may be used as an example of a semiconductor device to describe features and functions of the present disclosure. However, other advantages and capabilities of the present disclosure will be readily appreciated by those skilled in the art in light of the disclosure herein. The disclosure may be implemented or applied by other embodiments. Furthermore, the detailed description may be changed or modified according to viewpoints and applications without departing from the claims, scope and spirit of the present disclosure, and any other objects.

FIG. 1 is a block diagram illustrating a memory system according to an embodiment. Referring to fig. 1, a memory system 1000 of the present disclosure may include a memory controller 1100 and a memory device 1200.

According to an embodiment, the memory controller 1100 may perform an access operation for writing data to the memory device 1200 or reading data stored in the memory device 1200. For example, the memory controller 1100 may generate a command CMD and an address ADDR to write data to the memory device 1200 or read data stored in the memory device 1200. The memory controller 1100 may be at least one of memory controllers, such as a system on chip (SoC), an Application Processor (AP), a Central Processing Unit (CPU), a Digital Signal Processor (DSP), and a Graphics Processing Unit (GPU), for controlling the memory device 1200.

According to an embodiment, the memory controller 1100 may control the overall operation of the memory device 1200 by providing various signals to the memory device 1200. For example, the memory controller 1100 may control memory access operations of the memory device 1200, such as read operations and write operations. The memory controller 1100 provides a command CMD and an address ADDR to the memory device 1200 to write the DATA to the memory device 1200 or read the DATA from the memory device 1200.

According to an embodiment, the memory controller 1100 may generate various types of commands CMD for controlling the memory device 1200. For example, the memory controller 1100 may generate a bank request corresponding to a bank operation that changes the state of a memory bank included in the memory bank to read or write the DATA. As one example, the bank request may include an activation request to change a state of a memory bank included in the memory bank to an activated state. In response to the activation request, the memory device 1200 may activate a row, i.e., a word line, included within the memory bank. The bank request may include a precharge request for changing the memory bank from the active state to the standby state after the reading or writing of the DATA is completed. The memory controller 1100 may generate input/output (I/O) requests (e.g., column Address Strobe (CAS) requests) for performing read operations or write operations of DATA DATA in the memory device 1200.

According to an embodiment, the memory device 1200 may output the DATA requested to be read by the memory controller 1100 to the memory controller 1100, or may store the DATA requested to be written by the memory controller 1100 in a memory unit. The memory device 1200 may input/output DATA based on the command CMD and the address ADDR. The memory device 1200 may include a memory bank.

In this case, the memory device 1200 may be a volatile memory device such as a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Double Data Rate (DDR) DRAM, a DDR SDRAM, a Low Power Double Data Rate (LPDDR) SDRAM, a Graphic Double Data Rate (GDDR) SDRAM, a Rambus Dynamic Random Access Memory (RDRAM), and a static random access memory. Alternatively, the memory device 1200 may also be implemented as a non-volatile memory device, such as a resistive Random Access Memory (RAM) (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin-injection magnetization reversal memory (spin injection magnetization inversion memory, STT-RAM), or the like. In the present specification, the advantages of the present disclosure are described based on the DRAM, but the technical spirit of the present disclosure is not limited thereto.

According to an embodiment, a memory bank may include a memory cell array, a row decoder, a column decoder, a sense amplifier, a write driver, and the like, which are divided in units of banks. The memory bank may store the DATA requested to be written in the memory device 1200 through the write driver, and may read the DATA requested to be read using the sense amplifier. Further, a configuration for storing and holding data in the cell array or the selection circuit according to the address may be also included.

According to an embodiment, the memory system 1000 may detect whether a memory cell is defective based on a leakage current of a word line connected to the memory cell included in the memory device 1200. For example, the memory controller 1100 may send a memory defect detection command over a command line that instructs the memory device 1200 to compare the voltage of the activated word line to a reference voltage. The memory device 1200 may generate a fail flag including word line defect information based on the memory defect detection command, and may store a fail row address corresponding to the fail flag. The memory device 1200 may send a fail flag or a fail row address over a data line in response to a request by the memory controller 1100.

Fig. 2 is a block diagram illustrating the memory device of fig. 1. Referring to fig. 2, the memory device 1200 may include a memory cell array 1210, a row Decoder (DEC) 1211, a column decoder (COL DEC) 1212, an address buffer 1220, a Bit Line Sense Amplifier (BLSA) 1230, input/output circuitry 1240, a command decoder 1251, and control logic 1250.

According to an embodiment, the memory cell array 1210 may include a plurality of memory cells arranged in a matrix form arranged in rows and columns. For example, the memory cell array 1210 may include a plurality of word lines and a plurality of bit lines BL connected to memory cells. A plurality of word lines may be connected to rows of memory cells and a plurality of bit lines BL may be connected to columns of memory cells. The term "coupled to" may be used herein to mean physically and/or electrically connected. When a component or layer is referred to as being "directly on" … … or "directly connected," there are no intervening components or layers present.

According to an embodiment, address buffer 1220 may receive address ADDR from memory controller 1100 of fig. 1. For example, the address ADDR may include a row address RA that addresses a row of the memory cell array 1210 and a column address CA that addresses a column of the memory cell array 1210. The address buffer 1220 may send the row address RA to the row decoder 1211 and the column address CA to the column decoder 1212.

According to an embodiment, the row decoder 1211 may select any one of a plurality of word lines connected to the memory cell array 1210. The row decoder 1211 may decode the row address RA received from the address buffer 1220, may select one word line corresponding to the row address RA, and may activate the selected word line.

According to an embodiment, the column decoder 1212 may select a particular bit line from among the plurality of bit lines BL of the memory cell array 1210. The column decoder 1212 may decode the column address CA received from the address buffer 1220 to select a specific bit line BL corresponding to the column address CA.

According to an embodiment, the bit line sense amplifier 1230 may be connected to a bit line BL of the memory cell array 1210. For example, the bit line sense amplifier 1230 may sense a voltage change of a selected bit line among the plurality of bit lines BL, and may amplify and output the voltage change. The input/output circuit 1240 may output DATA output based on the sensed amplified voltage variation from the bit line sense amplifier 1230 to the memory controller 1100 through the DATA line.

According to an embodiment, the command decoder 1251 may decode the write enable signal (/ WE), the row address strobe signal (/ RAS), the column address strobe signal (/ CAS) and the chip select signal received from the memory controller 1100 such that a control signal corresponding to the command CMD is generated in the control logic 1250. The command CMD may include an activate request, a read request, a write request, or a precharge request. The control logic 1250 may control the overall operation of the bit line sense amplifier 1230 by a control signal corresponding to the command CMD.

According to an embodiment, the memory device 1200 may detect whether a memory cell is defective based on a leakage current of a word line connected to the memory cell included in the memory cell array 1210. For example, the memory device 1200 may receive a memory defect detection command from the memory controller 1100 over a command line, the memory defect detection command indicating that the voltage of the activated word line is compared to a reference voltage. The memory device 1200 may generate a fail flag including word line defect information based on the memory defect detection command, and may store a fail row address corresponding to the fail flag. When the failure flag is generated, the row decoder 1211 may identify a failed row address corresponding to the failure flag. The memory device 1200 may send a fail flag or a fail row address over a data line in response to a request of the memory controller 1100, identifying a defective memory cell or cells without performing write and read operations.

Fig. 3 is a block diagram illustrating a memory system of fig. 1 performing a memory defect detection operation. Referring to fig. 3, a memory system 1000 may include a memory controller 1100 and a memory device 1200. The memory device 1200 may include the components shown in fig. 2. In addition, the memory device 1200 may include a word line defect detection circuit (WDD) 1213, a first mode register 1214, and a second mode register 1215 connected to the memory cell array 1210 and the row decoder 1211. The first mode register 1214 and the second mode register 1215 may be included in the control logic 1250 of fig. 2, or may be separately set. The row decoder 1211, the word line defect detection circuit 1213, the first mode register 1214, and the second mode register 1215 may be controlled by control logic 1250. The terms "first," "second," and the like, herein may be used merely to distinguish one component, layer, direction, etc. from another component, layer, direction, etc.

According to an embodiment, the memory system 1000 may perform a memory defect detection operation. For example, the memory device 1200 may perform a memory defect detection operation under the control of the memory controller 1100. The memory controller 1100 may send a memory defect detection command DFT to the memory device 1200 over the command line. When the memory device 1200 receives the memory defect detection command DFT, the word line defect detection circuit 1213 may determine whether the word line WL connected to the memory cell array 1210 leaks current. When a current leak is detected among the word lines WL, the word line defect detection circuit 1213 may store a fault flag FFG (e.g., a first fault flag) indicating a word line defect (or referred to as a word line fault) in the first mode register 1214. Further, when a current leakage is detected among the word lines WL, the row decoder 1211 may store a fail row address FRA corresponding to the fail flag FFG in the second mode register 1215. In contrast, when no current leakage is detected among the word lines WL, the word line defect detection circuit 1213 may store a fault flag FFG (e.g., a second fault flag) indicating that the word line is normal (i.e., not defective) in the first mode register 1214. However, when no current leakage is detected among the word lines WL, the defective row address FRA may not be stored in the second mode register 1215.

According to an embodiment, the memory system 1000 may perform a memory defect identification operation. For example, the memory device 1200 may send defective word line information detected under the control of the memory controller 1100 to the memory controller 1100. After the memory defect detection command DFT is sent and a certain time passes, the memory controller 1100 may send a mode register read command MRRC (e.g., a first mode register read command) to the memory device 1200 through the command line. When the mode register read command MRRC is received, the memory device 1200 may send the failure flag FFG stored in the first mode register 1214 to the memory controller 1100 through the data line. The memory controller 1100 may identify the received failure flag FFG. When the received fault flag FFG is a fault flag FFG (e.g., a first fault flag) indicating a word line defect, the memory controller 1100 may send another mode register read command MRRC (e.g., a second mode register read command) to the memory controller 1100. When another mode register read command MRRC is received, the memory device 1200 may send the fail row address FRA (or the fail row address FRA corresponding to the fail flag FFG) stored in the second mode register 1215 to the memory controller 1100. Meanwhile, when the received fault flag FFG is a fault flag FFG (e.g., a second fault flag) indicating that the word line is normal, the memory controller 1100 may periodically transmit the memory defect detection command DFT without transmitting another mode register read command MRRC (e.g., a second mode register read command).

According to an embodiment, the memory system 1000 may perform a memory defect recovery operation. For example, when a fail flag FFG (e.g., a first fail flag) indicating a word line defect and a fail row address FRA corresponding to the fail flag FFG are received, the memory controller 1100 may allow at least one memory cell corresponding to the fail row address FRA to be replaced with a dummy memory cell. For example, the memory controller 1100 may map a logical address mapped to the failed row address FRA to a physical address corresponding to the dummy memory cell. The memory controller 1100 may allow the failed row address FRA to be blocked.

Fig. 4 is a diagram illustrating the word line defect detection circuit of fig. 3 by way of example. Referring to fig. 3 and 4, the word line defect detection circuit 1213 may detect whether the memory cell is defective based on the leakage current of the word line. Word lines WL (e.g., wl_0 to wl_n, e.g., N may be a positive integer) connected to the memory cell array 1210 may be connected to the word line driver 1216, and the word line defect detection circuit 1213 may be connected to the word line driver 1216. For example, the word line driver 1216 may be included in the memory cell array 1210, or may be separately provided.

According to an embodiment, the word line driver 1216 may include a driving transistor that supplies a power supply voltage (or referred to as an input voltage) VDD to each of the word lines (e.g., wl_0 to wl_n). For example, the driving transistors may include P-channel metal oxide semiconductor (PMOS) transistors dp_0 to dp_n and N-channel metal oxide semiconductor (NMOS) transistors dn_0 to dn_n. As one example, a word line (e.g., wl_0) may be enabled by one PMOS transistor (e.g., dp_0) and one NMOS transistor (e.g., dn_0). The drain of one PMOS transistor (e.g., dp_0) and the drain of one NMOS transistor (e.g., dn_0) may be connected to a word line (e.g., wl_0). The source of one NMOS transistor (e.g., dn_0) may be connected to the ground terminal. Each of the PMOS transistors dp_0 to dp_n may be turned on or off by the word line enable signals ewl_0 to ewl_n, respectively. Each of the NMOS transistors dn_0 to dn_n may be turned on or off by the inverted word line enable signals bewl_0 to bewl_n, respectively.

According to an embodiment, the word line defect detection circuit 1213 may include a switching transistor SP and a comparator 1213a. For example, the switching transistor SP may supply the power supply voltage VDD to the sources of the PMOS transistors dp_0 to dp_n based on the preparation voltage VPRE. In one example, the word line defect detection circuit 1213 may output a failure flag FFG based on the voltage of the activated word line and the reference voltage VREF. For example, the word line defect detection circuit 1213 (e.g., comparator 1213 a) may output a failure flag FFG by comparing the voltage of the activated word line with a reference voltage VREF. For another example, the word line defect detection circuit 1213 may output a failure flag FFG based on a difference between the voltage of the activated word line and the reference voltage VREF.

According to an embodiment, when the memory device 1200 receives the memory defect detection command DFT, the word line defect detection circuit 1213 may detect whether each word line is defective. For example, the switching transistor SP of the word line defect detection circuit 1213 may be turned on, and the power supply voltage VDD may be supplied to the sources of the PMOS transistors dp_0 to dp_n. The switching transistor SP of the word line defect detection circuit 1213 may be turned off, and one of the word lines (e.g., wl_0 to wl_n) may be activated. For example, when the PMOS transistor dp_0 and the NMOS transistor dn_0 are turned on based on the word line enable signal ewl_0 and the inverted word line enable signal bewl_0, the word line wl_0 may be activated. In this case, when the memory cell connected to the word line wl_0 has a defect, a leakage current occurs through the word line wl_0, and then the voltage of the word line wl_0 may be lowered. The comparator 1213a may compare the voltage of the word line wl_0 connected through the PMOS transistor dp_0 with the reference voltage VREF. When the voltage of the word line wl_0 is equal to or less than the reference voltage VREF, the comparator 1213a may output a fault flag FFG (e.g., a first fault flag) indicating a word line defect. When the voltage of the word line wl_0 exceeds the reference voltage VREF, the comparator 1213a may output a fault flag FFG (e.g., a second fault flag) indicating that the word line is normal. As in the above description, the word line defect detection circuit 1213 may determine whether each of the word lines (e.g., wl_0 to wl_n) is defective, and may output a corresponding failure flag FFG.

Fig. 5 is a timing diagram illustrating a memory defect detection operation of the memory system of fig. 3. Referring to fig. 3 and 5, the memory device 1200 may detect whether a memory cell is defective based on leakage current of a word line. The memory controller 1100 may send a memory defect detection command DFT to the memory device 1200 over the command line. For example, the memory controller 1100 may periodically send a memory defect detection command DFT to detect defects of memory cells in the memory device 1200. When the memory defect detection command DFT is received, the word line defect detection circuit 1213 of the memory device 1200 may output the failure flag FFG according to the method described with reference to fig. 4.

According to an embodiment, when a memory cell connected to a word line has a defect, the word line defect detection circuit 1213 may output a first failure flag FF1 (e.g., logic 1) indicating the word line defect. The first mode register 1214 may store a first fault flag FF1. When the first failure flag FF1 occurs, the row decoder 1211 may transfer the failure row address FRA corresponding to the first failure flag FF1 to the second mode register 1215 inside the memory device 1200. The second mode register 1215 may store a defective row address FRA corresponding to the first defective flag FF1. In one example, MRW in FIG. 5 represents a mode register write.

According to an embodiment, when there is no defect in the memory cell connected to the word line, the word line defect detection circuit 1213 may output a second failure flag FF2 (e.g., logic 0) indicating that the word line is normal. When there is no defect in the memory cell connected to the word line, the row decoder 1211 does not output the defective row address FRA, and the word line defect detection circuit 1213 may continue to detect defects of the subsequent word line.

As described above, the memory device 1200 may detect whether a memory cell connected to a word line is defective based on a leakage current of the word line. Thus, the memory device 1200 may detect whether a memory cell is defective through a bank request (e.g., a memory defect detection command DFT) for activating a word line, rather than through a write operation and a read operation. Accordingly, the memory defect detection method of the memory device 1200 may reduce time and power consumption compared to a method of detecting a memory cell defect through a write operation and a read operation of the memory cell.

Fig. 6 is a flowchart illustrating a memory defect detection operation of the memory system of fig. 3. Referring to fig. 3 through 6, the memory device 1200 may perform a memory defect detection operation under the control of the memory controller 1100. The memory device 1200 can detect whether a memory cell is defective based on the leakage current of the word line.

According to an embodiment, the memory device 1200 may receive a memory defect detection command DFT in operation S110. For example, the memory controller 1100 may periodically send a memory defect detection command DFT to the memory device 1200.

According to an embodiment, the memory device 1200 may perform a word line defect detection operation in response to the memory defect detection command DFT in operation S120. For example, when the memory defect detection command DFT is received, the word line defect detection circuit 1213 of the memory device 1200 may apply the input voltage VDD for each word line and may compare the voltage of the word line with the reference voltage VREF. When leakage current occurs due to defects in memory cells connected to the word line, the voltage of the word line may drop below the reference voltage VREF. When the memory cell connected to the word line is normal, the voltage of the word line may be maintained higher than the reference voltage VREF.

According to an embodiment, the memory device 1200 may generate the failure flag FFG according to whether a word line failure is detected in operation S130. For example, when the voltage of the word line is equal to or less than the reference voltage VREF, the word line defect detection circuit 1213 may output a first failure flag FF1 indicating that the word line fails. When the voltage of the word line exceeds the reference voltage VREF, the word line defect detection circuit 1213 may output a second failure flag FF2 indicating that the word line is normal.

According to an embodiment, the memory device 1200 may store the generated failure flag FFG in the first mode register 1214 in operation S140. For example, the memory device 1200 may store the first failure flag FF1 in the first mode register 1214 when the voltage of the word line is less than or equal to the reference voltage VREF (i.e., when the memory cell connected to the word line is defective or indicates that the memory cell connected to the word line is defective). When the voltage of the word line exceeds the reference voltage VREF (i.e., when the memory cell connected to the word line is not defective or indicates that the memory cell connected to the word line is not defective), the memory device 1200 may store the second failure flag FF2 to the first mode register 1214.

According to an embodiment, the memory device 1200 may store the fail row address FRA corresponding to the fail flag FFG in the second mode register 1215 in operation S150. For example, when the voltage of the word line is less than or equal to the reference voltage VREF (i.e., when the memory cell connected to the word line is defective or indicates that the memory cell connected to the word line is defective), the memory device 1200 may store the defective row address FRA corresponding to the first defective flag FF1 in the second mode register 1215. When the voltage of the word line exceeds the reference voltage VREF (i.e., when the memory cell connected to the word line is not defective or indicates that the memory cell connected to the word line is not defective), the memory device 1200 may not store anything (e.g., may not store the failed row address FRA) in the second mode register 1215.

Fig. 7 is a timing diagram illustrating a memory defect identification operation of the memory system of fig. 3. Referring to fig. 3 and 7, the memory controller 1100 may send a mode register read command MRRC to the memory device 1200 through a command line. The memory device 1200 may send a fail flag FFG in response to the mode register read command MRRC and additionally send a fail row address FRA to the memory controller 1100 through a data line.

According to an embodiment, the memory controller 1100 may send a first mode register read command MRR1 to the memory device 1200. The memory device 1200 may send a failure flag FFG (e.g., a first failure flag FF1 or a second failure flag FF 2) in response to the first mode register read command MRR 1. The memory controller 1100 may determine whether the word line is defective based on the received failure flag FFG, and may transmit an additional mode register read command MRRC. When a mode register read command MRRC is received, the memory device 1200 may activate the register read signal RRS. The first mode register 1214 or the second mode register 1215 may output stored data based on the register read signal RRS.

According to an embodiment, when a memory cell connected to a word line has a defect, the memory device 1200 may activate the first register read signal R1 in response to the first mode register read command MRR 1. The first mode register 1214 may output the first failure flag FF1 based on the first register read signal R1. The memory device 1200 may send the first failure flag FF1 to the memory controller 1100 through the data line. When the first failure flag FF1 is received, the memory controller 1100 may send a second mode register read command MRR2 to the memory device 1200 through the command line. The memory device 1200 may activate a second register read signal R2 in response to a second mode register read command MRR 2. The second mode register 1215 may output the fail row address FRA (e.g., FRA1 to FRA 8) corresponding to the first fail flag FF1 based on the second register read signal R2. The memory device 1200 may send the failed row address FRA to the memory controller 1100 through the data lines.

Additionally (or alternatively), when the failed row address FRA is relatively long (e.g., when the failed row address FRA is greater than a particular size), the memory controller 1100 may send a third mode register read command MRR3 to the memory device 1200 over the command line. The memory device 1200 may activate a third register read signal R3 in response to a third mode register read command MRR 3. The second mode register 1215 may output additional fault row addresses ("additional" FRAs) (e.g., FRA9 through FRA 16) corresponding to the first fault flag FF1 based on the third register read signal R3. The memory device 1200 may send additional failed row addresses ("additional" FRAs) to the memory controller 1100 through the data lines.

According to an embodiment, when a memory cell connected to a word line is not defective, the memory device 1200 may activate the first register read signal R1 in response to the first mode register read command MRR 1. The first mode register 1214 may output the second fault flag FF2 based on the first register read signal R1. The memory device 1200 may send the second failure flag FF2 to the memory controller 1100 through the data line. When the second failure flag FF2 is received, the memory controller 1100 may determine that the word line is not defective and may transmit the memory defect detection command DFT of fig. 5 to the memory device 1200 after a certain time elapses.

As described above, the memory device 1200 may determine whether a memory cell connected to a word line is defective based on a leakage current of the word line. Thus, the memory device 1200 may determine whether a memory cell is defective through an I/O request (e.g., a mode register read command MRRC) for outputting a relatively small capacity of a fail flag and a fail row address, rather than through a write operation and a read operation. Accordingly, the memory defect detection method of the memory device 1200 may reduce time and power consumption compared to a method of detecting a memory cell defect through a write operation and a read operation of the memory cell.

Fig. 8 is a flowchart illustrating a memory defect identification operation of the memory system of fig. 3. Referring to fig. 3, 7 and 8, the memory controller 1100 may receive the result of the memory defect detection operation performed according to the memory defect detection command DFT.

According to an embodiment, in operation S210, the memory device 1200 may receive a first mode register read command MRR1. For example, after the memory defect detection command DFT of fig. 5 is sent and a certain time passes, the memory controller 1100 may send the first mode register read command MRR1 to the memory device 1200 through the command line.

According to an embodiment, in operation S220, the memory device 1200 may transmit the fault flag FFG stored in the first mode register 1214 in response to the first mode register read command MRR 1. For example, the memory device 1200 may activate the first register read signal R1 in response to the first mode register read command MRR 1. The first mode register 1214 may output the first fault flag FF1 or the second fault flag FF2 based on the first register read signal R1. When the voltage of the word line is equal to or less than the reference voltage VREF (i.e., when the memory cell connected to the word line is defective or indicates that the memory cell connected to the word line is defective), the memory device 1200 may transmit the first failure flag FF1 stored in the first mode register 1214 to the memory controller 1100 through the data line. When the voltage of the word line exceeds the reference voltage VREF (i.e., when the memory cell connected to the word line is not defective or indicates that the memory cell connected to the word line is not defective), the memory device 1200 may send the second failure flag FF2 stored in the first mode register 1214 to the memory controller 1100 through the data line.

According to an embodiment, in operation S230, the memory device 1200 may receive a second mode register read command MRR2. For example, the memory controller 1100 may determine whether the word line is defective based on the fail flag FFG transmitted in operation S220. When the first failure flag FF1 is received, the memory controller 1100 may determine that the memory cell connected to the word line is defective. The memory controller 1100 may send the second mode register read command MRR2 through the command line in response to the first failure flag FF 1. However, when the second failure flag FF2 is received, the memory controller 1100 may determine that the memory cell connected to the word line is not defective. When it is determined that the memory cell connected to the word line is not defective, the memory controller 1100 may transmit the memory defect detection command DFT of fig. 5 to the memory device 1200 after a certain time elapses.

According to an embodiment, the memory device 1200 may send the fail row address FRA stored in the second mode register 1215 in response to the second mode register read command MRR2 in operation S240. For example, when a second mode register read command MRR2 is received (or when a memory cell connected to a word line has a defect), the memory device 1200 may activate the second register read signal R2 in response to the second mode memory read command MRR 2. The second mode register 1215 may output the fail row address FRA (e.g., FRA1 to FRA 8) corresponding to the first fail flag FF1 based on the second register read signal R2. The memory device 1200 may send the failed row address FRA to the memory controller 1100 through the data lines.

According to an embodiment, in operation S250, the memory device 1200 may receive a third mode register read command MRR3. For example, when an additional defective row address FRA exists, operations S250 and S260 may be performed. When the defective row address FRA is relatively long, the memory controller 1100 may additionally send a third mode register read command MRR3 to the memory device 1200 through the command line after receiving a front or first portion of the defective row address FRA (e.g., FRA 1-FRA 8).

According to an embodiment, the memory device 1200 may transmit the additional fail row address FRA stored in the second mode register 1215 in response to the third mode register read command MRR3 in operation S260. For example, the memory device 1200 may activate the third register read signal R3 in response to the third mode register read command MRR 3. The second mode register 1215 may output additional fault row addresses ("additional" FRAs) (e.g., FRA9 through FRA 16) corresponding to the first fault flag FF1 based on the third register read signal R3. The memory device 1200 may send additional failed row addresses ("additional" FRAs) to the memory controller 1100 through the data lines.

Fig. 9 is a timing diagram illustrating a memory defect detection operation of the memory system of fig. 3, in accordance with various embodiments. Referring to fig. 3 and 9, the memory system 1000 may continuously perform the memory defect detection operation of fig. 5 and the memory defect recognition operation of fig. 7. Fig. 9 may illustrate the operation of the memory system 1000 when a word line failure is detected.

According to an embodiment, the memory controller 1100 may send a memory defect detection command DFT to the memory device 1200 through the command line. For example, when a memory defect is detected according to the method of fig. 4, the word line defect detection circuit 1213 may output a first failure flag FF1 (e.g., logic 1). The first mode register 1214 may store a first fault flag FF1. The row decoder 1211 may transfer the defective row address FRA corresponding to the first defective flag FF1 to the second mode register 1215. The second mode register 1215 may store a defective row address FRA. In this case, the second mode register 1215 may perform a write operation of the failed row address FRA inside the memory device 1200 regardless of the memory controller 1100.

According to an embodiment, after the memory defect detection command DFT is sent and a certain time (e.g., mode register read time MRRT) has elapsed, the memory controller 1100 may send a first mode register read command MRR1 to the memory device 1200. For example, the mode register read time MRRT may be set considering the time at which the second mode register 1215 stores the defective row address FRA. For example, the first mode register read command MRR1 may be sent to the memory device 1200 during a write operation of the failed row address FRA. Optionally, the first mode register read command MRR1 may also be sent to the memory device 1200 after the write operation of the failed row address FRA is completed.

According to an embodiment, the memory device 1200 may activate the first register read signal R1 in response to the first mode register read command MRR 1. The first mode register 1214 may output the first failure flag FF1 based on the first register read signal R1. The memory device 1200 may send the first failure flag FF1 to the memory controller 1100 through the data line. When the first failure flag FF1 is received, the memory controller 1100 may send a second mode register read command MRR2 to the memory device 1200 through the command line. The memory device 1200 may activate a second register read signal R2 in response to a second mode register read command MRR 2. The second mode register 1215 may output the fail row address FRA (e.g., FRA1 to FRA 8) corresponding to the first fail flag FF1 based on the second register read signal R2. The memory device 1200 may send the failed row address FRA to the memory controller 1100 through the data lines.

Additionally (or alternatively), when the failed row address FRA is relatively long, the memory controller 1100 may send a third mode register read command MRR3 to the memory device 1200 over the command line. The memory device 1200 may activate a third register read signal R3 in response to a third mode register read command MRR 3. The second mode register 1215 may output additional fault row addresses ("additional" FRAs) (e.g., FRA9 through FRA 16) corresponding to the first fault flag FF1 based on the third register read signal R3. The memory device 1200 may send additional failed row addresses ("additional" FRAs) to the memory controller 1100 through the data lines.

As described above, the memory device 1200 can detect whether a memory cell connected to a word line is defective based on a leakage current of the word line. Thus, the memory device 1200 may detect whether a memory cell is defective through a bank request (e.g., a memory defect detection command DFT) for activating a word line and an I/O request (e.g., a mode register read command MRRC) for outputting a relatively small capacity of a fail flag and a fail row address, instead of through a write operation and a read operation. Accordingly, the memory defect detection method of the memory device 1200 may reduce time and power consumption compared to a method of detecting a memory cell defect through a write operation and a read operation of the memory cell.

FIG. 10 is a flowchart illustrating a memory defect detection and recovery operation of the memory system of FIG. 3. Referring to fig. 3 through 10, the memory system 1000 may detect defects related to word lines of the memory device 1200 and then perform a restore operation on the failed word line.

According to an embodiment, the memory system 1000 may perform a word line defect detection operation in operation S310. For example, the memory controller 1100 may periodically send a memory defect detection command DFT to the memory device 1200. When the memory defect detection command DFT is received, the word line defect detection circuit 1213 of the memory device 1200 may apply the input voltage VDD for each word line and may compare the voltage of the word line with the reference voltage VREF. When the voltage of the word line is equal to or less than the reference voltage VREF, the word line defect detection circuit 1213 may output a first failure flag FF1 indicating a word line failure. When the voltage of the word line exceeds the reference voltage VREF, the word line defect detection circuit 1213 may output a second failure flag FF2 indicating that the word line is normal. The memory device 1200 may store the first failure flag FF1 or the second failure flag FF2 in the first mode register 1214. When the first failure flag FF1 is stored in the first mode register 1214, the memory device 1200 may store the failure row address FRA corresponding to the first failure flag FF1 to the second mode register 1215.

According to an embodiment, the memory system 1000 may determine word line defect information included in the fail flag FFG in operation S320. For example, the memory controller 1100 may receive a first failure flag FF1 (e.g., logic 1) or a second failure flag FF2 (e.g., logic 0) in response to the first mode register read command MRR 1. When the first failure flag FF1 is received, the memory controller 1100 may send a second mode register read command MRR2 to the memory device 1200. The memory controller 1100 may receive the fail row address FRA corresponding to the first fail flag FF1, which is provided in response to the second mode register read command MRR 2.

According to an embodiment, when a defective word line exists, the memory system 1000 may store a defective address corresponding to the defective word line in operation S330. For example, the memory controller 1100 may store and manage the failed row address FRA as a list.

According to an embodiment, the memory system 1000 may restore a word line corresponding to a defective address in operation S340. For example, the memory controller 1100 may replace at least one memory cell corresponding to the failed row address FRA with a dummy memory cell. For example, the memory controller 1100 may map a logical address mapped to the failed row address FRA to a physical address corresponding to the dummy memory cell. The memory controller 1100 may allow the failed row address FRA to be blocked.

Fig. 11 is a diagram illustrating a mobile system according to an embodiment. Referring to fig. 11, a mobile system 2000 may include an Application Processor (AP) 2100 and a memory device 2200. The application processor 2100 may include a memory controller 2110. Memory device 2200 may include a memory core 2210 and control logic 2220.

According to an embodiment, the memory controller 2110 may control the overall operation of the memory device 2200 by providing various signals to the memory device 2200. For example, the memory controller 2110 may control memory access operations of the memory device 2200, such as read operations and write operations. The memory controller 2110 may provide a command CMD and an address ADDR to the memory device 2200 to write the DATA to the memory device 2200 or read the DATA from the memory device 1200. In addition, the memory controller 2110 may also provide a clock signal CLK to the memory device 2200.

According to an embodiment, the memory device 2200 may output the DATA requested for reading by the memory controller 2110 to the memory controller 2110, or may store the DATA requested for writing by the memory controller 2110 in a memory unit. The memory device 2200 may input/output the DATA based on the command CMD, the address ADDR, and the clock signal CLK. Memory device 2200 may include a memory core 2210 and control logic 2220. Memory core 2210 may include an array of memory cells divided in units of banks. The memory cell array may include a plurality of memory banks.

According to an embodiment, the mobile system 2000 may perform the memory defect detection and recovery operations described in fig. 3 through 10. For example, the memory device 2200 may also include a word line defect detection circuit 2230, a first mode register (MR 1) 2240, and a second mode register (MR 2) 2250. The memory controller 2110 may send a memory defect detection command DFT to the memory device 2200 through the command line. When a memory defect is detected according to the method of fig. 4, the word line defect detection circuit 2230 may output a first failure flag FF1 (e.g., logic 1). The first mode register 2240 may store a first failure flag FF1. The memory device 2200 may transfer the defective row address FRA corresponding to the first defective flag FF1 to the second mode register 2250. In this case, the second mode register 2250 may perform a write operation of the failed row address FRA inside the memory device 2200 regardless of the memory controller 2110.

According to an embodiment, the memory controller 2110 may send the first mode register read command MRR1 to the memory device 2200 after sending the memory defect detection command DFT and a certain time elapses. When a memory defect is detected according to the method of fig. 4, the memory device 2200 may output the first failure flag FF1 stored in the first mode register 2240 in response to the first mode register read command MRR 1. The memory device 2200 may send the first failure flag FF1 to the memory controller 2110 through a data line. When the first failure flag FF1 is received, the memory controller 2110 may send a second mode register read command MRR2 to the memory device 2200 through the command line. The memory device 2200 may output the defective row address FRA stored in the second mode register 2250 in response to the second mode register read command MRR 2. The memory device 2200 may send the failed row address FRA to the memory controller 2110 through a data line.

According to an embodiment, the word line defect detection circuit 2230 may output a second failure flag FF2 (e.g., logic 0) when a memory defect is not detected according to the method of fig. 4. The first mode register 2240 may store the second fault flag FF2. In this case, the memory device 2200 may not store anything (e.g., may not store the failed row address FRA) in the second mode register 2250. The memory controller 2110 may send the first mode register read command MRR1 to the memory device 2200 after the memory defect detection command DFT is sent and a certain time passes. The memory device 2200 may send the second failure flag FF2 to the memory controller 2110 in response to the first mode register read command MRR 1. When the second failure flag FF2 is received, the memory controller 2110 may determine that there is no memory defect and may not transmit the second mode register read command MRR2.

As described above, the memory device 2200 may detect whether a memory cell connected to a word line is defective based on a leakage current of the word line. Thus, rather than through write and read operations, memory device 2200 may detect whether a memory cell is defective by a bank request (e.g., memory defect detection command DFT) for activating a word line and/or an I/O request (e.g., mode register read command MRRC) for outputting a relatively small capacity of a fail flag and a fail row address. Thus, the memory defect detection method of the memory device 2200 may reduce time and power consumption compared to a method of detecting a memory cell defect through a write operation and a read operation of the memory cell.

According to embodiments of the present disclosure, the time and power for detecting a failed memory cell may be reduced by detecting a failed memory cell without performing a write operation or a read operation of the memory device.

The above description is of specific embodiments for carrying out the disclosure. Many variations may be included in the present disclosure and the above embodiments. Further, variations of the techniques implemented by using the above embodiments may be included in the present disclosure. While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the scope of the disclosure as set forth in the following claims.

Claims (20)

1. A memory device, comprising:

a memory cell array including a plurality of memory cells;

a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines; and

control logic configured to: controls the input/output operations of the memory cell array,

wherein the word line defect detection circuit is configured to: providing an input voltage to a selected word line among the plurality of word lines in response to receiving a memory defect detection command from the memory controller, and generating a failure flag based on the voltage of the selected word line and a reference voltage, and

Wherein the control logic is configured to: in response to receiving a mode register read command from the memory controller, a failure flag and/or a failure row address corresponding to the failure flag is sent to the memory controller.

2. The memory device of claim 1, further comprising:

a first mode register configured to store a fault flag; and

a second mode register configured to store a failed row address.

3. The memory device of claim 2, wherein the word line defect detection circuit is configured to:

storing a first failure flag in a first mode register in response to the voltage of the selected word line being less than or equal to a reference voltage, an

A second fault flag is stored in the first mode register in response to the voltage of the selected word line exceeding the reference voltage.

4. The memory device of claim 3, wherein the control logic is configured to: in response to storing the first failure flag in the first mode register, a failed row address is stored in the second mode register.

5. The memory device of claim 3, wherein the control logic is configured to: in response to storing the second failure flag in the first mode register, the failed row address is not stored.

6. The memory device of claim 3, wherein the control logic is configured to: in response to receiving the first mode register read command, the first failure flag or the second failure flag stored in the first mode register is sent to the memory controller.

7. The memory device of claim 6, wherein the control logic is configured to: in response to receiving the second mode register read command after transmitting the first failure flag in response to the first mode register read command, a failed row address stored in the second mode register is transmitted to the memory controller.

8. The memory device of claim 7, wherein the control logic is configured to: in response to the failed row address being greater than a particular size, an additional failed row address is sent to the memory controller in response to receiving a third mode register read command after receiving the second mode register read command.

9. The memory device of claim 3, wherein the control logic is configured to: in response to storing the first failure flag in the first mode register, a write operation of a failed row address associated with the second mode register is performed internally, independent of a command from the memory controller.

10. The memory device of claim 9, wherein the control logic is configured to: after a memory defect detection command is received and a certain time has elapsed, a mode register read command is received from the memory controller, and

wherein the specific time is based on the time required for a write operation of the failed row address.

11. A method of operating a memory device, the method comprising:

receiving a memory defect detection command from a memory controller;

generating a fault flag based on a voltage of a selected word line among a plurality of word lines of the memory device and a reference voltage in response to the memory defect detection command;

storing the fault flag in a first mode register of the memory device; and

a faulty row address corresponding to the faulty flag is stored in a second mode register of the memory device.

12. The method of claim 11, further comprising:

receiving a first mode register read command from a memory controller; and

in response to the first mode register read command, a fault flag stored in the first mode register is sent to the memory controller,

wherein the step of generating the fault flag comprises: a fault flag is generated based on a difference between the voltage of the selected word line and a reference voltage.

13. The method of claim 12, further comprising:

receiving a second mode register read command from the memory controller in response to a fault flag indicating a word line fault; and

in response to the second mode register read command, the failed row address stored in the second mode register is sent to the memory controller.

14. The method of any of claims 11 to 13, wherein the step of generating a fault flag comprises:

generating a first fault flag in response to the voltage of the selected word line being less than or equal to a reference voltage; and

a second fault flag is generated in response to the voltage of the selected word line exceeding the reference voltage.

15. The method of claim 14, wherein storing the failed row address corresponding to the failure flag in a second mode register of the memory device comprises:

storing a failed row address in response to storing the first failure flag in the first mode register; and

in response to storing the second failure flag in the first mode register, the failed row address is not stored.

16. A memory system, comprising:

a memory device including a plurality of memory cells; and

A memory controller configured to: controls the input/output operations of the memory device,

wherein the memory device is configured to: performing a defect detection operation of the plurality of memory cells in response to receiving a memory defect detection command from the memory controller, and generating a fault flag indicating current leakage of one or more word lines electrically connected to the plurality of memory cells by the defect detection operation, an

Wherein the memory controller is configured to: a fail flag from the memory device and/or a fail row address corresponding to the fail flag in response to a mode register read command is received, the mode register read command being sent after a memory defect detection command is sent and a certain time has elapsed.

17. The memory system of claim 16, wherein the memory device is configured to:

one of the one or more word lines is selected based on the memory defect detection command,

in response to the voltage of the selected word line being less than or equal to the reference voltage, storing a first failure flag in a first mode register,

in response to the voltage of the selected word line exceeding the reference voltage, a second failure flag is stored in the first mode register,

In response to storing the first failure flag in the first mode register, a failed row address is stored in the second mode register.

18. The memory system of claim 17, wherein the memory device is configured to: in response to receiving the first mode register read command, transmitting a first failure flag or a second failure flag, an

Wherein the memory controller is configured to: the second mode register read command is sent in response to receiving a first failure flag in response to the first mode register read command.

19. The memory system of claim 18, wherein the memory device is configured to: in response to receiving the second mode register read command, a failed row address is sent.

20. The memory system of any one of claims 16 to 19, wherein the memory controller is configured to: the failed memory cell of the memory device is restored based on the failed row address by mapping the logical address mapped to the failed row address to a physical address corresponding to the dummy memory cell.