KR20230108676A - Memory Device and Method of Operation thereof - Google Patents

Abstract

The present disclosure relates to a memory cell array including a plurality of memory cell rows, a monitoring cell array configured to generate bit data by determining a victim memory cell row among the plurality of memory cell rows, and a victim memory cell by receiving the bit data. A memory device including a bit data decoder configured to generate a victim memory address including address information of a row, and a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address do.

Description

Memory device and method of operation thereof

The present disclosure relates to a memory device and an operating method thereof, and more particularly, to a memory device configured to perform a row hammering refresh operation and an operating method thereof.

Semiconductor memory consists of volatile memory devices, such as SRAM and DRAM, in which stored data is lost when power supply is cut off, and non-volatile memory devices, such as flash memory devices, PRAM, MRAM, RRAM, and FRAM, which retain stored data even when power supply is cut off. It is classified as a volatile memory device.

A volatile memory device such as a dynamic random access memory (DRAM) determines data based on charges stored in a capacitor. However, since the charge stored in the capacitor may leak in various forms over time, the volatile memory device periodically performs a refresh operation. As the manufacturing process for manufacturing memory devices is scaled-down and the distance between word lines gradually narrows, the influence of the voltage distribution of one word line on the charge of a memory cell connected to an adjacent word line increases. When one word line is intensively accessed, a row hammer phenomenon occurs in which data stored in memory cells connected to adjacent word lines is lost due to an activation voltage of one word line.

An object to be solved by the present disclosure is to provide a memory device that performs a row hammering operation with improved electrical characteristics.

An object to be solved by the present disclosure is to provide a method of operating a memory device performing a row hammering operation with improved electrical characteristics.

An embodiment of the present disclosure for solving the above problems is a memory cell array including a plurality of memory cell rows, and a monitoring cell configured to generate bit data by determining a victim memory cell row among the plurality of memory cell rows. an array, a bit data decoder configured to receive the bit data and generate a victim memory address including address information of the victim memory cell row, and perform a refresh operation on the victim memory cell row based on the victim memory address and a memory device including a refresh manager configured to

One embodiment of the present disclosure for solving the above problems is a method of operating a memory device including memory cell rows by precharging capacitors of monitoring cells that share a word line with the memory cell rows to setting an applied voltage as an initial voltage, generating bit data by comparing the voltage applied to the capacitors of the monitoring cells with a threshold voltage, and generating a victim memory address based on the bit data; and performing a refresh operation on victim memory cell rows corresponding to the victim memory address.

One embodiment of the present disclosure for solving the above problems is a memory device including a plurality of memory cell rows and a memory controller configured to access data of the memory cell rows by providing a command/address signal to the memory device. wherein the command/address signal includes a refresh command and a row address, and the memory device includes a control logic configured to receive the refresh command and generate a refresh enable signal, the plurality of memory cell rows a memory cell array configured to generate bit data by determining a victim memory cell row among the plurality of memory cell rows, and a victim memory address receiving the bit data and including address information of the victim memory cell row A bit data decoder configured to generate a bit data decoder and a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address, wherein the refresh manager receives the refresh enable signal The refresh operation is performed, and the refresh enable signal is periodically generated in a memory system.

An embodiment of the present disclosure provides a memory device that performs a row hammering operation with improved electrical characteristics in a row hammering refresh operation for preventing row hammering.

An embodiment of the present disclosure provides a method of operating a memory device having improved electrical characteristics in a row hammering refresh operation to prevent row hammering.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
2 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.
FIG. 3 is a diagram showing an example of a memory cell array in the memory device of FIG. 2 .
FIG. 4 is a diagram illustrating the first sub-array, the first sub-memory cell array, and the first sub-bit data decoder of FIG. 3 .
FIG. 5 is a flowchart illustrating an operation of each monitoring cell determining a victim memory cell row in FIG. 4 .
FIG. 6 is a diagram for explaining an operation of determining a victim memory cell row in a second monitoring cell according to the flowchart of FIG. 5 .
FIG. 7 is a diagram showing an example of a memory cell array in the memory device of FIG. 2 .
FIG. 8 is a diagram illustrating the first sub-array, the first sub-memory cell array, and the first sub-bit data decoder of FIG. 7 .

Hereinafter, embodiments of the present disclosure will be described clearly and in detail to the extent that those skilled in the art can easily practice the present disclosure.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a memory system 10 according to the present disclosure may include a memory device 100 and a memory controller 200 .

The memory controller 200 may provide various signals to the memory device 100 through a memory interface to control memory operations such as writing and reading. For example, the memory controller 200 may access data DATA of the memory cell array 130 by providing a command/address CA to the memory device 100 .

The command/address CA may include a command. For example, the command may include an active command for a normal memory operation, such as writing and reading data, a precharge command, and a refresh command for a refresh operation.

The active command may refer to a command for converting the state of the memory cell array 130 into an active state in order to write data to or read data from the memory cell array 130 . there is. Memory cells included in the memory cell array 130 may be driven based on the active command. In this specification, access may mean driving a memory cell row included in the memory cell array 130 according to an active command and an address of the memory controller 200 .

In one embodiment, the precharge command, as described below, may mean a command for applying an initial voltage to capacitors of monitoring cells before a refresh operation is performed. However, it is not limited thereto, and the precharge command may mean a command for converting the state of the memory cell array 130 from an active state to a standby state after data writing or reading is completed.

The refresh command may refer to a command for performing a refresh operation on the memory cell array 130 . The refresh operation may include a row hammering refresh operation and a normal refresh operation.

The memory controller 200 may access the memory device 100 according to a request from an external host of the memory system 10 . The memory controller 200 may be configured to communicate with a host using various protocols.

The memory device 100 may be a storage device based on a semiconductor device. For example, the memory device 100 may include dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), double date rate SDRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, and phase-change PRAM (PRAM). RAM), a random access memory (RAM) device such as magnetic RAM (MRAM), resistive RAM (RRAM), and the like.

The memory device 100 may include any memory device requiring a refresh operation. For example, when a resistive memory device as a non-volatile memory performs a refresh operation, the memory device 100 may be a non-volatile memory device.

The memory device 100 may receive or output data DATA through data lines or perform a refresh operation in response to a command/address CA received from the memory controller 200 . The memory device 100 may include a refresh manager 110 , a monitoring cell array 120 , and a memory cell array 130 .

The refresh manager 110 may be configured to perform a refresh operation of the memory cell array 130 based on a refresh command among commands/addresses (CA) of the memory controller 200 . The refresh manager 110 may perform one of a row hammering refresh operation and a normal refresh operation in response to a refresh command of the memory controller 200 .

In this specification, a row hammering refresh operation may refer to an operation of mitigating a row hammer phenomenon by refreshing a victim memory cell row among memory cell rows of a memory cell array based on a victim memory address. In this specification, a normal refresh operation may refer to an operation of sequentially refreshing memory cell rows of a memory cell array.

The refresh manager 110 may perform a row hammering refresh operation when the victim memory address is received. When the refresh manager 110 performs a row hammering refresh operation, the refresh manager 110 may refresh the victim memory cell row based on the victim memory address.

The refresh manager 110 may be configured to perform a normal refresh operation when a victim memory address is not received. When the refresh manager 110 performs a normal refresh operation, the refresh manager 110 may sequentially refresh a plurality of memory cell rows of the memory cell array 130 .

In this specification, a memory cell row to which access is concentrated is referred to as an attack memory cell row, and a memory cell row adjacent to the attack memory cell row to become a victim is referred to as a victim memory cell row. Non-victim memory cell rows are referred to herein as normal memory cell rows.

1 shows an embodiment in which the refresh manager 110 performs a row hammering refresh operation and a normal refresh operation in response to a refresh command of the memory controller 200, but this is an exemplary embodiment, and the memory device (100) can also be applied to the case of self-refresh that periodically performs internal refresh.

The monitoring cell array 120 may monitor memory cell rows to detect whether they are victim memory cell rows. The monitoring cell array 120 may generate bit data by detecting a victim memory cell row among memory cell rows.

The monitoring cell array 120 may include a plurality of monitoring cells, and the plurality of monitoring cells may be connected to a plurality of memory cell rows one-to-one. Each monitoring cell may generate bit data.

In one embodiment, the memory device 100 may further include a bit data decoder, and a plurality of bit data generated by a plurality of monitoring cells of the monitoring cell array 120 may be output to the bit data decoder. The bit data decoder may be configured to generate and output a victim memory address based on the bit data received from the monitoring cell array 120 . The victim memory address may include address information of a memory cell row corresponding to a victim memory cell row among memory cell rows. The victim memory address output from the bit data decoder may be received by the refresh manager 110 .

The memory cell array 130 may include a plurality of memory cell rows. Each of the memory cell rows may include a plurality of memory cells. Each of the plurality of memory cells may be located at a point where a plurality of word lines and a plurality of bit lines intersect. A plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. Each of the plurality of memory cells may be provided in a matrix form.

In this specification, a memory cell row may refer to memory cells included in one row among a plurality of memory cells. A plurality of word lines may be respectively connected to a plurality of memory cell rows of the memory cell array 130 .

2 is a block diagram illustrating a memory device 100 according to an exemplary embodiment of the present disclosure. Hereinafter, overlapping content with FIG. 1 will be omitted.

Referring to FIG. 2 , the memory device 100 includes a refresh manager 110, a refresh latch 111, a precharge bit line decoder 112, a monitoring cell array 120, and a bit data decoder 121 memory cells. It may include an array 130 , a control logic 140 , an address buffer 150 , a row decoder 151 , a column decoder 152 , and an input/output circuit 160 .

The memory device 100 includes a dynamic random access memory such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), and the like. It may be access memory (DRAM).

The control logic 140 may control overall operations of the memory device 100 . The control logic 140 may include a command decoder 141 and a mode register 143 . The control logic 140 may generate control signals to perform a normal memory operation such as a write operation or a read operation and a refresh operation according to a command/address CA from the memory controller ( FIG. 1 200 ).

The control logic 140 may generate control signals for a refresh operation on the memory cell array 130 according to a refresh command from the memory controller ( 200 of FIG. 1 ). Also, the control logic 140 may generate control signals for a refresh operation of the memory cell array 130 in the self-refresh mode.

The command decoder 141 may be configured to generate control signals based on a command among command/address CAs. In an embodiment, the command decoder 141 may be configured to output the refresh enable signal EN_REF to the refresh manager 110 based on a refresh command among commands/addresses CA. In one example, when the command is a refresh command, the command decoder 141 may output a refresh enable signal EN_REF to the refresh manager 110 .

In one embodiment, the command decoder 141 is configured to output signals for accessing memory cell rows to the refresh manager 110 based on an active command or an access command among command/address CAs. can In one example, when the command is an active command, the command decoder 141 may output an access signal to the refresh manager 110 .

The mode register 143 may include a plurality of registers that store information for setting an operating environment of the memory device 100 .

The control logic 140 may be configured to generate a refresh enable signal EN_REF for performing a row hammering refresh operation. The refresh enable signal EN_REF generated by the control logic 140 may be output to the refresh manager 110 . The refresh enable signal EN_REF may be generated periodically, and based on the periodically generated refresh enable signal EN_REF, the refresh manager 110 performs a row hammering refresh operation or a normal refresh operation. can do.

The refresh manager 110 may receive the refresh enable signal EN_REF from the control logic 140 . When the refresh enable signal EN_REF is received, the refresh manager 110 may generate a refresh address REF_ADDR for selecting a memory cell row to be refreshed in the memory cell array 130 . . When the refresh enable signal EN_REF is received, the refresh manager 110 may generate a precharge signal PCH_REF and output it to the precharge bit line decoder 112 .

As will be described later, the refresh latch 111 may receive and store the victim memory address VT_ADDR generated by the bit data decoder 121 . In one embodiment, when the victim memory address VT_ADDR is stored in the refresh latch 111, the refresh latch 111 may output the stored victim memory address VT_ADDR to the refresh manager 110. In one embodiment, when the victim memory address VT_ADDR is not stored in the refresh latch 111, the refresh latch 111 may not output the victim memory address VT_ADDR to the refresh manager 110. .

The refresh manager 110 may receive the victim memory address VT_ADDR from the refresh latch 111 . When the victim memory address VT_ADDR is received from the refresh latch 111, the refresh manager 110 may perform a row hammering refresh operation. When the victim memory address VT_ADDR is not received from the refresh latch 111, the refresh manager 110 may perform a normal refresh operation.

In one example, the refresh manager 110 may perform a row hammering refresh operation according to the received refresh enable signal EN_REF. The row hammering refresh operation may be performed when the refresh manager 110 receives the victim memory address VT_ADDR. When the row hammering refresh operation is performed, the refresh address REF_ADDR output from the refresh manager 110 may include the victim memory address VT_ADDR.

In another example, the refresh manager 110 may perform a normal refresh operation according to the received refresh enable signal EN_REF. A normal refresh operation may be performed when the refresh manager 110 does not receive the victim memory address VT_ADDR. When a normal refresh operation is performed, the refresh manager 110 may sequentially generate refresh addresses REF_ADDR whose value increases according to the counting operation of the counter CNT included therein.

The precharge bit line decoder 112 may be configured to receive the precharge signal PCH_REF from the refresh manager 110 . The precharge bit line decoder 112 may apply an activation voltage to the precharge bit line of the monitoring cell array 120 .

In the embodiment of FIG. 2 , it has been described that the refresh address REF_ADDR indicating a row to be refreshed is generated in the memory device 100, but in another embodiment, the refresh manager 110 is a memory controller The refresh address REF_ADDR included in (FIG. 1, 200) may be directly provided from the memory controller (FIG. 1, 200).

The monitoring cell array 120 may be configured to detect a victim memory cell row among memory cell rows, generate bit data, and output the generated bit data to a bit data decoder. The monitoring cell array 120 may include a plurality of monitoring cells. The plurality of monitoring cells may correspond one-to-one to the plurality of memory cell rows of the memory cell array.

In one embodiment, the monitoring cell array 120 may be disposed adjacent to each other while sharing a plurality of word lines of the memory cell array 130 . In other words, the monitoring cells of the monitoring cell array 120 may utilize dummy memory cells outside the memory cell array 130 . Monitoring cells may share the same word line as corresponding memory cell rows.

In another embodiment, the monitoring cell array 120 may be spaced apart from the memory cell array 130 . In other words, the monitoring cells of the monitoring cell array 120 may be provided separately and spaced apart from the memory cell array 130 . The monitoring cells may share the same word line as the corresponding memory cell rows, but are not limited thereto, and may be connected to the memory cell rows through separate sub word lines.

Each of the monitoring cells may be configured to determine whether a connected memory cell row is a victim memory cell row. The monitoring cell may generate bit data by detecting the victim memory cell row. Bit data may include a high bit and a low bit. In one example, when it is determined that a row of memory cells connected to the monitoring cell is a victim, the monitoring cell may generate a high bit. In one example, if it is determined that a row of memory cells connected to the monitoring cell is not a victim, the monitoring cell may generate a row bit.

Generating a high bit herein may refer to generating a signal of 1. Generating a low bit in this specification may refer to generating a signal of 0, is not limited thereto, and may also mean not generating a signal.

The bit data decoder 121 may be configured to output the victim memory address VT_ADDR based on bit data received from the monitoring cell array 120 . The victim memory address VT_ADDR may include address information about victim memory cell rows. The bit data decoder 121 may output a victim memory address VT_ADDR including address information about memory cell rows determined to be victim memory cell rows.

In one example, when a high bit is received from a monitoring cell connected to specific memory cell rows, the bit data decoder 121 may output addresses of the corresponding memory cell rows as the victim memory address VT_ADDR. In one example, when low bits are received from monitoring cells connected to all memory cell rows, the bit data decoder 121 may not output the victim memory address VT_ADDR.

The memory cell array 130 may include a plurality of memory cell rows. Memory cells constituting each memory cell row may share the same word line. A plurality of memory cell rows may be connected one-to-one with corresponding monitoring cells. Accordingly, each monitoring cell may generate bit data by determining whether a corresponding memory cell row is a victim memory cell row.

The address buffer 150 may receive an address among command/address CAs provided from the memory controller 200 . The address received by the address buffer 150 may include a row address ROW_ADDR indicating a row of the memory cell array 130 and a column address COL_ADDR indicating a column. The row address ROW_ADDR may be provided to the row decoder 151 and the column address COL_ADDR may be provided to the column decoder 152 .

The row decoder 151 may receive the row address ROW_ADDR from the address buffer 150 . The row decoder 151 outputs one (or a plurality of) word lines among a plurality of word lines, for example, one (or a plurality of) memory cells among a plurality of memory cell rows, based on the received row address ROW_ADDR. A word line control signal PXI for selecting a cell row may be generated.

The row decoder 151 selects a word line based on the row address ROW_ADDR, applies a voltage (hereinafter referred to as an activation voltage) to turn on a memory cell row corresponding to the selected word line, and can be activated. After the selected word line is activated, access to data bits of the memory cells of the selected row may be allowed.

The row decoder 151 may deactivate the selected memory cell row by applying a voltage to turn off the selected memory cell row based on the row address ROW_ADDR. After the selected memory cell row is deactivated, other memory cell rows may be allowed to be activated.

The column decoder 152 may receive the column address COL_ADDR from the address buffer 150 . The column decoder 152 may select one bit line from among a plurality of bit lines of the memory cell array 130 based on the received column address COL_ADDR.

The column decoder 152 may further include a sense amplifier and a write driver. The sense amplifier and the write driver may be connected to the bit line to perform a read operation and a write operation.

When a write operation is performed on the memory cell array 130, the column decoder 152 applies a voltage to a write driver connected to a selected bit line based on the received column address COL_ADDR to activate the memory cell connected to the bit line. can occupy them.

When a read operation is performed on the memory cell array 130, the column decoder 152 may read data stored in the memory cells by means of a sense amplifier connected to the bit line.

The input/output circuit 160 may exchange data DATA with an external device (eg, the memory controller 200). The input/output circuit 160 may provide data DATA received from an external device to a sense amplifier and a write driver, or may provide data DATA received from a sense amplifier and a write driver to an external device.

Operations and structures of the memory cell array 130, the monitoring cell array 120, and the bit data decoder 121 according to an embodiment of the present disclosure will be described in more detail with reference to FIGS. 3 and 4 below.

FIG. 3 is a diagram showing an embodiment of a memory cell array in the memory device of FIG. 2 . 4 is a diagram illustrating the first sub-array 130-1, the first sub-memory cell array, and the first sub-bit data decoder 121-1 of FIG. 3 .

To more clearly describe the technical idea of the present disclosure, the memory cell array 130, the monitoring cell array 120, and the bit data decoder of the memory device 100 according to the present disclosure are provided with reference to FIGS. 3 and 4 121) is described. Hereinafter, for brevity of the drawings and convenience of description, components unnecessary for describing the exemplary embodiments of the present disclosure (eg, bit lines, memory cells, etc.) are omitted from the drawings. However, the scope of the present disclosure is not limited thereto. Also, in the drawings below, the number of word lines included in each sub array may be increased/decreased.

Hereinafter, the word line control signal PXI may be a signal for selecting and controlling at least one of a plurality of word lines included in the memory cell array 130 . The word line control signal PXI may be generated by the row decoder 151 or may be generated by a separate signal generator configured to generate a word line control signal based on a decoding result of the row decoder 151 .

Referring to FIG. 3 , the memory cell array 130 includes a plurality of sub arrays 130-1, 130-2, ..., 130-m and a plurality of sub word line drivers swd1, swd2, ... . , swdm).

Each of the plurality of sub arrays 130-1, 130-2, ..., 130-m may include a plurality of word lines WL11, WL12, ..., WLmn. For example, the first subarray 130-1 may include word lines WL11 to WL1n, and the second subarray 130-2 may include word lines WL21 to WL2n. , and the m-th sub-array 130-m may include word lines WLm1 to WLmn. In one embodiment, a reference symbol of WLxy may refer to a word line of a y-th row included in an x-th sub-array. That is, each of the word lines of WL11, WL21, and WLn1 may be word lines included in different sub-arrays but located in the same first row. In one embodiment, word lines located in the same row may be driven or activated at the same timing. That is, it will be understood that each of the word lines WL11, WL21, and WLn1 is referred to as a first word line WLx1 corresponding to the first row or shares the first word line WLx1 corresponding to the first row. .

The plurality of sub arrays 130-1, 130-2, ..., 130-m and the plurality of sub word line drivers swd1, swd2, ..., swdm may be alternately arranged. Each of the plurality of sub arrays 130-1, 130-2, ..., 130-m may correspond one-to-one with the plurality of sub word line drivers swd1, swd2, ..., swdm. For example, the first sub array 130-1 may be electrically connected to a corresponding first sub word line driver swd1. For example, the m-th sub-array 130-m may be electrically connected to the corresponding m-th sub-word line driver swdm.

The first sub-word line driver swd1 is connected to the word lines WL11 to WL1n of the first sub-array 130-1 and may be configured to control them in response to the word line control signal PXI. . The second sub word line driver swd2 may be connected to the word lines WL21 to WL2n of the second sub array 130-2 and control them in response to the word line control signal PXI. . The m-th sub-word line driver swdm is connected to the word lines WLm1 to WLmn of the m-th sub-array 130-m and controls them in response to the word line control signal PXI.

For example, the plurality of sub word line drivers swd1, swd2, ..., swdm may include word line driving circuits. The word line driving circuit may control word lines connected to the plurality of sub word line drivers swd1, swd2, ..., swdm in response to the word line control signal PXI.

In one embodiment, it is assumed that the third word lines WL13 to WLm3 are selected word lines. In this case, the word line driving circuits of the plurality of sub word line drivers swd1, swd2, ..., swdm supply high voltage to the third word lines WL13 to WLm3 in response to the word line control signal PXI. (HIGH) may be provided, and a low voltage (LOW) may be provided to unselected word lines excluding the third word lines.

In an embodiment, the high voltage HIGH may indicate a selected voltage provided to a selected word line, and the low voltage LOW may be a non-selected voltage provided to unselected word lines. The selection transistors of the memory cells may be turned on by the selection voltage, and the selection transistors may be turned off by the non-selection voltage.

In one embodiment, the monitoring cell array 120 may include a plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m. The plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m are directly connected to the plurality of sub-arrays 130-1, 130-2, ..., 130-m. can The plurality of sub arrays 130-1, 130-2, ..., 130-m and the plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m have the same word. lines can be shared. A plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m may share a precharge bit line. The precharge bit line may charge capacitors included in the plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m through the precharge control signal (PCH).

In one embodiment, each sub-monitoring cell array may be disposed adjacent to one side of a corresponding sub-array. In one embodiment, the monitoring cells of the monitoring cell array 120 may utilize dummy memory cells outside the memory cell array 130 .

For example, the first sub-array 130-1 and the first sub-monitoring cell array 120-1 may be disposed adjacent to each other while sharing the first to n-th word lines WL11 to WL1n. The second sub-array 130-2 and the second sub-monitoring cell array 120-2 may be disposed adjacent to each other while sharing the first to nth word lines WL21 to WL2n. The mth sub-array 130-m and the mth sub-monitoring cell array 120-m may be disposed adjacent to each other while sharing the first to nth word lines WLm1 to WLmn.

Each of the sub-monitoring cell arrays 120-1, 120-2, ..., 120-m may include a plurality of monitoring cells. Each monitoring cell may determine a victim memory cell row to generate and output bit data.

A plurality of sub-bit data decoders 121-1, 121-2, ..., 121-m are connected to a plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m can be directly connected. A plurality of sub-bit data decoders 121-1, 121-2, ..., 121-m use a plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m Bit data may be received from a plurality of constituting monitoring cells. The sub-bit data decoders 121-1, 121-2, ..., 121-m may generate and output a victim memory address VT_ADDR based on the received bit data. The sub-bit data decoders 121-1, 121-2, ..., 121-m generate a victim memory cell row based on bit data received from a monitoring cell sharing a word line with the victim memory cell row among the monitoring cells. A victim memory address VT_ADDR including address information of VT may be generated.

The first to mth sub-arrays 130-1, 130-2, ..., 130-m may have the same structure and simultaneously operate through the same word line control signal. Similarly, the first to mth sub-monitoring cell arrays 120-1, 120-2, ..., 120-m and the first to mth bit data decoders 121-1, 121-2, ... , 121-m) can also have the same structure and simultaneously perform the same operation. Hereinafter, with reference to FIG. 4, structures and operations of the first sub-array 130-1, the first sub-monitoring cell array 120-1, and the first sub-bit data decoder 121-1 are representatively described. do.

Referring to FIG. 4 , a first sub-array 130-1 and a first sub-monitoring cell array 120-1 may be disposed adjacent to each other while sharing word lines. The first sub-bit data decoder 121-1 may be connected to the first sub-monitoring cell array 120-1. The first sub-monitoring cell array 120-1 may be disposed between the first sub-array 130-1 and the first sub-bit data decoder 121-1.

The first sub-monitoring cell array 120-1 may include a plurality of monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln. The plurality of monitoring cells Mnt_cell1 , Mnt_cell2 , ... , Mnt_celln may have a one-to-one correspondence with the memory cell rows MCLR1 , MCLR2 , ... , MCLRn. For example, the first monitoring cell Mnt_cell1 may share the first memory cell row MCLR1 and the first word line WL11. For example, the second monitoring cell Mnt_cell2 may share the second word line with the second memory cell row MCLR2. For example, the nth monitoring cell Mnt_celln may share an nth word line with the nth memory cell row MCLRn.

Each of the monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln may include transistors, capacitors TC1, TC2, ..., TCn, and a bit data generator ADC. In each monitoring cell, a gate terminal of a transistor may be connected to a word line, and a first source/drain terminal of a transistor may be connected to a capacitor. A second source/drain terminal of the transistor may be connected to the precharge bit line. A connection structure of the transistors, capacitors TC1 , TC2 , ... , TCn constituting the monitoring cells Mnt_cell1 , Mnt_cell2 , ... , Mnt_celln and the precharge bit line PBL may be substantially the same as that of the memory cell.

A plurality of monitoring cells (Mnt_cell1, Mnt_cell2, ..., Mnt_celln) constituting the first sub-monitoring cell array 120-1 may share the precharge bit line (PBL). The precharge bit line PBL may be for applying voltages to the capacitors TC1, TC2, ..., TCn in an initial state, but may not be limited thereto. For example, the precharge bit line PBL may be for performing a refresh operation on a plurality of monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln in the process of performing the refresh operation. In one embodiment, the precharge bit line PBL is substantially the same as the bit line constituting the memory cell array 130 and may not be distinguished.

The bit data generator ADC may be connected to the first source/drain terminal of the transistor. The bit data generator ADC generates a high bit or a low bit based on the voltage applied to the capacitor of the monitoring cell and outputs the generated high bit or low bit to the first sub-bit data decoder 121-1.

The plurality of monitoring cells Mnt_cell1 , Mnt_cell2 , ... , Mnt_celln may be connected to a plurality of corresponding memory cell rows MCLR1 , MCLR2 , ... , MCLRn. For example, the first monitoring cell Mnt_cell1 may be connected to the first word line WL11. Accordingly, the first monitoring cell Mnt_cell1 may be connected to the first memory cell row MCLR1 and the first word line WL11. ) can be shared. For example, the second monitoring cell Mnt_cell2 may be connected to the second word line WL12. Accordingly, the second monitoring cell Mnt_cell2 may be connected to the second memory cell row MCLR2 and the second word line WL12. ) can be shared. For example, the n th monitoring cell Mnt_celln may be connected to the n th word line WL1n. Accordingly, the n th monitoring cell Mnt_celln may be connected to the n th memory cell row MCLRn and the n th word line WL1n. ) can be shared.

Each monitoring cell may determine whether a memory cell row sharing a word line is a victim memory cell row. For example, the first monitoring cell Mnt_cell1 may determine whether the first memory cell row MCLR1 is a victim memory cell row. For example, the second monitoring cell Mnt_cell2 may determine whether the second memory cell row MCLR2 is a victim memory cell row. For example, the nth monitoring cell Mnt_celln may determine whether the nth memory cell row MCLRn is a victim memory cell row.

When the monitoring cell determines that the corresponding memory cell row is a victim memory cell row, a high bit may be output from the monitoring cell. When the victim memory cell is not determined to be low by the monitoring cell, a low bit may be output from the monitoring cell.

In one embodiment, when a voltage applied to a capacitor in each monitoring cell drops below a threshold voltage, the bit data generator ADC may output a high bit. In one embodiment, when a voltage applied to a capacitor in each monitoring cell is equal to or greater than a threshold voltage, the bit data generator ADC may output a low bit. Bit data output from the bit data generators ADC of the plurality of monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln may be received by the first sub-bit data decoder 121-1.

In this specification, the initial voltage may refer to a voltage in an initial state applied to capacitors TC1, TC2, ..., TCn of memory cells or monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln by a refresh operation. . In this specification, a threshold voltage may refer to a voltage that is a reference for determining whether a monitoring cell is a victim memory cell row. In this specification, the loss voltage may refer to a reference voltage at which data is damaged in a capacitor of a memory cell.

In one embodiment, the threshold voltage may be greater than the loss voltage and less than the initial voltage. For example, the loss voltage may be 0.2 times or less of the initial voltage, and the threshold voltage may be 0.4 to 0.6 times of the initial voltage.

The first sub-bit data decoder 121-1 generates addresses (victim memory address VT_ADDR) for victim memory cell rows based on the bit data received from the monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln, can be printed out.

In one embodiment, the victim memory address VT_ADDR may include address information of a memory cell row corresponding to a monitoring cell generating a high bit. In another embodiment, when all of the plurality of monitoring cells generate low bits, the victim memory address VT_ADDR may not be output from the bit data decoder, or address information may not be included in the victim memory address VT_ADDR. When all of the plurality of monitoring cells generate low bits, the refresh manager may sequentially refresh the plurality of memory cell rows by performing a normal refresh operation.

When access is concentrated on some of the memory cell rows (hereinafter referred to as attack memory cell rows), memory cell rows disposed around the attack memory cell rows (hereinafter referred to as victim memory cell rows) The voltage applied to the capacitor may be affected. That is, data stored in victim memory cell rows may be damaged by row hammering. Hereinafter, an operation of determining a victim memory cell row by a monitoring cell according to an exemplary embodiment of the present disclosure will be described in detail with reference to FIGS. 5 and 6 .

FIG. 5 is a flowchart illustrating an operation of each monitoring cell determining a victim memory cell row in FIG. 4 . FIG. 6 is a diagram representatively illustrating an operation of determining a victim memory cell row in a second monitoring cell among monitoring cells according to the flowchart of FIG. 5 . Hereinafter, the operation of the monitoring cell will be described in detail with reference to FIGS. 1, 2 and 4.

Referring to FIGS. 1, 2, 4, 5, and 6 , in step S110, the memory device (FIG. 1, 100) monitors a plurality of monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln based on the precharge command. Capacitors TC1, TC2, ..., TCn of may be precharged. The memory device (FIG. 1, 100) may be set to an initial state by precharging the capacitors TC1, TC2, ..., TCn of the plurality of monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln. In one embodiment, the transistors of the monitoring cells are turned on by applying an activation voltage to the word lines (WL11, WL12, ..., WL1n) connected to the monitoring cells (Mnt_cell1, Mnt_cell2, ..., Mnt_celln), and the precharge bit line is turned on. The initial state may be set by applying an activation voltage to the capacitors TC1, TC2, ..., TCn through (PBL).

For example, in step S110, the monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln may be set to an initial state at time 0 t0. The memory device ( 100 in FIG. 1 ) may receive a precharge command at time zero (t0). The memory device (100 in FIG. 1 ) may precharge the capacitors TC1 , TC2 , ... , TCn of the plurality of monitoring cells Mnt_cell1 , Mnt_cell2 , ... , Mnt_celln based on the received precharge command. Accordingly, the initial voltage Vdd may be applied to the capacitor TC2 of the plurality of monitoring cells, for example, the second monitoring cell Mnt_cell2.

In step S120, the memory device 100 may receive an active command and a row address. The memory device 100 may perform read and write operations on data stored in the memory cell array 130 based on the received active command and row address.

The row decoder may generate word line control signals for the memory cell rows MCLR1 , MCLR2 , ... , MCLRn based on the received row address. When an active command is received, a voltage may be applied to word lines corresponding to row addresses to perform a read or write operation of data in memory cell rows.

When access is concentrated and repeatedly performed on word lines connected to memory cell rows, monitoring cell rows adjacent to word lines to which voltages are applied may be attacked. For example, due to row hammering of memory cell rows to which access is concentrated, capacitors in a charged state among memory cells of adjacent memory cell rows are discharged, and a voltage applied to the capacitor may drop.

Referring back to FIG. 6 , in step S120 , an access command for a first word line may be received at a first time t1 . At the first time t1, an activation voltage may be applied to the first word line based on the access command, and the voltage applied to the capacitor TC2 of the second monitoring cell Mnt_cell2 adjacent to the first word line may fall. can An access command for the first word line may be received at the second time t2 and the third time t3 . During the first to third times t1 to t3, access is concentrated on the first word line, and the voltage applied to the capacitor TC2 of the second monitoring cell Mnt_cell2 may drop below the threshold voltage.

In step S130, the monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln determine whether the voltage Vmc2 applied to the capacitors TC1, TC2, ..., TCn is equal to or greater than the threshold voltage Vth or the threshold voltage Vth. It can be judged whether or not it is below.

In step S140, each of the monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln generates a high bit when the voltage Vmc2 applied to the capacitors TC1, TC2, ..., TCn is less than or equal to the threshold voltage Vth, and the bit It can be output to the data decoder (FIG. 2, 121).

In step S141, each of the monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln generates a low bit when the voltage Vmc2 applied to the capacitors TC1, TC2, ..., TCn is greater than or equal to the threshold voltage Vth. It can be output to the data decoder (FIG. 2, 121).

In an embodiment, when the voltage Vmc2 applied to the capacitor TC2 of the second monitoring cell Mnt_cell2 is equal to or greater than the threshold voltage Vth, the bit data generator ADC of the second monitoring cell Mnt_cell2 generates a low bit can be generated and output. In an embodiment, when the voltage Vmc2 applied to the capacitor TC2 of the second monitoring cell Mnt_cell2 drops below the threshold voltage Vth, the bit data generator ADC of the second monitoring cell Mnt_cell2 can generate and output a high bit.

When a high bit is output from the bit data generator, the monitoring cell may determine a memory cell row corresponding thereto as a victim memory cell row. When a low bit is output from the bit data generator, the monitoring cell may determine the memory cell row as a normal memory cell row. The bit data decoder (FIG. 2, 121) may receive bit data output from the monitoring cell.

In operation S150 , the bit data decoder ( FIG. 2 , 121 ) may output a victim memory address VT_ADDR including address information about victim memory cell rows based on the received bit data. The victim memory address may include address information about memory cell rows corresponding to monitoring cells in which high bits are received.

For example, when a high bit is received from the second monitoring cell Mnt_cell2, the victim memory address VT_ADDR output from the first sub-bit data decoder 121-1 corresponds to the second word lines WL12, WL22, . . . , WLm2) may include address information.

The refresh latch ( 111 in FIG. 2 ) may receive and store the victim memory address VT_ADDR. The refresh latch (111 in FIG. 2) may output the stored victim memory address (VT_ADDR) to the refresh manager (110 in FIG. 2).

In one embodiment, when the victim memory address VT_ADDR is received by the refresh manager 110 of FIG. 2 , the refresh manager 110 of FIG. 2 performs a row hammering refresh operation based on the refresh command. can The row hammering refresh operation may include performing refresh on memory cell rows corresponding to the victim memory address.

For example, a refresh command may be received by the refresh manager ( 110 in FIG. 2 ) at the fourth time t4 . When address information on the second memory cell row MCLR2 is included in the victim memory address VT_ADDR, the second memory cell row MCLR2 may be refreshed at a fourth time t4. At the same time, the second monitoring cell Mnt_cell2 may also be refreshed at the fourth time t4 to set the voltage Vmc2 applied to the capacitor TC2 to the initial voltage Vdd. Thereafter, steps S110 to S150 may be performed again from the fifth time t5.

In one embodiment, when the victim memory address VT_ADDR is not stored in the refresh latch 111 of FIG. 2 , the refresh manager 110 of FIG. 2 may perform a normal refresh operation. In other words, when address information does not exist in the victim memory address VT_ADDR, the refresh manager ( 110 in FIG. 2 ) may sequentially refresh memory cell rows.

According to an exemplary embodiment of the present disclosure, a row hammering refresh operation may be performed before the victim memory cell rows are damaged to prevent loss of data stored in the victim memory cell rows.

In an embodiment of the present disclosure, since the monitoring cell array directly determines whether the row is a victim memory cell row, it is possible to perform a row hammering refresh operation rather than performing a refresh operation on all memory cell rows adjacent to an attack memory cell row. Power consumption may be reduced during the process.

In one embodiment of the present disclosure, a memory device does not require a register for storing access to memory cell rows to prevent row hammering, and thus a size occupied by the memory device may be reduced.

7 and 8 are diagrams for explaining another embodiment of a memory device of the present disclosure. FIG. 7 is a diagram showing an example of a memory cell array in the memory device of FIG. 2 . FIG. 8 is a diagram illustrating the first sub-array, the first sub-memory cell array, and the first sub-bit data decoder of FIG. 7 . Hereinafter, an embodiment of the memory device 100 of the present disclosure will be described with reference to FIGS. 1, 2, 7, and 8 . Content overlapping with FIGS. 1, 2, 3, and 4 will be omitted and differences will be described in detail.

Referring to FIG. 7 , the memory cell array 130 includes a plurality of sub arrays 130-1, 130-2, ..., 130-m and a plurality of sub word line drivers swd1, swd2, ... . , swdm).

Each of the plurality of sub arrays 130-1, 130-2, ..., 130-m may include a plurality of word lines WL11, WL12, ..., WLmn.

The plurality of sub arrays 130-1, 130-2, ..., 130-m and the plurality of sub word line drivers swd1, swd2, ..., swdm may be alternately arranged. Each of the plurality of sub arrays 130-1, 130-2, ..., 130-m may correspond one-to-one with a plurality of sub word line drivers.

In one embodiment, the monitoring cell array 120 may include a plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m. Each sub-monitoring cell array may be disposed adjacent to a corresponding sub-word line driver. For example, the first sub-monitoring cell array 120-1 may be connected to a first sub word line driver. For example, the second sub-monitoring cell array 120-2 may be connected to a second sub word line driver. For example, the mth sub-monitoring cell array 120-m may be connected to the mth sub word line driver. Each sub word line driver may be disposed between the sub monitoring cell array and the sub array.

In one embodiment, a plurality of sub arrays (130-1, 130-2, ..., 130-m) and a plurality of sub-monitoring cell arrays (120-1, 120-2, ..., 120-m) m) may share word lines. In another embodiment, the plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m may be connected to memory cell rows through separate sub word lines.

A plurality of sub-bit data decoders 121-1, 121-2, ..., 121-m are connected to a plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m can be directly connected. Each of the sub-bit data decoders 121-1, 121-2, ..., 121-m includes a plurality of sub-monitoring cell arrays 120-1, 120-2, ..., 120-m. Bit data may be received from a plurality of constituting monitoring cells. The sub-bit data decoders 121-1, 121-2, ..., 121-m may generate and output a victim memory address VT_ADDR based on the received bit data. The sub-bit data decoders 121-1, 121-2, ..., 121-m generate a victim memory cell row based on bit data received from a monitoring cell sharing a word line with the victim memory cell row among the monitoring cells. A victim memory address VT_ADDR including address information of VT may be generated.

The first to mth sub-arrays 130-1, 130-2, ..., 130-m may have the same structure and simultaneously operate through the same word line control signal. Similarly, the first to mth sub-monitoring cell arrays 120-1, 120-2, ..., 120-m and the first to mth bit data decoders have the same structure and simultaneously perform the same operation. can do. Hereinafter, the structures and operations of the first sub-array 130-1, the first sub-monitoring cell array 120-1, and the first sub-bit data decoder 121-1 are representatively described with reference to FIG. 8. do.

Referring to FIG. 8 , a first sub-bit data decoder 121-1 may be disposed between the first sub-array 130-1 and the first sub-monitoring cell array 120-1. Word lines connected to memory cell rows of the first sub-array 130-1 and monitoring cells of the first sub-monitoring cell array 120-1 are activated by the word line control signal received by the first sub-word line driver A voltage may be applied.

The first sub-monitoring cell array 120-1 may include a plurality of monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln. The plurality of monitoring cells Mnt_cell1 , Mnt_cell2 , ... , Mnt_celln may have a one-to-one correspondence with the memory cell rows MCLR1 , MCLR2 , ... , MCLRn.

A plurality of monitoring cells (Mnt_cell1, Mnt_cell2, ..., Mnt_celln) constituting the first sub-monitoring cell array 120-1 may share the precharge bit line (PBL). The precharge bit line PBL may be for applying a capacitor voltage in an initial state, but may not be limited thereto. For example, it may be for performing a refresh operation on a plurality of monitoring cells in the process of performing a refresh operation.

Each monitoring cell may determine whether a memory cell row sharing a word line is a victim memory cell row. For example, the first monitoring cell Mnt_cell1 may determine whether the first memory cell row MCLR1 is a victim memory cell row. For example, the second monitoring cell Mnt_cell2 may determine whether the second memory cell row MCLR2 is a victim memory cell row. For example, the nth monitoring cell Mnt_celln may determine whether the nth memory cell row MCLRn is a victim memory cell row.

When the monitoring cell determines that the corresponding memory cell row is a victim memory cell row, a high bit may be output from the monitoring cell. When the victim memory cell is not determined to be low by the monitoring cell, a low bit may be output from the monitoring cell.

The first sub-bit data decoder 121-1 may be disposed adjacent to the first sub-monitoring cell array 120-1. The first sub-monitoring cell array 120-1 may be disposed between the first sub-word line driver and the first sub-bit data decoder 121-1.

The first sub-bit data decoder 121-1 generates addresses (victim memory address VT_ADDR) for victim memory cell rows based on the bit data received from the monitoring cells Mnt_cell1, Mnt_cell2, ..., Mnt_celln, can be printed out.

The foregoing are specific embodiments for carrying out the present disclosure. The present disclosure will include not only the above-described embodiments, but also embodiments that can be simply or easily changed in design. In addition, the present disclosure will also include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments and should be defined by not only the claims to be described later but also those equivalent to the claims of the present invention.

100: memory device,
200: memory controller
110: Refresh manager
120: monitoring cell array
130: memory cell array

Claims (10)

a memory cell array including a plurality of memory cell rows;
a monitoring cell array configured to generate bit data by determining a victim memory cell row among the plurality of memory cell rows;
a bit data decoder configured to receive the bit data and generate a victim memory address including address information of the victim memory cell row; and
and a refresh manager configured to perform a refresh operation on the victim memory cell row based on the victim memory address. According to claim 1,
the monitoring cell array includes a plurality of monitoring cells corresponding to the plurality of memory cell rows in a one-to-one correspondence;
Each of the plurality of monitoring cells shares a corresponding monitoring cell row and word line;
wherein each of the plurality of monitoring cells detects whether the monitoring cell row sharing the word line is a victim memory cell row to generate the bit data. According to claim 2,
the monitoring cell comprises a bit data generator configured to generate the bit data;
The bit data generator is configured to generate a first bit when it is determined that the memory cell row sharing the word line with the monitoring cell is a victim memory cell row, and to generate a second bit when it is determined that the memory cell row is normal;
The victim memory address includes address information of the victim memory cell row corresponding to the monitoring cell generating the first bit. According to claim 3,
The refresh manager is configured to sequentially refresh the plurality of memory cell rows when all of the plurality of monitoring cells generate the second bit. According to claim 4,
The refresh manager further includes a counter,
The refresh manager is configured to generate a refresh address whose value increases according to a counting operation of the counter. According to claim 2,
Each of the monitoring cells includes a transistor, a capacitor, a precharge bit line and a bit data generator;
A gate terminal of the transistor is connected to the word line,
A first source/drain terminal of the transistor is connected to a capacitor,
A second source/drain terminal of the transistor is connected to a precharge bit line;
The bit data generator is connected to the first source/drain terminal of the transistor. According to claim 6,
The bit data generator measures a voltage applied to the capacitor, generates a second bit when the voltage is greater than a threshold voltage, and generates a first bit when the voltage drops below the threshold voltage,
The victim memory address includes address information of the victim memory cell row corresponding to the monitoring cell generating the first bit. According to claim 7,
The refresh manager is configured to sequentially refresh the plurality of memory cell rows when all of the plurality of monitoring cells generate the second bit. According to claim 1,
The memory cell array and the monitoring cell array are disposed adjacent to each other,
The memory cell array and the monitoring cell array share a plurality of word lines. A method of operating a memory device including a plurality of memory cell rows,
precharging capacitors of a plurality of monitoring cells sharing a word line with the plurality of memory cell rows to set a voltage applied to the capacitors as an initial voltage;
generating bit data by comparing the voltage applied to the capacitors of the plurality of monitoring cells with a threshold voltage;
generating a victim memory address based on the bit data; and
and performing a refresh operation on a victim memory cell row corresponding to the victim memory address.

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