CN117636923A

CN117636923A - Charge pump

Info

Publication number: CN117636923A
Application number: CN202311368556.1A
Authority: CN
Inventors: 杨光军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2023-10-20
Filing date: 2023-10-20
Publication date: 2024-03-01

Abstract

The invention discloses a charge pump, a charge pump unit includes: positive and negative input terminals, positive and negative output terminals, two capacitors and two voltage transmission units. The first polar plates of the first capacitor and the second capacitor are respectively connected with the first clock signal and the second clock signal, the second polar plates of the first capacitor are respectively connected with the two voltage transmission units through the first switch and the second switch, and the second polar plates of the second capacitor are respectively connected with the two voltage transmission units through the third switch and the fourth switch. The control terminals of the first and third switches are both connected to the first enable signal. The control terminals of the second and fourth switches are both connected to the second enable signal. By controlling the first and second enable signals, each charge pump unit has two operating states capable of time-sharing multiplexing. In a first working state, the positive input end charges the capacitor and boosts the positive output end; in the second operating state, the negative input terminal charges the capacitor and steps down the negative output terminal. The invention can realize time-sharing multiplexing and simultaneously output positive pressure and negative pressure, thereby realizing charge pump sharing.

Description

Charge pump

Technical Field

The present invention relates to a semiconductor integrated circuit, and more particularly, to a Charge Pump (CP).

Background

When a memory cell (cell) of the NORD flash memory (flash) is in an erase operation, a method of applying positive and negative voltages together is adopted, positive high voltage is applied to a Word Line (WL), and negative high voltage is applied to a control gate line (CG).

FIG. 1 is a schematic diagram of a memory cell of a conventional flash memory; the memory cell 101 employs a split gate floating gate device. The split gate floating gate device includes: a first source drain region and a second source drain region, a plurality of separate first gate structures having floating gates 104 located between the first source drain region and the second source drain region, a second gate structure 103 located between the first gate structures; the first gate structure has the control gate 105 located on top of the floating gate 104; each of the floating gates 104 is for storing a charge and corresponds to the stored bit. The split gate floating gate 104 device is a dual split gate floating gate 104 device, with the number of first gate structures being two, and two of the first gate structures being indicated by reference numerals 102a and 102b, respectively, in fig. 3.

In the memory array, the control gates 105 of the first gate structures in the same row are connected together, and in fig. 3, a control gate line, which is a row line of a control gate to which the control gate 105 of the first gate structure 102a is connected, is denoted by CG0, and a row line of a control gate to which the control gate 105 of the first gate structure 102b is connected is denoted by CG 1.

Each of the second gate structures 103 of the same row is connected to the same word line WL.

The split gate floating gate 104 device is an N-type device, and the first source drain region and the second source drain region are both composed of n+ regions. In fig. 3, the first source and drain regions may be connected to a bit line BLa, and the second source and drain regions may be connected to a bit line BLb.

A P-doped channel region is located between the first source drain region and the second source drain region and is covered by each of the first gate structure and the second gate structure 103, and each of the first gate structure and the second gate structure 103 controls a region section of the covered channel region, respectively.

Each first gate structure is formed by overlapping a tunneling dielectric layer, the floating gate 104, a control gate dielectric layer and the control gate 105.

Each of the second gate structures 103 is formed by overlapping a word line gate medium layer and a word line gate.

When erasing the memory cell 101 shown in fig. 1, the word line WL is applied with positive high voltage (Vpos), and the control gate lines CG0 and CG1 are both connected with negative high voltage (negative voltage Vneg), so that the voltage difference between Vpos and Vneg is used to remove the stored electrons stored in the floating gate 104. Vpos can be as high as 8V or more, while Vneg is below-7V.

In order to simultaneously provide Vpos and Vneg required for erasing the memory cell 101, two separate charge pumps are required in the prior art. FIG. 2 is a schematic diagram of a conventional charge pump for providing an erase voltage to a memory cell of the conventional flash memory of FIG. 1; it can be seen that two independent charge pumps, namely, a positive voltage charge pump 202 and a negative voltage charge pump 203, are required in the whole charge pump combination 201, the positive voltage charge pump 202 is also indicated by positive charge pump in fig. 2, the negative voltage charge pump 203 is also indicated by negative charge pump, the output end of the positive voltage charge pump 202 outputs a positive voltage Vpos, and the output end of the negative voltage charge pump 203 outputs a negative voltage Vneg.

Since each independent charge pump needs to use a multi-stage charge pump unit and each charge pump unit needs to use a capacitor for boosting, a large chip area is required.

Disclosure of Invention

The invention aims to solve the technical problem of providing a charge pump which can realize time-sharing multiplexing and simultaneously output positive pressure and negative pressure so as to realize charge pump sharing.

The charge pump provided by the invention comprises n stages of charge pump units which are cascaded together, wherein n is greater than or equal to 1.

Each of the charge pump units includes: the positive input end, the negative input end, the positive output end, the negative output end, the first capacitor, the second capacitor, the first voltage transmission unit and the second voltage transmission unit.

The first voltage transmission unit is connected between the positive input terminal and the positive output terminal.

The second voltage transmission unit is connected between the negative input terminal and the negative output terminal.

The first polar plate of the first capacitor is connected with a first clock signal, the second polar plate of the first capacitor is connected with the first voltage transmission unit through a first switch, and the second polar plate of the first capacitor is connected with the second voltage transmission unit through a second switch.

The first polar plate of the second capacitor is connected with a second clock signal, the second polar plate of the second capacitor is connected to the first voltage transmission unit through a third switch, and the second polar plate of the second capacitor is connected to the second voltage transmission unit through a fourth switch.

The control end of the first switch and the control end of the third switch are both connected with a first enabling signal.

And the control end of the second switch and the control end of the fourth switch are both connected with a second enabling signal.

Each charge pump unit has two working states capable of time-sharing multiplexing.

In a first working state, the first enabling signal is enabled, the second enabling signal is disabled, the first switch and the third switch are connected, and the second switch and the fourth switch are disconnected; under the action of the first clock signal, the positive input end of the first voltage transmission unit charges the second plate of the first capacitor, and after the second plate of the first capacitor is charged and boosted, the voltage of the second plate of the second capacitor enables the second plate of the first capacitor and the positive output end to be conducted and the positive output end to be boosted; or under the action of the second clock signal, the positive input end of the first voltage transmission unit charges the second plate of the second capacitor, and after the second plate of the second capacitor is charged and boosted, the voltage of the second plate of the first capacitor enables the second plate of the second capacitor and the positive output end to be conducted and the positive output end to be boosted.

In a second working state, the first enabling signal is not enabled, the second enabling signal is enabled, the first switch and the third switch are disconnected, and the second switch and the fourth switch are connected; under the action of the first clock signal, the negative input end of the second voltage transmission unit charges the second plate of the first capacitor, and after the second plate of the first capacitor is charged and reduced in voltage, the voltage of the second plate of the second capacitor enables the second plate of the first capacitor and the negative output end to be conducted and the negative output end to be reduced in voltage; or under the action of the second clock signal, the negative input end of the second voltage transmission unit charges the second plate of the second capacitor, and after the second plate of the second capacitor is charged and reduced, the voltage of the second plate of the first capacitor enables the second plate of the second capacitor and the negative output end to be conducted and the negative output end to be reduced.

The positive input end of the charge pump unit of the 1 st stage is connected with a power supply voltage through a fifth switch; the negative input end of the charge pump unit of the 1 st stage is grounded through a sixth switch.

Positive output end of the charge pump unit of the nth stage outputs positive pressure, and negative output end of the charge pump unit of the nth stage outputs negative pressure.

In a further improvement, the charge pump further comprises a voltage detection circuit for detecting the positive voltage and outputting a first feedback signal and detecting the negative voltage and outputting a second feedback signal.

The first feedback signal is high when the positive pressure is greater than or equal to a positive reference value and low when the positive pressure is less than the positive reference value.

The second feedback signal is high when the negative pressure is less than or equal to a negative reference value and low when the negative pressure is greater than the positive reference value.

In a further improvement, each charge pump unit is continuously switched between the first working state and the second working state during time-sharing multiplexing, and the charge pump outputs the positive pressure and the negative pressure simultaneously.

Controlling the first enabling signal and the second enabling signal by using the first feedback signal and the second feedback signal and realizing time division multiplexing, including:

and controlling the first enabling signal to switch from the enabling level to the disabling level by utilizing the rising edge of the first feedback signal, and controlling the second enabling signal to switch from the disabling level to the enabling level.

And controlling the second enabling signal to switch from the enabling level to the disabling level by utilizing the rising edge of the second feedback signal, and controlling the first enabling signal to switch from the disabling level to the enabling level.

A further improvement is that at a rising edge of the first feedback signal, a switching edge of the first enable signal from an enable level to a disable level is aligned with a rising edge of the first feedback signal, and a switching edge of the second enable signal from a disable level to an enable level is later than or equal to the rising edge of the first feedback signal.

At a rising edge of the second feedback signal, a switching edge of the second enable signal from an enable level to a disable level is aligned with a rising edge of the second feedback signal, and a switching edge of the first enable signal from the disable level to the enable level is later than or equal to the rising edge of the second feedback signal.

A further improvement is that the phase before the positive pressure reaches the positive reference value for the first time and the negative pressure reaches the negative reference value for the first time is the start-up phase of the charge pump.

In the start-up phase, at the moment of starting the charge pump, the first feedback signal and the second feedback signal are both at a low level, the first enabling signal is set to an enabling level, the second enabling signal is set to a non-enabling level, and the positive pressure continuously rises until the first feedback signal is switched to a high level; the rising edge of the first feedback signal causes the first enabling signal to be switched to a non-enabling level and the second enabling signal to be switched to an enabling level, and the negative pressure is continuously reduced until the second feedback signal is switched to a high level.

Or in the start-up phase, at the moment of starting the charge pump, the first feedback signal and the second feedback signal are both at a low level, the first enabling signal is set to a non-enabling level, and the second enabling signal is set to an enabling level, and the negative pressure is continuously reduced until the second feedback signal is switched to a high level; the positive pressure continuously rises until the first feedback signal is switched to a high level.

A further improvement is that at the rising edge of the first feedback signal after the charge pump start-up phase, the falling edge of the second feedback signal is also used to control the switching of the second enable signal from the non-enable level to the enable level at the same time, and the switching edge of the second enable signal from the non-enable level to the enable level is aligned with the falling edge of the second feedback signal.

After the charge pump start-up phase, at a rising edge of the second feedback signal, the first enable signal is also controlled to switch from a disable level to an enable level with a falling edge of the first feedback signal, and a switching edge of the first enable signal from the disable level to the enable level is aligned with the falling edge of the first feedback signal.

The first voltage transmission unit comprises a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube.

The drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are connected together and serve as the positive input end.

The grid electrode of the first NMOS tube, the source electrode of the second NMOS tube, the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube are all connected with the second polar plate of the first capacitor through the first switch.

The source electrode of the first NMOS tube, the grid electrode of the second NMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube are all connected with the second polar plate of the second capacitor through the third switch.

The source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected together and serve as the positive output end.

In a further improvement, the second voltage transmission unit comprises a third NMOS tube and a fourth NMOS tube.

And the source electrode of the third NMOS tube is used as the negative input end and is connected with the second polar plate of the first capacitor through the second switch.

And the grid electrode and the drain electrode of the third NMOS tube are connected with the source electrode of the fourth NMOS tube and are connected with the second polar plate of the second capacitor through the fourth switch.

And the grid electrode and the drain electrode of the fourth NMOS tube are connected together and serve as the negative output end.

In a further improvement, the enabling level of the first enabling signal is high level and the disabling level is low level, and the enabling level of the second enabling signal is high level and the disabling level is low level.

In a further improvement, each of the charge pump units further includes: a first inverter and a second inverter.

The first clock signal is output to the first polar plate of the first capacitor after being inverted by the first inverter.

The second clock signal is output to the first polar plate of the second capacitor after being inverted by the second inverter.

The further improvement is that the first NMOS tube and the second NMOS tube are both native NMOS tubes.

In a further improvement, the first switch, the second switch, the third switch and the fourth switch all adopt NMOS tubes.

A further improvement is that the first clock signal and the second clock signal are mutually inverted signals.

A further improvement is that the first capacitance and the second capacitance are equal in magnitude.

The charge pump unit is simultaneously provided with two independent voltage transmission units, and the two shared capacitors can be adopted to respectively boost and transmit the voltage for the two voltage transmission units by adding 4 switches, so that time-sharing multiplexing can be realized, positive voltage and negative voltage can be output simultaneously, charge pump sharing is realized, and finally the chip area can be reduced.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a schematic diagram of a memory cell of a conventional flash memory;

FIG. 2 is a schematic diagram of a conventional charge pump for providing an erase voltage to a memory cell of the conventional flash memory of FIG. 1;

FIG. 3 is a schematic diagram of a charge pump according to an embodiment of the present invention;

fig. 4 is a circuit diagram of the charge pump unit in fig. 3;

FIG. 5A is a block diagram of a voltage detection circuit in a charge pump according to an embodiment of the present invention;

FIG. 5B is a circuit diagram of a positive voltage detection circuit of the voltage detection circuit of FIG. 5A;

fig. 6 is a graph of an enable signal and a feedback signal of a charge pump according to an embodiment of the present invention.

Detailed Description

FIG. 3 is a schematic diagram of a charge pump according to an embodiment of the present invention; fig. 4 is a circuit diagram of the charge pump unit 301 in fig. 3; the charge pump of the embodiment of the invention comprises n stages of charge pump units 301 which are cascaded together, wherein n is greater than or equal to 1.

Each of the charge pump units 301 includes: positive input terminal vin+, negative input terminal Vin-, positive output terminal vout+, negative output terminal Vout-, first capacitor C101, second capacitor C102, first voltage transmission unit 302, and second voltage transmission unit 303.

The first voltage transmission unit 302 is connected between the positive input terminal vin+ and the positive output terminal vout+.

The second voltage transfer unit 303 is connected between the negative input terminal Vin-and the negative output terminal Vout-.

The first plate of the first capacitor C101 is connected to the first clock signal CLK1, the second plate of the first capacitor C101 is connected to the first voltage transmission unit 302 through the first switch K103, and the second plate of the first capacitor C101 is connected to the second voltage transmission unit 303 through the second switch K104.

The first plate of the second capacitor C102 is connected to the second clock signal CLK2, the second plate of the second capacitor C102 is connected to the first voltage transmission unit 302 through the third switch K105, and the second plate of the second capacitor C102 is connected to the second voltage transmission unit 303 through the fourth switch K106.

The control terminal of the first switch K103 and the control terminal of the third switch K105 are both connected to a first enable signal p_en.

The control terminal of the second switch K104 and the control terminal of the fourth switch K106 are both connected to a second enable signal n_en.

Each of the charge pump units 301 has two operating states capable of time-division multiplexing.

In the first working state, the first enabling signal p_en is enabled, the second enabling signal n_en is disabled, the first switch K103 and the third switch K105 are turned on, and the second switch K104 and the fourth switch K106 are turned off; under the action of the first clock signal CLK1, the positive input terminal vin+ of the first voltage transmission unit 302 charges the second plate of the first capacitor C101, and after the second plate of the first capacitor C101 is charged and boosted, the voltage of the second plate of the second capacitor C102 makes the second plate of the first capacitor C101 and the positive output terminal vout+ conduct and realizes the boosting of the positive output terminal vout+; or, under the action of the second clock signal CLK2, the positive input terminal vin+ of the first voltage transmission unit 302 charges the second plate of the second capacitor C102, and after the second plate of the second capacitor C102 is charged and boosted, the voltage of the second plate of the first capacitor C101 makes the second plate of the second capacitor C102 and the positive output terminal vout+ conduct and realizes the boosting of the positive output terminal vout+.

In the second working state, the first enabling signal p_en is not enabled, the second enabling signal n_en is enabled, the first switch K103 and the third switch K105 are disconnected, and the second switch K104 and the fourth switch K106 are connected; under the action of the first clock signal CLK1, the negative input terminal Vin-of the second voltage transmission unit 303 charges the second plate of the first capacitor C101, and after the second plate of the first capacitor C101 is charged and reduced, the voltage of the second plate of the second capacitor C102 makes the second plate of the first capacitor C101 and the negative output terminal Vout-conduct and realizes the reduction of the negative output terminal Vout; or, under the action of the second clock signal CLK2, the negative input terminal Vin-of the second voltage transmission unit 303 charges the second plate of the second capacitor C102, and after the second plate of the second capacitor C102 is charged and stepped down, the voltage of the second plate of the first capacitor C101 makes the second plate of the second capacitor C102 and the negative output terminal Vout-conduct and realizes the step-down of the negative output terminal Vout.

In the embodiment of the present invention, as shown in fig. 3, the positive input terminal vin+ of the charge pump unit 301 in the 1 st stage is connected to the power supply voltage Vdd through the fifth switch K101; the negative input Vin-of the charge pump unit 301 of stage 1 is grounded through the sixth switch K102.

The positive output terminal vout+ of the charge pump unit 301 at the nth stage outputs a positive voltage Vpos, and the negative output terminal Vout-of the charge pump unit 301 at the nth stage outputs a negative voltage Vneg.

As shown in fig. 5A, a block diagram of a voltage detection circuit 305 in a charge pump according to an embodiment of the present invention; the charge pump further comprises a voltage detection circuit 305, the voltage detection circuit 305 being configured to detect the positive voltage Vpos and output a first feedback signal p_rdy and to detect the negative voltage Vneg and output a second feedback signal n_rdy.

The first feedback signal p_rdy is high when the positive pressure Vpos is equal to or greater than a positive reference value and low when the positive pressure Vpos is less than the positive reference value.

The second feedback signal n_rdy is high when the negative pressure Vneg is less than or equal to a negative reference value and is low when the negative pressure Vneg is greater than the positive reference value.

As shown in fig. 5B, a circuit diagram of the positive voltage Vpos detection circuit of the voltage detection circuit 305 in fig. 5A; the resistor string formed by the resistors R101 and R102 divides the positive voltage Vpos and compares the positive voltage Vpos with the reference voltage Vref, the reference voltage Vref and the positive reference value are proportional, the divided voltage being larger than the reference voltage Vref indicates that the positive voltage Vpos is larger than the positive reference value, at this time, the first feedback signal P_rdy is at a high level, and conversely, the first feedback signal P_rdy is at a low level.

At the time of time-sharing multiplexing, each of the charge pump units 301 is continuously switched between the first operation state and the second operation state, and the charge pump outputs the positive voltage Vpos and the negative voltage Vneg at the same time.

As shown in fig. 6, which is a graph of an enable signal and a feedback signal of a charge pump according to an embodiment of the present invention, the first enable signal p_en and the second enable signal n_en are controlled and time-division multiplexed by using the first feedback signal p_rdy and the second feedback signal n_rdy, including:

the rising edge of the first feedback signal p_rdy is used to control the first enable signal p_en to switch from an enable level to a disable level and the second enable signal n_en to switch from the disable level to the enable level. The first rising edge of the first feedback signal p_rdy and the switching edge of the first enable signal p_en and the switching edge of the second enable signal n_en shown in fig. 6 are marked with arrow lines.

In the embodiment of the present invention, the enabling level of the first enabling signal p_en is a high level and the disabling level is a low level, and the enabling level of the second enabling signal n_en is a high level and the disabling level is a low level. The first switch K103, the second switch K104, the third switch K105 and the fourth switch K106 all adopt NMOS tubes. In other embodiments can also be: the first switch K103, the second switch K104, the third switch K105 and the fourth switch K106 are PMOS transistors, and at this time, the enabling level of the first enabling signal p_en is a low level and the disabling level is a high level, and the enabling level of the second enabling signal n_en is a low level and the disabling level is a high level.

And controlling the second enable signal N_EN to switch from an enable level to a disable level by using the rising edge of the second feedback signal N_rdy and controlling the first enable signal P_EN to switch from the disable level to the enable level. The first rising edge of the second feedback signal n_rdy and the switching edge of the first enable signal p_en and the switching of the second enable signal n_en shown in fig. 6 are marked with arrow lines.

In the embodiment of the present invention, at the rising edge of the first feedback signal p_rdy, the switching edge of the first enable signal p_en from the enable level to the disable level is aligned with the rising edge of the first feedback signal p_rdy, and the switching edge of the second enable signal n_en from the disable level to the enable level is later than or equal to the rising edge of the first feedback signal p_rdy. For example, in fig. 6, the rising edge corresponding to the T2 period of the second enable signal n_en is equal to the rising edge of the corresponding first feedback signal p_rdy.

At a rising edge of the second feedback signal n_rdy, a switching edge of the second enable signal n_en, which is switched from an enable level to a disable level, is aligned with a rising edge of the second feedback signal n_rdy, and a switching edge of the first enable signal p_en, which is switched from a disable level to an enable level, is later than or equal to the rising edge of the second feedback signal n_rdy. For example, in fig. 6, the rising edge corresponding to the T3 period of the first enable signal p_en is equal to the rising edge of the corresponding second feedback signal n_rdy.

In the embodiment of the present invention, the phase before the positive voltage Vpos reaches the positive reference value for the first time and the negative voltage Vneg reaches the negative reference value for the first time is the start-up phase of the charge pump, that is, the start-up phase corresponds to a period before the falling edge of the T2 period of the second enable signal n_en in fig. 6.

In the start-up phase, at the moment of starting the charge pump, the first feedback signal p_rdy and the second feedback signal n_rdy are both at a low level, the first enable signal p_en is set to an enable level and the second enable signal n_en is set to a disable level, and the positive voltage Vpos continuously rises until the first feedback signal p_rdy is switched to a high level; the rising edge of the first feedback signal p_rdy switches the first enable signal p_en to a disable level and the second enable signal n_en to an enable level, and the negative voltage Vneg is continuously reduced until the second feedback signal n_rdy is switched to a high level.

In other embodiments, namely: in the start-up phase, at the moment of starting the charge pump, the first feedback signal p_rdy and the second feedback signal n_rdy are both at a low level, the first enable signal p_en is set to a disable level and the second enable signal n_en is set to an enable level, and the negative pressure Vneg is continuously reduced until the second feedback signal n_rdy is switched to a high level; the positive voltage Vpos continuously rises until the first feedback signal p_rdy is switched to a high level by switching the first enable signal p_en to an enable level and switching the second enable signal n_en to a disable level.

After the charge pump start-up phase, at the rising edge of the first feedback signal p_rdy, the second enable signal n_en is also controlled to be switched from a disable level to an enable level by the falling edge of the second feedback signal n_rdy at the same time, and the switching edge of the second enable signal n_en, which is switched from the disable level to the enable level, is aligned with the falling edge of the second feedback signal n_rdy. As shown in fig. 6, after the second rising edge of the first feedback signal p_rdy occurs, the rising edge of the T3 period of the second enable signal n_en is aligned with the first falling edge of the second feedback signal n_rdy.

After the charge pump start-up phase, at the rising edge of the second feedback signal n_rdy, the first enable signal p_en is also controlled to be switched from a disable level to an enable level by the falling edge of the first feedback signal p_rdy at the same time, and the switching edge of the first enable signal p_en, which is switched from the disable level to the enable level, is aligned with the falling edge of the first feedback signal p_rdy. As shown in fig. 6, a rising edge corresponding to the T3 period of the first enable signal p_en is aligned with a first falling edge of the first feedback signal p_rdy.

By analogy with the above method, the control of the first enable signal p_en and the second enable signal n_en by the first feedback signal p_rdy and the second feedback signal n_rdy corresponding to each period of time after the charge pump start-up phase is obtained.

As shown in fig. 4, in the embodiment of the present invention, the first voltage transmission unit 302 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, and a second PMOS transistor MP2.

In some embodiments, the first NMOS transistor MN1 and the second NMOS transistor MN2 are native (active) NMOS transistors, and the threshold voltage region of the native NMOS transistors is 0V.

The drain electrode of the first NMOS transistor MN1 and the drain electrode of the second NMOS transistor MN2 are connected together and serve as the positive input terminal vin+.

The gate of the first NMOS transistor MN1, the source of the second NMOS transistor MN2, the gate of the first PMOS transistor MP1, and the drain of the second PMOS transistor MP2 are all connected to the second plate of the first capacitor C101 through the first switch K103.

The source electrode of the first NMOS transistor MN1, the gate electrode of the second NMOS transistor MN2, the drain electrode of the first PMOS transistor MP1, and the gate electrode of the second PMOS transistor MP2 are all connected to the second plate of the second capacitor C102 through the third switch K105.

The source electrode of the first PMOS tube MP1 and the source electrode of the second PMOS tube MP2 are connected together and serve as the positive output terminal vout+.

The second voltage transmission unit 303 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4.

The source electrode of the third NMOS transistor MN3 is used as the negative input end Vin-and is connected with the second polar plate of the first capacitor C101 through the second switch K104.

The gate and the drain of the third NMOS MN3 are connected to the source of the fourth NMOS MN4, and are connected to the second plate of the second capacitor C102 through the fourth switch K106.

The gate and drain of the fourth NMOS transistor MN4 are connected together and serve as the negative output terminal Vout-.

Each of the charge pump units 301 further includes: a first inverter 304a and a second inverter 304b.

The first clock signal CLK1 is inverted by the first inverter 304a and then outputted to the first plate of the first capacitor C101.

The second clock signal CLK2 is inverted by the second inverter 304b and then outputted to the first plate of the second capacitor C102.

The first clock signal CLK1 and the second clock signal CLK2 are mutually inverted signals.

The first capacitor C101 and the second capacitor C102 are equal in size.

In fig. 4, the specific working principle in the first working state is as follows:

the first clock signal CLK1 is inverted and applied to the first plate of the first capacitor C101, and the inverted second clock signal CLK2 is inverted and applied to the first plate of the second capacitor C102.

If the first polar plate of the first capacitor C101 is 0V, the starting potential of the second polar plate is also 0V; the potentials of the first polar plate and the second polar plate of the second capacitor C102 are Vdd; in this way, the NMOS transistor MN2 is turned on, the voltage at the positive input terminal vin+ charges the second plate of the first capacitor C101, and the charged voltage is also denoted by vin+. After the level of the first clock signal CLK1 is switched, the first plate of the first capacitor C101 is Vdd, and the second plate is vdd+ (vin+); the first electrode plate and the second electrode plate of the second capacitor C102 are both 0V, which makes the PMOS transistor MP2 conductive, so that vdd+ (vin+) is transferred to the positive output terminal vout+, and the voltage of the positive output terminal vout+ is increased.

In the structure of fig. 4 in the embodiment of the present invention, the structures connected by the capacitors C101 and C102, the NMOS transistors MN1 and MN2, and the PMOS transistors MP1 and MP2 are symmetrical, the capacitor C102 is also used as a boost capacitor, and the voltage of the positive output terminal vout+ is increased at the opposite phase according to the principle described above, which is only required to be described in detail herein.

In fig. 4, the specific working principle in the second working state is as follows:

also, the first clock signal CLK1 is inverted and applied to the first plate of the first capacitor C101, and the inverted second clock signal CLK2 is inverted and applied to the first plate of the second capacitor C102.

If the first plate of the first capacitor C101 is Vdd, the starting potential of the second plate is Vdd, the negative input terminal Vin-charges the second plate, so that the voltage of the second plate is continuously reduced, the reduced voltage is also denoted by Vin-, vin-is a negative value, and finally the voltage of the second plate is Vin-, and the voltage difference between the first plate and the second plate is Vdd- (Vin-). The first and second plates of the second capacitor C102 have a potential of 0V, so that the NMOS MN2 is turned off.

When the first plate of the first capacitor C101 is switched to 0V, the voltage difference between the first and second plates cannot be changed more, so that the voltage of the second plate is maintained at Vdd- (Vin-), and thus the voltage of the second plate is-Vdd+ (Vin-), and the voltage of the second plate is negative. At this time, the first and second plates of the second capacitor C102 are both at Vdd, the NMOS transistor MN2 is turned on, and after the voltage of-vdd+ (Vin-) is transferred to the source of the NMOS transistor MN3, the NMOS transistor MN3 is also turned on and transfers the negative voltage to the negative output terminal Vout-, so as to continuously reduce the voltage of the negative output terminal Vout-.

In the embodiment of the invention, two independent voltage transmission units are simultaneously arranged in the charge pump unit 301, and the two shared capacitors can be adopted to respectively boost and transmit the voltage for the two voltage transmission units by adding 4 switches, so that time-sharing multiplexing can be realized, positive voltage Vpos and negative voltage Vneg are output at the same time, charge pump sharing is realized, and finally the chip area can be reduced.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. The charge pump is characterized by comprising n stages of charge pump units which are cascaded together, wherein n is greater than or equal to 1;

each of the charge pump units includes: the positive input end, the negative input end, the positive output end and the negative output end, and the first capacitor, the second capacitor, the first voltage transmission unit and the second voltage transmission unit;

the first voltage transmission unit is connected between the positive input end and the positive output end;

the second voltage transmission unit is connected between the negative input end and the negative output end;

the first polar plate of the first capacitor is connected with a first clock signal, the second polar plate of the first capacitor is connected with the first voltage transmission unit through a first switch, and the second polar plate of the first capacitor is connected with the second voltage transmission unit through a second switch;

the first polar plate of the second capacitor is connected with a second clock signal, the second polar plate of the second capacitor is connected to the first voltage transmission unit through a third switch, and the second polar plate of the second capacitor is connected to the second voltage transmission unit through a fourth switch;

the control end of the first switch and the control end of the third switch are both connected with a first enabling signal;

the control end of the second switch and the control end of the fourth switch are both connected with a second enabling signal;

each charge pump unit has two working states capable of time-sharing multiplexing;

in a first working state, the first enabling signal is enabled, the second enabling signal is disabled, the first switch and the third switch are connected, and the second switch and the fourth switch are disconnected; under the action of the first clock signal, the positive input end of the first voltage transmission unit charges the second plate of the first capacitor, and after the second plate of the first capacitor is charged and boosted, the voltage of the second plate of the second capacitor enables the second plate of the first capacitor and the positive output end to be conducted and the positive output end to be boosted; or under the action of the second clock signal, the positive input end of the first voltage transmission unit charges the second plate of the second capacitor, and after the second plate of the second capacitor is charged and boosted, the voltage of the second plate of the first capacitor enables the second plate of the second capacitor and the positive output end to be conducted and the positive output end to be boosted;

2. The charge pump of claim 1, wherein: the positive input end of the charge pump unit of the 1 st stage is connected with a power supply voltage through a fifth switch; the negative input end of the charge pump unit of the 1 st stage is grounded through a sixth switch;

3. The charge pump of claim 2, wherein: the charge pump further comprises a voltage detection circuit, wherein the voltage detection circuit is used for detecting the positive voltage and outputting a first feedback signal and detecting the negative voltage and outputting a second feedback signal;

the first feedback signal is high when the positive pressure is greater than or equal to a positive reference value and low when the positive pressure is less than the positive reference value;

4. A charge pump as claimed in claim 3, wherein: when time-sharing multiplexing is performed, each charge pump unit is continuously switched between the first working state and the second working state, and the charge pump outputs the positive pressure and the negative pressure simultaneously;

controlling the first enable signal to switch from an enable level to a disable level by using a rising edge of the first feedback signal, and controlling the second enable signal to switch from the disable level to the enable level;

5. The charge pump of claim 4, wherein: at a rising edge of the first feedback signal, a switching edge of the first enable signal from an enable level to a disable level is aligned with a rising edge of the first feedback signal, and a switching edge of the second enable signal from the disable level to the enable level is later than or equal to the rising edge of the first feedback signal;

6. The charge pump of claim 5, wherein: the stage before the positive pressure reaches the positive reference value for the first time and the negative pressure reaches the negative reference value for the first time is the starting stage of the charge pump;

in the start-up phase, at the moment of starting the charge pump, the first feedback signal and the second feedback signal are both at a low level, the first enabling signal is set to an enabling level, the second enabling signal is set to a non-enabling level, and the positive pressure continuously rises until the first feedback signal is switched to a high level; the rising edge of the first feedback signal enables the first enabling signal to be switched to a non-enabling level and the second enabling signal to be switched to an enabling level, and the negative pressure is continuously reduced until the second feedback signal is switched to a high level;

7. The charge pump of claim 6, wherein: after the charge pump start-up phase, at a rising edge of the first feedback signal, also simultaneously controlling the switching of the second enable signal from a disable level to an enable level with a falling edge of the second feedback signal, and the switching edge of the second enable signal from the disable level to the enable level being aligned with the falling edge of the second feedback signal;

8. The charge pump of claim 1, wherein: the first voltage transmission unit comprises a first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube;

the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are connected together and serve as the positive input end;

the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube, the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube are all connected with the second polar plate of the first capacitor through the first switch;

the source electrode of the first NMOS tube, the grid electrode of the second NMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube are all connected with the second polar plate of the second capacitor through the third switch;

9. The charge pump of claim 1, wherein: the second voltage transmission unit comprises a third NMOS tube and a fourth NMOS tube;

the source electrode of the third NMOS tube is used as the negative input end and is connected with the second polar plate of the first capacitor through the second switch;

the grid electrode and the drain electrode of the third NMOS tube are connected with the source electrode of the fourth NMOS tube and are connected with the second polar plate of the second capacitor through the fourth switch;

10. The charge pump of claim 1, wherein: the enabling level of the first enabling signal is high level and the disabling level is low level, and the enabling level of the second enabling signal is high level and the disabling level is low level.

11. The charge pump of claim 1, wherein: each of the charge pump units further includes: a first inverter and a second inverter;

the first clock signal is output to a first polar plate of the first capacitor after being inverted through the first inverter;

12. The charge pump of claim 8, wherein: the first NMOS tube and the second NMOS tube are native NMOS tubes.

13. The charge pump of claim 10, wherein: the first switch, the second switch, the third switch and the fourth switch all adopt NMOS tubes.

14. The charge pump of claim 1, wherein: the first clock signal and the second clock signal are mutually inverted signals.

15. The charge pump of claim 1, wherein: the first capacitor and the second capacitor are equal in size.