CN117632411A - Interrupt processing program processing method, interrupt control method and processor - Google Patents

Abstract

The embodiment of the invention provides a processing method of an interrupt processing program, an interrupt control method and a processor, and belongs to the field of chips. The method comprises the following steps: generating a first instruction and a second instruction, wherein the first instruction is configured to indicate whether to perform a hardware auto-save interrupt context and the second instruction is configured to indicate whether to perform a hardware auto-resume interrupt context; and placing the first instruction at an entry of a specified interrupt handler and placing the second instruction at an end of the specified interrupt handler. The embodiment of the invention improves the default interrupt processing program and can separate the processing procedure of the common vector interrupt from the processing procedure of the task switching interrupt.

Description

Interrupt processing program processing method, interrupt control method and processor

Technical Field

The present invention relates to the field of chips, and in particular, to a method for processing an interrupt handler, an interrupt control method, and a processor.

Background

For current interrupt handling, such as interrupt nesting, it is often necessary to save interrupt context information in order to resume the interrupt context information when the interrupt returns. However, in the method of saving the interrupt context by software, the CPU executes a large number of instructions, and the delay in executing the effective part of the interrupt processing is large. In order to accelerate interrupt response, a method of hardware saving and restoring interrupt context is proposed in the prior art for RISC-V architecture, namely: when an interrupt occurs, the hardware automatically saves the interrupt context on the stack of the memory or on the hardware storage area, and after the interrupt processing is completed, the mret instruction is executed, so that the hardware automatically resumes the interrupt context information from the stack of the corresponding memory or the hardware storage area.

However, the inventors of the present application have found that this method of directly returning execution hardware to automatically restore interrupt context for all types of interrupts during the implementation of the present application has at least the following drawbacks:

in existing hardware save and resume interrupt context methods, interrupt return is accomplished by executing instruction mret for either type of interrupt, so that hardware automatic resumption of interrupt context from memory's stack or hardware storage area occurs. However, for a real-time operating system, for example, an interrupt is switched to its task, the interrupt return is also completed by executing an mret instruction, and during the interrupt processing process, the context of a new task is set by means of software, so that if the mret instruction is executed again at the end of the interrupt processing function to enable the hardware to automatically restore the interrupt context, the context of the new task which has been set by the operating system is covered. In this regard, a scheme of adding a hardware control bit to mask the hardware auto-recovery interrupt context is also proposed in the prior art, so that the operation of hardware auto-recovery interrupt context is not performed when the interrupt execution mret is exited. However, this approach requires not only adding hardware logic, but also modifying the task switching logic of the real-time operating system to operate the hardware control bits, making the real-time operating system no longer versatile and complex to operate.

Therefore, the embodiment of the invention provides a more concise scheme.

Disclosure of Invention

An object of an embodiment of the present invention is to provide a processing method, an interrupt control method, and a processor for an interrupt processing program, which are used for at least partially solving the above technical problems.

In order to achieve the above object, an embodiment of the present invention provides a method for processing an interrupt handler, including: generating a first instruction and a second instruction, wherein the first instruction is configured to indicate whether to perform a hardware auto-save interrupt context and the second instruction is configured to indicate whether to perform a hardware auto-resume interrupt context; and placing the first instruction at an entry of a specified interrupt handler and placing the second instruction at an end of the specified interrupt handler.

Optionally, the first instruction and the second instruction are generated by a compiler according to a preset interrupt handler attribute modifier.

Optionally, the second instruction is further configured to instruct interrupt tail biting.

Optionally, the first instruction is further configured to instruct hardware to automatically save an interrupt context to a hardware storage area or stack, and the second instruction is further configured to instruct hardware to automatically restore the interrupt context from the corresponding hardware storage area or stack.

Optionally, the first instruction is further configured to set a MIE bit in the MSTATUS register.

Optionally, the specified interrupt handler is an interrupt handler for any vector interrupt other than a task switch interrupt.

On the other hand, the embodiment of the invention also provides an interrupt control method based on RISC-V architecture, which is applied to a processor based on the RISC-V architecture and comprises the following steps: detecting a current interrupt processing program to be executed to judge whether the current interrupt processing program is the interrupt processing program modified by the processing method; if yes, when the current interrupt processing program is executed, the interrupt context is automatically saved through the first instruction execution hardware, and when the interrupt processing is finished, the interrupt context is automatically restored through the second instruction execution hardware; otherwise, when executing the current interrupt handler, skipping the hardware to automatically save the interrupt context and the hardware to automatically resume the interrupt context.

Optionally, in a case where the second instruction is further configured to instruct interrupt tail biting, the interrupt control method further includes performing the following steps for an interrupt tail biting scene of the second interrupt tail biting first interrupt: the first instruction of the interrupt processing program for controlling the first interrupt is used for completing the storage of the corresponding interrupt context; the first instruction of the interrupt handler controlling the second interrupt and the second instruction of the interrupt handler of the first interrupt are executed in a disabled manner; and controlling the second instruction of the interrupt handler of the second interrupt to complete restoration of the corresponding interrupt context.

Optionally, the interrupt control method further includes: for an interrupt handler having the first instruction and the second instruction, pre-executing a pre-boot instruction configured separately, the pre-boot instruction having the same function as the first instruction, before acquiring the first instruction at an entry of the interrupt handler; and comparing the instruction codes of the pre-starting instruction and the first instruction, if the two instruction codes are inconsistent, controlling the pre-starting instruction to fail to execute the first instruction, otherwise controlling the pre-starting instruction to take effect to skip executing the first instruction.

In another aspect, embodiments of the present invention provide a processor based on a RISC-V architecture, the processor being configured to respond to interrupts to perform any of the interrupt control methods described above.

Through the technical scheme, the default interrupt handling program is improved, on one hand, a first instruction for indicating whether to save the hardware interrupt context is added, so that the situation that the hardware automatic interrupt context is directly saved for any type of vector interrupt processing is avoided; on the other hand, a second instruction indicating whether to perform restoration of the hardware interrupt context is added to replace a conventional mret instruction to realize restoration of the hardware interrupt context.

Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:

FIG. 1 is a flow chart of a processing method of an interrupt handler according to an embodiment of the present invention;

FIGS. 2 and 3 are exemplary diagrams of interrupt handler source code and interrupt handler after compilation, respectively, in accordance with embodiments of the present invention;

FIG. 4 is a flow chart of an interrupt control method for RISC-V architecture according to an embodiment of the present invention;

FIG. 5 is a flow chart of an example interrupt tail biting process of an embodiment of the present invention;

FIG. 6 is an exemplary diagram of an exemplary interrupt tail biting handler of an embodiment of the present invention;

FIG. 7 is a flow chart of an interrupt control method of a preferred embodiment of the present invention; and

FIG. 8 is an exemplary diagram of pre-execution based on a 5-stage pipeline in accordance with an embodiment of the present invention.

Detailed Description

The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.

Before describing embodiments of the present invention in detail, some terminology is explained herein so that those skilled in the art can better understand the embodiments of the present invention.

1. CLIC (Core-Local Interrupt Controller): the interrupt controller is based on RISC-V, and can configure the attribute of each interrupt, such as the content of enabling, triggering mode, level, priority, interrupt processing mode, vector mode and the like. After the interrupt source generates the interrupt, the CLIC arbitrates the interrupt with the highest priority according to the priority of the interrupt and sends the interrupt to the processor (e.g. CPU) for response. The rules of arbitration are: interrupts with inconsistent grades are processed preferentially; interrupts of uniform class are prioritized for higher priority interrupts. In the low-level interrupt processing process, if the global interrupt enabling is started, the high-level interrupt can interrupt the low-level interrupt to form interrupt nesting. When interrupts are nested, interrupt context information needs to be saved in order to resume before the interrupt returns.

2. Interrupt context: for the RISC-V I architecture and CLIC, taking the Machine Mode (Machine Mode) interrupt handling as an example, the interrupt context contains 16 general purpose registers of the type of the impeller (denoted ra, t 0-t 6, a 0-a 7) and 2 CSR registers (denoted MEPC and MCAUSE) associated with the interrupt information.

3. The RISC-V based CPU takes Machine Mode as an example to process vector interrupt, and the response flow of vector interrupt to the default RISC-V sent by CLIC to the CPU is as follows in steps S1-S12:

s1, the processor stores the PC into a MEPC register.

S2, updating the acceptance Code domain in the MCAUSE register to the current valid interrupt number. Wherein, the highest position of the MCAUSE register is 1, which indicates that the CPU responds to the interrupt.

And S3, saving an interrupt enable bit MIE in the MSTATUS register into the MPIE.

S4, resetting an interrupt enable bit MIE in the MSTATUS register, and prohibiting response to the interrupt.

And S5, saving the privilege Mode before the interrupt occurs to the MPP domain of the MSTATUS register, and configuring the current Mode as a Machine Mode, namely, entering a Machine Mode by the CPU after the interrupt response.

S6, updating the MPIL domain of the MCAUSE register to the MIL domain of the MINTSTATUS register, and updating the MIL domain of the MINTSTATUS register to be the priority of the interrupt which is responded currently.

S7, the CPU acquires the entry address of the interrupt handler. Wherein, for vector interrupts in the CLIC, the hardware looks up a vector table with the address of the MTVT record as the base address.

S8, fetching an instruction from the inlet address of the handler and entering each stage of a subsequent instruction pipeline, and executing the first instruction of the handler.

S9, if a subfunction call exists in the handler, the compiler automatically generates an instruction for storing a caller type register at an interrupt handler entry, if the software is to realize interrupt nesting, the CSR MCAUSE and the CSR MEPC related to the interrupt need to be stored in the handler, and then global interrupt enabling is started to allow high-level interrupt to interrupt the execution of the current low-level interrupt handler to form interrupt nesting.

S10, executing effective content of the interrupt handler.

S11, closing the global interrupt enabling, and restoring the interrupt context through the software instruction.

S12, the compiler generates an mret instruction at the end of the handler, and executes the mret instruction to return the interrupt to the position when the interrupt occurs to continue program flow.

Based on steps S1-S12, it is apparent that the default vector interrupt response flow is to save the interrupt context with software, i.e., save the interrupt context to memory by software instruction through the interrupt handler entry, and resume the interrupt context at the end of the handler by software instruction by instruction. This method of saving and restoring interrupt context by software instructions involves memory read and write operations, one instruction saving a register value, the saving speed being slow, so that for an interrupt context comprising 18 registers as indicated in the above-mentioned point 2 "interrupt context", it takes 18 instructions to save and restore each of these 18 registers, and in addition the software-enabled global interrupt enabled instruction overhead. Therefore, the time in the interrupt handler to respond to the active portion of the interrupt process is late.

4. The task switching interrupt is compared with the common vector interrupt, and the context of a new task is set in a software mode in the interrupt processing process, so that the interrupt context does not need to be restored when the interrupt returns to execute mret, and otherwise, the context of the new task set by the operating system is covered. Specifically, the corresponding process comprises the steps of:

1) The task scheduler searches the ready task with the highest priority in the task follow-up table and determines the ready task as a new task to be switched;

2) Shielding global interrupt, and storing the context information of the original task into a context storage space of the original task;

3) Restoring the context content of the new task from the context storage space of the new task;

4) Taking the example that the operating system runs in the machine mode, the interrupt return instruction mret is executed to return to the breakpoint of the new task to continue execution, so as to unmask the interrupt.

It is easy to know that when executing task switching, the operating system has restored the context of the new task by means of software, and when the interrupt returns, the context content does not need to be restored from the memory stack or the hardware storage area. That is, for interrupts used when a real-time operating system task switches, it is not necessary to execute hardware to automatically save the interrupt context when an interrupt occurs, because hardware to automatically resume the interrupt context is not desirable when an interrupt returns.

In summary, the prior art implements hardware automatic save and restore of vector interrupt contexts. That is, the interrupt context is automatically saved by the hardware in response to the interrupt, and the hardware automatically resumes the interrupt context when the mret instruction interrupt return is executed. However, since the task switch interrupt is also returned by the mret instruction, the problem is that the hardware automatic resumption interrupt context triggered by the mret instruction will override the context of the new task at the task switch.

In order to overcome the defect of the prior technical scheme that the hardware realizes the saving and restoring of the interrupt context, the embodiment of the invention provides a processing method of an interrupt processing program to generate a new instruction for indicating the hardware to automatically save and restore the interrupt context.

As shown in fig. 1, the processing method of the interrupt handler according to the embodiment of the present invention may include the following steps:

step S110, generating a first instruction and a second instruction. Wherein the first instruction is configured to indicate whether a hardware auto-save interrupt context is performed and the second instruction is configured to indicate whether a hardware auto-resume interrupt context is performed.

Preferably, the first instruction and the second instruction are generated by a compiler according to a preset interrupt handler attribute modifier. The embodiment of the invention provides that the hardware automatic saving interrupt context can be determined only by executing the first instruction, otherwise, the interrupt handler without the first instruction is considered to be unnecessary to perform the hardware automatic saving interrupt context.

Step S120, the first instruction is placed at the entry of the specified interrupt handler and the second instruction is placed at the end of the specified interrupt handler.

Thus, through step S110 and step S120, the embodiment of the present invention improves the default interrupt handler, and on one hand, adds a first instruction for indicating whether to perform the hardware automatic save interrupt context, so as to avoid directly performing the hardware automatic save interrupt context for any type of vector interrupt processing; on the other hand, a second instruction indicating whether the hardware automatic restoration interrupt context is performed is added, wherein the second instruction corresponds to the first instruction, namely, the second instruction is utilized to replace a conventional mret instruction, so that the hardware automatic restoration interrupt context is realized.

In an example, referring to fig. 2 and 3, for a first instruction and a second instruction, e.g., respectively denoted as an ist rt instruction and an IEND instruction, they may be generated by a compiler according to a preset interrupt handler attribute (handler attribute) modifier and automatically placed at the entry and end of the modified interrupt handler, respectively, to identify the beginning and end of the corresponding vector interrupt handling function. FIGS. 2 and 3 are exemplary diagrams of the present example interrupt handler source code and interrupt handler assembly code after compilation, respectively, as shown by the compiler encountering an interrupt indication ("SC_PROPERTY")) to generate ISTART and IEND instructions at the beginning and end of its modified handler, while the compiler does not generate instructions that automatically generate interrupt context save and restore as the original interrupt (interrupt), but rather requires hardware to complete the save and restore of interrupt context in accordance with the ISTART instructions and IEND instructions. That is, instead of the hardware directly automatically saving, the hardware automatically saves the interrupt context as indicated by the ISTART instruction, and the process of automatically restoring the interrupt context by the hardware is triggered by the IEND instruction, instead of the mret instruction. It will be appreciated that the IEND instruction corresponds to the last split mret function to interrupt return, so that there is no need to add an mret instruction at the end of the handler.

In a preferred embodiment, the first instruction is further configured to instruct hardware to automatically save an interrupt context to a hardware storage area or stack, and the second instruction is further configured to instruct hardware to automatically resume the interrupt context from the corresponding hardware storage area or stack.

With the above example in mind, the first instruction of the vector interrupt handler entry is the ISTART, which can save the general purpose registers of the type of the teller to be saved by the interrupt entry and the CSR registers that need to be saved when the interrupt is nested, by hardware onto a hardware storage area or stack. Further, the vector interrupt handler modified with attribute ("sc_attribute") is used, and the return operation is completed by instruction IEND. The IEND corresponds to ISTART, and when the IEND instruction is executed, the hardware restores the interrupt context in a hardware storage area or stack to a general register of a teller type and a CSR register stored when the interrupt is nested. The implementation of the hardware automatic save interrupt context or the hardware automatic resume interrupt context is conventional to those skilled in the art, and will not be described in detail herein.

In this way, for the task switch interrupt of the real-time operating system, since hardware is not required to restore the context when the interrupt returns, the IEND instruction is not generated at the end of the corresponding handler, and in response thereto, the ISTART instruction is not generated at the entrance of the handler.

Therefore, taking the comparison of task switching interrupt processing and normal vector interrupt processing as an example, the interrupt processing program corresponding to the former is compiled without adopting the method of the embodiment of the invention, and the interrupt processing program corresponding to the latter is compiled with adopting the method of the embodiment of the invention, so that when executing interrupt processing, whether the current interrupt processing needs hardware automatic saving and interrupt context restoration can be distinguished through the interrupt processing program. In addition, the processing program corresponding to the task switching interrupt does not have a first instruction and a second instruction, namely the original mret (instead of IEND) can be continuously used during task switching, so that the hardware automatic interrupt context recovery cannot occur, and the context of a new task already configured by an operating system cannot be covered.

In a preferred embodiment, the first instruction is further configured to set the MIE bit in the MSTATUS register. For example, the last function performed by the ISTART instruction is to set the MIE bit in the MSTATUS register, enabling global interrupts to allow high-level interrupts to interrupt the current interrupt handling flow, forming interrupt nesting.

In a preferred embodiment, the second instruction is further configured to instruct an interrupt tail biting. Specific interrupt tail biting procedures are described below in conjunction with examples, and are not described in detail herein.

On the basis of the processing method of the interrupt processing program, the embodiment of the invention further provides an interrupt control method aiming at a RISC-V architecture.

FIG. 4 is a flow chart of an interrupt control method for RISC-V architecture according to an embodiment of the present invention, which is applied to a processor based on the RISC-V architecture, such as the CPU described above. As shown in fig. 4, the interrupt control method includes:

step S410, detecting the current interrupt handler to be executed to determine whether it is the interrupt handler modified by the above processing method, if so, executing step S420, otherwise, executing step S430.

Step S420, when executing the current interrupt handler, automatically saving the interrupt context by the first instruction execution hardware, and when the interrupt processing is finished, automatically restoring the interrupt context by the second instruction execution hardware.

Step S430, when executing the current interrupt handler, skipping the hardware auto-save interrupt context and the hardware auto-resume interrupt context.

For steps S410-S430, for example, the interrupt handler of the task switch interrupt does not have the first instruction and the second instruction, but the interrupt handler corresponding to other normal vector interrupts modified by the special modifier has the first instruction and the second instruction, so that the task switch interrupt is performed according to other software methods, and the situation that the hardware automatically resumes the interrupt context and covers the set new task context is avoided.

In a preferred embodiment, in a case where the second instruction is further configured to instruct interrupt tail biting, the interrupt tail biting scene of the first interrupt is biting for the second interrupt, as shown in fig. 5, the interrupt control method further includes the following steps S510 to S530:

step S510, controlling the first instruction of the interrupt handler of the first interrupt to complete the saving of the corresponding interrupt context.

Step S520, the first instruction of the interrupt handler controlling the second interrupt and the second instruction of the interrupt handler of the first interrupt are executed in a disabled manner. Wherein, failure means that no execution effect is generated.

In step S530, the second instruction of the interrupt handler of the second interrupt is controlled to complete the restoration of the corresponding interrupt context.

Accepting the above example for an IEND instruction, for steps S510-S530, using the IEND instruction to effect a tail biting operation for vector interrupts may include: when the IEND instruction starts to execute, the CLIC is queried to judge whether low-priority interrupt is waiting for processing, if yes, the entry waiting for the interrupt is considered to be an ISTART instruction, the process of restoring the interrupt context in the current interrupt processing program is skipped, and the interrupt context is restored at the end of the newly responded interrupt service program, so that the tail biting operation of the interrupt is realized. Since the interrupt context is resumed at the end of the newly responded interrupt service routine, this requires that the interrupt entry of the tail biting response must also be an ISTART instruction, the tail likewise implements the interrupt return by an IEND instruction, i.e., the tail biting interrupt must also be a vector interrupt, and its handler is also modified with an attribute of ((Interrupt) ("SC_PROPERTY")). When interrupt tail biting is successfully carried out, the current interrupt IEND instruction and the tail biting interrupt ISTART instruction can be immediately executed and completed, and no effect is produced. As shown in FIG. 6, interrupt B tails off interrupt A, and the recovery of interrupt context is accomplished by interrupting IEND in the Handler by B, the IEND in the Handler and the ISTART instruction in the Handler by B do not have any effect.

Fig. 7 is a flow chart of an interrupt control method according to a preferred embodiment of the present invention. As shown in fig. 7, in a preferred embodiment, the interrupt control method further includes step S440 and step S450:

step S440, for the interrupt handler having the first instruction and the second instruction, of executing a separately configured pre-boot instruction in advance, which has the same function as the first instruction, before acquiring the first instruction at the entry of the interrupt handler.

And S450, comparing the instruction codes of the pre-starting instruction and the first instruction, if the two instruction codes are inconsistent, controlling the pre-starting instruction to fail to execute the first instruction, otherwise controlling the pre-starting instruction to take effect to skip executing the first instruction.

For example, the first instruction and the pre-start instruction are both denoted as ISTART instructions, which are defined as "pre-execute" to increase CPU execution efficiency by pre-executing the ISTART instructions. When the vector interrupt occurs, after the CPU responds to the interrupt, before the inlet instruction of the vector interrupt handler is acquired, an ISTART instruction is pre-executed, and in the execution process, the ISTART instruction is compared with the instruction code of the inlet instruction returned by the fetch instruction (fetch), if the comparison is inconsistent, the executed ISTART instruction does not generate any effect, and the instruction returned by the current fetch is continuously executed. This indicates that the interrupt does not require hardware to save and restore the interrupt context, such as a task switch interrupt for a real-time operating system. If the comparison is successful, the pre-executed ISTART instruction takes effect, the instruction returned by the fetch is not repeatedly executed, and the executed ISTART instruction stores a general register of a teller type and a CSR register which needs to be stored when the interrupt is nested by hardware.

That is, in the example of the preferred embodiment, assuming that the first instruction of the vector interrupt handler is ISTART, by pre-execution, pipeline stall caused by the jump of the CPU program pointer to the vector interrupt handler entry address can be reduced, thereby improving CPU execution efficiency. As shown in fig. 8, taking the example of a CPU having a 5-stage pipeline, the 5-stage streams are respectively fetch, decode, execute, access and write back. In the normal process, when responding to vector interrupt, firstly calculating an entry address of an interrupt handler, and then completing execution of a handler entry instruction through each stage of a pipeline; by pre-executing the ISTART instruction, the ISTART instruction can be directly driven into the execution stage, and the previous processes of calculating the entry address, fetching and decoding of the interrupt handler are omitted. And comparing the instruction before the write-back stage starts with the instruction which is normally fetched and returned, if the instruction codes are consistent, immediately entering the write-back stage of the pre-execution process pipeline to finish the execution of the ISTART instruction, and no stages of decoding, executing, accessing and writing back of the normal pipeline are needed. Thus, the CPU execution efficiency is significantly improved.

In summary, the embodiment of the invention combines the implementation process of the hardware interrupt context processing, and can separate the processing process of the common vector interrupt from the processing process of the task switching interrupt, so that when the real-time operating system responds to the task switching interrupt, the real-time operating system responds to the interrupt occurrence without the need of saving and restoring the hardware interrupt context, and without adding hardware control bits (such as the hardware control bit HS_OFF_T for shielding a hardware bullet stack in the prior art) and modifying task switching logic adapted to the newly added hardware control bits, thereby avoiding the influence of logic modification on the universality of the real-time operating system, maintaining the universality of the real-time operating system and reducing the complexity of operation. In addition, in the example of the embodiment of the invention, the situation that no ISTART and IEND instructions exist in the interrupt handler can be completely compatible, and normal execution of the interrupt nesting flow comprising default realization by software is ensured.

Embodiments of the present invention also provide a processor based on a RISC-V architecture, the processor being configured to respond to interrupts to perform any of the interrupt control methods described above.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, etc., such as Read Only Memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises an element.

The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.

Claims (10)

1. A method of processing an interrupt handler, comprising:

generating a first instruction and a second instruction, wherein the first instruction is configured to indicate whether to perform a hardware auto-save interrupt context and the second instruction is configured to indicate whether to perform a hardware auto-resume interrupt context; and

the first instruction is placed at the entry of a specified interrupt handler and the second instruction is placed at the end of the specified interrupt handler.

2. The processing method of claim 1, wherein the first instruction and the second instruction are generated by a compiler according to a preset interrupt handler attribute modifier.

3. The processing method of claim 1, wherein the second instruction is further configured to instruct an interrupt tail biting.

4. The processing method of claim 1, wherein the first instruction is further configured to instruct hardware to automatically save an interrupt context to a hardware storage area or stack, and the second instruction is further configured to instruct hardware to automatically resume the interrupt context from the corresponding hardware storage area or stack.

5. The processing method of claim 1, wherein the first instruction is further configured to set a MIE bit in a MSTATUS register.

6. A processing method according to claim 1, wherein the specified interrupt handler is an interrupt handler for any vector interrupt other than a task switch interrupt.

7. An interrupt control method based on RISC-V architecture, which is applied to a processor based on RISC-V architecture and comprises:

detecting a current interrupt handler to be executed to determine whether it is an interrupt handler modified by the processing method according to any one of claims 1 to 6;

if yes, when the current interrupt processing program is executed, the interrupt context is automatically saved through the first instruction execution hardware, and when the interrupt processing is finished, the interrupt context is automatically restored through the second instruction execution hardware;

otherwise, when executing the current interrupt handler, skipping the hardware to automatically save the interrupt context and the hardware to automatically resume the interrupt context.

8. The interrupt control method of claim 7, wherein, in the case where the second instruction is further configured to instruct interrupt tail biting, the interrupt control method further comprises an interrupt tail biting scene for a second interrupt tail biting first interrupt, performing the steps of:

the first instruction of the interrupt processing program for controlling the first interrupt is used for completing the storage of the corresponding interrupt context;

the first instruction of the interrupt handler controlling the second interrupt and the second instruction of the interrupt handler of the first interrupt are executed in a disabled manner; and

the second instruction of the interrupt handler of the second interrupt is controlled to complete the restoration of the corresponding interrupt context.

9. The interrupt control method according to claim 7 or 8, characterized in that the interrupt control method further comprises:

for an interrupt handler having the first instruction and the second instruction, pre-executing a pre-boot instruction configured separately, the pre-boot instruction having the same function as the first instruction, before acquiring the first instruction at an entry of the interrupt handler; and

comparing the instruction codes of the pre-starting instruction and the first instruction, if the two instruction codes are inconsistent, controlling the pre-starting instruction to fail to execute the first instruction, otherwise controlling the pre-starting instruction to take effect to skip executing the first instruction.

10. A processor based on RISC-V architecture, characterized in that the processor is configured to respond to interrupts to perform the interrupt control method of any one of claims 7 to 9.