CN117632258A - Synchronous read-write method, storage device and readable storage medium - Google Patents

Synchronous read-write method, storage device and readable storage medium Download PDF

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Publication number
CN117632258A
CN117632258A CN202311634097.7A CN202311634097A CN117632258A CN 117632258 A CN117632258 A CN 117632258A CN 202311634097 A CN202311634097 A CN 202311634097A CN 117632258 A CN117632258 A CN 117632258A
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write
read
request
data
memory
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马伟硕
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Yusur Technology Co ltd
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Yusur Technology Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087Synchronisation or serialisation instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements

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  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The application provides a synchronous read-write method, a storage device and a readable storage medium, wherein a first write request and a second write request are alternately generated, and a first read request and a second read request are alternately generated; when the first write request and the first read request are not concurrent; writing the write data of the second write request into the write register; reading current read data and next read data stored by the memory from the data port and writing the next read data into a read register; writing the write data of the first write request into the memory, and writing the write data of the second write request written into the write register into the memory; the next read data is read out of the read register. By using the synchronous read-write method, the read request and the write request can be simultaneously generated in each unit time period, and the analog synchronous read-write of the memory can be realized.

Description

Synchronous read-write method, storage device and readable storage medium
Technical Field
The present application relates to the field of chip technology, and more particularly, to a synchronous read-write method, a storage device, and a readable storage medium.
Background
A Static Random-Access Memory (SRAM) is a Memory device, and if the SRAM has two data ports, one data port performs a read operation, the other data port may perform a write operation at the same time, so that a synchronous FIFO can be realized. The FIFO (First In First Out) queue is a first-in first-out queue, and comprises a synchronous FIFO and an asynchronous FIFO, wherein the synchronous FIFO reads and writes by adopting the same clock.
In the synchronous read-write process of the memory chip, a dual-port SRAM is generally used to implement the synchronous FIFO queue. The synchronous FIFO is generally used for buffering interactive data, and when burst writing (i.e. data writing is too fast and the interval time is long) occurs to the data, the FIFO with a certain depth can be set to play a role in temporary storage of the data, prevent data loss and enable the subsequent processing flow to be smooth.
However, compared to the sram with a single data port, the sram with a double data port occupies more area of the digital circuit of the memory chip, which is disadvantageous for reducing the overall area of the memory chip.
Therefore, reducing the data port data of sram is a major consideration in improving the memory chip process in the case of how to enable the memory chip to implement FIFO queues for synchronous reading and writing.
Disclosure of Invention
The application provides a synchronous read-write method, a storage device and a readable storage medium, which can realize synchronous read-write of a memory while reducing the number of data ports of the memory in a chip.
In a first aspect, a synchronous read-write method is provided, including:
alternately generating a first write request and a second write request, and alternately generating a first read request and a second read request, wherein the first write request and the first read request are both directed to a memory, the second write request is directed to a write register, the second write request is directed to a read register, and a data queue stored in the memory is a first-in first-out queue;
when the first write request or the first read request is generated, judging whether the first write request and the first read request are concurrent, if not:
writing the write data of the first write request into the memory in response to the first write request, and writing the write data of the second write request written into the write register into the memory;
reading current read data and next read data in a first-in first-out queue stored in the memory to the same data port of the memory in response to the first read request, and writing the next read data into a read register;
Reading the next read data from the read register in response to the second read request;
and responding to the second write request, and writing the write data of the second write request into the write register.
In a possible embodiment, the synchronous read-write method further includes: if the first write request and the first read request are concurrent, responding to the first write request, and writing the write data of the first write request into a conflict register; and in response to the first read request, reading current read data and next read data in a first-in first-out queue stored in the memory from the data port to the same data port of the memory, and writing the next read data into a read register; and after reading out the current read data and the next read data in a first-in first-out queue stored in the memory from the data port to the same data port of the memory, writing the write data of the first write request written in the conflict register into the memory, and writing the write data of the second write request written in the write register into the memory.
In one possible embodiment, the first-in first-out queue includes a first sub-queue and a second sub-queue;
the writing, in response to the first write request, write the write data of the first write request into the memory and the write data of the second write request written into the write register into the memory, includes:
writing the write data of the first write request into the first sub-queue;
writing the write data of the second write request written in the write register into the second queue; and, in addition, the processing unit,
the writing write data of the first write request that has been written into the conflict register into the memory and writing write data of the second write request that has been written into the write register into the memory includes:
writing the write data of the first write request written in the conflict register into the first sub-queue;
write the write data of the second write request that has been written into the write register into the second queue.
In one possible embodiment, the reading the current read data and the next read data in the fifo stored in the memory from the data port to the same data port of the memory in response to the first read request includes: reading the previous data in the first sub-queue as the next read data to the same data port of the memory in response to the first read request; and reading the previous data in the second sub-queue as the current read data to the same data port of the memory.
In a possible embodiment, the alternately generating the first write request and the second write request includes:
the status of the count of write requests is determined,
generating the second write request when the count state of the write request indicates an odd number of times;
the first write request is generated when a count state of the write requests indicates an even number of times.
In one possible embodiment, the alternately generating the first read request and the second read request includes:
the count state of the read request is determined,
generating the first read request when the count state of the read request indicates an odd number of times;
the second read request is generated when the count state of the read request indicates an even number of times.
In one possible embodiment, the method further comprises: and when the read register is in an empty state and the memory is in a stored state, responding to the first read request or the second read request, and reading the current read data in the first-in first-out queue to the data port.
In one possible embodiment, when the read register, the memory, the conflict register are all in an empty state, and the write register is in a stored state, the data in the write register is read out in response to the first read request or the second read request.
In a second aspect, the present application further provides a storage device, including: the memory comprises a data port; the data queue stored in the memory is a first-in first-out queue;
the read-write controller is used for: alternately generating the first write request and the second write request, and alternately generating the first read request and the second read request;
the instruction port is used for: acquiring the first write request, the second write request, the first read request and the second read request from the read-write controller, sending the first write request and the first read request to the memory, sending the second write request to the write register, and sending the second write request to the read register;
the write register is to: writing write data of the second write request in response to the second write request;
the instruction port is further configured to: judging whether the first write request and the first read request are concurrent; if no:
the memory is used for: responding to the first write request, writing write data of the first write request into the memory, and writing write data of the second write request written into the write register;
The memory is also for: responding to the first reading request, and reading current reading data and next reading data in a first-in first-out queue stored in the memory to a data port of the memory;
the read register is to: writing the next read data into a read register;
the read register is further to: and responding to the second reading request, and reading out the next reading data from the reading register.
In one possible embodiment, the storage device further comprises a conflict register,
if the instruction port judges that the first write request and the first read request are concurrent:
the conflict register is used for: writing the write data of the first write request in response to the first write request;
after the memory reads the current read data and the next read data in the first-in-first-out queue from the data port to the same data port of the memory in response to the first read request, the memory is further configured to: write data of the first write request in the conflict register and write data of the second write request that has been written in the write register into the memory.
In a third aspect, the present application further provides a readable storage medium, where a program of a synchronous read-write method is stored, where the program of the synchronous read-write method, when executed by a processor, implements the steps of the synchronous read-write method described above.
By the synchronous read-write method, by means of the write register and the read register, the first write request and the second write request are alternately generated, the first read request and the second read request are alternately generated, the read request and the write request can be simultaneously generated in each unit time period, and the analog synchronous read-write of the memory is realized. Therefore, by the synchronous read-write method provided by the application, synchronous read-write of the memory can be realized while the number of data ports of the memory in the chip is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described, and advantages and benefits in the solutions will become apparent to those skilled in the art from reading the detailed description of the embodiments below. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. In the drawings:
Fig. 1 shows a partial flowchart of a synchronous read-write method according to an embodiment of the present application.
Fig. 2 shows a partial flowchart of a synchronous read-write method according to an embodiment of the present application.
Fig. 3 shows a schematic data flow diagram in a synchronous read-write method according to an embodiment of the present application.
Fig. 4 is a schematic flow chart of alternately generating a first write request and a second write request in a synchronous read-write method according to an embodiment of the present application.
Fig. 5 is a schematic flow chart of alternately generating a first request and a second request in a synchronous read-write method according to an embodiment of the present application.
Fig. 6 shows a block diagram of a storage device according to an embodiment of the present application.
Reference numerals:
s101: alternately generating a first write request and a second write request, and alternately generating a first read request and a second read request;
s102: when the first write request or the first read request is generated, judging whether the first write request and the first read request are concurrent, if not, executing at least one of the following steps:
s104: writing write data of the second write request into the write register in response to the second write request;
S105: reading current read data and next read data in a first-in first-out queue stored in the memory to the same data port of the memory in response to the first read request, and writing the next read data into a read register;
s103: writing the write data of the first write request into the memory in response to the first write request, and writing the write data of the second write request written into the write register into the memory;
s106: reading the next read data from the read register in response to the second read request;
s201: writing write data of the first write request into a conflict register in response to the first write request;
s202: reading current read data and next read data in a first-in first-out queue stored in the memory to the same data port of the memory in response to the first read request, and writing the next read data into a read register;
s203: after the current read data and the next read data in a first-in first-out queue stored in the memory are read out to the same data port of the memory, writing the write data of the first write request written in the conflict register into the first-in first-out queue, and writing the write data of the second write request written in the write register into the memory;
S401: the status of the count of write requests is determined,
s402: generating the second write request when the count state of the write request indicates an odd number of times;
s403: generating the first write request when the count state of the write request indicates an even number of times;
s501: the count state of the read request is determined,
s502: generating the first read request when the count state of the read request indicates an odd number of times;
s503: generating the second read request when the count state of the read request indicates an even number of times;
600: a storage device; 601: a read-write controller; 602: a memory; 603: writing a register; 604: reading a register; 605: an instruction port; 606: a conflict register; 607: a data port.
Detailed Description
The technical solutions in the present application will be described below with reference to the accompanying drawings.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
In the related art, a chip includes a memory with one single data port and a plurality of internal registers, and since the memory has only one data port, synchronous read/write cannot be realized, that is, a synchronous FIFO function cannot be realized. To solve this problem, the present application provides a synchronous read-write method using a plurality of internal registers in a chip (i.e., a memory device), and referring to fig. 1, the synchronous read-write method includes:
step S101: alternately generating a first write request and a second write request, and alternately generating a first read request and a second read request, wherein the first write request and the first read request are both directed to a memory, the second write request is directed to a write register, the second write request is directed to a read register, and a data queue stored in the memory is a first-in first-out queue.
Step S102: when the first write request or the first read request is generated, determining whether the first write request and the first read request are concurrent, and if not, executing at least one of the following steps S103, S104, S105 and S106.
Step S104: and responding to the second write request, and writing the write data of the second write request into the write register.
Step S105: reading current read data and next read data in a first-in first-out queue stored in the memory to the same data port of the memory in response to the first read request, and writing the next read data into a read register; the method comprises the steps of,
step S103: and responding to the first write request, writing the write data of the first write request into the memory, and writing the write data of the second write request written into the write register into the memory.
Step S106: and responding to the second reading request, and reading out the next reading data from the reading register.
Based on the technical scheme, by means of the write register and the read register, the analog synchronous read-write of the memory with the single data port is realized by alternately generating the first write request and the second write request and alternately generating the first read request and the second read request.
Specifically, first, in a first unit time period, a second write request and a first read request may be concurrent, write data of the second write request into a write register in response to the second write request, read current read data and next read data in a fifo queue stored in the memory into the same data port of the memory in response to the first read request, and write the next read data into a read register. That is, in the first unit time period, the data port of the memory is not used in response to the second write request, and the data port of the memory is used in response to the first read request, so that analog synchronous read-write of the memory in the first unit time period is realized. It should be clear that, after the current read data is read out to the data port of the memory, the read data is further read out to the data port of the chip; after the next read data is read from the read register, it is further read to the data port of the chip. It should be appreciated that the memory may be an SRAM-based memory. The memory device includes a memory, a write register, and a read register, and read requests and write requests may be retrieved from an instruction port of the memory device. Further, read data is read from the data port of the memory device, and write data is written from the data port of the memory device.
Then, in a second unit period, a first write request and a second read request may be simultaneously generated, the next read data is read out from the read register in response to the second read request, simultaneously, in response to the first write request, the first requested write data is written into the memory, and the first requested write data that has been written into the write register is written into the memory. That is, in the second unit time period, the data port of the memory is used in response to the first write request, and the data port of the memory is not used in response to the second read request, so that analog synchronous reading and writing of the memory in the second unit time period is realized.
Then, for the concurrent second write request and first read request in the third unit time period, the second write request and the first read request can be responded as in the first unit time period, so that the analog synchronous read-write of the memory in the third unit time period is realized.
In summary, by such a cycle, a read request and a write request can be simultaneously generated in each unit time period, and analog synchronous read/write of the memory can be realized. Therefore, by the synchronous read-write method provided by the application, synchronous read-write of the memory can be realized while the number of data ports of the memory in the chip is reduced.
It should be clear that, if only the second write request or the second read request is generated within the same unit time period, writing the write data of the second write request into the write register in response to the second write request; and responding to the second reading request, and reading out the next reading data from the reading register.
In one possible embodiment, referring to fig. 2, if the first write request and the first read request are concurrent, the following steps S201, S202, and S203 are performed:
step S201: writing write data of the first write request into a conflict register in response to the first write request;
step S202: reading current read data and next read data in a first-in first-out queue stored in the memory to the same data port of the memory in response to the first read request, and writing the next read data into a read register;
step S203: and after reading out the current read data and the next read data in the fifo of the memory to the same data port of the memory,
write the write data of the first write request that has been written into the conflict register into the first-in first-out data queue, and write the write data of the second write request that has been written into the write register into the memory.
It can be understood that: in the first unit time period, only the second write request is generated, and the first read request is not generated, so that the condition that the first write request and the first read request are concurrent in the second unit time period is caused, and for the condition, the analog synchronous read-write of the memory can be realized by means of the conflict register.
Specifically, in the first step, in response to a first read request, current read data and next read data in a first-in first-out queue stored in the memory are read out from a data port of the memory, and meanwhile, in response to a first write request, write data of the first write request are written into a conflict register; then, in a second step, the next read data is written into a read register, and at the same time, the write data is written from the conflict register into the first-in first-out data queue, and the write data of the second write request that has been written into the write register is written into the memory. Thus, analog synchronous reading and writing of the memory are realized.
Then, in the next unit time period, if the second write request and the second read request are concurrent, the data is written into the write register in response to the second write request, and at the same time, the next read data is read out from the read register in response to the second read request.
Or if the second write request is generated and the second read request is not generated, responding to the second write request and writing the data into the write register; while the next read data is still present in the read register waiting to be regenerated in response to the second read request.
Or if the second write request is not generated but the second read request is generated, the next read data is read out from the read register in response to the second read request; and the write register waits for a second write request to be generated again.
In summary, by means of the conflict register, the above method provided by the present application can also solve the problem of concurrency of the first read request and the first write request. Thus, whether the first write request and the second write request are generated in a regular and alternate mode or not and whether the first read request and the second read request are generated in a regular and alternate mode or not can realize analog synchronous reading and writing of the single data port memory.
It is clear that the data port of the memory is one, but the bit width of the memory is twice the bit width of the memory with two data ports, which memory may allow writing of the write data of the first write request and the write data of the second write request, which has been written in the write register, into the memory at the same time. Similarly, the current read data and the next read data can be read out from the data ports at the same time.
In a specific implementation, referring to fig. 3, the first-in first-out queue includes a first sub-queue and a second sub-queue; the writing, in response to the first write request, write the write data of the first write request into the memory and the write data of the second write request written into the write register into the memory, includes: writing the write data of the first write request into the first sub-queue; writing the write data of the second write request written in the write register into the second queue;
and, the writing the write data of the first write request written in the conflict register into the memory, and writing the write data of the second write request written in the write register into the memory, includes: writing the write data of the first write request written in the conflict register into the first sub-queue; write the write data of the second write request that has been written into the write register into the second queue.
By the method, the write data of the first write request is conveniently stored in the first sub-queue according to the generation time sequence of the first write request and the second write request, and the write data of the second write request is conveniently stored in the second sub-queue. This provides for responding to the first read request and the second read request. The method comprises the following steps:
The reading the current read data and the next read data in the first-in first-out queue stored in the memory to the same data port of the memory in response to the first read request comprises: reading the previous data in the first sub-queue as the next read data to the same data port of the memory in response to the first read request; and reading the previous data in the second sub-queue as the current read data to the same data port of the memory.
Here, the preceding data in the first sub-queue is the preceding time of writing data into the first sub-queue, and the preceding data in the second sub-queue is the preceding time of writing data into the second sub-queue.
In summary, by distinguishing the first sub-queue from the second sub-queue and associating the first write request with the first sub-queue and the second write request with the second sub-queue, it is convenient to distinguish between the current read data and the next read data when the first read request is made. So that data is written to the memory and read from the memory in a first-in first-out mechanism.
In one possible embodiment, referring to fig. 4, the alternately generating the first write request and the second write request includes:
Step S401: the status of the count of write requests is determined,
step S402: generating the second write request when the count state of the write request indicates an odd number of times; that is, the second write request is generated at the odd number of times.
Step S403: the first write request is generated when a count state of the write requests indicates an even number of times. That is, the first write request is generated at the even number of times.
That is, when generating a write request, a first write request is first generated, then a second write request is generated, and then the first write request and the second write request are alternately generated. Further, by determining what number of write requests are generated, it is determined whether the currently generated write request is the first write request or the second write request.
In view of the foregoing, an embodiment is provided herein, specifically: the first occurring write request may be determined as a second write request, the second occurring write request may be determined as a first write request, and the third occurring write request may be determined as a second write request, and so on, and then the previous data in the second sub-queue corresponding to the corresponding second write request should be read out as current read data, and the previous data in the first sub-queue corresponding to the first write request should be read out as next read data.
In one possible embodiment, referring to fig. 5, the alternately generating the first read request and the second read request further includes:
step S501: the count state of the read request is determined,
step S502: generating the first read request when the count state of the read request indicates an odd number of times; that is, at the time when the first read request is generated at the odd number of times.
Step S503: the second read request is generated when the count state of the read request indicates an even number of times. That is, the second read request is generated at the even number of times.
That is, first read requests are generated first, then second read requests are generated, and then the first read requests and the second read requests are alternately generated. Further, by determining the number of times a read request is generated, whether the currently generated write request is a first read request or a second read request is determined, so that it is possible to determine whether each generated read request is for a memory or for a read register.
It should be noted that, when the first read request is first generated, the first write request may be generated simultaneously, or the second write request may be generated simultaneously, which is not limited in this application. And, the first second write request is generated before the first read request so that the first read request can read data from the write register, or the memory, or the read register.
In one possible implementation, when the read register is in an empty state and the memory is in a stored state, current read data in the fifo is read to the data port in response to the second read request.
In other words, for special cases that may occur: when the read register is in an empty state, i.e. the next read data is not stored, but the memory stores the current read data, the current read data in the first-in first-out queue can still be read to the data port to respond to the second read request although the second read request is directed to the read register.
In another possible implementation, when the read register, the memory, the conflict register are all in an empty state, and the write register is in a store state,
and responding to the first reading request or the second reading request, and reading out the data in the write register.
In other words, for special cases that may occur: when the read register, the memory and the conflict register are in an empty state, namely, the read register, the memory and the conflict register do not store data, but when the write data of the second write instruction is stored in the write register, the data in the write register can still be read out to realize the response to the first read request or the second read request.
The application can also protect a storage device, and the storage device can realize synchronous reading and writing by using the synchronous reading and writing method. In one possible example, the storage device may be a chip.
Referring to fig. 6, the memory device 600 includes a read/write controller 601, a memory 602, a write register 603, a read register 604, an instruction port 605, (e.g., may be implemented as an instruction port), the memory device 600 may further include a first data port 607, and the memory includes a second data port; the data storage queue in the memory is a first-in first-out queue;
the read-write controller 601 is configured to: alternately generating the first write request and the second write request, and alternately generating the first read request and the second read request;
the instruction port 605 is configured to: acquiring the first write request, the second write request, the first read request and the second read request from the read-write controller, sending the first write request and the first read request to the memory, sending the second write request to the write register, and sending the second write request to the read register;
the write register 603 is configured to: writing write data of the second write request in response to the second write request;
The instruction port 605 is also for: judging whether the first write request and the first read request are concurrent; if no:
the memory 602 is configured to: responding to the first write request, writing write data of the first write request into the memory, and writing write data of the second write request written into the write register;
the memory 602 is further configured to: reading current read data and next read data in a first-in first-out queue stored in the memory to a data port of the memory in response to the first read request,
the read register 604 is used to write the next read data;
the read register 604 is also used to: and responding to the second reading request, and reading out the next reading data from the reading register. The next read data is then read to the first data port 607.
Based on the technical scheme, the read-write controller alternately generates the first write request and the second write request, and alternately generates the first read request and the second read request, and by means of the write register and the read register, analog synchronous read-write of the memory with the single data port is realized, so that the memory device can realize synchronous read-write.
Specifically, first, in a first unit time period, a second write request and a first read request may be concurrent, write data of the second write request into a register in response to the second write request, simultaneously read current read data and next read data in a first-in first-out queue stored in the memory and next read data into a data port of the memory in response to the first read request, and write the next read data into a read register. That is, in the first unit time period, the data port of the memory is not used when responding to the second write request, and the data port of the memory is used when responding to the first read request, so that the analog synchronous read-write of the memory in the first unit time period is realized, that is, the memory device can realize the synchronous read-write. Of course, the current read data is read out to the data port of the memory and then further read out to the first data port 607.
Then, in a second unit period, a first write request and a second read request may be simultaneously generated, the next read data is read out from the read register in response to the second read request, simultaneously, in response to the first write request, the first requested write data is written into the memory, and the first requested write data that has been written into the write register is written into the memory. That is, in the second unit time period, the data port of the memory is used when responding to the first write request, and the data port of the memory is not used when responding to the second read request, so that the analog synchronous read-write of the memory in the second unit time period is realized, that is, the memory device can realize the synchronous read-write.
Then, in the third unit time period, for the concurrent second write request and first read request, the second write request and the first read request can be responded as in the first unit time period, so that the analog synchronous read-write of the memory in the third unit time period, namely, the synchronous read-write of the memory device is realized.
In summary, such a cycle can simultaneously generate a read request and a write request in each unit time period, and realize synchronous reading and writing to the storage device. Therefore, by the synchronous read-write method provided by the application, the storage device can realize synchronous read-write while reducing the number of the data ports of the storage in the storage device.
In a possible embodiment, the storage device further includes a conflict register 606, if the instruction port determines that the first write request and the first read request are concurrent:
the conflict register is used for: writing the write data of the first write request in response to the first write request;
after the memory reads out the current read data and the next read data in the first-in first-out queue to the data port of the memory in response to the first read request,
The memory is also for: write data of the first write request in the conflict register and write data of the second write request that has been written in the write register into the memory.
It can be understood that: in the first unit time period, the read-write controller only generates the second write request and does not generate the first read request, so that the condition that the first write request and the first read request are concurrent in the second unit time period is caused, and for the condition, the analog synchronous read-write of the memory can be realized by means of the conflict register.
Specifically, in the first step, in response to a first read request, current read data and next read data in a first-in first-out queue stored in the memory are read out to a data port of the memory, and simultaneously, in response to a first write request, a conflict register writes write data of the first write request; then, in a second step, the next read data is written into a read register, and at the same time, the write data is written from the conflict register into the first-in first-out data queue, and the write data of the second write request that has been written into the write register is written into the memory. In this way, the storage device can realize synchronous reading and writing.
Then, in the next unit time period, if the second write request and the second read request are concurrent, the data is written into the write register in response to the second write request, and at the same time, the next read data is read out from the read register in response to the second read request.
Or if the second write request is generated and the second read request is not generated, responding to the second write request and writing the data into the write register; while the next read data is still present in the read register waiting to be regenerated in response to the second read request.
Or if the second write request is not generated but the second read request is generated, the next read data is read out from the read register in response to the second read request; and the write register waits for a second write request to be generated again.
In summary, the problem of concurrency of the first read request and the first write request can be solved by means of the conflict register. Therefore, whether the first write request and the second write request are generated in a regular and alternate mode or not and whether the first read request and the second read request are generated in a regular and alternate mode or not can realize analog synchronous read-write of the memory with the single data port, namely the memory device can realize synchronous read-write.
It is clear that the data port of the memory is one, but the bit width of the memory is twice the bit width of the memory with two data ports, the memory may allow writing of write data of the first write request and write data of the second write request, which have been written in the write register, into the memory at the same time. Similarly, the current read data and the next read data can be read out to the same data port of the memory at the same time.
In a specific implementation manner, the memory includes a first storage area and a second storage area, the first storage area is used for storing a first sub-queue, the second storage area is used for storing a second sub-queue, and the first sub-queue and the second sub-queue are both first-in first-out queues;
the memory is then used in particular for: writing the write data of the first write request into the first sub-queue; writing the write data of the first write request written in the conflict register into the first sub-queue; write the write data of the second write request that has been written into the write register into the second queue.
By the method, the write data of the first write request is conveniently stored in the first sub-queue according to the generation time sequence of the first write request and the second write request, and the write data of the second write request is conveniently stored in the second sub-queue. This provides for the memory to respond to the first read request and the second read request. The method comprises the following steps:
in one example, the memory has a memory for: in response to the first request, the prior data in the first sub-queue is read out as the next read data to the data port of the memory, and the prior data in the second sub-queue is read out as the current read data to the data port of the memory.
It can also be understood that:
the reading the current read data and the next read data in the first-in first-out queue stored in the memory to the data port of the memory in response to the first read request comprises: reading the prior data in the first sub-queue as the next read data to a data port of the memory in response to the first read request; and reading the previous data in the second sub-queue as the current read data to a data port of the memory.
Here, the preceding data in the first sub-queue is the preceding time of writing data into the first sub-queue, and the preceding data in the second sub-queue is the preceding time of writing data into the second sub-queue. In summary, by distinguishing the first sub-queue from the second sub-queue and associating the first write request with the first sub-queue and the second write request with the second sub-queue, it is convenient to distinguish between the current read data and the next read data when the first read request is made. So that data is written to the memory and read from the memory in a first-in first-out mechanism.
In one possible embodiment, the read-write controller may comprise a first counting device,
The first counting means is for judging a counting state of the write request,
generating the second write request by the read-write controller when the count state of the write request indicates the odd number;
the read-write controller generates the first write request when the count state of the write request indicates an even number of times.
That is, when generating a write request, a first write request is first generated, then a second write request is generated, and then the first write request and the second write request are alternately generated. Further, by determining what number of write requests are generated, whether the currently generated write request is the first write request or the second write request, it is possible to determine whether each generated write request is for the memory or for the write register.
In view of the foregoing, an embodiment is provided herein, specifically: the first occurring write request may be determined as a second write request, the second occurring write request may be determined as a first write request, and the third occurring write request may be determined as a second write request, and so on, and then the previous data in the second sub-queue corresponding to the corresponding second write request should be read out as current read data, and the previous data in the first sub-queue corresponding to the first write request should be read out as next read data.
In a possible embodiment, the read-write controller may include a second counting device, further including:
the second counting device is used for judging the counting state of the read request, the read-write controller obtains the counting state of the read request,
generating the first read request by the read-write controller when the counting state of the read request indicates the odd number;
the read-write controller generates the second read request when the count state of the read request indicates an even number of times.
That is, the read-write controller generates first read requests first, then generates second read requests, and then alternately generates the first read requests and the second read requests. Further, by determining the number of times a read request is generated, whether the currently generated write request is a first read request or a second read request is determined, so that it is possible to determine whether each generated read request is for a memory or for a read register.
It should be noted that, when the read-write controller generates the first read request for the first time, the first write request may be generated simultaneously, or the second write request may be generated simultaneously, which is not limited in this application. And, the first second write request is generated before the first read request so that the first read request can read data from the write register, or the memory, or the read register.
In one possible implementation, when the read register is in the empty state and the memory is in the stored state, the memory is further configured to read the current read data in the fifo queue to the data port in response to the second read request.
In other words, for special cases that may occur: when the read register is in an empty state, i.e. the next read data is not stored, but the memory stores the current read data, the current read data in the first-in first-out queue can still be read to the data port to respond to the second read request although the second read request is directed to the read register.
In another possible implementation, when the read register, the memory, the conflict register are all in an empty state, and the write register is in a store state,
the write register is further configured to read out data in the write register in response to the first read request or the second read request.
In other words, for special cases that may occur: when the read register, the memory and the conflict register are in an empty state, namely, the read register, the memory and the conflict register do not store data, but when the write data of the second write instruction is stored in the write register, the data in the write register can still be read out to realize the response to the first read request or the second read request.
The application also provides a program of the synchronous read-write method stored on the readable storage medium, wherein when the program of the synchronous read-write method is executed by a processor, the steps of the synchronous read-write method are realized.
It should be noted that, on the premise of no conflict, the embodiments described in the present application and/or the technical features in the embodiments may be arbitrarily combined with each other, and the technical solutions obtained after the combination should also fall into the protection scope of the present application.
It should be understood that the specific examples in the embodiments of the present application are only for helping those skilled in the art to better understand the embodiments of the present application, and not limit the scope of the embodiments of the present application, and those skilled in the art may make various improvements and modifications based on the above embodiments, and these improvements or modifications fall within the protection scope of the present application.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A synchronous read-write method, comprising:
alternately generating a first write request and a second write request, and alternately generating a first read request and a second read request, wherein the first write request and the first read request are both directed to a memory, the second write request is directed to a write register, the second write request is directed to a read register, and a data queue stored in the memory is a first-in first-out queue;
when the first write request or the first read request is generated, judging whether the first write request and the first read request are concurrent, if not:
writing the write data of the first write request into the memory in response to the first write request, and writing the write data of the second write request written into the write register into the memory;
reading current read data and next read data in a first-in first-out queue stored in the memory to the same data port of the memory in response to the first read request, and writing the next read data into a read register;
reading the next read data from the read register in response to the second read request;
and responding to the second write request, and writing the write data of the second write request into the write register.
2. The synchronous read-write method according to claim 1, characterized in that the synchronous read-write method further comprises: if the first write request and the first read request are concurrent,
writing write data of the first write request into a conflict register in response to the first write request;
and in response to the first read request, reading current read data and next read data in a first-in first-out queue stored in the memory from the data port to the same data port of the memory, and writing the next read data into a read register;
and after reading the current read data and the next read data in the memory-stored fifo from the data port to the same data port of the memory,
write the write data of the first write request that has been written into the conflict register into the memory, and write the write data of the second write request that has been written into the write register into the memory.
3. The method of synchronizing read and write according to claim 2, wherein the first-in first-out queue comprises a first sub-queue and a second sub-queue;
The writing, in response to the first write request, write the write data of the first write request into the memory and the write data of the second write request written into the write register into the memory, includes:
writing the write data of the first write request into the first sub-queue;
writing the write data of the second write request written in the write register into the second queue; and, in addition, the processing unit,
the writing write data of the first write request that has been written into the conflict register into the memory and writing write data of the second write request that has been written into the write register into the memory includes:
writing the write data of the first write request written in the conflict register into the first sub-queue;
write the write data of the second write request that has been written into the write register into the second queue.
4. The method of claim 3, wherein said reading current read data and next read data in a fifo queue stored in said memory from said data port to the same data port of said memory in response to said first read request comprises:
Reading the previous data in the first sub-queue as the next read data to the same data port of the memory in response to the first read request; and, in addition, the processing unit,
and reading the previous data in the second sub-queue as the current read data to the same data port of the memory.
5. The synchronized reading and writing method of claim 1, wherein said alternately generating first and second write requests includes:
the status of the count of write requests is determined,
generating the second write request when the count state of the write request indicates an odd number of times;
the first write request is generated when a count state of the write requests indicates an even number of times.
6. The method of claim 1, wherein the alternately generating the first read request and the second read request comprises:
the count state of the read request is determined,
generating the first read request when the count state of the read request indicates an odd number of times;
the second read request is generated when the count state of the read request indicates an even number of times.
7. The synchronized reading and writing method of claim 1, further comprising: when the read register is in an empty state, the memory is in a stored state,
And responding to the first reading request or the second reading request, and reading the current reading data in the first-in first-out queue to the data port.
8. The method of claim 2, wherein when the read register, the memory, and the conflict register are all in a null state and the write register is in a store state,
and responding to the first reading request or the second reading request, and reading out the data in the write register.
9. A memory device, comprising: the memory comprises a data port; the data queue stored in the memory is a first-in first-out queue;
the read-write controller is used for: alternately generating the first write request and the second write request, and alternately generating the first read request and the second read request;
the instruction port is used for: acquiring the first write request, the second write request, the first read request and the second read request from the read-write controller, sending the first write request and the first read request to the memory, sending the second write request to the write register, and sending the second write request to the read register;
The write register is to: writing write data of the second write request in response to the second write request;
the instruction port is further configured to: judging whether the first write request and the first read request are concurrent; if no:
the memory is used for: responding to the first write request, writing write data of the first write request into the memory, and writing write data of the second write request written into the write register;
the memory is also for: responding to the first reading request, and reading current reading data and next reading data in a first-in first-out queue stored in the memory to a data port of the memory;
the read register is to: writing the next read data into a read register;
the read register is further to: and responding to the second reading request, and reading out the next reading data from the reading register.
10. The memory device of claim 9, further comprising a conflict register,
if the instruction port judges that the first write request and the first read request are concurrent:
the conflict register is used for: writing the write data of the first write request in response to the first write request;
After the memory reads the current read data and the next read data in the first-in-first-out queue from the data port to the same data port of the memory in response to the first read request,
the memory is also for: write data of the first write request in the conflict register and write data of the second write request that has been written in the write register into the memory.
11. A readable storage medium, wherein a program of a synchronous read-write method is stored on the readable storage medium, which when executed by a processor, implements the steps of the synchronous read-write method according to any one of claims 1-8.
CN202311634097.7A 2023-11-30 2023-11-30 Synchronous read-write method, storage device and readable storage medium Pending CN117632258A (en)

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