CN117629279A - Data acquisition device, data acquisition method, chip and electronic equipment - Google Patents

Abstract

The application discloses a data acquisition device, a data acquisition method, a chip and electronic equipment, which are applied to the chip, wherein the device comprises a sensor module which is correspondingly arranged in each processing unit of the chip, and a plurality of sensor modules are connected in sequence; the sensor module is used for receiving the clock signal and the data signal, carrying out data acquisition on the current processing unit, and generating an intermediate data signal according to the acquired data and the data signal; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and inputting the new clock signal as a clock signal to the next stage sensor module, and inputting the new data signal as a data signal to the next stage sensor module. The device is easy to wire and has good expandability; and the delay difference between the clock and the data can be reduced, so that the data acquisition is stable.

Description

Data acquisition device, data acquisition method, chip and electronic equipment

Technical Field

The application relates to the technical field of chips, in particular to a data acquisition device, a data acquisition method, a chip and electronic equipment.

Background

With the continuous development of integrated circuit technology, the integration level of the chip is higher and higher, and the function of the chip is also stronger and stronger. In developing and designing large-scale integrated circuits, the integrated circuits are typically split into smaller modules for processing. In the process of realizing different module designs, in order to ensure the correctness of the chip functions, the time sequences of the modules are required to meet the design requirements.

In the related art, a sensor is currently placed inside each module to collect data of each module inside the chip, and then each module needs to send the collected data to a centralized processing unit, and the modules are synchronized by using clock signals. However, the related art solutions still have some drawbacks, for example, as the number of sensors increases, a part of sensors needs to be transmitted over a long distance to reach the centralized processing unit, so long-distance transmission of data not only has a problem of complicated wiring, but also easily causes a problem of increased delay in the data transmission process, resulting in failure of data acquisition.

Disclosure of Invention

The data acquisition device, the data acquisition method, the chip and the electronic equipment can reduce wiring complexity, delay time difference between a clock and data in a transmission process, so that data acquisition is stable, and meanwhile, the data acquisition device has good expandability.

In order to achieve the above purpose, the technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a data acquisition device, which is applied to a chip, where the data acquisition device includes a sensor module correspondingly disposed inside each processing unit of the chip, and a plurality of sensor modules are sequentially connected; the sensor module is used for receiving clock signals and data signals, carrying out data acquisition on a current processing unit, and generating intermediate data signals according to acquired data and data signals; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and inputting the new clock signal as a clock signal to the next stage sensor module, and inputting the new data signal as a data signal to the next stage sensor module.

In some embodiments, a plurality of sensor modules are connected in sequence by way of a link.

In some embodiments, the new data signal output by the last sensor module includes the respective acquired data for each processing unit of the chip.

In some embodiments, the sensor module comprises an acquisition sensor and a trigger, wherein an input end of the trigger is connected with an output end of the acquisition sensor, a clock end of the trigger is used for receiving a clock signal, and an output end of the trigger is used for outputting a new data signal; the acquisition sensor is used for acquiring data of a processing unit where the sensor module is located, so as to obtain acquisition data of the processing unit; the trigger is used for sampling the intermediate data signal by using the clock signal after generating the intermediate data signal according to the acquired data and the received data signal, and outputting a new data signal; wherein the new data signal is the input data signal of the next stage sensor module.

In some embodiments, the triggering manner of the trigger includes: rising edge triggering or falling edge triggering; the trigger is used for sampling the intermediate data signal by utilizing the rising edge of the clock signal when the trigger mode is rising edge trigger, and outputting a new data signal; or the trigger is used for sampling the intermediate data signal by using the falling edge of the clock signal when the trigger mode is falling edge trigger, and outputting a new data signal.

In some embodiments, the acquisition sensor is a PVT sensor; wherein the acquired data comprises at least one of: temperature data, process data, and voltage data.

In some embodiments, a clock line and a data line are arranged between the sensor module and the next-stage sensor module, the clock line is used for transmitting a new clock signal output by the sensor module, and the data line is used for transmitting a new data signal output by the sensor module; the transmission distances of the clock lines and the data lines arranged between the sensor module and the next-stage sensor module are the same.

In some embodiments, a combination logic module is further arranged on a data line between the sensor module and the next-stage sensor module, an input end of the combination logic module is connected with an output end of the sensor module, and an output end of the combination logic module is connected with an input end of the next-stage sensor module; the combination logic module is used for receiving the new data signals output by the sensor module, carrying out combination logic processing on the new data signals to obtain processed data signals, and taking the processed data signals as input data signals of the next-stage sensor module.

In some embodiments, a sum of a path delay time between an output of the sensor module and an input of the combinational logic module, a delay time required for the combinational logic module to perform combinational logic processing, and a path delay time between an output of the combinational logic module and an input of a next stage sensor module is less than a difference between a preset clock period and a clock setup time; the preset clock period is a clock period of a new clock signal, and the clock establishment time represents time when a new data signal needs to reach the input end of a next-stage sensor module in advance compared with the new clock signal.

In a second aspect, an embodiment of the present application provides a data acquisition method, which is applied to a data acquisition device, where the data acquisition device includes a sensor module correspondingly disposed inside each processing unit of a chip, and a plurality of sensor modules are sequentially connected; the method comprises the following steps:

receiving clock signals and data signals through a sensor module, carrying out data acquisition on a current processing unit, and generating intermediate data signals according to acquired data and data signals; data acquisition is carried out on the data signals by using the clock signals, and new clock signals and new data signals are output; and inputting a new clock signal as a clock signal to the next-stage sensor module, inputting a new data signal as a data signal to the next-stage sensor module, and cyclically executing the steps of receiving the clock signal and the data signal through the next-stage sensor module and outputting the new clock signal and the new data signal until the last sensor module connected in sequence outputs the new clock signal and the new data signal.

In some embodiments, the sensor module includes an acquisition sensor and a trigger, performs data acquisition on a currently located processing unit, and generates an intermediate data signal according to the acquired data and data signals; data acquisition is performed on the data signal by using the clock signal, and a new clock signal and a new data signal are output, including: the data acquisition is carried out on the processing unit where the sensor module is located through the acquisition sensor, so that acquisition data of the processing unit are obtained; after generating an intermediate data signal according to the acquired data and the received data signal, sampling the intermediate data signal by using a clock signal through a trigger, and outputting a new data signal; wherein the new data signal is the input data signal of the next stage sensor module.

In some embodiments, the triggering manner of the trigger includes: rising edge triggering or falling edge triggering; accordingly, sampling the intermediate data signal with the clock signal by the flip-flop, outputting a new data signal, comprising: when the trigger mode of the trigger is rising edge triggering, sampling the intermediate data signal by utilizing the rising edge of the clock signal, and outputting a new data signal; or when the trigger mode of the trigger is falling edge trigger, the intermediate data signal is sampled by the falling edge of the clock signal, and a new data signal is output.

In some embodiments, the acquisition sensor is a PVT sensor; wherein the acquired data comprises at least one of: temperature data, process data, and voltage data.

In some embodiments, the method further comprises: and sequentially connecting a plurality of sensor modules in a link mode.

In a third aspect, embodiments of the present application provide a chip comprising a plurality of processing units and a data acquisition device according to any one of the first aspects.

In a fourth aspect, embodiments of the present application provide an electronic device including a chip as described in the third aspect.

The data acquisition device comprises a sensor module which is correspondingly arranged in each processing unit of the chip, and a plurality of sensor modules are sequentially connected; the sensor module is used for receiving clock signals and data signals, carrying out data acquisition on a current processing unit, and generating intermediate data signals according to acquired data and data signals; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and inputting the new clock signal as a clock signal to the next stage sensor module, and inputting the new data signal as a data signal to the next stage sensor module. Therefore, as the sensor modules are connected in sequence, not only all acquired data can be summarized together, but also the data acquisition is stable, flexible and strong, and has better expandability; in addition, each sensor module can provide independent clock signals and data signals to be transmitted to the next-stage sensor module, so that wiring complexity can be reduced, meanwhile, the fact that data between every two sensor modules and the transmission path of the clock are identical can be guaranteed, further, the time difference between the clock and the data is reduced, and the problem of data acquisition failure is avoided.

Drawings

FIG. 1 is a schematic diagram of an interconnection scheme of PVT sensors inside a chip;

FIG. 2 is a schematic diagram of an application framework for data transmission;

fig. 3 is a schematic diagram of a composition structure of a data acquisition device according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a sensor module according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another data acquisition device according to an embodiment of the present application;

fig. 6 is a schematic flow chart of a data acquisition method according to an embodiment of the present application;

fig. 7 is a schematic diagram of a composition structure of a chip according to an embodiment of the present application;

fig. 8 is a schematic diagram of a composition structure of an electronic device according to an embodiment of the present application;

fig. 9 is a schematic diagram of a composition structure of another electronic device according to an embodiment of the present application.

Detailed Description

For a more complete understanding of the features and technical content of the embodiments of the present application, reference should be made to the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings, which are for purposes of illustration only and not intended to limit the embodiments of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict. It should also be noted that the term "first/second/third" in reference to the embodiments of the present application is used merely to distinguish similar objects and does not represent a specific ordering for the objects, it being understood that the "first/second/third" may be interchanged with a specific order or sequence, if allowed, to enable the embodiments of the present application described herein to be implemented in an order other than that illustrated or described herein.

It is understood that a large scale integrated circuit, such as a System On Chip (SOC), may be split into tens and hundreds of modules for design during a particular circuit design process. For example, the modules may be divided according to the functions and the positional relationship of the modules, each module may implement a specific function, and each module may send the data collected by the respective module to the centralized processing unit.

Currently, with the improvement of chip integration, in order to collect data of each sampling position inside a chip, a sensor may be placed at each sampling position inside the chip, where the sensor may be a sensor for sensing a Process, a Voltage and a temperature (PVT), and abbreviated as PVT sensor. Thus, data that can be collected using PVT sensors includes: parameters such as temperature, process, voltage and the like, and the data of all sampling positions are processed by a unified centralized processing unit after being summarized. In the related art, after each PVT sensor collects data, it is required to connect with a centralized processing unit.

Fig. 1 shows a schematic diagram of an interconnection scheme of an on-chip PVT sensor. As shown in fig. 1, different filling areas represent different modules, and a PVT sensor is placed inside each module; each module needs to send the collected data to the centralized processing unit, and each module uses the same clock to synchronize. Specifically, in fig. 1, a chip may be split into a plurality of modules. In different modules, the PVT sensor may be represented by a module a, a module B, a module C, a module D, a module E, a module F, a module G, a module H, a module I, respectively, while the module I may be regarded as a centralized processing unit. In addition, combinational Logic (Logic) modules, represented by Logic module 11, logic module 12, logic module 13, logic module 14, logic module 15, logic module 16, logic module 17, and Logic module 18, respectively, may be provided between module a and module I, between module B and module I, between module C and module I, between module D and module I, between module E and module I, between module F and module I, and between module H and module I. Note that in fig. 1, a bold solid line indicates a data signal, and a bold dashed line indicates a clock signal.

According to the technical solution shown in fig. 1, the problems brought about mainly have two aspects: on the one hand, as the number of PVT sensors increases, each needs to transmit data to the centralized processing unit independently, so that the wires need to be transmitted in a long distance, which causes a certain problem for layout and wiring; on the other hand, since the distances between the PVT sensors are not uniform, there are some distances, and there is a problem in timing when the clocks are synchronized, and the distance between the flip-flop a and the flip-flop B will be described as an example.

By way of example, fig. 2 shows a schematic diagram of an application framework for data transmission. As shown in fig. 2, the long-distance transmission of data is briefly summarized here as the transmission from the flip-flop a to the flip-flop B, so that when data is transmitted according to a synchronous clock, the application framework can be decomposed into several delays, respectively: t (T) _ab 、T _cd 、T _de 、T _ef 、T _fh 、T _ag 、T _clock And T _setup . Wherein T is _ab The delay of the rising edge of the clock from the point a to the point b is shown; t (T) _cd Representing the delay used by data transfer from point c to point d after the clock rising edge is received at point b; t (T) _de Representing the time taken for data to pass from point d to point e; t (T) _ef Representing the delay required for the processing of the data through the combinational logic module 11; t (T) _fh Representing the delay of the data input h point of the next stage trigger B after the data is output by the combinational logic module 11; t (T) _ag Representing the delay required for the clock rising edge to pass to flip-flop B; t (T) _clock Representing the size of a clock cycle; t (T) _setup Indicating the time at which the data needs to reach the h-point in advance before the clock rising edge reaches the flip-flop B.

Thus, for each of the above delays, the following relationship needs to be satisfied:

T _ab +T _cd +T _ef +T _de +T _fh ≤T _ag +T _clock -T _setup (1)

that is, the data needs to be advanced by T at least before the clock rising edge reaches the g-point _setup Is reached; otherwise, trigger B will not collect the data transmitted from trigger a.

The conversion of equation (1) can be changed to:

T _ef ≤T _ag -T _ab +T _clock -T _setup -T _cd -T _de -T _fh (2)

in the formula (2), T _clock And clockFrequency-dependent, fixed value; t (T) _setup 、T _cd Is also a fixed value, and is therefore able to decide to leave T _ef Time and T of (2) _ag -T _ab And T _de +T _fh In order to ensure that each device can operate synchronously, in chip design, it is necessary to ensure T _ag -T _ab The value of (2) is as close to 0 as possible; and for T _de +T _fh As the transmission distance increases, it becomes larger and larger, then it is left for T _ef The time margin of (c) will be smaller and smaller.

In short, for the data transmission mode of the PVT sensor in the related art, the long-distance transmission has wiring problem, and a buffer is also needed to be inserted into a clock tree to balance the clock tree, so that the time when the clock reaches each PVT sensor is ensured to be the same, and the time sequence meets the design requirement; in addition, due to long-distance data transmission, delay in the data transmission process is increased, as shown in formula (2), when T _ef <0 will cause data to be unable to be collected at the target trigger.

Based on this, the embodiment of the application provides a data acquisition device, which is applied to a chip, and the data acquisition device may include a sensor module correspondingly disposed inside each processing unit of the chip, where a plurality of sensor modules are sequentially connected; the sensor module is used for receiving clock signals and data signals, carrying out data acquisition on a current processing unit, and generating intermediate data signals according to acquired data and data signals; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and inputting the new clock signal as a clock signal to the next stage sensor module, and inputting the new data signal as a data signal to the next stage sensor module. Therefore, as the sensor modules are connected in sequence, not only all acquired data can be summarized together, but also the data acquisition is stable, flexible and strong, and has better expandability; in addition, each sensor module can provide independent clock signals and data signals to be transmitted to the next-stage sensor module, so that wiring complexity can be reduced, meanwhile, the fact that data between every two sensor modules and the transmission path of the clock are identical can be guaranteed, further, the time difference between the clock and the data is reduced, and the problem of data acquisition failure is avoided.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present application, referring to fig. 3, a schematic diagram of a composition structure of a data acquisition device according to an embodiment of the present application is shown. As shown in fig. 3, the data acquisition device 30 may include a sensor module correspondingly disposed inside each processing unit of the chip, and a plurality of sensor modules are sequentially connected; wherein,

the sensor module is used for receiving the clock signal and the data signal, carrying out data acquisition on the current processing unit, and generating an intermediate data signal according to the acquired data and the data signal; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and

the new clock signal is input as a clock signal to the next stage sensor module, and the new data signal is input as a data signal to the next stage sensor module.

In the embodiment of the application, the data acquisition device can be applied to a chip. For a chip, each chip may include a plurality of processing units inside. In order to obtain parameters such as temperature, process, voltage and the like of each processing unit, a sensor module can be arranged in each processing unit, and the sensor module can be used for not only collecting data of the processing unit, but also synchronously processing the data by using a clock signal.

Specifically, as shown in fig. 3, a plurality of processing units may be denoted by 311, 312, 313, 314, 315, 316, 317, 318, and 319, respectively; wherein, inside the processing unit 311 is provided with a sensor module a, inside the processing unit 312 is provided with a sensor module B, inside the processing unit 313 is provided with a sensor module C, inside the processing unit 314 is provided with a sensor module D, inside the processing unit 315 is provided with a sensor module E, inside the processing unit 316 is provided with a sensor module F, inside the processing unit 317 is provided with a sensor module G, inside the processing unit 318 is provided with a sensor module H, inside the processing unit 319 is provided with a sensor module I.

Here, the sensor modules a, B, C, D, E, F, G, H, I are sequentially connected, so that the collected data obtained by different sensor modules are all summarized together, i.e. finally summarized into the sensor module I. That is, the processing unit in which the sensor module I is located may be regarded as a centralized processing unit (or referred to as a "central processing unit").

It is also noted that in some embodiments, the plurality of sensor modules are connected in series by way of a link. Specifically, in the data acquisition device 30, the sensor modules dispersed to each processing unit can be connected by using a chain structure, so that when the subsequent modules are expanded, only the corresponding sensor modules are required to be added to the head of the link, thereby having better expandability.

Further, for the plurality of sensor modules, the input data signals of the other sensor modules except for the first sensor module are all output data signals of the sensor module of the previous stage until the last sensor module outputs a new data signal. In some embodiments, the new data signal output by the last sensor module may include the respective acquired data for each processing unit of the chip.

It should be noted that, in the embodiment of the present application, for the first sensor module a in fig. 3, the clock signal and the data signal are received, and the data signal may be zero at this time; after the current processing unit 311 performs data acquisition, the generated intermediate data signal represents acquired data corresponding to the processing unit 311; then, the intermediate data signal is sampled by the clock signal, and a new clock signal and a new data signal can be output; alternatively, for the first sensor module a, only the clock signal may be received, and the data signal may be obtained by performing data acquisition on the processing unit 311 where the clock signal is currently located; then, the clock signal is utilized to sample the data signal, so as to obtain a new clock signal and a new data signal; next, the new clock signal is used as the input clock signal of the sensor module B, and the new data signal is used as the input data signal of the sensor module B.

For non-first sensor modules (e.g., sensor module B, sensor module C, sensor module D, sensor module E, sensor module F, sensor module G, sensor module H, sensor module I, etc.) in fig. 3, the clock signal and the data signal provided by the last sensor module may be received; generating an intermediate data signal according to acquired acquisition data and a data signal provided by a last sensor module by acquiring data of a processing unit where the processing unit is currently located, wherein the intermediate data signal comprises acquisition data corresponding to the processing unit where the processing unit is currently located and acquisition data corresponding to a previous processing unit; sampling the intermediate data signal by using a clock signal to obtain a new clock signal and a new data signal; the new clock signal is then used as the input clock signal of the next stage sensor module, the new data signal is used as the input data signal of the next stage sensor module, and the new data signal is output by the last sensor module I. Therefore, as the plurality of sensor modules are connected together, the collected data of all the processing units can be summarized to the position of the last sensor module I, namely, the embodiment of the application can also cause all the collected data to be summarized together, and then the collected data is uniformly processed by the centralized processing unit.

It will be appreciated that, taking a certain sensor module as an example, the input of the sensor module may be a clock signal and a data signal, and the output of the sensor module may be a new clock signal and a new data signal; meanwhile, the new clock signal can be used as the input clock signal of the next-stage sensor module, and the new data signal can be used as the input data signal of the next-stage sensor module.

In some embodiments, for any one sensor module, referring to fig. 4, the sensor module may include an acquisition sensor 411 and a trigger 412; the input end of the trigger 412 is connected to the output end of the acquisition sensor 411, the clock end of the trigger 412 is used for receiving a clock signal, and the output end of the trigger 412 is used for outputting a new data signal;

the acquisition sensor 411 is configured to perform data acquisition on a processing unit where the sensor module is located, so as to obtain acquired data of the processing unit;

a trigger 412 for sampling the intermediate data signal with a clock signal after generating the intermediate data signal from the collected data and the received data signal, and outputting a new data signal; wherein the new data signal is the input data signal of the next stage sensor module.

It should be noted that, in the embodiment of the present application, the acquisition sensor 411 may be a PVT sensor, and is capable of sensing the parameters of the processing unit, such as the process, the voltage, and the temperature. That is, the collected data herein may include at least one of: temperature data, process data, and voltage data.

It should be further noted that, in the embodiment of the present application, the triggering manner of the trigger 412 may include: rising edge triggering or falling edge triggering; wherein,

a flip-flop 412 for sampling the intermediate data signal with the rising edge of the clock signal when the trigger mode is the rising edge trigger, and outputting a new data signal; or,

and a flip-flop 412 for sampling the intermediate data signal by the falling edge of the clock signal when the trigger mode is the falling edge trigger, and outputting a new data signal.

Here, the flip-flop 412 may be a basic unit of a sequential logic circuit for storing 1-bit binary information, having a memory and storage function. Illustratively, the Flip-Flop 412 may be a D-type Flip-Flop (Data Flip-Flop or Delay Flip-Flop, DFF). The trigger has two stable states, namely '0' and '1', and can be turned from one stable state to the other stable state under the action of a certain external signal.

In practice, the flip-flop 412 is usually "triggered" to operate when the rising edge of the clock signal comes, and changes the state of the output signal according to the input signal. In addition, the transitions at the input between two rising edges of the clock signal do not affect the value stored by the flip-flop, but the input must be reserved for sufficient clock setup time before the rising edge comes, to ensure signal stability.

In addition, in the present embodiment, the acquired data is represented in binary. For example, the temperature data may be represented by eight bits (bits) and the voltage data may be represented by four bits. While one flip-flop is required for each bit, there is not only one flip-flop 412, and the number of flip-flops 412 is related to the bit number, only one flip-flop 412 is provided in fig. 4 for illustration.

In a specific implementation, taking fig. 3 as an example, assuming that the collected data corresponding to the processing unit 311 is represented by four bits, the number of triggers in the sensor module a is four; the collected data corresponding to the processing unit 312 is also represented by four bits, and then the number of the triggers in the sensor module B is eight (wherein four triggers are used for data collection of the collected data of the processing unit 311, and the other four triggers are used for data collection of the collected data of the processing unit 312); the collected data corresponding to the processing unit 313 is also represented by four bits, and then twelve triggers are provided in the sensor module C (wherein four triggers are used for data collection of the collected data of the processing unit 311, and the other four triggers are used for data collection of the collected data of the processing unit 312, and the remaining four triggers are used for data collection of the collected data of the processing unit 313); and so on so that at the last sensor module I all the acquired data can be summarized together.

In another specific implementation, still taking fig. 3 as an example, it is assumed that the collected data corresponding to each processing unit is represented by four bits, and the number of triggers in each sensor module is four. In this way, the data acquisition is performed by the four triggers in the sensor module a by the acquired data corresponding to the processing unit 311; in the sensor module B, after the acquired data corresponding to the processing unit 311 and the acquired data corresponding to the processing unit 312 are calculated, the obtained first intermediate data is still represented by four bits, and the four bits of first intermediate data can be acquired by four triggers in the sensor module B; in the sensor module C, after the acquired data corresponding to the processing unit 311, the acquired data corresponding to the processing unit 312 and the acquired data corresponding to the processing unit 313 are calculated, the obtained second intermediate data is still represented by four bits, and the four bits of second intermediate data can be subjected to data acquisition by four triggers in the sensor module C; and so on so that at the last sensor module I, all the acquired data can be summarized together as well.

It should be noted that, in practical applications, the number of triggers in each sensor module may be specifically set according to practical situations, and the embodiments of the present application are not limited in any way.

It will also be appreciated that in embodiments of the present application, for each adjacent two sensor modules, a clock line and a data line are provided between the sensor module and the next stage sensor module. Referring specifically to fig. 3, the bold dashed lines shown in fig. 3 represent clock lines, and the bold solid lines shown in fig. 3 represent data lines. Here, the clock line may be used to transmit a new clock signal output from the sensor module, and the data line may be used to transmit a new data signal output from the sensor module.

To reduce the delay difference between data and clock during transmission, in some embodiments, the transmission distances of the clock lines and the data lines provided between the sensor module and the next stage sensor module are the same.

It should be noted that, for each sensor module, the sensor module may provide separate clock signals and data signals to the next-stage sensor module, so that the transmission distances between the clock lines and the data lines provided between the sensor module and the next-stage sensor module are the same, so that the data transmission delay and the clock transmission delay between every two sensor modules are substantially the same, that is, the transmission delay difference between the data and the clock is very small, and thus, the output of the previous-stage sensor module can be collected for each sensor module.

It should also be noted that although only one data line is shown in fig. 3, this is merely as an illustration. In practical applications, there is not only one data line, and the number of data lines is related to the number of flip-flops, where the output end of each flip-flop is connected to one data line.

It should also be noted that, in the embodiment of the present application, the rising edge of the clock signal of the sensor module is offset from the rising edge of the clock signal of the next sensor module by one clock period, using T _clock And (3) representing. That is, taking the sensor module a and the sensor module B of the next stage as an example, the clock sampling of the data signal and adding the delay of the signal transmission by the sensor module a need to be completed within one clock period before reaching the input end of the sensor module B.

In addition, different sensor modules may use different clock domains. In other words, sensor module a may use the clock signal generated by the clock generation circuit, while sensor module B may use the new clock signal provided by sensor module a, sensor module C may use the new clock signal provided by sensor module B, sensor module D may use the new clock signal provided by sensor module C, and so on. The new clock signal provided by each sensor module may be different from each other, or may be generated by a clock generating circuit, but the rising edges of the clock signals are sequentially staggered by one clock period, which is not limited in this embodiment of the present application.

Further, in some embodiments, on the basis of the data acquisition device 30 shown in fig. 3, referring to fig. 5, a combinational logic module is further disposed on a data line between the sensor module and the next-stage sensor module, where an input end of the combinational logic module is connected to an output end of the sensor module, and an output end of the combinational logic module is connected to an input end of the next-stage sensor module;

and the combination logic module is used for receiving the new data signals output by the sensor module, carrying out combination logic processing on the new data signals to obtain processed data signals, and taking the processed data signals as input data signals of the next-stage sensor module.

It should be noted that, in the embodiment of the present application, since the data signal may be represented in binary, that is, the data line is not only one, the combination logic module may perform the combination logic on the data signal to generate the processed signal to be provided to the input terminal of the next stage sensor module. The combination logic module may be composed of logic gates such as an or gate and a nor gate.

It should be further noted that, as shown in fig. 5, the data acquisition device 30 may include a plurality of combinational logic modules, and one combinational logic module is disposed on a data line between every two sensor modules. Specifically, the plurality of combinational logic modules may be denoted by 11, 12, 13, 14, 15, 16, 17, 18, respectively, wherein the combinational logic module 11 is provided between the sensor module a and the sensor module B, the combinational logic module 12 is provided between the sensor module B and the sensor module C, the combinational logic module 13 is provided between the sensor module C and the sensor module D, the combinational logic module 14 is provided between the sensor module D and the sensor module E, the combinational logic module 15 is provided between the sensor module E and the sensor module F, the combinational logic module 16 is provided between the sensor module F and the sensor module G, the combinational logic module 17 is provided between the sensor module G and the sensor module H, and the combinational logic module 18 is provided between the sensor module H and the sensor module I.

Further, in some embodiments, the delay time on the data line between the output of the sensor module and the input of the next stage sensor module is less than the difference between the preset clock period and the clock setup time.

In an embodiment of the present application, a delay time of a new data signal on a data line between an output end of a sensor module and an input end of a next stage sensor module may include: the path delay time between the output end of the sensor module and the input end of the combinational logic module, the delay time required by the combinational logic module to execute combinational logic processing, and the path delay time between the output end of the combinational logic module and the input end of the next-stage sensor module. That is, in a specific embodiment, the sum of the path delay time between the output of the sensor module and the input of the combinational logic module, the delay time required for the combinational logic module to perform combinational logic processing, and the path delay time between the output of the combinational logic module and the input of the next stage sensor module is smaller than the difference between the preset clock period and the clock setup time.

It should be noted that the preset clock period is a new clock period of the clock signal, and T can be used _clock A representation; the clock set-up time represents the time when a new data signal needs to reach the input end of the next stage sensor module in advance compared with the new clock signal, and can be T _setup And (3) representing. In a specific embodiment, T _setup It may be indicated that the new data signal needs to arrive at the input of the next stage sensor module in advance before the rising edge of the new clock signal arrives at the input of the next stage sensor module.

Thus, for the input clock signal and the input data signal of each sensor module, the data signal at the input must be reserved for a sufficient clock set-up time before the rising edge of the clock signal can occur. That is, for the input data signal of each sensor module, the transmission delay between the output of the previous sensor module and the input of the current sensor module is smaller than the difference between the preset clock period and the clock set-up time, so that the output of the previous sensor module which can be collected by each sensor module can be ensured, the data collection is stable, and the problem of data collection failure is avoided.

The embodiment of the application provides a data acquisition device, in which a plurality of sensor modules are connected in sequence. The sensor module is used for receiving the clock signal and the data signal, carrying out data acquisition on the current processing unit, and generating an intermediate data signal according to the acquired data and the data signal; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and inputting the new clock signal as a clock signal to the next stage sensor module, and inputting the new data signal as a data signal to the next stage sensor module. In this way, the sensor modules are sequentially connected in a link mode, so that not only can all collected data be summarized together, but also the data collection is stable, flexible and strong, and the system has better expandability; in addition, each sensor module can provide independent clock signals and data signals to be transmitted to the next-stage sensor module, so that wiring complexity can be reduced, meanwhile, the fact that data between every two sensor modules and the transmission path of the clock are identical can be guaranteed, further, the time difference between the clock and the data is reduced, and the problem of data acquisition failure is avoided.

In another embodiment of the present application, based on the data acquisition device 30 described in the foregoing embodiment, the embodiment of the present application proposes a policy of ring data transmission, as shown in fig. 3 or fig. 5, where the line indicated by the bold dashed line is a clock line, the line indicated by the bold solid line is a data line, and each sensor module may individually send a clock signal and a data signal to the sensor module of the next stage, so that each sensor module may be connected together, and finally, all data may be summarized to the last sensor module (i.e. the central processing module), as shown by the sensor module I in fig. 3 or fig. 5. Because each sensor module can be transmitted into the sensor module of the next stage by the independent clock signal and data, the transmission distance of the clock line and the data line is the same, and the time delay between every two sensor modules is the same, so that the output of the sensor module of the last stage can be acquired for each sensor module. The sensor module may include a PVT sensor for acquiring data such as temperature and voltage, and a trigger for synchronizing the data with a clock.

By adopting the technical scheme of the embodiment of the application, the acquired PVT data is the same as the transmission path of the clock, so that the delay can be counteracted, the delay difference between the PVT data and the clock in the transmission process is reduced, and the data acquisition is stable.

In short, considering that the real-time requirement of data interaction of the PVT sensors is not high, and each PVT sensor is distributed at each position inside the chip, the distance between the PVT sensors is long, if centralized communication is used for data collection, the problems of complex back-end wiring, data collection failure and the like can be encountered, so that the sensor modules distributed at each position are connected by using a chain structure, and each stage of the chain can use different clock domains; in the data transmission process, the distances between the clock lines and the data lines between every two sensor modules are the same, so that the delay difference is very small, and the data is stable when collected by the sensor modules.

The embodiment provides a data acquisition device, and detailed explanation is made on specific implementation of the foregoing embodiment, so that through the technical scheme of the foregoing embodiment, the connection of the PVT sensor is performed by using a link, so that data acquisition is stable, flexibility is high, and expandability is good, and only a corresponding sensor module is required to be added at the head of the link; in addition, the wiring complexity can be reduced because only one set of data lines and clock lines are used between every two sensor modules.

In yet another embodiment of the present application, referring to fig. 6, a flow chart of a data acquisition method provided in the embodiment of the present application is shown based on the data acquisition device 30 described in the foregoing embodiment. As shown in fig. 6, the method may include:

s601: receiving clock signals and data signals through a sensor module, carrying out data acquisition on a current processing unit, and generating intermediate data signals according to acquired data and data signals; and carrying out data acquisition on the data signals by using the clock signals, and outputting new clock signals and new data signals.

S602: and judging whether the sensor module is the last sensor module in the link.

S603: if the determination result is no, the new clock signal is input as the clock signal to the next stage sensor module, the new data signal is input as the data signal to the next stage sensor module, and the process returns to continue to step S601.

S604: if the judgment result is yes, outputting a new clock signal and a new data signal through the last sensor module.

It should be noted that, the method described in the embodiments of the present application is applied to the data acquisition device described in the foregoing embodiments, where the data acquisition device may include a plurality of processing units and a sensor module correspondingly disposed inside each processing unit, and the plurality of sensor modules are sequentially connected.

It should be further noted that, in the embodiment of the present application, after the plurality of sensor modules are sequentially connected, the sensor modules and the next-stage sensor module are described in detail, which may specifically include: receiving clock signals and data signals through a sensor module, carrying out data acquisition on a current processing unit, and generating intermediate data signals according to acquired data and data signals; data acquisition is carried out on the data signals by using the clock signals, and new clock signals and new data signals are output; and inputting a new clock signal as a clock signal to the next-stage sensor module, inputting a new data signal as a data signal to the next-stage sensor module, and cyclically executing the steps of receiving the clock signal and the data signal through the next-stage sensor module and outputting the new clock signal and the new data signal until the last sensor module connected in sequence outputs the new clock signal and the new data signal.

In some embodiments, the method may further comprise: the plurality of sensor modules are sequentially connected in the form of a link.

Specifically, in the data acquisition device, the sensor modules distributed to each processing unit can be connected by using a chain structure, so that when the subsequent modules are expanded, the corresponding sensor modules are only required to be added to the head of the link, and the data acquisition device has better expandability. Therefore, as the plurality of sensor modules are connected together, collected data of all processing units can be collected to the last sensor module, namely, according to the embodiment of the application, all the collected data can be collected together, and then unified processing is performed by the centralized processing unit.

In some embodiments, for any one sensor module, the sensor module may include an acquisition sensor and a trigger. Thus, for S601, this step may include:

the data acquisition is carried out on the processing unit where the sensor module is located through the acquisition sensor, so that acquisition data of the processing unit are obtained;

after generating an intermediate data signal according to the acquired data and the received data signal, sampling the intermediate data signal by using a clock signal through a trigger, and outputting a new data signal; wherein the new data signal is the input data signal of the next stage sensor module.

It should be noted that, in the embodiment of the present application, the acquisition sensor may be a PVT sensor, which is capable of sensing the parameters such as the process, the voltage, and the temperature of the processing unit. That is, the collected data herein may include at least one of: temperature data, process data, and voltage data.

It should be further noted that, in the embodiment of the present application, the triggering manner of the trigger may include: rising edge triggering or falling edge triggering. Accordingly, in some embodiments, outputting a new data signal by sampling the intermediate data signal with the clock signal by the flip-flop may include:

When the trigger mode of the trigger is rising edge triggering, sampling the intermediate data signal by utilizing the rising edge of the clock signal, and outputting a new data signal; or,

when the trigger mode of the trigger is falling edge triggering, the intermediate data signal is sampled by the falling edge of the clock signal, and a new data signal is output.

In practical applications, a flip-flop is usually "triggered" to operate when a rising edge of a clock signal arrives, and changes the state of an output signal according to an input signal. In addition, the transitions at the input between two rising edges of the clock signal do not affect the value stored by the flip-flop, but the input must be reserved for sufficient clock setup time before the rising edge comes, to ensure signal stability.

In addition, in the present embodiment, the acquired data is represented in binary. For example, the temperature data may be represented by eight bits and the voltage data may be represented by four bits. While one flip-flop is required for each bit, there is not only one flip-flop, and the number of flip-flops is related to the bit number, and only one flip-flop 412 is provided in fig. 4 as described above for illustration. That is, in practical application, the number of triggers in each sensor module may be specifically set according to practical situations, and the embodiment of the present application is not limited in any way.

Further, a clock line and a data line are arranged between the sensor module and the next-stage sensor module, wherein the clock line can be used for transmitting a new clock signal output by the sensor module, and the data line can be used for transmitting a new data signal output by the sensor module. Accordingly, in some embodiments, the transmission distances of the clock lines and the data lines provided between the sensor module and the next stage sensor module are the same.

It should be noted that, for each sensor module, the sensor module may provide separate clock signals and data signals to the next-stage sensor module, so that the transmission distances between the clock lines and the data lines provided between the sensor module and the next-stage sensor module are the same, so that the data transmission delay and the clock transmission delay between every two sensor modules are substantially the same, that is, the transmission delay difference between the data and the clock is very small, and thus, the output of the previous-stage sensor module can be collected for each sensor module.

Further, a combinational logic module can be further arranged on a data line between the sensor module and the next-stage sensor module. Accordingly, in some embodiments, the method may further comprise:

The new data signals output by the sensor modules are received through the combinational logic module, combinational logic processing is carried out on the new data signals, processed data signals are obtained, and the processed data signals are used as input data signals of the next-stage sensor modules.

On the data line, the input end of the combinational logic module is connected with the output end of the sensor module, and the output end of the combinational logic module is connected with the input end of the next stage sensor module. Here, since the data signal is represented in binary, i.e., there is not only one data line, it is combined by the combinational logic module to generate a processed signal to be provided to the input of the next stage sensor module.

In some embodiments, a sum of a path delay time between an output of the sensor module to an input of the combinational logic module, a delay time required for the combinational logic module to perform combinational logic processing, and a path delay time between an output of the combinational logic module to an input of a next stage sensor module is less than a difference between a preset clock period and a clock setup time.

It should be noted that, the preset clock period is a new clock period of the clock signal, and T may be used _clock A representation; the clock set-up time represents the time when a new data signal needs to reach the input end of the next stage sensor module in advance compared with the new clock signal, and can be T _setup And (3) representing. In a specific embodiment, T _setup It may be indicated that the new data signal needs to arrive at the input of the next stage sensor module in advance before the rising edge of the new clock signal arrives at the input of the next stage sensor module.

Thus, for the input clock signal and the input data signal of each sensor module, the data signal at the input must be reserved for a sufficient clock set-up time before the rising edge of the clock signal can occur. That is, for the input data signal of each sensor module, the transmission delay between the output of the previous sensor module and the input of the current sensor module is smaller than the difference between the preset clock period and the clock setup time, so that the output of the previous sensor module which can be collected by each sensor module can be ensured, and the data collection is stable when the sensor module performs the data collection.

The embodiment of the application provides a data acquisition method, in which a plurality of sensor modules are connected in sequence. Receiving clock signals and data signals through a sensor module, carrying out data acquisition on a current processing unit, and generating intermediate data signals according to acquired data and data signals; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and inputting a new clock signal as a clock signal to the next-stage sensor module, inputting a new data signal as a data signal to the next-stage sensor module, and cyclically executing the steps of receiving the clock signal and the data signal through the next-stage sensor module and outputting the new clock signal and the new data signal until the last sensor module connected in sequence outputs the new clock signal and the new data signal. In this way, the sensor modules are sequentially connected in a link mode, so that not only can all collected data be summarized together, but also the data collection is stable, flexible and strong, and the system has better expandability; in addition, each sensor module can provide independent clock signals and data signals to be transmitted to the next-stage sensor module, so that wiring complexity can be reduced, meanwhile, the fact that data between every two sensor modules and the transmission path of the clock are identical can be guaranteed, further, the time difference between the clock and the data is reduced, and the problem of data acquisition failure is avoided.

In yet another embodiment of the present application, reference is made to fig. 7, which shows a schematic diagram of the composition structure of a chip provided in an embodiment of the present application. As shown in fig. 7, the chip 70 may include a plurality of processing units and the data acquisition device 30 described in the previous embodiments. Wherein, referring specifically to fig. 7, the plurality of processing units may include processing unit 1, processing unit 2, …, processing unit n, n being an integer greater than 1.

In the embodiment of the present application, for the chip 70, a plurality of processing units, such as the processing unit 1, the processing units 2, …, the processing unit n, and the like, may be obtained based on a preset division rule. In order to obtain parameters such as temperature, process, voltage and the like of each processing unit, a sensor module can be arranged in each processing unit, and the sensor module can be used for not only collecting data of the processing unit, but also synchronously processing the data by using a clock signal.

In the embodiment of the present application, for the chip 70, the plurality of sensor modules may also be connected by a link, so that data acquisition is stable and flexible, and expandability is better, and only a corresponding sensor module needs to be added to the head of the link; in addition, the wiring is simpler because only one set of data line and clock line is used between every two sensor modules.

In yet another embodiment of the present application, reference is made to fig. 8, which shows a schematic diagram of the composition structure of an electronic device provided in an embodiment of the present application. As shown in fig. 8, the electronic device 80 may include a plurality of processing units (specifically, the processing unit 1, the processing units 2, …, the processing unit n) and the data collection apparatus 30 described in the foregoing embodiments.

In yet another embodiment of the present application, reference is made to fig. 9, which shows a schematic diagram of the composition structure of another electronic device provided in an embodiment of the present application. As shown in fig. 9, the electronic device 80 may include the chip 70 described in the previous embodiments.

In the embodiment of the present application, for the electronic device 80, since the chip 70 is included therein, and the chip 70 includes a plurality of processing units and sensor modules correspondingly disposed inside each processing unit, the plurality of sensor modules are sequentially connected in a link manner; therefore, not only can all the acquired data be summarized together, but also the data acquisition is stable, flexible and strong, and has better expandability; in addition, each sensor module can provide independent clock signals and data signals to be transmitted to the next-stage sensor module, so that wiring complexity can be reduced, meanwhile, the fact that data between every two sensor modules and the transmission path of the clock are identical can be guaranteed, further, the time difference between the clock and the data is reduced, and the problem of data acquisition failure is avoided.

It should be noted that, in this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present application may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present application may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present application may be arbitrarily combined without conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (16)

1. The data acquisition device is applied to a chip and is characterized by comprising a sensor module which is correspondingly arranged in each processing unit of the chip, and a plurality of sensor modules are connected in sequence; wherein,

the sensor module is used for receiving clock signals and data signals, carrying out data acquisition on the current processing unit, and generating intermediate data signals according to the acquired data and the data signals; sampling the intermediate data signal by using the clock signal to output a new clock signal and a new data signal; and

and the new clock signal is used as a clock signal to be input into the sensor module at the next stage, and the new data signal is used as a data signal to be input into the sensor module at the next stage.

2. The data acquisition device of claim 1, wherein a plurality of the sensor modules are sequentially connected in the form of a link.

3. The data acquisition device of claim 1, wherein the new data signal output by the last sensor module comprises the respective acquired data for each processing unit of the chip.

4. The data acquisition device of claim 1, wherein the sensor module comprises an acquisition sensor and a trigger, wherein an input of the trigger is connected to an output of the acquisition sensor, a clock of the trigger is configured to receive the clock signal, and an output of the trigger is configured to output the new data signal;

the acquisition sensor is used for acquiring data of the processing unit where the sensor module is located, so as to obtain acquisition data of the processing unit;

the trigger is used for sampling the intermediate data signal by utilizing the clock signal after generating the intermediate data signal according to the acquired data and the received data signal, and outputting a new data signal; wherein the new data signal is an input data signal of the sensor module of the next stage.

5. The data acquisition device of claim 4, wherein the trigger means of the trigger comprises: rising edge triggering or falling edge triggering; wherein,

the trigger is used for sampling the intermediate data signal by utilizing the rising edge of the clock signal when the trigger mode is rising edge trigger and outputting the new data signal; or,

and the trigger is used for sampling the intermediate data signal by utilizing the falling edge of the clock signal when the trigger mode is falling edge trigger and outputting the new data signal.

6. The data acquisition device of claim 4, wherein the acquisition sensor is a PVT sensor; wherein the acquired data includes at least one of: temperature data, process data, and voltage data.

7. The data acquisition device according to any one of claims 1 to 6, wherein a clock line and a data line are provided between the sensor module and the sensor module of the next stage, the clock line being used for transmitting the new clock signal output by the sensor module, and the data line being used for transmitting the new data signal output by the sensor module; wherein,

The transmission distance between the clock line and the data line arranged between the sensor module and the sensor module at the next stage is the same.

8. The data acquisition device according to claim 7, wherein a combinational logic module is further arranged on a data line between the sensor module and the sensor module at the next stage, wherein an input end of the combinational logic module is connected with an output end of the sensor module, and an output end of the combinational logic module is connected with an input end of the sensor module at the next stage;

the combination logic module is used for receiving the new data signals output by the sensor module, carrying out combination logic processing on the new data signals to obtain processed data signals, and taking the processed data signals as input data signals of the sensor module of the next stage.

9. The data acquisition device of claim 8, wherein a sum of a path delay time between an output of the sensor module and an input of the combinational logic module, a delay time required for the combinational logic module to perform combinational logic processing, and a path delay time between an output of the combinational logic module and an input of the sensor module at a next stage is smaller than a difference between a preset clock period and a clock setup time;

The preset clock period is a clock period of the new clock signal, and the clock establishment time represents a time when the new data signal needs to reach the input end of the sensor module of the next stage in advance compared with the new clock signal.

10. The data acquisition method is characterized by being applied to a data acquisition device, wherein the data acquisition device comprises a sensor module which is correspondingly arranged in each processing unit of a chip, and a plurality of sensor modules are connected in sequence; the method comprises the following steps:

receiving a clock signal and a data signal through the sensor module, carrying out data acquisition on the current processing unit, and generating an intermediate data signal according to the acquired data and the data signal; the clock signal is utilized to carry out data acquisition on the data signal, and a new clock signal and a new data signal are output; and

and inputting the new clock signal as a clock signal to the next stage of sensor module, inputting the new data signal as a data signal to the next stage of sensor module, and circularly executing the steps of receiving the clock signal and the data signal and outputting the new clock signal and the new data signal through the next stage of sensor module until the last sensor module connected in sequence outputs the new clock signal and the new data signal.

11. The method of claim 10, wherein the sensor module comprises an acquisition sensor and a trigger, the current processing unit performs data acquisition, and an intermediate data signal is generated according to the acquired acquisition data and the data signal; and performing data acquisition on the data signal by using the clock signal, and outputting a new clock signal and a new data signal, wherein the data acquisition comprises the following steps:

the data acquisition is carried out on the processing unit where the sensor module is located through the acquisition sensor, so that acquisition data of the processing unit are obtained;

after generating an intermediate data signal according to the acquired data and the received data signal, sampling the intermediate data signal by using the clock signal through the trigger, and outputting a new data signal; wherein the new data signal is an input data signal of the sensor module of the next stage.

12. The method of claim 11, wherein the triggering of the trigger comprises: a rising edge trigger or a falling edge trigger, wherein the sampling processing is performed on the intermediate data signal by the trigger by using the clock signal, and a new data signal is output, which includes:

When the trigger mode of the trigger is rising edge trigger, sampling the intermediate data signal by utilizing the rising edge of the clock signal, and outputting the new data signal; or,

and when the trigger mode of the trigger is falling edge trigger, sampling the intermediate data signal by utilizing the falling edge of the clock signal, and outputting the new data signal.

13. The method of claim 11, wherein the acquisition sensor is a PVT sensor; wherein the acquired data includes at least one of: temperature data, process data, and voltage data.

14. The method according to claim 10, wherein the method further comprises:

and sequentially connecting a plurality of sensor modules in a link mode.

15. A chip comprising a plurality of processing units and a data acquisition device according to any one of claims 1 to 9.

16. An electronic device comprising the chip of claim 15.