CN117616585A

CN117616585A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN117616585A
Application number: CN202280049794.3A
Authority: CN
Inventors: 斋藤暁; 高桥正弘; 奥野直树; 马场晴之; 国武寛司; 山崎舜平
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2021-07-21
Filing date: 2022-07-08
Publication date: 2024-02-27

Abstract

A semiconductor device in which the non-uniformity of the electrical characteristics of a transistor is small is provided. The semiconductor device includes: oxide, first conductor, second conductor and first insulator on oxide, second insulator on first conductor and second conductor, third insulator on first insulator, third conductor on third insulator, and fourth insulator on second insulator and third conductor. The fourth insulator is in contact with the top surface of the second insulator and the top surface of the third conductor. The first insulator has regions respectively contacting the top surface of the oxide, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator. The oxide comprises indium, gallium, aluminum, and zinc. The first insulator and the fourth insulator both include aluminum and oxygen. The fourth insulator has an amorphous structure. The oxide has a concentration gradient in which the concentration of aluminum becomes higher from the bottom surface of the oxide to the top surface of the oxide.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Technical Field

One embodiment of the present invention relates to a method for producing a metal oxide. Further, one embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Further, one embodiment of the present invention relates to a method for manufacturing a semiconductor device. Further, one embodiment of the present invention relates to a semiconductor wafer and a module.

Note that in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, or a memory device is one embodiment of a semiconductor device. Display devices (liquid crystal display devices, light-emitting display devices, and the like), projection devices, illumination devices, electro-optical devices, power storage devices, semiconductor circuits, imaging devices, electronic devices, and the like may include semiconductor devices.

Note that one embodiment of the present invention is not limited to the above-described technical field. One embodiment of the disclosed invention in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product, or a composition (composition of matter).

Background

In recent years, semiconductor devices have been developed, and LSI, CPU, memory, and the like are mainly used. The CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit (including at least a transistor and a memory) formed by processing a semiconductor wafer to form a chip, and formed with electrodes serving as connection terminals.

A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board (e.g., a printed wiring board), and is used as one of the components of various electronic devices.

In addition, a technique of forming a transistor by using a semiconductor thin film formed over a substrate having an insulating surface is attracting attention. Such a transistor is widely used in electronic devices such as an Integrated Circuit (IC) and an image display device (simply referred to as a display device). As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known. As other materials, oxide semiconductors are attracting attention.

In addition, it is known that a leakage current of a transistor using an oxide semiconductor is extremely small in a non-conductive state. For example, patent document 1 discloses a low power consumption CPU or the like that uses a characteristic of low leakage current of a transistor using an oxide semiconductor. Further, for example, patent document 2 discloses a memory device or the like that realizes long-term retention of memory contents by utilizing the characteristic of low leakage current of a transistor using an oxide semiconductor.

In recent years, with miniaturization and weight reduction of electronic devices, demands for further higher density of integrated circuits have been increasing. In addition, there is a need to improve productivity of semiconductor devices including integrated circuits.

[ Prior Art literature ]

[ patent literature ]

[ patent document 1] Japanese patent application laid-open No. 2012-257187

[ patent document 2] Japanese patent application laid-open No. 2011-151383 ]

Disclosure of Invention

Technical problem to be solved by the invention

An object of one embodiment of the present invention is to provide a semiconductor device in which non-uniformity in electrical characteristics of a transistor is small. An object of one embodiment of the present invention is to provide a semiconductor device with excellent reliability. An object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. An object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. An object of one embodiment of the present invention is to provide a semiconductor device capable of performing multipoint measurement.

Note that the description of these objects does not hinder the existence of other objects. Note that one embodiment of the present invention is not required to achieve all of the above objects. Objects other than the above objects are apparent from and can be extracted from the description of the specification, drawings, claims, and the like.

Means for solving the technical problems

One embodiment of the present invention is a semiconductor device including an oxide, a first conductor over the oxide, a second conductor and a first insulator, a second insulator over the first conductor and the second conductor, a third insulator over the first insulator, a third conductor over the third insulator, and a fourth insulator over the second insulator and the third conductor. The fourth insulator is in contact with the top surface of the second insulator and the top surface of the third conductor. The first insulator has regions respectively contacting the top surface of the oxide, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator. The oxide comprises indium, gallium, aluminum, and zinc. The first insulator and the fourth insulator both include aluminum and oxygen. The fourth insulator has an amorphous structure. The oxide has a concentration gradient in which the concentration of aluminum becomes higher from the bottom surface of the oxide to the top surface of the oxide.

In the above semiconductor device, it is preferable that the fourth insulator includes a first laminate including a first layer and a second layer on the first layer, and the first layer has a region having a film thickness of 3.0nm or more and 8.0nm or less.

In the semiconductor device, it is preferable that the first conductor and the second conductor each include a second laminate, the second laminate include a third layer and a fourth layer on the third layer, the third layer and the fourth layer each include tantalum and nitrogen, and the third layer has a region having a film thickness of 1.0nm or more and 3.0nm or less. Further, it is more preferable that the fourth layer has a region having higher conductivity than the third layer.

One embodiment of the present invention is a semiconductor device including an oxide, a first conductor over the oxide, a second conductor and a first insulator, a second insulator over the first conductor and the second conductor, a third insulator over the first insulator, a third conductor over the third insulator, a fourth insulator over the second insulator and the third conductor, and a fourth conductor and a fifth insulator under the oxide. The fourth insulator is in contact with the top surface of the second insulator and the top surface of the third conductor. The first insulator has regions respectively contacting the top surface of the oxide, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator. The fourth conductor has a region overlapping the third conductor with an oxide interposed therebetween. The fifth insulator is located between the fourth conductor and the oxide. The oxide comprises indium, gallium, aluminum, and zinc. The first insulator and the fourth insulator both include aluminum and oxygen. The fourth insulator has an amorphous structure. The oxide has a concentration gradient in which the concentration of aluminum becomes higher from the bottom surface of the oxide to the top surface of the oxide.

In the semiconductor device, it is preferable that the first conductor and the second conductor each include a second laminate, the second laminate include a third layer and a fourth layer on the third layer, the third layer and the fourth layer each include tantalum and nitrogen, and the third layer has a region having a film thickness of 1.0nm or more and 3.0nm or less.

One embodiment of the present invention is a semiconductor device including an oxide, a first conductor over the oxide, a second conductor and a first insulator, a second insulator over the first conductor and the second conductor, a third insulator over the first insulator, a third conductor over the third insulator, and a fourth insulator over the second insulator and the third conductor. The fourth insulator is in contact with the top surface of the second insulator and the top surface of the third conductor. The first insulator has regions respectively contacting the top surface of the oxide, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator. The oxide includes a first metal oxide layer and a second metal oxide layer over the first metal oxide layer. The first metal oxide layer contains at least one of indium, elemental Mb, and zinc. The second metal oxide layer contains aluminum and at least one of indium, elemental Mb, and zinc. The element Mb is one or more selected from gallium, yttrium and tin. The first insulator and the fourth insulator both include aluminum and oxygen. The fourth insulator has an amorphous structure. The oxide has a concentration gradient in which the concentration of aluminum becomes higher from the bottom surface of the oxide to the top surface of the oxide.

Effects of the invention

According to one embodiment of the present invention, a semiconductor device in which non-uniformity in electrical characteristics of a transistor is small can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device capable of performing multipoint measurement can be provided.

Note that the description of these effects does not hinder the existence of other effects. Furthermore, one embodiment of the present invention need not have all of the above effects. Further, it is apparent that effects other than the above-described effects exist in the descriptions of the specification, drawings, claims, and the like, and effects other than the above-described effects can be obtained from the descriptions of the specification, drawings, claims, and the like.

Brief description of the drawings

Fig. 1A is a plan view of a semiconductor device according to an embodiment of the present invention. Fig. 1B to 1D are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 2A and 2B are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view of a transistor for use in the calculation.

Fig. 4A and 4B are diagrams showing calculation results.

Fig. 5A is a diagram showing a calculation model shown in the present embodiment. Fig. 5B is a diagram showing the calculation result shown in the present embodiment.

Fig. 6A and 6B are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 7A to 7D are schematic diagrams of aluminum concentration distribution in metal oxide.

Fig. 8A to 8C are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 9A and 9B are energy band diagrams.

Fig. 10A to 10E are diagrams showing the calculation model shown in the present embodiment. Fig. 10F is a diagram showing the calculation result shown in the present embodiment.

Fig. 11A is a plan view of a semiconductor device according to an embodiment of the present invention. Fig. 11B to 11D are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 12A is a plan view of a semiconductor device according to an embodiment of the present invention. Fig. 12B to 12D are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 13A is a plan view of a semiconductor device according to an embodiment of the present invention. Fig. 13B to 13D are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 14A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 15A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 16A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 17A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 18A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 19A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 19B to 19D are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 20A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 21A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 22A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 22B to 22D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 23A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 23B to 23D are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 24A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 25A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 25B to 25D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 26 is a plan view illustrating a microwave processing apparatus according to an embodiment of the present invention.

Fig. 27 is a cross-sectional view illustrating a microwave processing apparatus according to an embodiment of the present invention.

Fig. 28 is a cross-sectional view illustrating a microwave processing apparatus according to an embodiment of the present invention.

Fig. 29 is a sectional view illustrating a microwave processing apparatus according to an embodiment of the present invention.

Fig. 30A is a plan view of a semiconductor device according to an embodiment of the present invention. Fig. 30B and 30C are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 31 is a circuit diagram of the semiconductor device.

Fig. 32A is a perspective view of the semiconductor device. Fig. 32B is a perspective view illustrating the structure of the semiconductor device.

Fig. 33 is a cross-sectional view showing the structure of a memory device according to an embodiment of the present invention.

Fig. 34 is a cross-sectional view showing the structure of a memory device according to an embodiment of the present invention.

Fig. 35 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 36A and 36B are cross-sectional views of a semiconductor device according to an embodiment of the present invention.

Fig. 37 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 38A is a block diagram showing a configuration example of a memory device according to an embodiment of the present invention. Fig. 38B is a perspective view showing a configuration example of a memory device according to an embodiment of the present invention.

Fig. 39A to 39H are circuit diagrams showing a configuration example of a memory device according to an embodiment of the present invention.

Fig. 40A and 40B are schematic views of a semiconductor device according to an embodiment of the present invention.

Fig. 41A and 41B are diagrams illustrating an example of the electronic component.

Fig. 42A to 42E are schematic views of a memory device according to an embodiment of the present invention.

Fig. 43A to 43H are diagrams showing an electronic device according to an embodiment of the present invention.

Fig. 44 is a graph illustrating the film thickness dependence of the oxygen release amount on the silicon oxide film.

Fig. 45A is a view illustrating a cross-sectional STEM image of an aluminum oxide film. Fig. 45B is a diagram illustrating the film thickness of a cross section of an aluminum oxide film.

Fig. 46A is a diagram illustrating a stacked structure of stacked films. Fig. 46B shows the SIMS analysis result of the laminated film.

Fig. 47A is a diagram illustrating the structure of an aluminum oxide film. Fig. 47B is a graph illustrating the dependence of the oxygen release amount on the structure of the aluminum oxide film.

Fig. 48A is a cross-sectional STEM image of a sample fabricated in the example. Fig. 48B and 48C show EDX analysis results of samples manufactured in examples.

Fig. 49A to 49C show SIMS analysis results of samples manufactured in examples.

Fig. 50 is a plan view, a cross-sectional TEM image, and a diagram showing the TEG manufactured in the embodiment.

Fig. 51A and 51B show Id-Vg characteristics of transistors manufactured in the embodiments.

Fig. 52A and 52B show cumulative probability distributions of Vth of the transistors fabricated in the embodiments.

Fig. 53A to 53C show Id-Vg characteristics of transistors manufactured in the embodiments.

Fig. 54A to 54C show cumulative probability distributions of Vth of the transistors manufactured in the embodiments.

Fig. 55A to 55C are graphs showing the relationship of Vth versus Id-Vg characteristics of the transistors fabricated in the embodiments.

Fig. 56A shows Id-Vg characteristics of a transistor manufactured in the embodiment. Fig. 56B shows the cumulative probability distribution of Vth of the transistor manufactured in the embodiment.

Fig. 57A shows Id-Vg characteristics of a transistor manufactured in the embodiment. Fig. 57B shows the cumulative probability distribution of Vth of the transistor manufactured in the embodiment.

Fig. 58A to 58C are graphs showing the relationship of Vth versus Id-Vg characteristics of the transistors fabricated in the embodiments.

Fig. 59A1 to 59C2 are cross-sectional TEM images taken in the embodiment.

Fig. 60A1 to 60B2 are cross-sectional TEM images taken in the embodiment.

Fig. 61 is a diagram illustrating the film thickness of each film before the heat treatment and the film thickness of each film after the heat treatment.

Fig. 62A is a diagram illustrating a stacked structure of a sample. Fig. 62B is a diagram illustrating sheet resistance of metal oxide.

Fig. 63A to 63C show Id-Vg characteristics of transistors manufactured in the embodiment. Fig. 63D to 63F are cross-sectional TEM images of transistors fabricated in the embodiments.

Fig. 64A and 64B show Id-Vg characteristics of transistors. Fig. 64C is a schematic cross-sectional view of a transistor manufactured in the embodiment.

Fig. 65 is a diagram illustrating stress of the conductor formed in the embodiment.

Fig. 66 is a diagram illustrating a relationship between Ion and stress of a transistor.

Fig. 67 is a diagram illustrating a relationship between the on-state current and the ratio of the area of the channel formation region with respect to the area of the source electrode or the drain electrode.

Fig. 68A is a diagram illustrating a stacked structure of a sample. Fig. 68B is a diagram illustrating the results of SIMS analysis.

Fig. 69A shows an Id-Vg characteristic of a transistor. Fig. 69B is a schematic diagram concerning oxygen supply to a metal oxide.

Fig. 70A and 70B are planar TEM images of metal oxides. Fig. 70C and 70D are FFT images.

Fig. 71 shows Id-Vg characteristics of transistors manufactured in the examples.

Fig. 72 shows Id-Vg characteristics of transistors manufactured in the examples.

Fig. 73A and 73B are diagrams showing Vth of a transistor.

Fig. 74A to 74D are histograms of Vth, S value, gm, and Ion of the transistors.

Fig. 75A is a schematic diagram of the structure of a fabricated transistor. Fig. 75B is a cross-sectional view of a channel width direction of a transistor to be manufactured.

Fig. 76A and 76B show drain current-top gate voltage characteristics of the fabricated transistors.

Fig. 77A and 77B show drain current-top gate voltage characteristics of the transistors that are manufactured in advance.

Fig. 78A and 78B are diagrams illustrating the capacitance. Fig. 78C and 78D show top gate voltage-capacitance characteristics of the fabricated transistors.

Modes for carrying out the invention

The embodiments will be described below with reference to the drawings. It is noted that one of ordinary skill in the art can easily understand the fact that the embodiments may be implemented in a plurality of different forms, and that the manner and details thereof may be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

In the drawings, the size, thickness of layers, or regions are sometimes exaggerated for clarity. Accordingly, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the present invention is not limited to the shapes, numerical values, and the like shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally thinned due to processing such as etching, but may not be reflected in the drawings for ease of understanding. In the drawings, the same reference numerals are used in common between the different drawings to denote the same parts or parts having the same functions, and a repetitive description thereof may be omitted. In addition, the same hatching is sometimes used when representing portions having the same function, and no reference numerals are particularly attached.

In particular, in a plan view (also referred to as a plan view) or a perspective view, some components may be omitted to facilitate understanding of the present invention. In addition, a description of a partially hidden line or the like may be omitted.

In this specification and the like, for convenience, first, second, and the like ordinal numbers are appended, and do not indicate the order of steps or the order of lamination. Accordingly, for example, "first" may be replaced with "second" or "third" as appropriate. Further, the ordinal words described in the specification and the like may not coincide with the ordinal words used to designate one embodiment of the present invention.

In this specification and the like, words such as "upper" and "lower" are used for convenience to describe positional relationships of constituent elements with reference to the drawings. In addition, the positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the words and phrases described in the specification are not limited to the words and phrases, and may be appropriately replaced according to circumstances.

For example, in the present specification and the like, when explicitly described as "X and Y are connected", it means that X and Y are electrically connected; x and Y are functionally linked; x is directly connected with Y. Accordingly, the present invention is not limited to the predetermined connection relationships such as the connection relationships shown in the drawings or the text, and connection relationships other than the connection relationships shown in the drawings or the text are also disclosed in the drawings or the text. Here, X and Y are objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

In this specification and the like, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a region (hereinafter also referred to as a channel formation region) forming a channel between a drain (drain terminal, drain region, or drain electrode) and a source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.

In addition, in the case of using transistors having different polarities, the case of changing the current direction during circuit operation, or the like, the functions of the source and the drain may be exchanged with each other. Therefore, in this specification and the like, the source and the drain may be exchanged with each other.

Note that the channel length refers to, for example, a distance between a semiconductor (or a portion where a current flows in the semiconductor) and a gate electrode overlap each other in a top view of the transistor or a source (source region or source electrode) and a drain (drain region or drain electrode) in a channel formation region when the transistor is in an on state. In addition, in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor is sometimes not limited to one value. Therefore, in this specification, the channel length is any one of a value, a maximum value, a minimum value, or an average value in the channel formation region.

The channel width refers to, for example, a region where a semiconductor and a gate electrode overlap each other in a top view of a transistor (or a portion where a current flows in the semiconductor when the transistor is in an on state) or a length of a channel formation region perpendicular to a channel length direction among the channel formation regions. In addition, in one transistor, the channel width is not necessarily the same value in all regions. That is, the channel width of one transistor is sometimes not limited to one value. Therefore, in this specification, the channel width is any one of a value, a maximum value, a minimum value, or an average value in the channel formation region.

In this specification and the like, depending on the structure of the transistor, a channel width in reality (hereinafter, also referred to as "effective channel width") in a region where a channel is formed may be different from a channel width shown in a top view of the transistor (hereinafter, also referred to as "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may be larger than the apparent channel width, and thus the influence thereof cannot be ignored. For example, in a transistor in which the side surface of the semiconductor is covered with a gate electrode, the proportion of a channel formation region formed on the side surface of the semiconductor may be increased. In this case, the effective channel width is larger than the apparent channel width.

In the above case, it is sometimes difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, an assumption that the shape of the semiconductor is known in advance is required. Therefore, when the shape of the semiconductor is not determined, it is difficult to accurately measure the effective channel width.

In this specification, when simply described as "channel width", it may be referred to as an apparent channel width. Alternatively, in the present specification, when simply representing "channel width", the effective channel width may be represented. Note that values of the channel length, the channel width, the effective channel width, the apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

Note that the impurity of the semiconductor refers to an element other than a main component constituting the semiconductor, for example. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, an increase in defect density, a decrease in crystallinity, and the like of the semiconductor occur. When the semiconductor is an oxide semiconductor, examples of impurities that change characteristics of the semiconductor include a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and a transition metal other than a main component of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. In addition, water may also act as an impurity. In addition, for example, the mixing of impurities sometimes causes oxygen vacancies (also called V _O Oxygen vacuum) is formed.

Note that in this specification and the like, silicon oxynitride refers to a substance having an oxygen content greater than a nitrogen content. Further, silicon oxynitride refers to a substance having a nitrogen content greater than an oxygen content. In addition, aluminum oxynitride refers to a substance having an oxygen content greater than a nitrogen content. Further, aluminum oxynitride refers to a substance having a nitrogen content greater than an oxygen content. Further, hafnium oxynitride refers to a substance having an oxygen content greater than the nitrogen content. Further, hafnium oxynitride refers to a substance having a nitrogen content greater than an oxygen content.

Note that in this specification and the like, the "insulator" may be replaced with "insulating film" or "insulating layer". In addition, "conductor" may be referred to as "conductive film" or "conductive layer". In addition, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

In the present specification and the like, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less. Therefore, the state in which the angle is-5 ° or more and 5 ° or less is also included. "substantially parallel" means a state in which two straight lines form an angle of-30 DEG or more and 30 DEG or less. The term "vertical" refers to a state in which the angle of two straight lines is 80 ° or more and 100 ° or less. Therefore, the state in which the angle is 85 ° or more and 95 ° or less is also included. The term "substantially perpendicular" means a state in which an angle formed by two straight lines is 60 ° or more and 120 ° or less.

In the present specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, which may also be simply referred to as OS), and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor may be referred to as a transistor including a metal oxide or an oxide semiconductor.

Note that in this specification or the like, normally-off means that a drain current of 1 μm per channel width flowing through a transistor when no potential is applied to the gate or a ground potential is applied to the gate is 1×10 at room temperature ^-20 A is 1X 10 at 85℃ or less ^-18 A is less than or equal to 1X 10 at 125 DEG C ^-16 A is less than or equal to A.

In this specification and the like, the "voltage" and the "potential" may be appropriately exchanged. The "voltage" refers to a potential difference from a reference potential, and may be referred to as a "potential" when the reference potential is a ground potential (ground potential), for example. The ground potential does not necessarily mean 0V. The potential is relatively, and the potential supplied to the wiring, the potential applied to the circuit, or the like, the potential output from the circuit, or the like also changes according to the change in the reference potential.

In the present specification and the like, when the same symbol is used for a plurality of elements and it is necessary to distinguish them, a symbol for identification such as "_1", "[ n ]", "[ m, n ]" may be added to the symbol.

Note that in this specification and the like, "substantially uniform in height" refers to a structure in which heights from a surface (for example, a flat surface such as a substrate surface) serving as a reference are equal when viewed in cross section. For example, in a manufacturing process of a semiconductor device, a planarization process (typically, CMP (Chemical Mechanical Polishing: chemical mechanical polishing) process) is sometimes performed to expose a surface of a single layer or a plurality of layers. In this case, the heights of the surfaces to be processed in the CMP process are equal to each other from the surface serving as a reference. In addition, "substantially uniform in height" also includes the case of uniform in height. Note that the heights of the plurality of layers may be different depending on the processing apparatus, the processing method, or the material of the surface to be processed at the time of performing CMP processing. In the present specification and the like, "substantially uniform in height" also includes the above-described case. For example, when a layer having two heights (referred to herein as a first layer and a second layer) to a reference plane appears, when the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20nm or less, it is also referred to as "substantially uniform height".

Note that in this specification and the like, "side surfaces or end portions are substantially uniform" means that at least a part of the outline overlaps between the upper layer and the lower layer when seen from the top surface. For example, the case where the upper layer and the lower layer are processed by the same mask pattern or a part thereof is included. Further, "side surfaces or end portions are substantially identical" also includes cases where side surfaces or end portions are identical. However, in strict terms, the contours do not overlap, but the contours of the upper layer are located inside the contours of the lower layer or the contours of the upper layer are located outside the contours of the lower layer, and these cases are also included in the case where "side surfaces or end portions are substantially uniform".

(embodiment 1)

In this embodiment mode, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a method for manufacturing the same are described with reference to fig. 1A to 30C.

< structural example of semiconductor device >

The structure of a semiconductor device including the transistor 200 is described with reference to fig. 1. Fig. 1A to 1D are a top view and a cross-sectional view of a semiconductor device including a transistor 200. Fig. 1A is a plan view of the semiconductor device. Fig. 1B to 1D are sectional views of the semiconductor device. Here, fig. 1B is a cross-sectional view of a portion along the chain line A1-A2 in fig. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Fig. 1C is a cross-sectional view of a portion along the chain line A3 to A4 in fig. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In addition, fig. 1D is a sectional view of a portion along the chain line A5 to A6 in fig. 1A. Note that in the plan view of fig. 1A, some constituent elements are omitted for clarity.

A semiconductor device according to one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 274 over the insulator 283, an insulator 283, and an insulator 285 over the insulator 274. Insulator 212, insulator 214, insulator 216, insulator 280, insulator 282, insulator 283, insulator 285, and insulator 274 are used as interlayer films. Further, a conductor 240 (a conductor 240a and a conductor 240 b) which is electrically connected to the transistor 200 and is used as a plug is also included. Further, insulators 241 (an insulator 241a and an insulator 241 b) are provided so as to be in contact with the side surfaces of the conductors 240 serving as plugs. Further, conductors 246 (conductors 246a and 246 b) electrically connected to the conductors 240 and used as wirings are provided on the insulators 285 and 240. Insulator 283 is in contact with a portion of the top surface of insulator 214, the side surface of insulator 216, the side surface of insulator 222, the side surface of insulator 275, the side surface of insulator 280, and the side and top surfaces of insulator 282.

The insulator 241a is provided so as to be in contact with the inner walls of the openings of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240a is provided so as to be in contact with the side surface of the insulator 241 a. Further, the insulator 241b is provided so as to be in contact with the inner walls of the openings of the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and the conductor 240b is provided so as to be in contact with the side surface of the insulator 241 b. The insulator 241 has a structure in which a first insulator is provided so as to be in contact with the inner wall of the opening and a second insulator is provided inside the first insulator. The conductor 240 has a structure in which a first conductor is provided so as to contact the side surface of the insulator 241 and a second conductor is provided inside the first conductor. Here, the top surface of the conductor 240 is substantially equal to the top surface of the insulator 285 in the region overlapping the conductor 246.

In addition, in the transistor 200, the first insulator of the insulator 241 and the second insulator of the insulator 241 are stacked, but the present invention is not limited thereto. For example, the insulator 241 may have a single-layer structure or a stacked structure of three or more layers. In the transistor 200, the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, but the present invention is not limited thereto. For example, the conductor 240 may have a single-layer structure or a stacked structure of three or more layers. In addition, when the structure has a laminated structure, ordinals may be given in order of formation to distinguish them from each other.

[ transistor 200]

As shown in fig. 1A to 1D, the transistor 200 includes an insulator 216 on the insulator 214, an insulator 205 (the insulator 205a and the conductor 205 b) arranged so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an insulator 242a on the oxide 230b, an insulator 271A on the conductor 242a, an insulator 242b on the oxide 230b, an insulator 271b on the conductor 242b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, an insulator 260 (the conductor 260a and the conductor 260 b) which is located on the insulator 254 and overlaps with a part of the oxide 230b, and an insulator 275 arranged on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 271b, and the insulator 271 b. Here, as shown in fig. 1B and 1C, the insulator 252 is in contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side and top surface of the oxide 230B, the side surface of the conductor 242, the side surface of the insulator 271, the side surface of the insulator 275, the side surface of the insulator 280, and the bottom surface of the insulator 250. The top surface of the conductor 260 is disposed so as to have a height substantially equal to the heights of the uppermost portion of the insulator 254, the uppermost portion of the insulator 250, the uppermost portion of the insulator 252, and the top surface of the insulator 280. In addition, insulator 282 is in contact with at least a portion of the top surface of each of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

Hereinafter, the oxide 230a and the oxide 230b may be collectively referred to as an oxide 230. Further, the conductors 242a and 242b may be collectively referred to as conductors 242. In addition, the insulator 271a and the insulator 271b are sometimes collectively referred to as an insulator 271.

Openings to the oxide 230b are formed in the insulator 280 and the insulator 275. An insulator 252, an insulator 250, an insulator 254, and a conductor 260 are provided in the opening. Further, in the channel length direction of the transistor 200, the conductors 260, 252, 250, and 254 are provided between the conductors 271a and 242a and between the conductors 271b and 242 b. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260.

Oxide 230 preferably includes oxide 230a on insulator 224 and oxide 230b on oxide 230 a. When the oxide 230a is included under the oxide 230b, diffusion of impurities from a structure formed under the oxide 230a to the oxide 230b can be suppressed.

Note that in the transistor 200, the oxide 230 has a two-layered structure of the oxide 230a and the oxide 230b, but the present invention is not limited thereto. For example, the oxide 230 may have a single-layer or three-layer or more stacked structure of the oxide 230b, or may have a stacked structure of the oxide 230a and the oxide 230b.

The electrical conductor 260 is used as a first gate (also referred to as a top gate) electrode and the electrical conductor 205 is used as a second gate (also referred to as a back gate) electrode. In addition, the insulator 252, the insulator 250, and the insulator 254 are used as a first gate insulator, and the insulator 222 and the insulator 224 are used as a second gate insulator. Note that the gate insulator is sometimes referred to as a gate insulating layer or a gate insulating film. Further, the conductor 242a is used as one of a source electrode and a drain electrode, and the conductor 242b is used as the other of the source electrode and the drain electrode. Further, at least a part of the region of the oxide 230 overlapping with the conductor 260 is used as a channel formation region.

Here, fig. 2A shows an enlarged view of the vicinity of the channel formation region in fig. 1B. Since the oxide 230b is supplied with oxygen, a channel formation region is formed in a region between the conductor 242a and the conductor 242 b. Accordingly, as shown in fig. 2A, the oxide 230b includes a region 230bc serving as a channel formation region of the transistor 200, and a region 230ba and a region 230bb which are provided so as to sandwich the region 230bc and serve as a source region or a drain region. At least a portion of region 230bc overlaps with conductor 260. In other words, the region 230bc is provided in the region between the conductor 242a and the conductor 242 b. Region 230ba overlaps conductor 242a and region 230bb overlaps conductor 242 b.

Since the region 230bc serving as a channel formation region has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, the region 230bc is a high-resistance region having a low carrier concentration. Thus, region 230bc may be said to be an i-type (intrinsic) or substantially i-type region.

In addition, the regions 230ba and 230bb used as the source region and the drain region have a large number of oxygen vacancies or have a high concentration of impurities such as hydrogen, nitrogen, and metal elements, and thus have a high carrier concentration, and therefore have a low resistance. That is, the region 230ba and the region 230bb are n-type regions having a higher carrier concentration and a lower resistance than the region 230 bc.

Here, the carrier concentration of the region 230bc used as the channel formation region is preferably 1×10 ¹⁸ cm ^-3 Hereinafter, more preferably less than 1X 10 ¹⁷ cm ^-3 More preferably less than 1X 10 ¹⁶ cm ^-3 More preferably less than 1X 10 ¹³ cm ^-3 Further preferably less than 1X 10 ¹² cm ^-3 . The lower limit value of the carrier concentration of the region 230bc used as the channel formation region is not particularly limited, and may be set to 1×10, for example ^-9 cm ^-3 。

Further, a region having a carrier concentration equal to or lower than that of the region 230ba and the region 230bb and equal to or higher than that of the region 230bc may be formed between the region 230bc and the region 230ba or the region 230 bb. In other words, this region is used as a junction region of the region 230bc and the region 230ba or the region 230 bb. The hydrogen concentration of the junction region is sometimes equal to or lower than the hydrogen concentration of the regions 230ba and 230bb and equal to or higher than the hydrogen concentration of the region 230 bc. In addition, the oxygen vacancies of the junction region are sometimes equal to or less than the oxygen vacancies of region 230ba and region 230bb and equal to or more than the oxygen vacancies of region 230 bc.

Note that fig. 2A shows an example in which the region 230ba, the region 230bb, and the region 230bc are formed in the oxide 230b, but the present invention is not limited thereto. For example, the above regions may be formed in the oxide 230b and the oxide 230 a.

In the oxide 230, it may be difficult to clearly observe the boundary of each region. The concentrations of the metal element and the impurity element such as hydrogen and nitrogen detected in each region do not need to be changed stepwise for each region, and may be changed gradually for each region. That is, the concentration of the metal element and the impurity element such as hydrogen and nitrogen may be lower as the channel formation region is closer.

A metal oxide (hereinafter, sometimes referred to as an oxide semiconductor) to be used as a semiconductor in the transistor 200 is preferably used for the oxide 230 (the oxide 230a or the oxide 230 b) including a channel formation region.

The band gap of the metal oxide used as the semiconductor is preferably 2eV or more, more preferably 2.5eV or more. By using a metal oxide with a wider band gap, the off-state current (off-state current) of the transistor can be reduced.

For example, as the oxide 230, a metal oxide such as an in—m—zn oxide containing indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. Further, as the oxide 230, in—ga oxide, in—zn oxide, or indium oxide can also be used.

The oxide 230 preferably has a stacked structure of a plurality of oxide layers having different chemical compositions from each other. For example, the atomic number ratio of the element M of the metal element with respect to the main component in the metal oxide for the oxide 230a is preferably larger than the atomic number ratio of the element M of the metal element with respect to the main component in the metal oxide for the oxide 230 b. Further, the atomic number ratio of In to the element M In the metal oxide for the oxide 230a is preferably larger than the atomic number ratio of In to the element M In the metal oxide for the oxide 230 b. By adopting such a structure, diffusion of impurities and oxygen from a structure formed below the oxide 230a to the oxide 230b can be suppressed.

Here, it is preferable that the atomic ratio of In to the element M In the metal oxide used for the oxide 230b is larger than the atomic ratio of In to the element M In the metal oxide used for the oxide 230 a. By adopting this structure, the transistor 200 can obtain a high on-state current and a high frequency characteristic.

Further, since the oxide 230a and the oxide 230b contain a common element as a main component in addition to oxygen, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Since the defect state density of the interface between the oxide 230a and the oxide 230b can be reduced, the influence of the interface scattering on the carrier conduction is small, and thus a high on-state current can be obtained.

Specifically, as the oxide 230a, a metal oxide having a composition of In: M: zn=1:3:4 [ atomic number ratio ] or the vicinity thereof or a composition of In: M: zn=1:1:0.5 [ atomic number ratio ] or the vicinity thereof may be used. As the oxide 230b, a metal oxide having a composition of In: M: zn=1:1:1 [ atomic number ratio ] or a vicinity thereof, a composition of In: M: zn=1:1:1.2 [ atomic number ratio ] or a vicinity thereof, a composition of In: M: zn=1:1:2 [ atomic number ratio ] or a vicinity thereof, or a composition of In: M: zn=4:2:3 [ atomic number ratio ] or a vicinity thereof may be used. Note that the nearby composition includes a range of ±30% of the desired atomic number ratio. Further, gallium is preferably used as the element M. In addition, when a single layer of the oxide 230b is provided as the oxide 230, a metal oxide which can be used for the oxide 230a can be used as the oxide 230b.

In the case of depositing a metal oxide by a sputtering method, the atomic ratio is not limited to the atomic ratio of the deposited metal oxide, and may be an atomic ratio of a sputtering target used for the deposition of the metal oxide.

The oxide 230b preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor: c-axis oriented crystalline oxide semiconductor) is preferably used as the oxide 230b.

CAAC-OS has a dense structure with high crystallinity and is an impurity and defect (for example, oxygen vacancy (V) _O ) Etc.) little metal oxide. In particular, the CAAC-OS can have a dense structure with higher crystallinity by performing a heat treatment at a temperature (for example, 400 ℃ or more and 600 ℃ or less) at which the metal oxide is not polycrystallized after the metal oxide is formed. Thus, by further increasing the density of the CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

In addition, since a clear grain boundary is not easily observed in CAAC-OS, a decrease in electron mobility due to the grain boundary is not easily generated. Thus, the metal oxide containing CAAC-OS is stable in physical properties. Therefore, the metal oxide having the CAAC-OS has heat resistance and high reliability.

In addition, when an oxide having crystallinity such as CAAC-OS is used as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Therefore, oxygen extraction from the oxide 230b can be reduced even by heat treatment, so that the transistor 200 is stable to a high temperature (so-called thermal budget) in the manufacturing process.

In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region of the oxide semiconductor where a channel is formed, electrical characteristics tend to be changed, and reliability may be lowered. In addition, in the case of the optical fiber, Hydrogen in the vicinity of the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V _O H) Electrons may be generated as carriers. Therefore, when oxygen vacancies are included in a region of the oxide semiconductor where a channel is formed, the transistor has normally-on characteristics (characteristics that a channel exists and a current flows in the transistor even if a voltage is not applied to the gate electrode). Accordingly, in the region of the oxide semiconductor where the channel is formed, it is preferable to minimize impurities, oxygen vacancies, and V _O H. In other words, it is preferable that the carrier concentration of the region forming the channel in the oxide semiconductor is reduced and is i-type (intrinsic) or substantially i-type.

In contrast, by providing an insulator containing oxygen desorbed by heating (hereinafter, sometimes referred to as excess oxygen) in the vicinity of the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V _O H. Note that when too much oxygen is supplied to the source region or the drain region, there is a possibility that on-state current of the transistor 200 is lowered or field-effect mobility is lowered. Also, when the amount of oxygen supplied to the source region or the drain region is uneven in the substrate surface, the characteristics of the semiconductor device including the transistor are uneven.

Therefore, in the oxide semiconductor, it is preferable that the carrier concentration of the region 230bc serving as the channel formation region is reduced and is i-shaped or substantially i-shaped. On the other hand, it is preferable that the regions 230ba and 230bb serving as the source region or the drain region have a high carrier concentration and are n-type. In other words, it is preferable to reduce oxygen vacancies and V in the region 230bc of the oxide semiconductor _O H and regions 230ba and 230bb are not supplied with excess oxygen.

In other words, in the oxide semiconductor, it is preferable that the region 230ba and the region 230bb serving as the source region or the drain region have a high carrier concentration and are n-type, and the region 230bc serving as the channel formation region have a reduced carrier concentration and are i-type or substantially i-type. That is, the n-type region preferably does not extend to the channel formation region.

< influence of extension of n-type region to channel formation region on OS transistor >

In this section, the effect of extending the n-type region to the channel formation region on the OS transistor is described using the results of device simulation.

Device simulations were performed using TCAD Sentaurus from Synopsys, inc. Fig. 3 is a schematic cross-sectional view of a transistor used in the simulation of the device. The transistor includes an Oxide Semiconductor (OS), source and Drain electrodes (Drain) on the oxide semiconductor, and a Gate electrode (Gate) overlapping the oxide semiconductor.

L in FIG. 3 _SD Indicating the distance between the source electrode and the drain electrode. Δl in fig. 3 represents the length of the n-type region extending from the end of the source electrode or the drain electrode to the channel formation region.

In the simulation of the device, L _SD 60nm, 120nm or 240nm. ΔL is 0nm, 5nm, 10nm, 20nm or 30nm. Source region, drain region and donor concentration N of N-type region _d Is 1X 10 ¹⁹ cm ^-3 Or 5X 10 ¹⁹ cm ^-3 . Further, the channel width was 60nm.

Fig. 4A and 4B show the results of the device simulation. FIG. 4A shows the donor concentration N of the source, drain and N-type regions _d Is 1X 10 ¹⁹ cm ^-3 The result is shown in FIG. 4B, which shows the donor concentrations N of the source, drain and N-type regions _d Is 5 multiplied by 10 ¹⁹ cm ^-3 Results at that time.

In fig. 4A and 4B, the vertical axis represents the variation amount (Δvth) [ V ] of the threshold voltage]The horizontal axis represents ΔL [ nm ]]. Here, the threshold voltage (Vth) is defined as the gate voltage Vg at which the drain current becomes 1 pA. In addition, the plot represented by circles is L _SD The graph represented by a square is L as a result at 240nm _SD The graph represented by diamond is L as a result at 120nm _SD Results at 60nm.

As can be seen from FIGS. 4A and 4B, L _SD The shorter the n-type region is, the larger the amount of change in threshold voltage due to the extension (increase in Δl) of the n-type region is. Thus, the n-type region preferably does not extend to the channel formation region.

The effect of the extension of the n-type region to the channel formation region on the OS transistor is described above.

Then, in this embodiment, the oxide 230b is subjected to microwave treatment in an oxygen-containing atmosphere in a state where the conductor 242a and the conductor 242b are provided on the oxide 230b, so that oxygen vacancies and V in the region 230bc are reduced _O H. Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source for generating high-density plasma by microwaves.

By performing the microwave treatment in an atmosphere containing oxygen, the oxygen gas can be plasmatized using high Frequency such as microwave or RF (Radio Frequency) to cause the oxygen plasma to act. At this time, a high frequency such as microwave or RF may be irradiated to the region 230bc. V of region 230bc can be set by the action of plasma, microwave, etc _O H is separated into oxygen vacancies (V _O ) And hydrogen (H) which may be removed from region 230bc to fill the oxygen vacancies with oxygen. Thereby, the hydrogen concentration, oxygen vacancies, and V in the region 230bc can be reduced _O H to reduce the carrier concentration.

When the microwave treatment is performed in an oxygen-containing atmosphere, the action of high frequency such as microwaves and RF, oxygen plasma, and the like is shielded by the conductors 242a and 242b, and does not relate to the regions 230ba and 230bb. Further, the effect of oxygen plasma can be reduced by the insulator 271 and the insulator 280 covering the oxide 230b and the conductor 242. Thus, V does not occur in the region 230ba and the region 230bb during the microwave treatment _O H reduction and excessive oxygen supply, and thus a decrease in carrier concentration can be prevented.

In addition, it is preferable to perform microwave treatment with an oxygen-containing atmosphere after depositing the insulating film to be the insulator 252 or after depositing the insulating film to be the insulator 250. In this manner, by performing microwave treatment in an oxygen-containing atmosphere through the insulator 252 or the insulator 250, oxygen can be efficiently injected into the region 230 bc. Further, by disposing the insulator 252 so as to be in contact with the side surface of the conductor 242 and the surface of the region 230bc, the region 230bc can be prevented from being injected with unnecessary oxygen, and therefore oxidation of the side surface of the conductor 242 can be prevented. In addition, the side surface of the conductor 242 can be suppressed from being oxidized when the insulating film serving as the insulator 250 is deposited.

As oxygen injected into the region 230bc, there are various modes such as an oxygen atom, an oxygen molecule, and an oxygen radical (also referred to as an O radical, including an atom, a molecule, or an ion of unpaired electrons). Oxygen injected into region 230bc may be any one or more of the ways described above, with oxygen radicals being particularly preferred. In addition, since the film quality of the insulator 252 and the insulator 250 can be improved, the reliability of the transistor 200 can be improved.

As described above, oxygen vacancies and V can be selectively removed in the region 230bc of the oxide semiconductor _O H makes the region 230bc i-type or substantially i-type. Further, the region 230ba and the region 230bb serving as the source region or the drain region can be kept from being supplied with excessive oxygen, and the n-type region before the microwave treatment can be kept in a state. This suppresses variation in the electrical characteristics of the transistor 200, and suppresses variation in the electrical characteristics of the transistor 200 in the substrate plane.

By adopting the above structure, a semiconductor device with small non-uniformity of transistor characteristics can be provided. Further, a semiconductor device with good reliability can be provided. Further, a semiconductor device having good electrical characteristics can be provided.

As shown in fig. 1C, a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b when viewed in cross section of the channel width of the transistor 200. That is, the end portions of the side surfaces and the end portions of the top surface may also be curved (hereinafter, also referred to as rounded).

The radius of curvature of the curved surface is preferably greater than 0nm and less than the thickness of the oxide 230b in the region overlapping the conductor 242 or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0nm and 20nm or less, preferably 1nm or more and 15nm or less, and more preferably 2nm or more and 10nm or less. By adopting the above-described shape, the coverage of the insulator 252, the insulator 250, the insulator 254, and the oxide 230b of the conductor 260 can be improved.

Further, as shown in fig. 1C and the like, since the insulator 252 formed of aluminum oxide or the like is provided so as to be in contact with the top surface and the side surface of the oxide 230, indium contained in the oxide 230 may be distributed at and near the interface between the oxide 230 and the insulator 252. Therefore, the surface vicinity of the oxide 230 has an atomic number ratio close to that of indium oxide or an atomic number ratio close to that of in—zn oxide. When the atomic number of indium in the vicinity of the surface of the oxide 230, particularly the oxide 230b is relatively large, the field-effect mobility of the transistor 200 can be improved.

By providing the oxide 230a and the oxide 230b with the above structure, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and thus the transistor 200 can obtain high on-state current and high frequency characteristics.

At least one of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 is preferably used as a blocking insulating film which suppresses diffusion of impurities such as water, hydrogen, or the like from the substrate side or over the transistor 200 to the transistor 200. Accordingly, at least one of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 preferably has a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O、NO、NO ₂ Etc.), the function of diffusion of impurities such as copper atoms (the impurities are not easily penetrated). Further, an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) (which is not easily permeable to the oxygen) is preferably used.

In this specification, the barrier insulating film means an insulating film having barrier properties. In the present specification, the barrier property means a function of suppressing diffusion of a corresponding substance (also referred to as low permeability). Or, it means a function of capturing and immobilizing a corresponding substance (also referred to as gettering).

As the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285, an insulator having a function of suppressing diffusion of impurities such as water and hydrogen, oxygen, and the like is preferably used, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, or the like can be used. For example, silicon nitride or the like having higher hydrogen barrier property is preferably used as the insulator 212, the insulator 275, and the insulator 283. For example, as the insulator 214, the insulator 271, the insulator 282, and the insulator 285, alumina, magnesia, or the like having high hydrogen capturing and fixing performance is preferably used. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214. Alternatively, diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed outside the insulator 285 to the transistor 200 side can be suppressed. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing to the substrate side through the insulator 212 and the insulator 214. Alternatively, oxygen contained in the insulator 280 or the like can be prevented from diffusing upward of the transistor 200 through the insulator 282 or the like. As described above, the transistor 200 is preferably surrounded by the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285, which have a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen.

Here, as the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285, an oxide having an amorphous structure is preferably used. For example, alO is preferably used _x (x is any number greater than 0) or MgO _y (y is an arbitrary number greater than 0), and the like. The above metal oxide having an amorphous structure sometimes has a property that an oxygen atom has a dangling bond and hydrogen is trapped or immobilized by the dangling bond. By using the metal oxide having the amorphous structure described above as a constituent element of the transistor 200 or disposing the metal oxide around the transistor 200, hydrogen contained in the transistor 200 or hydrogen existing around the transistor 200 can be trapped or fixed. In particular, hydrogen contained in a channel formation region in the transistor 200 is preferably trapped or fixed. By using a metal oxide having an amorphous structure as a constituent element of the transistor 200 or by providing the metal oxide around the transistor 200, the transistor 200 and the semiconductor device having favorable characteristics and high reliability can be manufactured.

The insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 preferably have an amorphous structure, but a region having a polycrystalline structure may be formed in a part thereof. The insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a layer having a polycrystalline structure is formed over a layer having an amorphous structure may be used.

The insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 may be deposited by sputtering, for example. The sputtering method does not require the use of molecules containing hydrogen as a deposition gas, and therefore, the hydrogen concentration of the insulator 212, the insulator 214, the insulator 271, the insulator 275, the insulator 282, the insulator 283, and the insulator 285 can be reduced. As the deposition method, a chemical vapor deposition (CVD: chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: pulsed Laser Deposition) method, an atomic layer deposition (ALD: atomic Layer Deposition) method, or the like can be suitably used in addition to the sputtering method.

In addition, it is sometimes preferable to reduce the resistivity of the insulator 212, the insulator 275, and the insulator 283. For example, by making the resistivity of the insulator 212, the insulator 275, and the insulator 283 approximately 1×10 ¹³ In the treatment with plasma or the like in the semiconductor device manufacturing process, the insulator 212, the insulator 275, and the insulator 283 may mitigate the charge accumulation of the conductor 205, the conductor 242, the conductor 260, or the conductor 246. The resistivity of the insulator 212, the insulator 275, and the insulator 283 is preferably 1×10 ¹⁰ Omega cm above and 1×10 ¹⁵ And Ω cm or less.

Further, dielectric constants of the insulator 216, the insulator 274, the insulator 280, and the insulator 285 are preferably lower than those of the insulator 214. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 216, the insulator 274, the insulator 280, and the insulator 285, silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, or the like may be appropriately used.

The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be fitted into an opening formed in the insulator 216. In addition, a portion of the conductor 205 is sometimes embedded in the insulator 214.

The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided so as to contact the bottom surface and the side wall of the opening formed in the insulator 216. The conductor 205b is provided so as to be fitted into a recess formed in the conductor 205 a. Here, the height of the top surface of the conductor 205b is substantially equal to the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216.

Here, the conductor 205a preferably has a structure that suppresses a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, and a nitrogen oxide molecule (N ₂ O、NO、NO ₂ Etc.), a conductive material having a function of diffusing impurities such as copper atoms. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) is preferably used.

By using a conductive material having a function of reducing diffusion of hydrogen as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the oxide 230 through the insulator 224 or the like. Further, by using a conductive material having a function of suppressing diffusion of oxygen as the conductive body 205a, the conductive body 205b can be suppressed from being oxidized and the conductivity can be reduced. As the conductive material having a function of suppressing oxygen diffusion, for example, titanium nitride, tantalum nitride, ruthenium oxide, or the like can be used. Therefore, the conductive material may be used as the conductive body 205a in a single layer or a stacked layer. For example, titanium nitride may be used as the conductor 205 a.

Further, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, tungsten may be used for the conductor 205 b.

The conductor 205 is sometimes used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, vth of the transistor 200 can be increased and off-state current can be reduced. Thus, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced as compared with the case where a negative potential is not applied to the conductor 205.

Further, the resistivity of the conductor 205 is designed in consideration of the above-described potential applied to the conductor 205, and the thickness of the conductor 205 is set in accordance with the resistivity. The thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, the thickness of the conductor 205 and the insulator 216 is preferably reduced within a range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that diffusion of the impurities into the oxide 230 can be reduced.

As shown in fig. 1A, the conductor 205 is preferably larger than a region of the oxide 230 that does not overlap with the conductor 242a and the conductor 242 b. In particular, as shown in fig. 1C, the conductor 205 preferably extends to a region outside the channel width direction end portions of the oxide 230a and the oxide 230 b. That is, it is preferable that the conductor 205 and the conductor 260 overlap each other with an insulator therebetween on the outer side of the side surface in the channel width direction of the oxide 230. By having the above-described structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 serving as the first gate electrode and the electric field of the conductor 205 serving as the second gate electrode. In this specification, a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

In this specification and the like, a transistor of an S-channel structure refers to a structure in which a channel formation region is electrically surrounded by an electric field of one of a pair of gate electrodes and the other. The S-channel structure disclosed in the present specification and the like is different from the Fin-type structure and the planar structure. By adopting the S-channel structure, a transistor having improved resistance to short channel effects, in other words, a transistor in which short channel effects are unlikely to occur can be realized.

The channel formation region may be electrically surrounded by the transistor 200 being normally off and having the S-channel structure described above. Thus, the transistor 200 can also be said to have a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around: lateral All Around Gate) structure. By providing the transistor 200 with an S-channel structure, a GAA structure, or an lga structure, a channel formation region formed at or near the interface of the oxide 230 and the gate insulator can be provided over the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be increased, and thus an on-state current of the transistor or an improvement in field-effect mobility of the transistor can be expected.

Further, as shown in fig. 1C, the conductor 205 is extended to serve as a wiring. However, the present invention is not limited to this, and an electric conductor used as a wiring may be provided under the electric conductor 205. Furthermore, one conductor 205 need not be provided in each transistor. For example, the conductor 205 may be commonly used in a plurality of transistors.

Note that although the structure in which the conductor 205a and the conductor 205b are stacked as the conductor 205 in the transistor 200 is shown, the present invention is not limited to this. For example, the conductor 205 may have a single-layer structure or a stacked structure of three or more layers.

Insulator 222 and insulator 224 are used as gate insulators.

The insulator 222 preferably has a function of suppressing diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like). For example, the insulator 222 preferably has a function of suppressing diffusion of one or both of hydrogen and oxygen, as compared with the insulator 224.

As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used as an insulating material. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Alternatively, oxides containing hafnium and zirconium are preferably used, for example hafnium zirconium oxide. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer which suppresses release of oxygen from the oxide 230 to the substrate side and diffusion of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, diffusion of impurities such as hydrogen to the inside of the transistor 200 can be suppressed, and generation of oxygen vacancies in the oxide 230 can be suppressed. Further, the reaction of the conductor 205 with oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be subjected to nitriding treatment. Further, as the insulator 222, silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

As the insulator 222, for example, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, or the like may be used in a single layer or a stacked layer. When miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material as an insulator to be used as a gate insulator, the gate potential of the transistor when operating can be reduced while maintaining physical thickness. In addition, lead zirconate titanate (PZT) or strontium titanate (SrTiO) may be used as the insulator 222 ₃ )、(Ba,Sr)TiO ₃ (BST) and the like.

As the insulator 224 in contact with the oxide 230, for example, silicon oxide, silicon oxynitride, or the like may be appropriately used.

In the manufacturing process of the transistor 200, the heat treatment is preferably performed in a state where the surface of the oxide 230 is exposed. The heat treatment is preferably performed at 100 ℃ or more and 600 ℃ or less, more preferably 350 ℃ or more and 550 ℃ or less, for example. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed under an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 230, so that oxygen vacancies can be reduced. The heat treatment may be performed under reduced pressure. The heat treatment may be performed under an atmosphere of nitrogen gas or inert gas, and then under an atmosphere containing 10ppm or more, 1% or more, or 10% or more of oxidizing gas in order to fill out the detached oxygen. The heat treatment may be performed in an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed continuously in an atmosphere of nitrogen gas or an inert gas.

By subjecting the oxide 230 to the oxidation treatment, oxygen vacancies in the oxide 230 can be filled with supplied oxygen. Further, the hydrogen remaining in the oxide 230 reacts with the supplied oxygen to convert the hydrogen into H ₂ Morphology removal (dehydration) of O. Thereby, recombination of hydrogen and oxygen vacancies remaining in the oxide 230 to form V can be suppressed _O H。

The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the stacked structure is not limited to the stacked structure using the same material, and may be a stacked structure using a different material. Further, the insulator 224 may be formed in an island shape and overlap with the oxide 230 a. In this case, the insulator 275 is in contact with the side surface of the insulator 224 and the top surface of the insulator 222. Note that in this specification and the like, an island shape refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

Conductors 242a and 242b contact the top surface of oxide 230 b. The conductors 242a and 242b are used as a source electrode or a drain electrode of the transistor 200, respectively.

As the conductor 242 (the conductor 242a and the conductor 242 b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferably used. Further, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like can also be used. These materials are preferably conductive materials that do not oxidize easily or materials that maintain conductivity even when oxygen is absorbed.

Note that hydrogen contained in the oxide 230b or the like sometimes diffuses into the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used as the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b or the like may be easily diffused into the conductor 242a or the conductor 242b, and the diffused hydrogen is bonded to nitrogen contained in the conductor 242a or the conductor 242b. That is, hydrogen contained in the oxide 230b or the like is sometimes absorbed by the conductor 242a or the conductor 242b.

Further, it is preferable that a curved surface is not formed between the side surface of the conductor 242 and the top surface of the conductor 242. By making the conductor 242 not have such a curved surface, as shown in fig. 1D, the cross-sectional area of the conductor 242 in the cross-section in the channel width direction can be increased. This increases the conductivity of the conductor 242, and thus the on-state current of the transistor 200 can be increased.

When the heat treatment is performed in a state where the conductor 242a (conductor 242 b) is in contact with the oxide 230b, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242 b) may be reduced. In addition, the carrier concentration may increase. Accordingly, the oxide 230b in the region overlapping with the conductor 242a (conductor 242 b) can be self-aligned to have low resistance.

The conductor 242 is preferably formed using a conductive film having a compressive stress. Thus, a strain (hereinafter, sometimes referred to as a stretching strain) that expands in the stretching direction can be formed in the region 230ba and the region 230 bb. By steadily forming V by tensile strain _O H may make the region 230ba and the region 230bb stable n-type regions. Note that the compressive stress of the conductor 242 is a stress that relieves the compressive shape of the conductor 242, and is a stress having a vector in a direction from the center portion to the end portion of the conductor 242.

The compressive stress of the conductor 242 may be 500MPa or more, preferably 1000MPa or more, more preferably 1500MPa or more, and even more preferably 2000MPa or more, for example. Note that a sample in which a conductive film for the conductor 242 is deposited over a substrate may be manufactured, and the magnitude of stress of the conductor 242 may be specified based on a stress measurement value of the sample.

Due to the compressive stress of the electric body 242, strain is formed in the region 230ba and the region 230bb, respectively. The strain is a strain (tensile strain) that expands in the tensile direction due to the compressive stress of the conductor 242. When the region 230ba and the region 230bb have the CAAC structure, the strain corresponds to an extension in a direction perpendicular to the c-axis of the CAAC structure. As described later, oxygen vacancies and V are easily formed in the strain by the CAAC structure extending in a direction perpendicular to the c-axis of the CAAC structure _O H and easily obtain oxygen vacancies and V _O H stable structure. Thus, the regions 230ba and 230bb are n-type regions having high and stable carrier concentrations.

Note that the strain formed in the oxide 230b is described above, but the present invention is not limited thereto. The same strain may be formed in the oxide 230 a.

< ease of oxygen vacancy formation in Strain in Metal oxide >

In this section, the ease of oxygen vacancy formation in the strain in the metal oxide was evaluated by calculation. Specifically, the formation energy of oxygen vacancies of a model that calculates strain in the metal oxide is calculated using the first principle.

< calculation model >

A calculation model for first principle calculation is described herein.

As a calculation model of strain In the metal oxide, a model of In-Ga-Zn oxide of a single crystal structure was prepared. The model of the In-Ga-Zn oxide of single crystal structure is hereafter referred to as sc-IGZO model.

FIG. 5A shows the sc-IGZO model. The sc-IGZO model had a composition of In: ga: zn: o=1:1:1:4 [ atomic ratio ]. In addition, the sc-IGZO model is composed of 112 atoms. Three models having different lattice constants perpendicular to the c-axis direction were prepared as sc-IGZO models. In other words, three models having different lattice constants in the a-axis direction and different lattice constants in the b-axis direction were prepared as sc-IGZO models. Specifically, the rate of change of the lattice constant of the sc-IGZO model in the direction perpendicular to the c-axis was set to 0%, 1%, and 2%, respectively. Note that, when the lattice constant of the sc-IGZO model perpendicular to the c-axis direction is changed, the lattice constant of the c-axis direction is fixed.

Here, the sc-IGZO model in which the rate of change of the lattice constant in the direction perpendicular to the c-axis is 1% or 2% is a model in which tensile strain is formed in the metal oxide. In addition, by changing the lattice constant perpendicular to the c-axis by 1%, a stress of about 3.3GPa is generated in the direction perpendicular to the c-axis, and a stress of about 2.3GPa is generated in the direction of the c-axis.

Next, the internal coordinates of the sc-IGZO model, which change the lattice constant perpendicular to the c-axis direction, are structurally optimized.

Next, in each sc-IGZO model, one oxygen atom was removed. The oxygen atoms removed are oxygen atoms bonded to indium and zinc or oxygen atoms bonded to indium and gallium. Each sc-IGZO model after removal of this oxygen atom has oxygen vacancies. In the following description, this model is sometimes referred to as sc-IGZO model including oxygen vacancies. In addition, oxygen vacancies formed by removal of oxygen atoms bonded to indium and zinc are sometimes referred to as V _O 1, the oxygen vacancy formed by removing the oxygen atom bonded to indium and gallium is sometimes referred to as V _O 2。

The above is an illustration of a computational model.

< calculation condition >

Next, the calculation conditions of the first principle calculation are explained.

As the first principle calculation, a first principle electronic state calculation program VASP is used. Table 1 shows the calculation conditions.

TABLE 1

Calculation program	VASP
		Basis function	Plane wave
Generalized function	GGA-PBE
		Pseudo potential	PAW
Energy cut-off	800eV
		Number of electrons	Neutral

The electron state pseudopotential was formed by the PAW method, and GGA/PBE was used as a functional. The grid of k points is set to 2×2×3.

And calculating the energy of oxygen vacancy formation of each sc-IGZO model according to the calculation conditions. The energy of formation of oxygen vacancies (E) is calculated according to the following equation (1) _form (IGZO:V _O ))。

[ formula 1]

E _form (IGZO：Vo)＝E(IGZO；Vo)+μ _O -E(IGZO) (1)

Here, E (IGZO) is the total energy of the sc-IGZO model. E (IGZO: V) _O ) Is the total energy of the sc-IGZO model containing oxygen vacancies. Mu (mu) _O Is the chemical potential of oxygen and is 1/2 of the energy of the oxygen molecule.

The energy of formation of oxygen vacancies in each calculation model is calculated using the above expression (1). Fig. 5B shows the energy of formation of oxygen vacancies of each model. In FIG. 5B, the horizontal axis represents the rate of change of the lattice constant (Variation of Lattice Constant) [%]The vertical axis represents oxygen vacancy formation energy (Formation Energy of V) _O )[eV]。

As shown in fig. 5B, a tendency that the energy of formation of oxygen vacancies becomes smaller as the lattice constant in the direction perpendicular to the c-axis becomes larger is observed. In other words, a negative correlation was observed between the formation energy of oxygen vacancies and the rate of change of the lattice constant of each calculation model in the direction perpendicular to the c-axis.

The calculation result shows that: when a tensile strain is formed in the metal oxide, the energy of formation of oxygen vacancies is small, that is, there is a tendency that oxygen vacancies are easily formed.

As is clear from this, by using a source electrode and a drain electrode having compressive stress as in the transistor according to this embodiment, tensile strain is formed in the source region and the drain region of the oxide semiconductor film, and thus oxygen vacancies are easily formed. Thus, in the transistor according to the present embodiment, a stable n-type region can be formed in the source region and the drain region of the oxide semiconductor film.

The above is a description of the ease of forming oxygen vacancies in the strain in the metal oxide.

Although the conductor 242 has a single-layer structure in fig. 1A to 1D, the present invention is not limited to this, and a stacked structure of two or more layers may be used. For example, as shown in fig. 6B, a two-layer laminated structure of the conductor 242a1 and the conductor 242a2 on the conductor 242a1 may be used as the conductor 242a, and a two-layer laminated structure of the conductor 242B1 and the conductor 242B2 on the conductor 242B1 may be used as the conductor 242B. At this time, the conductors 242a1 and 242b1 are arranged on the side in contact with the oxide 230 b.

Note that, hereinafter, the conductor 242a1 and the conductor 242b1 are sometimes collectively referred to as a lower layer of the conductor 242. In addition, the conductors 242a2 and 242b2 may be collectively referred to as an upper layer of the conductor 242.

The lower layer of the conductor 242 (the conductor 242a1 and the conductor 242b 1) is preferably made of a conductive material having a property of being less susceptible to oxidation. This can suppress the decrease in conductivity of the conductor 242 due to oxidation of the lower layer of the conductor 242. Further, the lower layer of the conductor 242 may have a property of easily absorbing (extracting) hydrogen. Thus, hydrogen of the oxide 230 diffuses into the lower layer of the conductor 242, and the hydrogen concentration of the oxide 230 can be reduced. Therefore, the transistor 200 can have stable electrical characteristics.

The upper layer of the conductor 242 (the conductor 242a2 and the conductor 242b 2) is preferably made of a conductive material having higher conductivity than the lower layer of the conductor 242 (the conductor 242a1 and the conductor 242b 1). At this time, at least a part of the upper layer of the conductor 242 may have a region having higher conductivity than the lower layer of the conductor 242. Alternatively, the upper layer of the conductor 242 is preferably composed of a conductive material having a lower resistivity than the lower layer of the conductor 242. Thus, a semiconductor device with suppressed wiring delay can be manufactured.

The upper layer of the conductor 242 may have a property of easily absorbing hydrogen. Thereby, the hydrogen absorbed by the lower layer of the conductor 242 also diffuses to the upper layer of the conductor 242, and the hydrogen concentration in the oxide 230 can be further reduced. Therefore, the transistor 200 can have stable electrical characteristics.

Here, it is preferable to use conductive materials having the same constituent elements and different chemical compositions for the lower layer of the conductor 242 and the upper layer of the conductor 242. At this time, the lower layer of the conductor 242 and the upper layer of the conductor 242 may be continuously formed without being exposed to the atmosphere. By forming the film so as not to be exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to the surface of the lower layer of the conductor 242, whereby the vicinity of the interface of the lower layer of the conductor 242 and the upper layer of the conductor 242 can be kept clean.

Further, it is preferable that a tantalum-containing nitride having a high atomic number ratio with respect to nitrogen of tantalum is used as the lower layer of the conductor 242, and a tantalum-containing nitride having a low atomic number ratio with respect to nitrogen of tantalum is used as the upper layer of the conductor 242. For example, as the lower layer of the conductor 242, the following tantalum-containing nitride is used: the atomic number ratio of nitrogen to tantalum is 1.0 to 2.0, preferably 1.1 to 1.8, more preferably 1.2 to 1.5. For example, as the upper layer of the conductor 242, the following tantalum-containing nitride is used: the atomic number ratio of nitrogen to tantalum is 0.3 to 1.5, preferably 0.5 to 1.3, more preferably 0.6 to 1.0.

In addition, by increasing the atomic number ratio of nitrogen to tantalum in the tantalum-containing nitride, oxidation of the tantalum-containing nitride can be suppressed. In addition, the oxidation resistance of tantalum-containing nitrides can be improved. Oxygen diffusion into tantalum-containing nitrides can be suppressed. Therefore, as the lower layer of the conductor 242, a tantalum-containing nitride having a high atomic number ratio with respect to nitrogen of tantalum is preferably used. Thereby, an oxide layer can be prevented from being formed between the lower layer of the conductor 242 and the oxide 230, or the thickness of the oxide layer can be reduced.

Further, by reducing the atomic number ratio of nitrogen relative to tantalum in a tantalum-containing nitride, the resistivity of the nitride can be reduced. Therefore, as the upper layer of the conductor 242, a tantalum-containing nitride having a lower atomic number ratio of nitrogen to tantalum is preferably used. Thus, a semiconductor device with suppressed wiring delay can be manufactured.

Note that in the conductor 242, the boundary between the upper layer and the lower layer may be difficult to clearly observe. In the case where a nitride containing tantalum is used for the conductor 242, the concentrations of tantalum and nitrogen detected in each layer are not limited to being changed stepwise for each layer, and may be changed gradually (also referred to as gradation) in a region between an upper layer and a lower layer. That is, the closer to the region of the oxide 231, the higher the atomic ratio of nitrogen to tantalum in the conductor 242 is. Therefore, the atomic ratio of nitrogen to tantalum in the region below the conductor 242 is preferably higher than the atomic ratio of nitrogen to tantalum in the region above the conductor 242.

The film thickness of the lower layer of the conductor 242 is 0.1nm or more and 5.0nm or less, preferably 0.5nm or more and 3.0nm or less, and more preferably 1.0nm or more and 3.0nm or less. At this time, at least a part of the lower layer of the conductor 242 may have a region having the film thickness. Further, the film thickness of the lower layer of the conductor 242 is preferably thinner than the film thickness of the upper layer of the conductor 242. At this time, at least a part of the lower layer of the conductor 242 may have a region having a thinner film thickness than the upper layer of the conductor 242.

Although the example in which the lower layer of the conductor 242 and the upper layer of the conductor 242 are made of the same conductive material having the same constituent elements and different chemical compositions is described here, the present invention is not limited thereto, and the lower layer of the conductor 242 and the upper layer of the conductor 242 may be made of different conductive materials.

Note that the structure of the lower layer of the conductor 242 and the upper layer of the conductor 242 is not limited to the above-described structure. For example, the stress of the conductor 242 may be adjusted by making one or more of constituent elements, chemical compositions, and deposition conditions of the lower layer of the conductor 242 and the upper layer of the conductor 242 different. For example, a nitride containing tantalum is used as the lower layer of the conductor 242, and a nitride containing titanium is used as the upper layer of the conductor 242. The compressive stress or tensile stress of the titanium-containing nitride is small compared to the tantalum-containing nitride, so the stress of the conductor 242 can be adjusted.

Insulator 271a is in contact with the top surface of conductor 242a and insulator 271b is in contact with the top surface of conductor 242 b. The insulator 271 is preferably used as an insulating film having at least barrier property against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of further suppressing oxygen diffusion as compared with the insulator 280. As the insulator 271, for example, an insulator such as aluminum oxide or magnesium oxide can be used.

Insulator 275 is provided so as to cover insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 271. The insulator 275 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 275 preferably includes silicon nitride or a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide. For example, a stacked film of aluminum oxide and silicon nitride over the aluminum oxide may be used as the insulator 275.

By providing the insulator 271 and the insulator 275, the insulator having a barrier property against oxygen can surround the conductor 242. In other words, oxygen contained in the insulator 224 and the insulator 280 can be suppressed from diffusing into the conductor 242. This can suppress the on-state current from decreasing due to the increase in resistivity caused by the direct oxidation of the conductor 242 by oxygen contained in the insulator 224 and the insulator 280.

The insulator 252 is used as part of a gate insulator. An oxygen barrier insulating film is preferably used as the insulator 252. As the insulator 252, an insulator usable for the insulator 282 may be used. As the insulator 252, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, alumina is used as the insulator 252. At this time, the insulator 252 is an insulator containing at least oxygen and aluminum.

As shown in fig. 1C, the insulator 252 is provided in contact with the top and side surfaces of the oxide 230b, the side surface of the oxide 230a, the side surface of the insulator 224, and the top surface of the insulator 222. That is, the region of the oxide 230a, the oxide 230b, and the insulator 224 overlapping the conductor 260 in the cross section in the channel width direction is covered with the insulator 252. Accordingly, oxygen in the oxide 230a and the oxide 230b can be prevented from being removed by the insulator 252 having oxygen barrier property during heat treatment or the like. Therefore, oxygen vacancies formed in the oxide 230a and the oxide 230b can be reduced. Thereby, oxygen vacancies and V formed in the region 230bc can be reduced _O H. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

In addition, conversely, even if the insulator 280, the insulator 250, or the like contains excessive oxygen, the oxygen can be prevented from being excessively supplied to the oxide 230a and the oxide 230b. Therefore, the region 230ba and the region 230bb are excessively oxidized by the region 230bc, and thus, the on-state current of the transistor 200 is prevented from being reduced or the field-effect mobility is prevented from being reduced.

As shown in fig. 1B, the insulator 252 is provided so as to contact the side surfaces of the conductors 242, 271, 275, and 280. Therefore, the side surface of the conductor 242 can be reduced from being oxidized and an oxide film can be formed on the side surface. Therefore, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.

In addition, the insulator 252 needs to be provided in an opening formed in the insulator 280 or the like together with the insulator 254, the insulator 250, and the conductor 260. To achieve miniaturization of the transistor 200, the thickness of the insulator 252 is preferably small. The thickness of the insulator 252 is 0.1nm or more and 5.0nm or less, preferably 0.5nm or more and 3.0nm or less, and more preferably 1.0nm or more and 3.0nm or less. At this time, at least a part of the insulator 252 may be a region having the above thickness. In addition, the thickness of insulator 252 is preferably smaller than the thickness of insulator 250. At this time, at least a part of the insulator 252 may be a region having a smaller thickness than the insulator 250.

To deposit the insulator 252 thin as described above, the insulator 252 is preferably deposited using an ALD method. Examples of the ALD method include a thermal ALD (Thermal ALD) method in which a precursor and a reactant are reacted only by thermal energy, and a PEALD (Plasma Enhanced ALD) method in which a reactant excited by plasma is used. In the PEALD method, deposition can be performed at a lower temperature by using plasma, so that it is sometimes preferable.

The ALD method can deposit atoms in layers, and thus has effects such as being capable of depositing extremely thin films, being capable of depositing structures having a high aspect ratio, being capable of depositing with few defects such as pinholes, being capable of depositing with excellent coverage, and being capable of depositing at low temperatures. Accordingly, the insulator 252 can be deposited with the above-described small thickness and high coverage on the side surface or the like of the opening formed in the insulator 280 or the like.

The precursor used in the ALD method sometimes contains carbon or the like. Therefore, the film formed by the ALD method may contain more impurities such as carbon than the film formed by other deposition methods. Further, the quantification of impurities can be measured by secondary ion mass spectrometry (SIMS: secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or Auger electron spectroscopy (AES: auger Electron Spectroscopy).

Further, by appropriately adjusting the deposition condition of the insulating film to be the insulator 250, the condition of the microwave treatment in the oxygen-containing atmosphere, the amount of oxygen added to the insulator 280 due to the deposition of the insulator 282, or the like, oxygen vacancies and V formed in the region 230bc can be reduced in some cases _O H, excessive oxidation of the region 230ba and the region 230bb can be suppressed. In this case, by adopting a structure in which the insulator 252 is not provided, the manufacturing process of the semiconductor device can be simplified, and improvement in productivity can be achieved.

When alumina is used as the insulator 252, aluminum is added to the region of the oxide 230b in contact with the insulator 252 and the vicinity thereof. Note that the addition of aluminum to the region of the oxide 230b in contact with the insulator 252 and the vicinity thereof occurs in a step after the deposition of the insulating film to be the insulator 252, which is a step of depositing the insulating film to be the insulator 252, forming a film on the insulating film to be the insulator 252, performing a heat treatment after the deposition of the insulating film to be the insulator 252, or the like.

Fig. 7A to 7D schematically show aluminum concentration distributions in the insulator 252 and in the oxide 230 in the depth direction. In fig. 7A to 7D, the vertical axis represents the aluminum (Al) concentration, and the horizontal axis represents the depth direction. Note that the depth direction may be alternatively referred to as a film thickness direction.

Note that the dotted line In fig. 7A to 7D indicates a detection lower limit of the aluminum concentration when In-Mb-Zn oxide (element Mb is one or more selected from gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like), in-Mb oxide, in-Zn oxide, or indium oxide is used as the oxide 230. In addition, a dotted line In fig. 7A to 7D indicates an aluminum concentration of the oxide 230 In the vicinity of the insulator 224 when in—al—zn oxide, in—al—mb—zn oxide, or in—al oxide is used as the oxide 230.

As shown in fig. 7A to 7D, the oxide 230 has a concentration gradient in which the aluminum concentration becomes higher from the lower side of the oxide 230 toward the top surface of the oxide 230. In other words, the oxide 230 has a concentration gradient in which the aluminum concentration becomes higher toward the insulator 252 in the film thickness direction.

As shown in fig. 7A, the oxide 230 sometimes has a region in which the aluminum concentration decreases monotonously with the interface between the insulator 252 and the oxide 230 as a peak and a region in which the aluminum concentration is constant. At this time, a region in which the aluminum concentration monotonically decreases is located on the insulator 252 side as compared with a region in which the aluminum concentration is constant.

As shown in fig. 7B, the oxide 230 may have a first region in which the aluminum concentration monotonically decreases with the interface between the insulator 252 and the oxide 230 as a peak, and a second region in which the aluminum concentration monotonically decreases. At this time, the first region is located on the insulator 252 side as compared with the second region.

As shown in fig. 7C, the oxide 230 may have a region where the aluminum concentration decreases as an exponential function with the interface between the insulator 252 and the oxide 230 as a peak, and a region where the aluminum concentration is constant. At this time, a region where the aluminum concentration decreases as an exponential function is located on the insulator 252 side as compared with a region where the aluminum concentration is constant.

As shown in fig. 7D, the aluminum concentration of the oxide 230 may decrease as an exponential function with the interface between the insulator 252 and the oxide 230 as a peak.

By adding aluminum to the region of the oxide 230b in contact with the insulator 252 and the vicinity thereof, formation of oxygen vacancies in the region and the vicinity thereof can be suppressed. Since a channel is easily formed in this region of the oxide 230b and the vicinity thereof, oxygen vacancies in the channel formation region can be reduced by adopting this structure. Therefore, variations in the electrical characteristics of the transistor 200 can be suppressed, and variations in the electrical characteristics of the transistor 200 in the substrate surface can be suppressed. Note that when in—mb-Zn oxide is used as the oxide 230b before aluminum addition, the oxide 230b is a metal oxide containing at least indium, the element Mb, aluminum, and zinc.

Note that when a metal oxide containing no aluminum or a metal oxide having an aluminum concentration equal to or lower than the detection lower limit is used as the oxide 230b before aluminum addition, the oxide 230b may be regarded as a stacked structure of a first metal oxide layer containing a metal element mainly composed of the metal oxide and a second metal oxide layer containing the metal oxide as a main component and aluminum. In addition, the second metal oxide layer may be said to be a metal oxide layer to which aluminum is added.

The bonding energy of the aluminum atom and the oxygen atom is large as compared with the indium atom or the zinc atom, and therefore oxygen vacancies are not easily formed in the second metal oxide layer to which the aluminum atom is added. In addition, since the second metal oxide layer and the vicinity thereof are easy to form a channel, oxygen vacancies of the channel formation region can be reduced by forming the second metal oxide layer. Therefore, variations in the electrical characteristics of the transistor 200 can be suppressed, and variations in the electrical characteristics of the transistor 200 in the substrate surface can be suppressed.

Note that a metal oxide containing no aluminum or a metal oxide having an aluminum concentration below the detection lower limit may be replaced with a metal oxide containing at least one of In, element Mb, and Zn. For example, when in—mb-Zn oxide is used as the oxide 230b before aluminum addition, the oxide 230b can be regarded as a stacked structure of a first metal oxide layer containing indium, the element Mb, and zinc, and a second metal oxide layer containing indium, the element Mb, aluminum, and zinc.

Fig. 8A is an enlarged view of the vicinity of the channel formation region when viewed in cross section in the channel length direction of the transistor 200, and fig. 8B is an enlarged view of the vicinity of the channel formation region when viewed in cross section in the channel width direction of the transistor 200. For example, as shown in fig. 8A and 8B, the oxide 230B includes an oxide 230B1 and an oxide 230B2 on the oxide 230B 1. Oxide 230b2 is located between oxide 230b1 and insulator 252. Oxide 230b1 corresponds to the first metal oxide layer and oxide 230b2 corresponds to the second metal oxide layer.

Note that a structure in which a metal oxide layer to which aluminum is added is formed over the oxide 230B is shown in fig. 8B, but the present invention is not limited thereto. Since the insulator 252 is also in contact with the side surface of the oxide 230a, a metal oxide layer to which aluminum is added is sometimes formed also on the side surface of the oxide 230 a. For example, as shown in fig. 8C, the oxide 230a sometimes includes an oxide 230a1 and an oxide 230a2. Oxide 230a2 is disposed between oxide 230a1 and insulator 252. When an in—mb-Zn oxide is used as the oxide 230a before aluminum addition, the oxide 230a1 contains indium, the element Mb, and zinc, and the oxide 230a2 contains indium, the element Mb, aluminum, and zinc.

Here, fig. 9A shows an energy band diagram when aluminum is added to the oxide 230 b. In fig. 9A, the vertical axis represents energy, and the horizontal direction represents the film thickness direction of the central portion of the channel formation region. In fig. 9A, the valence band top (VBM) and conduction band bottom (CBM) of each of the oxide 230a, the oxide 230b, the insulator 252, and the insulator 250 are shown in a state where no voltage is applied between the gate and the source. Note that since the energy of the top of the valence band and the energy of the bottom of the conduction band vary depending on the constituent elements of each of the oxide 230a, the oxide 230b, the insulator 252, and the insulator 250 and the composition thereof, the relationship between the energy of the top of the valence band and the relationship between the energy of the bottom of the conduction band will be mainly described with reference to the energy band diagram of fig. 9A.

Fig. 9A is an energy band diagram when the oxide 230b has a concentration gradient in which the aluminum concentration becomes higher from the lower side of the oxide 230b toward the top surface of the oxide 230 b. In fig. 9A, a region of the oxide 230b where the aluminum concentration is relatively low is illustrated as a first region of the oxide 230b and a region of the oxide 230b where the aluminum concentration is relatively high is illustrated as a second region of the oxide 230 b.

Alumina is an insulator, and oxide 230b is used as a semiconductor layer, so the bandgap of insulator 252 is larger than the bandgap of oxide 230 b. In addition, when aluminum is added, the band gap of the second region of oxide 230b is larger than the band gap of the first region of oxide 230 b. That is, the second region of the oxide 230b is widened.

For example, as shown in fig. 9A, it is presumed that the energy of the conduction band bottom of the oxide 230b becomes higher as it approaches the insulator 252 (changes in such a manner as to approach the vacuum level as it approaches the insulator 252). In addition, it is presumed that the energy of the valence band top of oxide 230b becomes lower as it approaches insulator 252 (in a manner that varies as it approaches insulator 252 away from the vacuum level).

As shown in fig. 9A, the transistor 200 has a structure in which a first region of the oxide 230b is sandwiched between an oxide 230a having a larger band gap than the first region of the oxide 230b and a second region of the oxide 230 b. By adopting this structure, embedding of the channel can be achieved. That is, in this structure, a path through which more current flows is formed near the interface between the oxide 230a and the first region of the oxide 230b, near the interface between the first region of the oxide 230b and the second region of the oxide 230b, and/or near the interface between the second region of the oxide 230b and the insulator 252. Therefore, trap levels near the respective interfaces can be reduced in the current path. As a result, on-state current can be increased or reliability can be improved.

For example, the second region of the oxide 230b preferably has a region having an aluminum concentration of 5 atomic% or less or 3 atomic% or less and 0.5 atomic% or more. By adopting this structure, effects such as reduction of oxygen vacancies in the second region of the oxide 230b, realization of embedded channels, and the like can be exhibited.

Fig. 9B shows an energy band diagram when the oxide 230B has a stacked structure of the oxide 230B1 and the oxide 230B 2. In fig. 9B, the vertical axis represents energy, and the horizontal direction represents the film thickness direction of the central portion of the channel formation region. Fig. 9B shows the top and bottom of the valence band of oxide 230a, oxide 230B, insulator 252, and insulator 250, respectively, in a state where no voltage is applied between the gate and the source. Note that since the energy of the top of the valence band and the energy of the bottom of the conduction band vary depending on the constituent elements of each of the oxide 230a, the oxide 230B, the insulator 252, and the insulator 250 and the composition thereof, the relationship between the energy of the top of the valence band and the relationship between the energy of the bottom of the conduction band will be mainly described with reference to the energy band diagram of fig. 9B.

Fig. 9B is an energy band diagram in the case where the oxide 230B has a stacked structure of the oxide 230B1 and the oxide 230B 2.

As described above, the oxide 230b2 is made wide-gap by adding aluminum. For example, as shown in fig. 9B, it can be assumed that the conduction band bottom of oxide 230B2 is located between the conduction band bottom of oxide 230B1 and the conduction band bottom of insulator 252. In other words, it is presumed that the energy of the conduction band bottom of oxide 230b2 is greater than the energy of the conduction band bottom of oxide 230b1 and less than the energy of the conduction band bottom of insulator 252. Further, it is presumed that the valence band top of oxide 230b2 is located between the valence band top of oxide 230b1 and the valence band top of insulator 252. In other words, it is presumed that the energy of the top of the valance band of oxide 230b2 is less than the energy of the top of the valance band of oxide 230b1 and greater than the energy of the top of the valance band of insulator 252.

As shown in fig. 9B, the transistor 200 has a structure in which the oxide 230B1 is sandwiched between an oxide 230a and an oxide 230B2 which have a larger band gap than the oxide 230B 1. By adopting this structure, embedding of the channel can be achieved. That is, in this structure, a path through which more current flows is formed near the interface between the oxide 230a and the oxide 230b1, near the interface between the oxide 230b1 and the oxide 230b2, and/or near the interface between the oxide 230b2 and the insulator 252. Therefore, trap levels near the respective interfaces can be reduced in the current path. As a result, on-state current can be increased or reliability can be improved.

For example, the oxide 230b2 preferably has a region having an aluminum concentration of 5 atomic% or less or 3 atomic% or less and 0.5 atomic% or more. By adopting this structure, effects such as reduction of oxygen vacancies of the oxide 230b, realization of embedded channels, and the like can be exhibited.

< inhibition of formation of oxygen vacancies in Metal oxide due to Al >

In this section, formation of oxygen vacancies in the metal oxide due to aluminum was inhibited by calculation evaluation. Specifically, the formation energy of oxygen vacancies in the calculation model of the metal oxide is calculated using the first principle.

< calculation model >

Here, a calculation model of the metal oxide for first principle calculation is described.

First, a model of In-Ga-Zn oxide of a single crystal structure (sc-IGZO model) was prepared. The sc-IGZO model had a composition of In: ga: zn: o=1:1:1:4 [ atomic ratio ]. Furthermore, the sc-IGZO model is composed of 112 atoms.

Next, a model was produced in which one gallium atom in the sc-IGZO model was replaced with an aluminum atom. The model in which one gallium atom is substituted for an aluminum atom is hereinafter referred to as sc-IGAZO (1) model. Further, a model was produced in which two gallium atoms in the sc-IGZO model were replaced with aluminum atoms. The model in which two gallium atoms were substituted for aluminum atoms was hereinafter referred to as sc-IGAZO (2) model.

Fig. 10A to 10E show the sc-IGZO model. Fig. 10A is a sc-IGZO model when viewed from the B-axis direction, fig. 10B is a sc-IGZO model when viewed from the a-axis direction, and fig. 10C is a plan view of a layer including Ga and Zn surrounded by dotted lines in fig. 10B. Fig. 10D and 10E show the sc-IGAZO (1) model and the sc-IGAZO (2) model, respectively. Fig. 10D is a top view of a layer containing Al, ga, and Zn in the sc-IGAZO (1) model, and fig. 10E is a top view of a layer containing Al, ga, and Zn in the sc-IGAZO (2) model. The sc-IGZO model, sc-IGAZO (1) model, and sc-IGAZO (2) model are collectively referred to as a metal oxide calculation model hereinafter.

Next, one oxygen atom in the sc-IGZO model is removed. The oxygen atom is an oxygen atom not bonded to an aluminum atom, and is shown by an arrow in fig. 10C. In addition, one oxygen atom in the sc-IGAZO (1) model was removed. The oxygen atom is an oxygen atom bonded to one aluminum atom, and is shown by an arrow in fig. 10D. In addition, one oxygen atom in the sc-IGAZO (2) model was removed. The oxygen atom is an oxygen atom bonded to two aluminum atoms, and is shown by an arrow in fig. 10E. The calculated model of each metal oxide after removal of the oxygen atoms has oxygen vacancies. This model is sometimes referred to hereinafter as a computational model of a metal oxide having oxygen vacancies.

The above is an illustration of a computational model of the metal oxide.

< calculation condition >

As the first principle calculation, a first principle electronic state calculation program VASP is used. Note that the calculation conditions are the same as those in table 1 above.

And calculating the energy of formation of oxygen vacancies of the calculation model of the metal oxide according to the calculation conditions. Calculating energy (E) of oxygen vacancy formation based on the above expression (1), the following expression (2) and the following expression (3) _form (IGZO：V _○ )、E _form (IGAZO(1)：V _O ) E and E _form (IGAZO(2)：V _O ))。

[ formula 2]

E _form (IGAZO(1)：Vo)＝E(IGAZO(1)：Vo)+μ _O -E(IGAZO(1)) (2)

E _form (IGAZO(2)：Vo)＝E(IGAZO(2)：Vo)+μ _O -E(IGAZO(2)) (3)

Here, E (IGZO) is the total energy of the sc-IGZO model, E (IGZO: V) _O ) Is the total energy of the sc-IGZO model with oxygen vacancies. E (IGAZO (1)) is the total energy of the sc-IGAZO (1) model, E (IGAZO (1): V _O ) Is a sc-IGAZO (1) mould with oxygen vacanciesTotal energy of the type. E (IGAZO (2)) is the total energy of the sc-IGAZO (2) model, E (IGAZO (2): V _O ) Is the total energy of the sc-IGAZO (2) model with oxygen vacancies. In addition, mu _O Is the chemical potential of oxygen and is 1/2 of the energy of the oxygen molecule.

Fig. 10F shows the result of energy of formation of oxygen vacancies of the calculation model of each metal oxide calculated using the above formula. In FIG. 10F, the horizontal axis represents the number of Al atoms [ number ] in the calculation model of each metal oxide]The vertical axis represents oxygen vacancy formation energy (V _○ formation energy)[eV]. Note that the number of Al atoms in the calculation model of each metal oxide may be replaced with the number of Al atoms coordinated around the removed oxygen atoms or the number of Al atoms near the oxygen vacancies.

As shown in fig. 10F, the greater the number (ratio) of Al coordinated around the oxygen atom, the greater the energy of formation of oxygen vacancies. In other words, it was observed that there was a positive correlation between the energy of formation of oxygen vacancies and the number (ratio) of Al coordinated around the oxygen atoms.

From the calculation results, there is shown a tendency that the formation energy of oxygen vacancies is large when Al is added to the metal oxide, i.e., a tendency that oxygen vacancies are not easily formed.

From this, it is found that when Al is added to a metal oxide as in the transistor of the present embodiment, formation of oxygen vacancies is suppressed. Thus, in the transistor according to the present embodiment, a stable i-type region can be formed in the channel formation region of the oxide semiconductor.

The above description is about the suppression of oxygen vacancies formed in the metal oxide by Al.

Note that a structure in which the oxide 230 has a concentration gradient or a structure in which the oxide 230 has a stacked structure of a first metal oxide layer and a second metal oxide layer is described as an example when aluminum oxide is used as the insulator 252, but the present invention is not limited thereto. As described above, as the insulator 252, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), magnesium oxide, or the like may be used in addition to aluminum oxide. The bonding energy of the hafnium atom, the silicon atom, the magnesium atom, and the like to the oxygen atom is larger than that of the indium atom or the zinc atom. Therefore, even when hafnium oxide, an aluminum-and hafnium-containing oxide (hafnium aluminate), a hafnium-and silicon-containing oxide (hafnium silicate), magnesium oxide, or the like is used as the insulator 252 in addition to aluminum oxide, the above-described structure may be employed.

For example, when magnesium oxide is used as the insulator 252, the oxide 230 may have a concentration gradient in which the magnesium concentration increases from the lower surface of the oxide 230 toward the top surface of the oxide 230. Alternatively, the oxide 230 may have a stacked structure of a first metal oxide layer and a second metal oxide layer containing magnesium. Further, for example, when hafnium oxide is used as the insulator 252, the oxide 230 may have a concentration gradient that increases from the lower surface of the oxide 230 toward the top surface of the oxide 230. Alternatively, the oxide 230 may have a stacked structure of a first metal oxide layer and a second metal oxide layer containing hafnium.

The insulator 250 is used as part of a gate insulator. Insulator 250 is preferably configured to contact the top surface of insulator 252. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having voids, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. At this time, the insulator 250 is an insulator containing at least oxygen and silicon.

Like the insulator 224, the concentration of impurities such as water and hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1nm to 20nm, more preferably 0.5nm to 15.0 nm. At this time, at least a part of the insulator 250 may be a region having the above thickness.

In fig. 1A to 1D, etc., the insulator 250 is shown as having a single-layer structure, but the present invention is not limited thereto, and a stacked structure of two or more layers may be employed. For example, as shown in fig. 2B, the insulator 250 may have a laminated structure of two layers, that is, an insulator 250a and an insulator 250B on the insulator 250 a.

As shown in fig. 2B, in the case where the insulator 250 has a two-layered structure, it is preferable that the insulator 250a of the lower layer is formed using an insulator that easily transmits oxygen, and the insulator 250B of the upper layer is formed using an insulator that has a function of suppressing diffusion of oxygen. By adopting such a structure, diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Further, oxidation of the conductor 260 due to oxygen contained in the insulator 250a can be suppressed. For example, the insulator 250a may be made of the material that can be used for the insulator 250, and the insulator 250b may be made of an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, hafnium oxide is used as the insulator 250 b. At this time, the insulator 250b is an insulator containing at least oxygen and hafnium. The thickness of the insulator 250b is 0.5nm or more and 5.0nm or less, preferably 1.0nm or more and 5.0nm or less, and more preferably 1.0nm or more and 3.0nm or less. At this time, at least a part of the insulator 250b may be a region having the above thickness.

Note that when silicon oxide, silicon oxynitride, or the like is used for the insulator 250a, the insulator 250b may be formed using an insulating material of a high-k material having a high relative dielectric constant. By using a stacked structure of the insulator 250a and the insulator 250b as a gate insulator, a stacked structure having high thermal stability and a high relative dielectric constant can be formed. Accordingly, the gate potential applied when the transistor operates can be reduced while maintaining the physical thickness of the gate insulator. In addition, the Equivalent Oxide Thickness (EOT) of the insulator used as the gate insulator can be reduced. Therefore, the dielectric breakdown voltage of the insulator 250 can be improved.

The insulator 254 is used as part of the gate insulator. A hydrogen blocking insulating film is preferably used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and the oxide 230b. The insulator 254 may be the insulator 283. For example, silicon nitride deposited by PEALD method may be used as the insulator 254. At this time, the insulator 254 is an insulator containing at least nitrogen and silicon.

The insulator 254 may also have oxygen barrier properties. Thereby, diffusion of oxygen contained in the insulator 250 to the conductor 260 can be suppressed.

In addition, the insulator 254 needs to be provided in an opening formed in the insulator 280 or the like together with the insulator 252, the insulator 250, the conductor 260. To achieve miniaturization of the transistor 200, the thickness of the insulator 254 is preferably small. The thickness of the insulator 254 is 0.1nm or more and 5.0nm or less, preferably 0.5nm or more and 3.0nm or less, and more preferably 1.0nm or more and 3.0nm or less. At this time, at least a part of the insulator 254 may be a region having the above thickness. In addition, the thickness of the insulator 254 is preferably smaller than the thickness of the insulator 250. At this time, at least a part of the insulator 254 may be a region having a smaller thickness than the insulator 250.

Further, as shown in fig. 2B, when the insulator 250 has a two-layer stacked structure, the insulator 250B can also have the function of the insulator 254 by using an insulator such as hafnium oxide having a function of suppressing permeation of impurities such as hydrogen and oxygen as the insulator 250B. In this case, by adopting a structure in which the insulator 254 is not provided, the manufacturing process of the semiconductor device can be simplified, and improvement in productivity can be achieved.

The conductor 260 is used as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surfaces of the conductor 260b. Further, as shown in fig. 1B and 1C, the top surface of the conductor 260 is substantially aligned with the top surface of the insulator 250. Although the conductor 260 has a two-layer structure of the conductor 260a and the conductor 260B in fig. 1B and 1C, a single-layer structure or a stacked structure of three or more layers may be used.

As the conductor 260a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms is preferably used. Further, a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) is preferably used.

Further, when the conductor 260a has a function of suppressing diffusion of oxygen, oxygen contained in the insulator 250 can be suppressed from oxidizing the conductor 260b, resulting in a decrease in conductivity. As the conductive material having a function of suppressing oxygen diffusion, for example, titanium nitride, tantalum nitride, ruthenium oxide, or the like can be used.

Further, since the conductor 260 is also used as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used for the conductor 260 b. The conductor 260b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-described conductive material.

In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be surely arranged without alignment in the region between the conductor 242a and the conductor 242 b.

As shown in fig. 1C, the height of the bottom surface of the region of the conductor 260 where the conductor 260 does not overlap with the oxide 230b is preferably lower than the height of the bottom surface of the oxide 230b with respect to the bottom surface of the insulator 222 in the channel width direction of the transistor 200. By adopting a structure in which the conductor 260 serving as a gate electrode covers the side surface and the top surface of the channel formation region of the oxide 230b with the insulator 250 or the like interposed therebetween, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230 b. This can improve the on-state current and frequency characteristics of the transistor 200. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a and the oxide 230b do not overlap the conductor 260 when the bottom surface of the insulator 222 is the reference is 0nm or more and 100nm or less, preferably 3nm or more and 50nm or less, and more preferably 5nm or more and 20nm or less.

Insulator 280 is disposed on insulator 275, and openings are formed in the areas where insulator 252, insulator 250, insulator 254, and conductor 260 are disposed. In addition, the top surface of insulator 280 may also be planarized.

It is preferable that the dielectric constant of the insulator 280 used as the interlayer film is low. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Insulator 280 is preferably formed of the same material as insulator 216, for example. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. Alternatively, a material such as silicon oxide, silicon oxynitride, or silicon oxide having voids is particularly preferable because a region containing oxygen which is desorbed by heating is easily formed.

The concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. For example, an oxide containing silicon such as silicon oxide or silicon oxynitride may be appropriately used as the insulator 280.

The insulator 282 is preferably used as a barrier insulating film for suppressing diffusion of impurities such as water and hydrogen from above to the insulator 280, and has a function of trapping impurities such as hydrogen. Further, the insulator 282 is preferably used as a blocking insulating film that suppresses oxygen permeation. As the insulator 282, a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide may be used. The insulator 282 in this case is an insulator containing at least oxygen and aluminum. By providing the insulator 282 which is in contact with the insulator 280 and has a function of capturing impurities such as hydrogen in the region sandwiched between the insulator 212 and the insulator 283, the impurities such as hydrogen contained in the insulator 280 and the like can be captured, and the amount of hydrogen in the region can be kept constant. In particular, the insulator 282 preferably uses alumina having an amorphous structure, because hydrogen can be trapped or fixed more effectively in some cases. Thus, the transistor 200 and the semiconductor device having good characteristics and high reliability can be manufactured.

As the insulator 282, aluminum oxide is preferably deposited by a sputtering method, and more preferably aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform to improve the sputtering rate and film quality. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into the lower layer of insulator 282 may be controlled according to the amount of RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the underlying layer of insulator 282, which is susceptible to saturation even if insulator 282 is thinner. In addition, the greater the RF power, the greater the amount of oxygen injected into the underlying layers of insulator 282.

The RF power is set to, for example, 0W/cm ² Above and 1.86W/cm ² The following is given. In other words, the oxygen amount may be changed to an amount suitable for the characteristics of the transistor according to the RF power at the time of forming the insulator 282 and injected. Accordingly, oxygen in an amount suitable for improving the reliability of the transistor can be injected.

The frequency of RF is preferably 10MHz or more. Typically 13.56MHz. The higher the frequency of RF, the less damage can be done to the substrate.

In fig. 1A to 1D, etc., the insulator 282 is shown as having a single-layer structure, but the present invention is not limited to this, and a stacked structure of two or more layers may be employed. For example, as shown in fig. 6A, the insulator 282 may have a two-layered structure of the insulator 282a and the insulator 282b on the insulator 282 a.

Preferably, the insulator 282a and the insulator 282b are formed in different ways using the same material. For example, in the case where aluminum oxide is deposited as the insulator 282 by a pulsed DC sputtering method using an aluminum target in an atmosphere containing oxygen, it is preferable that the RF power applied to the substrate when the insulator 282a is deposited is different from the RF power applied to the substrate when the insulator 282b is deposited, and more preferable that the RF power applied to the substrate when the insulator 282a is deposited is lower than the RF power applied to the substrate when the insulator 282b is deposited. Specifically, the RF power applied to the substrate was set to 0W/cm ² Above and 0.62W/cm ² The insulator 282a is deposited below, and the RF power applied to the substrate is set to 1.86W/cm ² Insulator 282b is deposited as follows. More specifically, the RF power applied to the substrate was set to 0W/cm ² Insulator 282a was deposited and the RF power applied to the substrate was set to 0.31W/cm ² Insulator 282b is deposited. By adopting this structure, the insulator 282 can be made amorphous and the amount of oxygen supplied to the insulator 280 can be adjusted.

Note that the number of the components to be processed,the RF power applied to the substrate when insulator 282a is deposited may also be higher than the RF power applied to the substrate when insulator 282b is deposited. Specifically, the RF power applied to the substrate was set to 1.86W/cm ² The insulator 282a is deposited below, and the RF power applied to the substrate is set to 0W/cm ² Above and 0.62W/cm ² Insulator 282b is deposited as follows. More specifically, the RF power applied to the substrate was set to 1.86W/cm ² Insulator 282a was deposited and the RF power applied to the substrate was set to 0.62W/cm ² Insulator 282b is deposited. By adopting this structure, the amount of oxygen supplied to the insulator 280 can be increased.

The film thickness of the insulator 282a is 1.0nm to 20nm, preferably 1.5nm to 15nm, more preferably 2.0nm to 10nm, still more preferably 3.0nm to 8.0 nm. By adopting this structure, the insulator 282a can be made amorphous regardless of the magnitude of RF power. Further, by making the insulator 282a amorphous, the insulator 282b can be easily made amorphous, and the insulator 282 can be made amorphous.

The insulator 282a and the insulator 282b have a laminated structure made of the same material, but the present invention is not limited thereto. The insulator 282a and the insulator 282b may have a stacked structure formed of different materials.

The insulator 283 serves as a barrier insulating film that suppresses diffusion of impurities such as water, hydrogen, and the like from above to the insulator 280. Insulator 283 is disposed on insulator 282. As the insulator 283, a nitride containing silicon such as silicon nitride or silicon oxynitride is preferably used. For example, silicon nitride deposited by a sputtering method may be used as the insulator 283. By depositing the insulator 283 using a sputtering method, a silicon nitride film with high density can be formed. Further, as the insulator 283, silicon nitride deposited by a PEALD method or a CVD method may be further stacked on silicon nitride deposited by a sputtering method.

The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a stacked structure.

When a stacked structure is used as the conductor 240, a conductive material having a function of suppressing permeation of impurities such as water and hydrogen is preferably used as the first conductor disposed in the vicinity of the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271. For example, tantalum nitride, titanium nitride, ruthenium oxide, or the like is preferably used. The conductive material having a function of suppressing permeation of impurities such as water and hydrogen can be used in a single layer or a stacked layer. Further, impurities such as water and hydrogen contained in a layer over the insulator 283 can be prevented from being mixed into the oxide 230 through the conductors 240a and 240 b.

As the insulator 241a and the insulator 241b, a block insulating film which can be used for the insulator 275 or the like may be used. As the insulator 241a and the insulator 241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 283, the insulator 282, and the insulator 271, impurities such as water and hydrogen contained in the insulator 280 and the like can be prevented from being mixed into the oxide 230 through the conductors 240a and 240 b. In particular, silicon nitride is preferable because it has high hydrogen barrier properties. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240 b.

When the insulator 241a and the insulator 241B have a stacked structure as shown in fig. 1B, it is preferable to use an oxygen-blocking insulating film and a hydrogen-blocking insulating film in combination as a first insulator in contact with the inner wall of the opening of the insulator 280 or the like and a second insulator inside thereof.

For example, aluminum oxide deposited by an ALD method may be used as the first insulator, and silicon nitride deposited by a PEALD method may be used as the second insulator. By adopting such a structure, oxidation of the conductor 240 can be suppressed, and entry of hydrogen into the conductor 240 can be suppressed.

In addition, the conductor 246a used as a wiring may be arranged so as to be in contact with the top surface of the conductor 240 a. In addition, the conductor 246b used as a wiring may be arranged so as to be in contact with the top surface of the conductor 240 b. The conductor 246 (the conductor 246a and the conductor 246 b) is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above-described conductive material. The conductor may be formed so as to be fitted into an opening formed in the insulator.

< constituent Material of semiconductor device >

The constituent materials that can be used for the semiconductor device are described below.

Substrate

As a substrate for forming the transistor 200, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, a semiconductor substrate having an insulator region inside the semiconductor substrate may be exemplified by an SOI (Silicon On Insulator; silicon on insulator) substrate or the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, or the like can be given. Further, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like can be given. Alternatively, a substrate having an element provided over these substrates may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

Insulator

Examples of the insulator include insulating oxides, nitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.

For example, when miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material as an insulator used as a gate insulator, a low voltage at the time of transistor operation can be achieved while maintaining physical thickness. On the other hand, by using a material having a low relative dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material is preferably selected according to the function of the insulator.

Examples of the insulator having a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Examples of the insulator having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, and resin.

Further, the transistor using a metal oxide is surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, whereby the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, for example, a single layer or a stacked layer of an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or a metal nitride such as aluminum nitride, silicon oxynitride, or silicon nitride can be used.

Further, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen which is desorbed by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen which is desorbed by heating is in contact with the oxide 230, oxygen vacancies contained in the oxide 230 can be filled.

< conductor >

As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like, an alloy containing the above metal element as a component, an alloy in which the above metal element is combined, or the like is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity are preferable. Further, a semiconductor having high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

In addition, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked-layer structure of a material containing the above metal element and a conductive material containing oxygen may be used. In addition, a stacked structure of a material containing the above metal element and a conductive material containing nitrogen may be used. In addition, a stacked-layer structure in which a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may also be employed.

In addition, in the case where an oxide is used for a channel formation region of a transistor, a stacked-layer structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is preferably used as a conductive body to be used as a gate electrode. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is easily supplied to the channel formation region.

In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in a metal oxide in which a channel is formed is preferably used. In addition, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon is added may also be used. In addition, indium gallium zinc oxide containing nitrogen may also be used. By using the above material, hydrogen contained in the metal oxide forming the channel may be trapped in some cases. Alternatively, hydrogen mixed from an insulator or the like outside may be trapped.

Metal oxide

As the oxide 230, a metal oxide (oxide semiconductor) used as a semiconductor is preferably used. Next, a metal oxide which can be used for the oxide 230 according to the present invention will be described.

The metal oxide preferably contains at least indium or zinc. Particularly preferred are indium and zinc. In addition, aluminum, gallium, yttrium, tin, and the like are preferably contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like may be contained.

Consider here the case where the metal oxide is an In-M-Zn oxide comprising indium, the element M and zinc. Note that element M is aluminum, gallium, yttrium, or tin. As other elements that can be applied to the element M, there are boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like. Note that as the element M, a plurality of the above elements may be combined in some cases. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium and tin.

In particular, as a semiconductor layer of a transistor, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, as the semiconductor layer of the transistor, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used. Alternatively, as a semiconductor layer of the transistor, an oxide (IAGZO or IGAZO) containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) may be used.

In this specification and the like, a metal oxide containing nitrogen may be referred to as a metal oxide (metal oxide). In addition, the metal oxide containing nitrogen may also be referred to as metal oxynitride (metal oxynitride).

Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) is described as an example of a metal oxide. Note that oxides containing indium (In), gallium (Ga), and zinc (Zn) are sometimes referred to as In-Ga-Zn oxides.

< classification of Crystal Structure >

Examples of the crystalline structure of the oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (closed-aligned composite), single crystal (single crystal), and polycrystalline (poly crystal).

The crystalline structure of the film or substrate can be evaluated using X-Ray Diffraction (XRD) spectroscopy. For example, the XRD spectrum measured by GIXD (Graving-incoedence XRD) measurement can be used for evaluation. Furthermore, the GIXD process is also referred to as a thin film process or a Seemann-Bohlin process. Hereinafter, the XRD spectrum obtained by the GIXD measurement may be simply referred to as XRD spectrum.

For example, the peak shape of the XRD spectrum of the quartz glass substrate is substantially bilaterally symmetrical. On the other hand, the peak shape of the XRD spectrum of the In-Ga-Zn oxide film having a crystal structure is not bilaterally symmetrical. The shape of the peaks of the XRD spectrum are left-right asymmetric to indicate the presence of crystals in the film or in the substrate. In other words, unless the XRD spectrum peak shape is bilaterally symmetrical, it cannot be said that the film or substrate is in an amorphous state.

In addition, the crystalline structure of the film or substrate can be evaluated using a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by a nanobeam electron diffraction method (NBED: nano Beam Electron Diffraction). For example, it can be confirmed that the quartz glass is in an amorphous state by observing a halo pattern in a diffraction pattern of the quartz glass substrate. In addition, a spot-like pattern was observed In the diffraction pattern of the In-Ga-Zn oxide film deposited at room temperature without the halo being observed. It is therefore presumed that the In-Ga-Zn oxide film deposited at room temperature is In an intermediate state that is neither single crystal or polycrystalline nor amorphous, and it cannot be concluded that the In-Ga-Zn oxide film is amorphous.

Structure of oxide semiconductor

Note that, when focusing attention on the structure of an oxide semiconductor, the classification of the oxide semiconductor may be different from the above. For example, oxide semiconductors can be classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors other than the single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the CAAC-OS and nc-OS described above. The non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, an a-like OS (amorphorus-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

Details of the CAAC-OS, nc-OS, and a-like OS will be described herein.

[CAAC-OS]

The CAAC-OS is an oxide semiconductor including a plurality of crystal regions, the c-axis of which is oriented in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystallization region is a region having periodicity of atomic arrangement. Note that the crystal region is also a region in which lattice arrangements are uniform when the atomic arrangements are regarded as lattice arrangements. The CAAC-OS may have a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have distortion. In addition, distortion refers to a portion in which the direction of lattice arrangement changes between a region in which lattice arrangements are uniform and other regions in which lattice arrangements are uniform among regions in which a plurality of crystal regions are connected. In other words, CAAC-OS refers to an oxide semiconductor that is c-axis oriented and has no significant orientation in the a-b plane direction.

Each of the plurality of crystal regions is composed of one or more fine crystals (crystals having a maximum diameter of less than 10 nm). In the case where the crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10nm. In the case where the crystal region is composed of a plurality of fine crystals, the maximum diameter of the crystal region may be about several tens of nm.

In addition, the CAAC-OS has a layered crystal structure (also referred to as a layered structure) In which a layer containing indium (In) and oxygen (hereinafter, in layer), and a layer containing gallium (Ga), zinc (Zn) and oxygen (hereinafter, (Ga, zn) layer) are stacked In the In-Ga-Zn oxide. In addition, indium and gallium may be substituted for each other. Therefore, the (Ga, zn) layer sometimes contains indium. In addition, sometimes the In layer contains gallium. Note that sometimes the In layer contains zinc. The layered structure is observed as a lattice image, for example, in a high resolution TEM (Transmission Electron Microscope) image.

For example, when structural analysis is performed on a CAAC-OS film using an XRD device, a peak representing c-axis orientation is detected at or near 2θ=31° in Out-of-plane XRD measurement using θ/2θ scanning. Note that the position (2θ value) of the peak representing the c-axis orientation may vary depending on the kind, composition, and the like of the metal element constituting the CAAC-OS.

Further, for example, a plurality of bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. In addition, when a spot of an incident electron beam (also referred to as a direct spot) passing through a sample is taken as a symmetry center, a certain spot and other spots are observed at a point-symmetrical position.

When the crystal region is observed from the above specific direction, the lattice arrangement in the crystal region is basically a hexagonal lattice, but the unit cell is not limited to a regular hexagon, and may be a non-regular hexagon. In addition, the distortion may have a lattice arrangement such as pentagonal or heptagonal. In addition, no clear grain boundary (grain boundary) was observed near the distortion of CAAC-OS. That is, distortion of the lattice arrangement suppresses the formation of grain boundaries. This is probably because CAAC-OS can accommodate distortion due to low density of arrangement of oxygen atoms in the a-b face direction or change in bonding distance between atoms due to substitution of metal atoms, or the like.

In addition, the crystal structure in which a clear grain boundary is confirmed is called "polycrystal". Since the grain boundary serves as a recombination center and carriers are trapped, there is a possibility that on-state current of the transistor is lowered, field effect mobility is lowered, or the like. Therefore, CAAC-OS, in which no clear grain boundaries are found, is one of crystalline oxides that give a semiconductor layer of a transistor an excellent crystalline structure. Note that, in order to constitute the CAAC-OS, a structure containing Zn is preferable. For example, in—zn oxide and in—ga—zn oxide are preferable because occurrence of grain boundaries can be further suppressed than In oxide.

CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundary is confirmed. Therefore, it can be said that in the CAAC-OS, a decrease in electron mobility due to grain boundaries does not easily occur. Further, since crystallinity of an oxide semiconductor is sometimes lowered by contamination with impurities, generation of defects, or the like, CAAC-OS is said to be an oxide semiconductor having few impurities and defects (oxygen vacancies, or the like). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, an oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Thus, by using CAAC-OS for a transistor including a metal oxide in a channel formation region (which is sometimes referred to as an OS transistor), the degree of freedom in manufacturing processes can be increased.

[nc-OS]

In nc-OS, atomic arrangements in minute regions (for example, regions of 1nm to 10nm, particularly, regions of 1nm to 3 nm) have periodicity. In other words, nc-OS has a minute crystal. For example, the size of the fine crystals is 1nm to 10nm, particularly 1nm to 3nm, and the fine crystals are called nanocrystals. Furthermore, the nc-OS did not observe regularity of crystal orientation between different nanocrystals. Therefore, the orientation was not observed in the whole film. Therefore, nc-OS is sometimes not different from a-like OS or amorphous oxide semiconductor in some analytical methods. For example, when the nc-OS film is subjected to structural analysis by using an XRD device, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ/2θ scanning. In addition, when an electron diffraction (also referred to as selective electron diffraction) using an electron beam having a beam diameter larger than that of nanocrystals (for example, 50nm or more) is performed on the nc-OS film, a diffraction pattern resembling a halo pattern is observed. On the other hand, when an electron diffraction (also referred to as a "nanobeam electron diffraction") using an electron beam having a beam diameter equal to or smaller than the size of a nanocrystal (for example, 1nm or more and 30nm or less) is performed on an nc-OS film, an electron diffraction pattern in which a plurality of spots are observed in an annular region centered on a direct spot may be obtained.

[a-like OS]

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-likeOS contains voids or low density regions. That is, the crystallinity of a-likeOS is lower than that of nc-OS and CAAC-OS. The concentration of hydrogen in the film of a-like OS is higher than that in the films of nc-OS and CAAC-OS.

Structure of oxide semiconductor

Next, the details of the CAC-OS will be described. In addition, CAC-OS is related to material composition.

[CAC-OS]

The CAC-OS refers to, for example, a constitution in which elements contained in a metal oxide are unevenly distributed, wherein the size of a material containing unevenly distributed elements is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size. Note that a state in which one or more metal elements are unevenly distributed in a metal oxide and a region including the metal elements is mixed is also referred to as a mosaic shape or a patch shape hereinafter, and the size of the region is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size.

The CAC-OS is a structure in which a material is divided into a first region and a second region, and the first region is mosaic-shaped and distributed in a film (hereinafter also referred to as cloud-shaped). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

Here, the atomic number ratios of In, ga and Zn with respect to the metal elements constituting the CAC-OS of the In-Ga-Zn oxide are each represented by [ In ], [ Ga ] and [ Zn ]. For example, in CAC-OS of In-Ga-Zn oxide, the first region is a region whose [ In ] is larger than that In the composition of the CAC-OS film. Further, the second region is a region whose [ Ga ] is larger than [ Ga ] in the composition of the CAC-OS film. Further, for example, the first region is a region whose [ In ] is larger than that In the second region and whose [ Ga ] is smaller than that In the second region. Further, the second region is a region whose [ Ga ] is larger than that In the first region and whose [ In ] is smaller than that In the first region.

Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, or the like. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, or the like. In other words, the first region may be referred to as a region mainly composed of In. The second region may be referred to as a region containing Ga as a main component.

Note that a clear boundary between the first region and the second region may not be observed.

The CAC-OS In the In-Ga-Zn oxide is constituted as follows: in the material composition containing In, ga, zn, and O, a region having a part of the main component Ga and a region having a part of the main component In are irregularly present In a mosaic shape. Therefore, it is presumed that the CAC-OS has a structure in which metal elements are unevenly distributed.

The CAC-OS can be formed by, for example, sputtering without heating the substrate. In the case of forming CAC-OS by the sputtering method, as the deposition gas, any one or more selected from inert gas (typically argon), oxygen gas, and nitrogen gas may be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas at the time of deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas at the time of deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

For example, in CAC-OS of In-Ga-Zn oxide, it was confirmed that the structure was mixed by unevenly distributing a region (first region) mainly composed of In and a region (second region) mainly composed of Ga based on an EDX-plane analysis (mapping) image obtained by an energy dispersive X-ray analysis method (EDX: energy Dispersive X-ray spectroscopy).

Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, conductivity as a metal oxide is exhibited. Thus, when the first region is distributed in a cloud in the metal oxide, high field effect mobility (μ) can be achieved.

On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

In the case of using the CAC-OS for the transistor, the CAC-OS can be provided with a switching function (a function of controlling on/off) by a complementary effect of the conductivity due to the first region and the insulation due to the second region. In other words, the CAC-OS material has a conductive function in one part and an insulating function in the other part, and has a semiconductor function in the whole material. By separating the conductive function from the insulating function, each function can be improved to the maximum extent. Thus, by using CAC-OS for the transistor, a high on-state current (I _on ) High field effect mobility (μ) and good switching operation.

Further, a transistor using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as display devices.

Oxide semiconductors have various structures and various characteristics. The oxide semiconductor according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-likeOS, CAC-OS, nc-OS, and CAAC-OS.

< transistor including oxide semiconductor >

Next, a case where the above oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor described above for a transistor, a transistor with high field effect mobility can be realized. Further, a transistor with high reliability can be realized.

An oxide semiconductor having a low carrier concentration is preferably used for the transistor. For example, the carrier concentration of the oxide semiconductor may be 1×10 ¹⁷ cm ^-3 Hereinafter, it is preferably 1X 10 ¹⁵ cm ^-3 Hereinafter, more preferably 1X 10 ¹³ cm ^-3 Hereinafter, it is more preferable that 1×10 ¹¹ cm ^-3 Hereinafter, it is more preferably less than 1X 10 ¹⁰ cm ^-3 And is 1X 10 ^-9 cm ^-3 The above. In the case of aiming at reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification and the like, a state in which the impurity concentration is low and the defect state density is low is referred to as a high-purity intrinsic or substantially high-purity intrinsic. Further, an oxide semiconductor having a low carrier concentration is sometimes referred to as a high-purity intrinsic oxide semiconductor or a substantially high-purity intrinsic oxide semiconductor.

Since the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, it is possible to have a low trap state density.

Further, it takes a long time until the charge trapped in the trap state of the oxide semiconductor disappears, and the charge may act like a fixed charge. Therefore, the transistor in which the channel formation region is formed in the oxide semiconductor having a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like. Note that impurities in an oxide semiconductor refer to elements other than the main component constituting the oxide semiconductor, for example. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity.

< impurity >

Here, the influence of each impurity in the oxide semiconductor will be described.

When the oxide semiconductor contains silicon or carbon which is one of group 14 elements, a defect state is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon (concentration measured by SIMS) of the oxide semiconductor is set to, for example, 2X 10 ¹⁸ atoms/cm ³ Hereinafter, it is preferably 2×10 ¹⁷ atoms/cm ³ The following is given.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has normally-on characteristics. Thus, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS was set to 1X 10 ¹⁸ atoms/cm ³ Hereinafter, it is preferably 2X 10 ¹⁶ atoms/cm ³ The following is given.

When the oxide semiconductor contains nitrogen, electrons are generated as carriers, and the carrier concentration is increased, so that n-type is easily performed. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor tends to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, a trap state may be formed. As a result, the electrical characteristics of the transistor may be unstable. Therefore, the nitrogen concentration in the oxide semiconductor measured by SIMS is set to be lower than 5X 10 ¹⁹ atoms/cm ³ Preferably 5X 10 ¹⁸ atoms/cm ³ Hereinafter, more preferably 1X 10 ¹⁸ atoms/cm ³ Hereinafter, it is more preferable that the ratio is 5X 10 ¹⁷ atoms/cm ³ The following is given.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, and thus oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons are sometimes generated as carriers. In addition, some of the hydrogen may be bonded to oxygen bonded to a metal atom, thereby generating electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has normally-on characteristics. Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration of the oxide semiconductor measured by SIMS is set to be less than 1×10 ²⁰ atoms/cm ³ Preferably less than 1X 10 ¹⁹ atoms/cm ³ More preferably less than 5X 10 ¹⁸ atoms/cm ³ More preferably less than 1X 10 ¹⁸ atoms/cm ³ 。

By using an oxide semiconductor whose impurity is sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

< other semiconductor materials >

The semiconductor material that can be used for the oxide 230 is not limited to the above-described metal oxide. As the oxide 230, a semiconductor material having a band gap (a semiconductor material other than a zero band gap semiconductor) may be used. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, a layered substance (also referred to as an atomic layer substance, a two-dimensional material, or the like) used as a semiconductor, or the like is preferably used for the semiconductor material. In particular, a layered substance used as a semiconductor is preferably used for the semiconductor material.

In this specification and the like, a lamellar substance is a generic term for a group of materials having a lamellar crystal structure. The layered crystal structure is a structure in which layers formed of covalent bonds or ionic bonds are laminated by bonding weaker than covalent bonds and ionic bonds, such as van der waals forces. The layered substance has high conductivity in the unit layer, that is, has high two-dimensional conductivity. By using a material which is used as a semiconductor and has high two-dimensional conductivity for the channel formation region, a transistor with high on-state current can be provided.

As the layered substance, there are graphene, silylene, chalcogenide, and the like. Chalcogenides are compounds that contain an oxygen element. Further, the oxygen group element is a generic term for elements belonging to group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, . Examples of the chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

As the oxide 230, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As the transition metal chalcogenide that can be used as the oxide 230, there can be specifically mentioned molybdenum sulfide (typically MoS ₂ ) Molybdenum selenide (typically MoSe) ₂ ) Molybdenum telluride (typically MoTe ₂ ) Tungsten sulfide (typically WS) ₂ ) Tungsten selenide (typically WSe) ₂ ) Tungsten telluride (typically WTE) ₂ ) Hafnium sulfide (typically HfS) ₂ ) Hafnium selenide (typically HfSe) ₂ ) Zirconium sulfide (typically ZrS) ₂ ) SeleniumZirconium oxide (typically ZrSe) ₂ ) Etc.

< method for manufacturing semiconductor device >

Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention shown in fig. 1A to 1D will be described with reference to fig. 14A to 25D.

A in each drawing is a plan view. In addition, B in each drawing is a sectional view of a portion along a dash-dot line A1-A2 in a, which corresponds to a sectional view in the channel length direction of the transistor 200. C in each drawing is a sectional view of a portion along a dash-dot line A3 to A4 in a, which corresponds to a sectional view in the channel width direction of the transistor 200. Further, D in each drawing is a sectional view of a portion along a chain line A5 to A6 in a. For clarity, some constituent elements are omitted from the plan view of a in each drawing.

Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor may be deposited by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

Examples of the sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a direct-current power source is used, and a pulsed DC sputtering method in which a voltage applied to an electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, carbides, and the like by a reactive sputtering method.

Note that the CVD method can be classified into a Plasma Enhanced CVD (PECVD) method using plasma, a Thermal CVD (TCVD) method using heat, a light CVD (Photo CVD) method using light, and the like. The source gases used may be classified into a Metal CVD (MCVD: metal CVD) method and a Metal organic CVD (MOCVD: metal Organic CVD) method.

By using the plasma CVD method, a high-quality film can be obtained at a low temperature. In addition, since plasma is not used in the thermal CVD method, plasma damage to the object to be processed can be reduced. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) and the like included in a semiconductor device may generate charge accumulation (charge) by receiving charge from plasma. At this time, the wirings, electrodes, elements, and the like included in the semiconductor device may be damaged due to the accumulated charges. On the other hand, in the case of the thermal CVD method using no plasma, the plasma damage is not generated, and thus the yield of the semiconductor device can be improved. Further, in the thermal CVD method, plasma damage during deposition is not generated, and thus a film having fewer defects can be obtained.

As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted only with thermal energy, a PEALD method in which a reactant excited by plasma is used, or the like is used.

CVD and ALD are different from sputtering in which particles released from a target or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have good step coverage. In particular, the ALD method has excellent step coverage and thickness uniformity, and therefore, the ALD method is suitable for forming a film or the like covering the surface of an opening having a high aspect ratio. However, the ALD method may be used preferably in combination with other deposition methods such as a CVD method having a relatively low deposition rate.

Further, when the CVD method is used, a film of an arbitrary composition can be deposited by adjusting the flow ratio of the source gases. For example, when the CVD method is used, a film whose composition is continuously changed can be deposited by changing the flow ratio of the source gas while deposition is performed. When deposition is performed while changing the flow ratio of the source gases, since the time required for transferring or adjusting the pressure is not required, the deposition time can be shortened as compared with the case of forming using a plurality of deposition chambers. Therefore, the productivity of the semiconductor device may be improved.

When using ALD, films of arbitrary composition can be deposited by introducing different multiple precursors simultaneously. Alternatively, when a plurality of different precursors are introduced, films of arbitrary composition can be deposited by controlling the number of cycles of each precursor.

First, a substrate (not shown) is prepared, and an insulator 212 is deposited over the substrate (see fig. 14A to 14D). Insulator 212 is preferably deposited using a sputtering process. By using a sputtering method that does not require the use of a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 can be reduced. Note that deposition of the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.

In this embodiment, silicon nitride is deposited as the insulator 212 by a pulsed DC sputtering method using a silicon target in a nitrogen-containing gas atmosphere. By using the pulsed DC sputtering method, particles generated by arc (arcing) on the target surface can be suppressed, so that the thickness can be made more uniform. Further, by using the pulse voltage, the rise or fall at the time of discharge can be made sharp as compared with the high-frequency voltage. Thus, the power can be supplied to the electrode more efficiently, and the sputtering rate and the film quality can be improved.

Further, by using an insulator such as silicon nitride, which is not easily permeable to impurities such as water and hydrogen, diffusion of impurities such as water and hydrogen contained in a layer below the insulator 212 can be suppressed. Further, by using an insulator such as silicon nitride which does not easily allow copper to pass through as the insulator 212, even if a metal which easily diffuses such as copper is used as a conductor of a layer (not shown) below the insulator 212, the metal can be prevented from diffusing upward through the insulator 212.

Next, an insulator 214 is deposited over the insulator 212 (see fig. 14A to 14D). Insulator 214 is preferably deposited using a sputtering process. The concentration of hydrogen in the insulator 214 can be reduced by using a sputtering method that does not require the use of a molecule containing hydrogen as a deposition gas. Note that deposition of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.

In the present embodiment, alumina is deposited as the insulator 214 by a pulsed DC sputtering method using an aluminum target in an oxygen-containing gas atmosphere. By using the pulsed DC sputtering method, the thickness can be made more uniform to improve the sputtering rate and film quality. Here, RF power may be applied to the substrate. The amount of oxygen implanted into the underlying layer of insulator 214 may be controlled according to the amount of RF power applied to the substrate. Acting as Is RF power, set to 0W/cm ² Above and 1.86W/cm ² The following is given. In other words, the oxygen amount may be changed to an amount suitable for the characteristics of the transistor using RF power at the time of forming the insulator 214. Accordingly, oxygen in an amount suitable for improving the reliability of the transistor can be injected. The frequency of RF is preferably 10MHz or more. Typically 13.56MHz. The higher the frequency of RF, the less damage can be done to the substrate.

As the insulator 214, a metal oxide having an amorphous structure, such as aluminum oxide, which has high hydrogen capturing and fixing performance, is preferably used. Thereby, hydrogen contained in the insulator 216 or the like can be trapped or fixed to prevent the hydrogen from diffusing to the oxide 230. In particular, the insulator 214 particularly preferably uses alumina having an amorphous structure or alumina having an amorphous structure, because hydrogen can be trapped or fixed more effectively in some cases. Thus, the transistor 200 and the semiconductor device having good characteristics and high reliability can be manufactured.

Next, insulator 216 is deposited over insulator 214. Insulator 216 is preferably deposited using a sputtering process. The concentration of hydrogen in the insulator 216 can be reduced by using a sputtering method that does not require the use of a molecule containing hydrogen as a deposition gas. Note that deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used.

In this embodiment, silicon oxide is deposited as the insulator 216 by a pulsed DC sputtering method using a silicon target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the thickness can be made more uniform to improve the sputtering rate and film quality.

Insulator 212, insulator 214, and insulator 216 are preferably deposited continuously in a manner that is not exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, the insulator 212, the insulator 214, and the insulator 216 can be deposited with hydrogen in the film reduced, and hydrogen incorporation into the film between deposition steps can be reduced.

Next, an opening reaching the insulator 214 is formed in the insulator 216. The openings include, for example, grooves, slits, and the like. The region where the opening is formed is sometimes referred to as an opening. In forming the opening, a wet etching method may be used, but a dry etching method is preferable for micromachining. As the insulator 214, an insulator that is used as an etching stopper when etching the insulator 216 to form a groove is preferably selected. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used as the insulator 214.

As the dry etching apparatus, a capacitively coupled plasma (CCP: capacitively Coupled Plasma) etching apparatus including parallel plate electrodes can be used. The capacitive coupling type plasma etching apparatus including parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, a configuration may be adopted in which a plurality of different high-frequency voltages are applied to one of the parallel flat-plate electrodes. Alternatively, a configuration may be adopted in which high-frequency voltages having the same frequency are applied to the parallel flat electrodes. Alternatively, a configuration may be adopted in which high-frequency voltages having different frequencies are applied to the parallel flat electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP: inductively Coupled Plasma) etching apparatus or the like can be used.

After forming the opening, a conductive film to be the conductor 205a is deposited. The conductive film preferably includes a conductive body having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminate film of a conductor having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy may be used. The conductive film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, titanium nitride is deposited as a conductive film to be the conductor 205 a. By using the above metal nitride as the lower layer of the conductor 205b, oxidation of the conductor 205b by the insulator 216 or the like can be suppressed. Further, even if a metal which is easily diffused such as copper is used as the conductor 205b, the metal can be prevented from diffusing outward from the conductor 205 a.

Next, a conductive film to be the conductor 205b is deposited. As the conductive film, tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy, or the like can be used. The conductive film can be deposited by electroplating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment mode, tungsten is deposited as the conductive film.

Next, the conductive film to be the conductor 205a and a part of the conductive film to be the conductor 205b are removed by CMP processing, so that the insulator 216 is exposed (see fig. 14A to 14D). As a result, the conductors 205a and 205b remain only in the openings. In addition, a portion of the insulator 216 is sometimes removed by the CMP process.

Next, an insulator 222 is deposited over the insulator 216 and the conductor 205 (see fig. 15A to 15D). The insulator 222 is preferably an insulator in which an oxide containing one or both of aluminum and hafnium is deposited. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in the surrounding structure of the transistor 200 to the inside of the transistor 200 through the insulator 222 can be suppressed, and generation of oxygen vacancies in the oxide 230 can be suppressed.

The insulator 222 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide is deposited as the insulator 222 by an ALD method. In particular, a method for forming hafnium oxide with a reduced hydrogen concentration according to one embodiment of the present invention is preferably used.

Then, heat treatment is preferably performed. The heat treatment may be performed at 250 ℃ to 650 ℃, preferably 300 ℃ to 500 ℃, more preferably 320 ℃ to 450 ℃. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas may be set to about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed under a nitrogen gas or an inert gas atmosphere, and then the heat treatment may be performed under an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to fill the detached oxygen.

The gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment may be 1ppb or less, preferably 0.1ppb or less, and more preferably 0.05ppb or less. By performing the heat treatment using the gas with high purity, moisture and the like can be prevented from being absorbed by the insulator 222 and the like as much as possible.

In this embodiment, after the insulator 222 is deposited as the heat treatment, the treatment is performed at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 400 ℃. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. In the case of using a hafnium-containing oxide for the insulator 222, a part of the insulator 222 may be crystallized by performing the heat treatment. Further, the heat treatment may be performed at a timing such as after the insulator 224 is deposited.

Next, an insulating film 224A is deposited over the insulator 222 (see fig. 15A to 15D). The insulating film 224A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a silicon oxide film is deposited as the insulating film 224A by a sputtering method. The concentration of hydrogen in the insulating film 224A can be reduced by using a sputtering method which does not need to use a molecule containing hydrogen as a deposition gas. Since the insulating film 224A is in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this way.

Next, an oxide film 230A and an oxide film 230B are sequentially deposited over the insulating film 224A (see fig. 15A to 15D). The oxide films 230A and 230B are preferably deposited continuously without exposure to the atmospheric environment. By performing deposition without exposure to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to the oxide film 230A and the oxide film 230B, and therefore the vicinity of the interface between the oxide film 230A and the oxide film 230B can be kept clean.

The oxide film 230A and the oxide film 230B can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The ALD method is preferable because a film having a uniform thickness can be formed even in a trench or an opening having a large aspect ratio by depositing the oxide film 230A and the oxide film 230B. Further, by using the PEALD method, the oxide film 230A and the oxide film 230B can be formed at a lower temperature than the thermal ALD method, which is preferable. In this embodiment, a sputtering method is used for depositing the oxide film 230A and the oxide film 230B.

For example, in the case where the oxide film 230A and the oxide film 230B are deposited by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. In the case of depositing the oxide film by sputtering, for example, the in—m—zn oxide target material or the like may be used.

In particular, when the oxide film 230A is deposited, a part of oxygen contained in the sputtering gas may be supplied to the insulator 224. Accordingly, the ratio of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

In the case where the oxide film 230B is formed by a sputtering method, an oxygen-excess oxide semiconductor can be formed by deposition under a condition that the ratio of oxygen contained in a sputtering gas exceeds 30% and is 100% or less, preferably 70% or more and 100% or less. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can obtain relatively high reliability. Note that one mode of the present invention is not limited to this. In the case of forming the oxide film 230B by a sputtering method, when deposition is performed with the ratio of oxygen contained in the sputtering gas set to 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have higher field effect mobility. Further, by performing deposition while heating the substrate, crystallinity of the oxide film can be improved.

In this embodiment, the oxide film 230A is deposited by a sputtering method using an oxide target having In: ga: zn=1:3:4 [ atomic number ratio ]. The oxide film 230B was deposited by a sputtering method using an oxide target of In: ga: zn=4:2:4.1 [ atomic ratio ], an oxide target of In: ga: zn=1:1:1 [ atomic ratio ], an oxide target of In: ga: zn=1:1:1.2 [ atomic ratio ], or an oxide target of In: ga: zn=1:1:2 [ atomic ratio ]. The oxide films can be formed by appropriately selecting deposition conditions and atomic number ratios according to characteristics required for the oxide 230a and the oxide 230b.

Note that the insulating film 224A, the oxide film 230A, and the oxide film 230B are preferably deposited by a sputtering method so as not to be exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. This can reduce hydrogen from entering the insulating film 224A, the oxide film 230A, and the oxide film 230B between the deposition steps.

Then, heat treatment is preferably performed. The heat treatment may be performed at a temperature within a range where polycrystallization does not occur in the oxide film 230A or the oxide film 230B, and may be performed at 250 ℃ or higher and 650 ℃ or lower, preferably 400 ℃ or higher and 600 ℃ or lower. The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas may be set to about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed under a nitrogen gas or an inert gas atmosphere, and then the heat treatment may be performed under an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to fill the detached oxygen.

The gas used in the heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the heat treatment may be 1ppb or less, preferably 0.1ppb or less, and more preferably 0.05ppb or less. By performing the heat treatment using the gas with high purity, moisture and the like can be prevented from being absorbed by the oxide film 230A, the oxide film 230B, and the like as much as possible.

In this embodiment, as the heat treatment, the treatment was performed for 1 hour under the conditions that the flow ratio of the nitrogen gas to the oxygen gas was 4:1 and the temperature was 400 ℃. By such heat treatment with the oxygen-containing gas, impurities such as carbon, water, and hydrogen in the oxide film 230A and the oxide film 230B can be reduced. By reducing the impurities in the film in this manner, the crystallinity of the oxide film 230B is improved, and a dense structure with higher density can be realized. Therefore, the crystal regions in the oxide film 230A and the oxide film 230B can be increased, and in-plane unevenness of the crystal regions in the oxide film 230A and the oxide film 230B can be reduced. Accordingly, in-plane unevenness of the electrical characteristics of the transistor 200 can be reduced.

In addition, by performing heat treatment, hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B is transferred to the insulator 222 and absorbed by the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B diffuses into the insulator 222. Therefore, although the hydrogen concentration of the insulator 222 increases, the hydrogen concentration in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B decreases.

In particular, the insulating film 224A is used as a gate insulator of the transistor 200, and the oxide film 230A and the oxide film 230B are used as channel formation regions of the transistor 200. Therefore, the transistor 200 including the insulating film 224A, the oxide film 230A, and the oxide film 230B in which the hydrogen concentration is reduced has excellent reliability, so that it is preferable.

Next, a conductive film 242A is deposited over the oxide film 230B (see fig. 15A to 15D). The conductive film 242A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, tantalum nitride may be deposited as the conductive film 242A by a sputtering method. In addition, heat treatment may be performed before the conductive film 242A is deposited. The heat treatment may also be performed under reduced pressure, and the conductive film 242A is continuously deposited therein so as not to be exposed to the atmosphere. By performing such treatment, moisture and hydrogen adhering to the surface of the oxide film 230B can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A and the oxide film 230B can be reduced. The temperature of the heat treatment is preferably 100 ℃ or more and 400 ℃ or less. In this embodiment, the temperature of the heat treatment is set to 200 ℃.

Next, an insulating film 271A is deposited over the conductive film 242A (see fig. 15A to 15D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 271A, an insulating film having a function of suppressing permeation of oxygen is preferably used. For example, aluminum oxide or silicon nitride may be deposited as the insulating film 271A by a sputtering method.

The conductive film 242A and the insulating film 271A are preferably deposited by a sputtering method so as not to be exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, hydrogen in the film can be reduced to deposit the conductive film 242A and the insulating film 271A, and hydrogen can be reduced from being mixed into the film between the deposition steps. In addition, when a hard mask is formed over the insulating film 271A, a film to be the hard mask may be deposited continuously so as not to be exposed to the atmosphere.

Next, the insulating film 224A, the oxide film 230B, the conductive film 242A, and the insulating film 271A are processed into island shapes by photolithography, so that the insulator 224, the oxide 230A, the oxide 230B, the conductive layer 242B, and the insulating layer 271B are formed (see fig. 16A to 16D). Here, the insulator 224, the oxide 230a, the oxide 230B, the conductive layer 242B, and the insulating layer 271B are formed so that at least a part thereof overlaps with the conductor 205. As the processing, a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for micromachining. The insulating film 224A, the oxide film 230B, the conductive film 242A, and the insulating film 271A may be formed under different conditions.

Note that in the photolithography, the resist is first exposed to light through a mask. Next, the exposed regions are removed or left using a developer to form a resist mask. Then, the resist mask is etched to form a conductor, a semiconductor, an insulator, or the like into a desired shape. For example, a resist mask may be formed by exposing a resist to light using a KrF excimer laser, arF excimer laser, EUV (Extreme Ultraviolet: extreme ultraviolet) light, or the like. In addition, a liquid immersion technique in which exposure is performed in a state where a space between the substrate and the projection lens is filled with a liquid (for example, water) may be used. In addition, an electron beam or an ion beam may be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing dry etching such as ashing, wet etching after dry etching, or dry etching after wet etching.

Further, a hard mask made of an insulator or a conductor may be used under the resist mask. When a hard mask is used, an insulating film or a conductive film which becomes a hard mask material may be formed over the conductive film 242A and a resist mask is formed thereover, and then the hard mask material is etched to form a hard mask of a desired shape. The etching of the conductive film 242A or the like may be performed after or without removing the resist mask. In the latter case, the resist mask may disappear when etching is performed. The hard mask may be removed by etching after etching of the conductive film 242A or the like. On the other hand, in the case where the hard mask material does not affect the post-process or can be used in the post-process, the hard mask does not necessarily need to be removed. In this embodiment mode, the insulating layer 271B is used as a hard mask.

Here, the insulating layer 271B is used as a mask for the conductive layer 242B, and as shown in fig. 16B to 16D, the conductive layer 242B has no curved surface between the side surface and the top surface. Thus, the end portions of the side surfaces and the top surfaces of the conductors 242a and 242B shown in fig. 1B and 1D are angled. When the end portion of the conductor 242 where the side surface and the top surface intersect is angled, the cross-sectional area of the conductor 242 increases as compared with the case where the end portion has a curved surface. This reduces the resistance of conductor 242, which increases the on-state current of transistor 200.

As shown in fig. 16B to 16D, the side surfaces of the insulator 224, the oxide 230a, the oxide 230B, the conductive layer 242B, and the insulating layer 271B may have tapered shapes. Note that, in this specification and the like, the tapered shape refers to a shape in which at least a part of a side surface of a constituent element is provided obliquely with respect to a substrate surface. For example, the angle formed by the inclined side surface and the substrate surface (hereinafter, sometimes referred to as taper angle) is preferably smaller than 90 °. The insulator 224, the oxide 230a, the oxide 230B, the conductive layer 242B, and the insulating layer 271B are formed so that a taper angle is 60 ° or more and less than 90 °, for example. When the side surface has such a tapered shape, the coverage of the insulator 275 or the like in the subsequent steps is improved, and defects such as voids can be reduced.

However, the structure is not limited to this, and the side surfaces of the insulator 224, the oxide 230a, the oxide 230B, the conductive layer 242B, and the insulating layer 271B may be substantially perpendicular to the top surface of the insulator 222. By adopting such a structure, a small area and a high density can be achieved when a plurality of transistors 200 are provided.

In addition, by-products generated in the etching step may be formed in layers on the side surfaces of the insulator 224, the oxide 230a, the oxide 230B, the conductive layer 242B, and the insulating layer 271B. In this case, the layered by-product is formed between the insulator 224, the oxide 230a, the oxide 230B, the conductive layer 242B, and the insulating layer 271B and the insulator 275. Accordingly, it is preferable to remove the layered byproducts that contact the top surface of the insulator 222.

Next, an insulator 275 is deposited so as to cover the insulator 224, the oxide 230a, the oxide 230B, the conductive layer 242B, and the insulating layer 271B (see fig. 17A to 17D). Here, insulator 275 is preferably in close contact with the top surface of insulator 222 and the side surface of insulator 224. The insulator 275 may be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 275 preferably uses an insulating film having a function of suppressing oxygen permeation. For example, as the insulator 275, aluminum oxide may be deposited by a sputtering method and silicon nitride may be deposited thereon by a PEALD method. When the insulator 275 has such a stacked structure, the function of suppressing diffusion of impurities such as water and hydrogen, and oxygen may be improved.

In this manner, the oxide 230a, the oxide 230B, and the conductive layer 242B can be covered with the insulator 275 and the insulating layer 271B which have a function of suppressing oxygen diffusion. This can suppress oxygen from directly diffusing from the insulator 280 or the like into the insulator 224, the oxide 230a, the oxide 230B, and the conductive layer 242B in a later process.

Next, an insulating film to be an insulator 280 is deposited on the insulator 275. The insulating film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be deposited as the insulating film by a sputtering method. By depositing the insulating film using a sputtering method under an atmosphere containing oxygen, the insulator 280 containing excess oxygen can be formed. The concentration of hydrogen in insulator 280 can be reduced by using a sputtering method that does not require the use of a hydrogen-containing molecule as a deposition gas. In addition, heat treatment may be performed before depositing the insulating film. The heat treatment may also be performed under reduced pressure, and wherein the insulating film is continuously deposited in such a manner as not to be exposed to the atmosphere. By performing such treatment, moisture and hydrogen adhering to the surface of the insulator 275 or the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the insulator 224 can be reduced. The heat treatment may be performed under the conditions described above.

Next, an insulating film serving as the insulator 280 is subjected to CMP treatment, whereby the insulator 280 having a flat top surface is formed (see fig. 17A to 17D). Further, silicon nitride may be deposited on the insulator 280, for example, by sputtering, and CMP may be performed until the silicon nitride reaches the insulator 280.

Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 271B, and a portion of the conductive layer 242B are processed to form an opening to the oxide 230B. The opening is preferably formed so as to overlap with the conductor 205. By forming the opening, an insulator 271a, an insulator 271b, a conductor 242a, and a conductor 242b are formed (see fig. 18A to 18D).

Here, as shown in fig. 18B and 18C, side surfaces of the insulator 280, the insulator 275, the insulator 271, and the conductor 242 may be tapered. In addition, the taper angle of the insulator 280 is sometimes greater than the taper angle of the conductor 242. In addition, although not shown in fig. 18A to 18C, the top of the oxide 230b is sometimes removed when the above-described opening is formed.

Further, a part of the insulator 280, a part of the insulator 275, a part of the insulating layer 271B, and a part of the conductive layer 242B may be processed by a dry etching method or a wet etching method. Processing by dry etching is suitable for micromachining. The processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by a dry etching method, a part of the insulator 275 and a part of the insulating layer 271B may be processed by a wet etching method, and a part of the conductive layer 242B may be processed by a dry etching method.

Here, the following sometimes occurs: impurities adhere to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductor 242, the side surfaces of the insulator 280, and the like; or the impurities diffuse into their interiors. The step of removing these impurities may be performed. In addition, a damaged region may be formed on the surface of the oxide 230b by the dry etching. Such damaged areas may also be removed. Examples of the impurities include impurities derived from the following components: an insulator 280, an insulator 275, a part of the insulating layer 271B, and a component included in the conductive layer 242B; a component contained in a member used for a device used for forming the opening; a gas or liquid for etching contains a component. Examples of the impurity include hafnium, silicon, tantalum, fluorine, chlorine, and the like.

The above impurities sometimes cause a decrease in crystallinity of the oxide 230 b. Therefore, the above impurities are preferably removed at and near the surface of the oxide 230 b. Further, the concentration of the above impurities is preferably reduced. For example, the concentration of silicon atoms on the surface of the oxide 230b and the vicinity thereof may be 5.0 atomic% or less, preferably 2.0 atomic% or less, more preferably 1.5 atomic% or less, further preferably 1.0 atomic% or less, and particularly preferably less than 0.3 atomic%.

Due to the above impurities, the density of the crystalline structure is reduced in the regions where the crystallinity of the oxide 230b is low, so that a large amount of V is generated _O H, and the transistor is liable to become normally on. Accordingly, the region of low crystallinity of the oxide 230b is preferably reduced or removed.

In contrast, the oxide 230b preferably has a layered CAAC structure. In particular, the lower end portion of the drain of the oxide 230b also preferably has a CAAC structure. Here, in the transistor 200, the conductor 242a or the conductor 242b and the vicinity thereof are used as a drain. In other words, the oxide 230b near the lower end portion of the conductor 242a (conductor 242 b) preferably has a CAAC structure. In this manner, by removing the region of low crystallinity of the oxide 230b at the drain end portion, which has a significant influence on the drain withstand voltage, and providing the CAAC structure, variations in the electrical characteristics of the transistor 200 can be further suppressed. In addition, the reliability of the transistor 200 can be further improved.

In order to remove impurities and the like adhering to the surface of the oxide 230b in the etching step, a washing treatment is performed. As a washing method, wet washing using a washing liquid or the like (may also be referred to as wet etching treatment), plasma treatment using plasma, washing using heat treatment, or the like can be used, and the above washing may be appropriately combined. Note that the groove portion may be deepened by performing the washing treatment.

As the wet washing, an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water, carbonated water, or the like may be used for the washing treatment. Alternatively, the ultrasonic washing may be performed using the above aqueous solution, pure water, or carbonated water. Further, the above-mentioned washing may be appropriately combined.

Note that in this specification and the like, an aqueous solution of diluted hydrogen fluoride acid with pure water is sometimes referred to as diluted hydrogen fluoride acid and an aqueous solution of diluted ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution may be appropriately adjusted according to impurities to be removed, the structure of the semiconductor device to be washed, etc. The ammonia concentration of the dilute aqueous ammonia may be set to 0.01% or more and 5% or less, and preferably set to 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the dilute hydrogen fluoride acid may be set to 0.01ppm or more and 100ppm or less, and preferably 0.1ppm or more and 10ppm or less.

Further, it is preferable to use a frequency of 200kHz or more, preferably 900kHz or more, for ultrasonic washing. By using this frequency, damage to the oxide 230b or the like can be reduced.

The washing treatment may be performed a plurality of times, or the washing liquid may be changed for each washing treatment. For example, the treatment using dilute hydrogen fluoride acid or dilute ammonia water may be performed as the first washing treatment, and the treatment using pure water or carbonated water may be performed as the second washing treatment.

As the washing treatment, in the present embodiment, wet washing is performed using dilute aqueous ammonia. By performing this washing treatment, impurities adhering to the surface of the oxide 230a, the oxide 230b, or the like or diffusing into the inside thereof can be removed. Further, crystallinity of the oxide 230b can be improved.

The heat treatment may be performed after the etching or the washing. The heat treatment is performed at 100 ℃ to 450 ℃, preferably 350 ℃ to 400 ℃. The heat treatment is performed under a nitrogen gas, an inert gas, or an atmosphere containing 10ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed under an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 230a and the oxide 230b, and oxygen vacancies can be reduced. Further, by performing the heat treatment described above, crystallinity of the oxide 230b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed under an oxygen atmosphere, and then the heat treatment may be performed continuously under a nitrogen atmosphere without being exposed to the atmosphere.

Next, an insulating film 252A is deposited (see fig. 19A to 19D). The insulating film 252A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 252A is preferably deposited by an ALD method. As described above, the insulating film 252A is preferably deposited thin, and it is necessary to suppress thickness unevenness to be small. In contrast, the ALD method is a deposition method in which a precursor and a reactant (for example, an oxidizing agent or the like) are alternately introduced, and the thickness of a film can be adjusted according to the number of times of repeating the cycle, so that the thickness can be precisely adjusted. In addition, as shown in fig. 19B and 19C, the insulating film 252A needs to be deposited with high coverage on the bottom surface and the side surface of the opening formed in the insulator 280 or the like. In particular, the insulating film 252A needs to be deposited on the top and side surfaces of the oxide 230 and the side surfaces of the conductor 242 with high coverage. Since an atomic layer of each layer can be deposited on the bottom surface and the side surface of the opening, the insulating film 252A can be deposited with high coverage in the opening.

In addition, when the insulating film 252A is deposited by an ALD method, ozone (O ₃ ) Oxygen (O) ₂ ) Water (H) ₂ O), and the like. By using ozone (O) containing no hydrogen ₃ ) Oxygen (O) ₂ ) Etc. as an oxidizing agent, hydrogen diffusing into the oxide 230b can be reduced.

In this embodiment, aluminum oxide is deposited as the insulating film 252A by a thermal ALD method.

Then, the microwave treatment is preferably performed in an oxygen-containing atmosphere (see fig. 19A to 19D). Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source for generating high-density plasma by microwaves. In the present specification, microwaves refer to electromagnetic waves having a frequency of 300MHz to 300 GHz.

The dotted lines shown in fig. 19B to 19D indicate high frequency such as microwaves, RF, oxygen plasma, oxygen radicals, and the like. For example, a microwave processing apparatus including a power source for generating high-density plasma by microwaves is preferably used for the microwave processing. Here, the frequency of the microwave processing apparatus may be set to 300MHz to 300GHz, preferably 2.4GHz to 2.5GHz, for example, 2.45 GHz. By using a high density plasma, oxygen radicals of high density can be generated. The power of the microwave-applied power supply of the microwave processing apparatus may be 1000W or more and 10000W or less, and preferably 2000W or more and 5000W or less. In addition, the microwave processing apparatus may also include a power source for applying RF to one side of the substrate. Further, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide 230 b.

The microwave treatment is preferably performed under reduced pressure, and the pressure is preferably 10Pa to 1000Pa, more preferably 300Pa to 700 Pa. The treatment temperature is 750 ℃ or lower, preferably 500 ℃ or lower, for example, about 400 ℃. Further, the heat treatment may be performed continuously so as not to be exposed to the atmosphere after the oxygen plasma treatment. For example, the treatment temperature may be 100 ℃ to 750 ℃, preferably 300 ℃ to 500 ℃.

In addition, for example, the above-mentioned microThe wave treatment may be performed using an oxygen gas or an argon gas. Here, the oxygen flow rate ratio (O ₂ /(O ₂ +ar)) is more than 0% and 100% or less, preferably more than 0% and 50% or less, more preferably 10% or more and 40% or less, and still more preferably 10% or more and 30% or less. In this manner, by performing the microwave treatment in the oxygen-containing atmosphere, the carrier concentration in the region 230bc can be reduced. Further, by preventing excessive oxygen from being introduced into the processing chamber during the microwave processing, the carrier concentration in the region 230ba and the region 230bb can be prevented from being excessively lowered.

As shown in fig. 19B to 19D, by performing the microwave treatment in the oxygen-containing atmosphere, the oxygen gas can be plasmatized using high frequency such as microwave or RF, and the oxygen plasma can be applied to the region between the conductor 242a and the conductor 242B of the oxide 230B. At this time, a high frequency such as microwave or RF may be irradiated to the region 230bc. In other words, the microwave, RF, or other high-frequency, oxygen plasma, or the like can be caused to act in the region 230bc shown in fig. 2A. V of the region 230bc can be caused by the action of plasma, microwave, or the like _O H separates to remove hydrogen from region 230 bc. In other words, V contained in the region 230bc can be reduced _O H. Therefore, oxygen vacancies and V in region 230bc can be reduced _O H to reduce the carrier concentration. Further, by supplying oxygen radicals generated in the above-described oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, whereby the carrier concentration can be reduced.

On the other hand, conductors 242A and 242b are provided in the regions 230ba and 230bb shown in fig. 2A. Here, the conductor 242 is preferably used as a shielding film for protecting against high frequency such as microwaves and RF, oxygen plasma, and the like when performing microwave treatment in an oxygen-containing atmosphere. Accordingly, the conductor 242 preferably has a function of shielding electromagnetic waves of 300MHz to 300GHz, for example, 2.4GHz to 2.5 GHz.

As shown in fig. 19B to 19D, the conductors 242a and 242B shield the action of high-frequency, e.g., microwave or RF, oxygen plasma, and the like, and therefore do not act on the region 230ba and the region230bb. Thus, V due to the microwave treatment does not occur in the region 230ba and the region 230bb _O H and excessive oxygen supply, a decrease in carrier concentration can be prevented.

Further, an insulator 252 having oxygen barrier property is provided so as to contact the side surfaces of the conductors 242a and 242 b. Therefore, formation of an oxide film on the side surfaces of the conductors 242a and 242b by the microwave treatment can be suppressed.

Since the film quality of the insulator 252 can be improved, the reliability of the transistor 200 is improved.

As described above, oxygen vacancies and V can be selectively removed in the region 230bc of the oxide semiconductor _O H makes the region 230bc i-type or substantially i-type. Further, the regions 230ba and 230bb serving as the source region or the drain region can be suppressed from being supplied with excessive oxygen, and the state of the n-type region before the microwave treatment can be maintained. This suppresses variation in the electrical characteristics of the transistor 200, and suppresses variation in the electrical characteristics of the transistor 200 in the substrate plane.

In addition, in the microwave treatment, thermal energy may be directly transferred to the oxide 230b due to electromagnetic interaction of microwaves with molecules in the oxide 230 b. The oxide 230b is sometimes heated by this thermal energy. This heat treatment is sometimes referred to as microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. In addition, it can be considered that: when the oxide 230b contains hydrogen, the thermal energy is transferred to the hydrogen in the oxide 230b, and the activated hydrogen is released from the oxide 230 b.

Next, an insulating film 250A is deposited (see fig. 20A to 20D). Here, the heat treatment may also be performed before the insulating film 250A is deposited, and it is preferable that the heat treatment is performed under reduced pressure so that the insulating film 250A is continuously deposited without being exposed to the atmosphere. Further, the heat treatment is preferably performed under an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adhering to the surface or the like of the insulating film 252A can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100 ℃ or more and 400 ℃ or less.

The insulating film 250A can be deposited by a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably deposited using a deposition method of a gas that reduces or removes hydrogen atoms. Thereby, the hydrogen concentration of the insulating film 250A can be reduced. Since the insulating film 250A is an insulator 250A facing the oxide 230b through the insulator 252 having a small thickness in the subsequent steps, it is preferable that the hydrogen concentration be reduced in this manner.

In this embodiment mode, silicon oxynitride is deposited as the insulating film 250A by a PECVD method.

In addition, when the insulating film 250 has a two-layer stacked structure shown in fig. 2B, an insulating film to be the insulating film 250B may be deposited after the insulating film 250A is deposited. The insulating film to be the insulator 250b can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film to be the insulator 250b is preferably formed using an insulator having a function of suppressing diffusion of oxygen. By adopting such a structure, diffusion of oxygen contained in the insulator 250a to the conductor 260 can be suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Further, oxidation of the conductor 260 due to oxygen contained in the insulator 250a can be suppressed. The insulating film serving as the insulator 250b may be formed using the same material as that of the insulator 222. For example, hafnium oxide may be deposited as an insulating film serving as the insulator 250b by a thermal ALD method.

Further, after the insulating film 250A is deposited, microwave treatment may be performed (see fig. 20A to 20D). The microwave treatment may be performed under the conditions of the microwave treatment performed after the insulating film 252A is deposited. In addition, the microwave treatment may be performed after the insulating film 250A is deposited, instead of the microwave treatment after the insulating film 252A is deposited. In addition, in the case of providing an insulating film to be the insulator 250b as described above, microwave treatment may be performed after deposition. The microwave treatment may be performed under the conditions of the microwave treatment performed after the insulating film 252A is deposited. Further, the microwave treatment may be performed after the insulating film to be the insulator 250b is deposited, instead of the microwave treatment performed after the insulating film 252A or the insulating film 250A is deposited.

The heat treatment may be performed in a state of being reduced in pressure after the microwave treatment after the insulating film 252A and the insulating film 250A are deposited and after the insulating film serving as the insulator 250b is deposited. By performing such a treatment, hydrogen in the insulating film 252A, the insulating film 250A, the insulating film which becomes the insulator 250b, the oxide 230b, and the oxide 230A can be efficiently removed. In addition, some of the hydrogen may be gettered by the conductors 242 (the conductor 242a and the conductor 242 b). The step of performing the heat treatment may be repeated while maintaining the reduced pressure after the microwave treatment. By repeating the heat treatment, hydrogen in the insulating film 252A, the insulating film 250A, the insulating film which becomes the insulator 250b, the oxide 230b, and the oxide 230A can be further efficiently removed. Note that the heat treatment temperature is preferably 300 ℃ or higher and 500 ℃ or lower. The microwave treatment, that is, the microwave annealing may also be used as the heat treatment. When the oxide 230b is sufficiently heated by microwave annealing or the like, the heat treatment may not be performed.

Further, by performing the microwave treatment to change the film quality of the insulating film 252A, the insulating film 250A, and the insulating film to be the insulator 250b, diffusion of hydrogen, water, impurities, and the like can be suppressed. This can suppress diffusion of hydrogen, water, impurities, and the like into the oxide 230b, the oxide 230a, and the like through the insulator 252 due to a post-process such as deposition of the conductive film serving as the conductor 260, or a post-process such as heat treatment.

Next, an insulating film 254A is deposited (see fig. 21A to 21D). The insulating film 254A can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Like the insulating film 252A, the insulating film 254A is preferably deposited by an ALD method. By deposition using the ALD method, the thin insulating film 254A can be deposited with high coverage. In this embodiment, silicon nitride is deposited as the insulating film 254A by PEALD method.

Next, a conductive film to be the conductor 260a and a conductive film to be the conductor 260b are sequentially deposited. The conductive film to be the conductive body 260a and the conductive film to be the conductive body 260b can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, titanium nitride is deposited as a conductive film to be the conductive body 260a by an ALD method, and tungsten is deposited as a conductive film to be the conductive body 260b by a CVD method.

Next, the insulator 252, the insulator 250, the insulator 254, and the conductors 260 (the conductors 260A and 260 b) are formed by polishing the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive film that becomes the conductor 260A, and the conductive film that becomes the conductor 260b by CMP until the insulator 280 is exposed (see fig. 22A to 22D). Thus, the insulator 252 is disposed so as to cover the opening reaching the oxide 230 b. The conductor 260 is disposed so as to fill the opening through the insulator 252 and the insulator 250.

Then, the heat treatment may be performed under the same conditions as those of the heat treatment described above. In this embodiment, the treatment is performed at a temperature of 400℃for 1 hour under a nitrogen atmosphere. By this heat treatment, the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced. Further, after the above heat treatment, deposition of the insulator 282 is continuously performed in such a manner as not to be exposed to the atmosphere.

Next, an insulator 282 is formed over the insulator 252, the insulator 250, the conductor 260, and the insulator 280 (see fig. 22A to 22D). The insulator 282 may be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Insulator 282 is preferably deposited using a sputtering process. The concentration of hydrogen in the insulator 282 can be reduced by using a sputtering method that does not require the use of a molecule containing hydrogen as a deposition gas.

In this embodiment, alumina is deposited as the insulator 282 by a pulsed DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the thickness can be made more uniform to improve the sputtering rate and film quality. In addition, the RF power applied to the substrate was set to 1.86W/cm ² The following is given. Preferably 0W/cm ² Above and 0.31W/cm ² The following is given. By reducing the RF power, the amount of oxygen injected into insulator 280 can be suppressed. In this embodiment, the insulator 282 having a two-layer stacked structure is formed. Setting the RF power applied to the substrate to 0W/cm ² To form an underlying layer of insulator 282 to be applied to the substrateRF power was set to 0.31W/cm ² To form an upper layer of insulator 282.

In addition, by depositing the insulator 282 under an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulator 280 at the same time as the deposition is performed. Thereby, the insulator 280 may be made to contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate.

Next, an etching mask is formed over the insulator 282 by photolithography, and a portion of the insulator 282, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulator 222, and a portion of the insulator 216 are processed until the top surface of the insulator 214 is exposed (see fig. 23A to 23D). In performing this processing, wet etching may be used, but dry etching is preferable for micromachining.

Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250 ℃ to 650 ℃, preferably 350 ℃ to 600 ℃. In addition, the heat treatment is preferably performed at a temperature lower than that of the heat treatment performed after the deposition of the oxide film 230B. Further, the heat treatment is performed under a nitrogen gas or an inert gas atmosphere. By performing this heat treatment, a part of oxygen added to the insulator 280 diffuses through the insulator 250 and the like to the oxide 230.

By performing this heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the insulator 280 formed by processing the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216. Note that hydrogen bonded to oxygen is released as water. Accordingly, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.

In the region of the oxide 230 overlapping the conductor 260, an insulator 252 is provided so as to contact the top surface and the side surface of the oxide 230. The insulator 252 has oxygen barrier properties and thus may reduce excessive oxygen diffusion to the oxide 230. Thereby, oxygen can be supplied to the region 230bc and the vicinity thereof in such a manner that the supply of excessive oxygen is avoided. Thereby, oxidation of the side surface of the conductor 242 due to excessive oxygen can be suppressed while reducing formation in the region 230bc Oxygen vacancy and V _O H. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

On the other hand, when the transistor 200 is integrated with high density, the volume of the insulator 280 with respect to one transistor 200 is sometimes too small. At this time, in the above heat treatment, the amount of oxygen diffused into the oxide 230 is significantly small. When the oxide 230 is heated in a state where an oxide insulator (for example, the insulator 250 or the like) having a low oxygen content is in contact with the oxide insulator, oxygen constituting the oxide 230 may be desorbed. However, in the transistor 200 according to the present embodiment, the insulator 252 is provided so as to contact the top surface and the side surfaces of the oxide 230 in the region of the oxide 230 overlapping the conductor 260. Oxygen detachment from the oxide 230 may also be reduced in the above-described thermal treatment because the insulator 252 has oxygen barrier properties. Thereby, oxygen vacancies and V formed in the region 230bc can be reduced _O H. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

As described above, in the semiconductor device according to the present embodiment, a transistor having good electrical characteristics and high reliability can be formed both in the case where the amount of oxygen supplied from the insulator 280 is large and in the case where the amount of oxygen supplied from the insulator 280 is small. Accordingly, a semiconductor device in which non-uniformity in electrical characteristics of the transistor 200 in the substrate plane can be suppressed can be provided.

Next, an insulator 283 is formed over the insulator 282 (see fig. 24A to 24D). The insulator 283 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Insulator 283 is preferably deposited using a sputtering process. By using a sputtering method that does not require the use of a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In addition, the insulator 283 may have a multi-layered structure. For example, silicon nitride may be deposited by a sputtering method, and silicon nitride may be deposited on the silicon nitride by an ALD method. By surrounding the transistor 200 with the insulator 283 and the insulator 214 having high barrier properties, moisture and hydrogen can be prevented from entering from the outside.

Next, an insulator 274 is formed over the insulator 283. The insulator 274 may be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is deposited as the insulator 274 by a CVD method.

Next, the insulator 274 is polished by using a CMP process until the insulator 283 is exposed, so that the top surface of the insulator 274 is planarized (see fig. 24A to 24D). A portion of the top surface of the insulator 283 is sometimes removed by the CMP process.

Next, an insulator 285 is formed over the insulator 274 and the insulator 283 (see fig. 25A to 25D). The insulator 285 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Insulator 285 is preferably deposited using a sputtering process. The concentration of hydrogen in the insulator 285 can be reduced by using a sputtering method that does not require the use of a molecule containing hydrogen as a deposition gas.

In this embodiment, silicon oxide is deposited as the insulator 285 by a sputtering method.

Next, openings reaching the conductors 242 are formed in the insulators 271, 275, 280, 282, 283, and 285 (see fig. 25A and 25B). In forming the opening, photolithography may be used. Note that the shape of the opening in plan view in fig. 25A is circular, but is not limited thereto. For example, the opening may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which corners of the polygonal shape such as the quadrangle are curved in a plan view.

Next, an insulating film to be the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241 (see fig. 25B). The insulating film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film, an insulating film having a function of suppressing permeation of oxygen is preferably used. For example, an aluminum oxide film is preferably deposited by an ALD method, and a silicon nitride film is deposited thereon using a PEALD method. Silicon nitride is preferred because of its high barrier to hydrogen.

As the anisotropic etching for the insulating film serving as the insulator 241, for example, a dry etching method or the like can be used. By providing the insulator 241 on the side wall portion of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 240a and the conductor 240b to be formed next can be prevented. Further, impurities such as water and hydrogen contained in the insulator 280 and the like can be prevented from diffusing into the conductor 240a and the conductor 240b.

Next, conductive films to be the conductors 240a and 240b are formed. The conductive film preferably has a laminated structure including a conductive body having a function of suppressing permeation of impurities such as water and hydrogen. For example, a stack of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like may be provided. The conductive film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a CMP process is performed to remove a portion of the conductive film that becomes the conductors 240a and 240b, thereby exposing the top surface of the insulator 285. As a result, the conductive film remains only in the opening, and thus the conductors 240a and 240b having flat top surfaces can be formed (see fig. 25A to 25D). Note that a portion of the top surface of the insulator 285 is sometimes removed due to this CMP process.

Next, a conductive film which becomes the conductor 246 is deposited. The conductive film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductor 246 is processed by photolithography to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240 b. At this time, a part of the insulator 285 in a region where the conductors 246a and 246b do not overlap with the insulator 285 may be removed.

Note that when alumina is used as the insulator 252, aluminum is added to a region of the oxide 230b in contact with the insulator 252 and the vicinity thereof in a step after the insulating film serving as the insulator 252 is deposited, that is, the insulating film serving as the insulator 252 is deposited, a film is formed on the insulating film serving as the insulator 252, or a heat treatment is performed after the insulating film serving as the insulator 252 is deposited, or the like.

Through the above steps, a semiconductor device including the transistor 200 shown in fig. 1A to 1D can be manufactured. As shown in fig. 14A to 25D, the transistor 200 can be manufactured by using the manufacturing method of the semiconductor device shown in this embodiment mode.

< microwave treatment apparatus >

A microwave processing apparatus that can be used in the above-described method for manufacturing a semiconductor device will be described below.

First, a structure of a manufacturing apparatus with less impurity contamination in manufacturing a semiconductor device or the like will be described with reference to fig. 26 to 29.

Fig. 26 schematically illustrates a top view of a single-piece multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes: an atmosphere side substrate supply chamber 2701 including a cassette 2761 for accommodating substrates and an aligner 2762 for performing substrate alignment; an atmosphere side substrate transfer chamber 2702 for transferring a substrate from the atmosphere side substrate supply chamber 2701; a load lock chamber 2703a in which a substrate is carried in and the pressure in the chamber is changed from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber 2703b for carrying out the substrate and switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transfer chamber 2704 in which a substrate is transferred in vacuum; a process chamber 2706a; a process chamber 2706b; a process chamber 2706c; a process chamber 2706d.

The atmospheric substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is connected to the process chamber 2706a, the process chamber 2706b, the process chamber 2706c, and the process chamber 2706 d.

Since the gate valve GV is provided at the connection portion between the chambers, the chambers can be independently maintained in a vacuum state except for the atmospheric substrate supply chamber 2701 and the atmospheric substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. The substrate can be transferred in the manufacturing apparatus 2700 by using the transfer robot 2763a and the transfer robot 2763b.

The back pressure (total pressure) of the transfer chamber 2704 and the processing chambers is, for example, 1×10 ^-4 Pa or less, preferably 3×10 ^-5 Pa or less, more preferably 1×10 ^-5 Pa or below. Transfer chamber 2704The mass-to-charge ratio (m/z) of each chamber is 18, and the partial pressure of gas molecules (atoms) is, for example, 3X 10 ^-5 Pa or less, preferably 1×10 ^-5 Pa or less, more preferably 3×10 ^-6 Pa or below. The partial pressure of gas molecules (atoms) in the transfer chamber 2704 and the processing chambers, in which m/z is 28, is, for example, 3×10 ^-5 Pa or less, preferably 1×10 ^-5 Pa or less, more preferably 3×10 ^-6 Pa or below. The partial pressure of gas molecules (atoms) in the transfer chamber 2704 and the respective processing chambers at m/z of 44 is, for example, 3×10 ^-5 Pa or less, preferably 1×10 ^-5 Pa or less, more preferably 3×10 ^-6 Pa or below.

The total pressure and partial pressure in the transfer chamber 2704 and the respective processing chambers can be measured using an ionization gauge, a mass analyzer, or the like.

The transfer chamber 2704 and each processing chamber preferably have a structure with little external leakage or internal leakage. For example, the transfer chamber 2704 has a leak rate of 1×10 ⁰ Pa/min or less, preferably 5×10 ^-1 Pa/min or less. In addition, the leakage rate of each treatment chamber was 1×10 ^-1 Pa/min or less, preferably 5×10 ^-2 Pa/min or less.

The leak rate may be derived from the total pressure and the partial pressure measured by an ionization gauge, a mass analyzer, or the like. For example, the total pressure may be derived from the total pressure at 10 minutes after the evacuation by a vacuum pump such as a turbo molecular pump and the total pressure at 10 minutes after the valve is closed. Note that the above-described full pressure at 10 minutes after the start of evacuation may be an average value at the time of measuring the full pressure a plurality of times.

The leak rate depends on the external leak and the internal leak. The external leakage is a phenomenon in which gas flows in from the outside of the vacuum system due to a minute hole, a defective seal, or the like. Internal leakage results from leakage from a diaphragm such as a valve in a vacuum system or from released gas from internal components. In order to set the leak rate to the above-described value or less, measures are required in both of the external leak and the internal leak.

For example, the transfer chamber 2704 and the opening/closing portions of the respective processing chambers are preferably sealed with a metal gasket. The metal gasket is preferably a metal covered with ferric fluoride, aluminum oxide or chromium oxide. The metal gasket has higher tightness than the O-ring, so that external leakage can be reduced. By using a metal covered with a passive state by iron fluoride, aluminum oxide, chromium oxide, or the like, the release gas containing impurities released from the metal gasket can be suppressed, whereby internal leakage can be reduced.

As a member constituting the manufacturing apparatus 2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium containing less impurity-containing release gas is used. The alloy containing iron, chromium, nickel, and the like may be covered with the metal containing less impurity-containing gas emissions. The alloy containing iron, chromium, nickel and the like has rigidity, is heat-resistant and is suitable for processing. Here, by reducing irregularities on the surface of the member by polishing or the like to reduce the surface area, the released gas can be reduced.

Alternatively, a member such as iron fluoride, aluminum oxide, or chromium oxide may be used to cover the manufacturing apparatus 2700.

The member of the manufacturing apparatus 2700 is preferably made of only metal as much as possible, and for example, when a viewing window (viewing window) made of quartz or the like is provided, the surface of the viewing window is preferably covered with iron fluoride, aluminum oxide, chromium oxide or the like having a small thickness in order to suppress the release of gas.

Although the adherent substances present in the transfer chamber 2704 and the processing chambers adhere to the inner wall or the like and do not affect the pressure of the transfer chamber 2704 and the processing chambers, the adherent substances cause gas release generated when the transfer chamber 2704 and the processing chambers are exhausted. Therefore, although the leak rate does not relate to the exhaust speed, it is important to remove the adhering substances existing in the transfer chamber 2704 and each processing chamber as much as possible by using a pump having a high exhaust capacity and perform the exhaust in advance. In order to promote detachment of the attached matter, the transfer chamber 2704 and the processing chambers may be baked. By baking, the detachment speed of the attached matter can be increased to about 10 times. The baking is performed at 100 ℃ to 450 ℃. At this time, by removing the attached matter while introducing the inert gas into the transfer chamber 2704 and each processing chamber, the removal speed of water or the like which is not easily removed only by the exhaust gas can be further improved. Further, by heating the inert gas introduced at a temperature equal to the baking temperature, the speed of detachment of the deposit can be further increased. Here, a rare gas is preferably used as the inert gas.

It is preferable that the pressure in the transfer chamber 2704 and each processing chamber be increased by introducing an inert gas such as a heated rare gas or oxygen, and that the transfer chamber 2704 and each processing chamber be subjected to an exhaust treatment again after a predetermined time has elapsed. The transfer chamber 2704 and the attachments in the respective processing chambers can be separated by introducing the heated gas, and impurities existing in the transfer chamber 2704 and the respective processing chambers can be reduced. It is effective to repeat this treatment 2 times or more and 30 times or less, preferably 5 times or more and 15 times or less. Specifically, the pressure in the transfer chamber 2704 and each processing chamber may be set to 0.1Pa or more and 10kPa or less, preferably 1Pa or more and 1kPa or less, more preferably 5Pa or more and 100Pa or less by introducing an inert gas or oxygen or the like at 40 ℃ or more and 400 ℃ or less, preferably 50 ℃ or more and 200 ℃ or less, and the period of holding the pressure may be set to 1 minute or more and 300 minutes, preferably 5 minutes or more and 120 minutes or less. Then, the transfer chamber 2704 and each processing chamber are exhausted for 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

Next, the process chambers 2706b and 2706c will be described with reference to a schematic cross-sectional view shown in fig. 27.

The processing chambers 2706b and 2706c are processing chambers capable of performing microwave processing on an object to be processed, for example. Note that the processing chamber 2706b differs from the processing chamber 2706c only in the atmosphere at the time of performing microwave processing. Since the other structures of the process chamber 2706b and the process chamber 2706c are the same, they will be described together.

The processing chamber 2706b and the processing chamber 2706c include a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Further, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power source 2816, a vacuum pump 2817, and a valve 2818 are provided outside the process chamber 2706b and the process chamber 2706c.

The high frequency generator 2803 is connected to the mode converter 2805 through a waveguide 2804. The mode converter 2805 is connected to a slot antenna board 2808 through a waveguide 2807. The slot antenna plate 2808 is disposed in contact with the dielectric plate 2809. Further, a gas supply 2801 is connected to a mode converter 2805 through a valve 2802. Then, a gas is introduced into the process chambers 2706b and 2706c through the gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has a function of exhausting gas or the like from the process chambers 2706b and 2706c through the valve 2818 and the exhaust port 2819. The high-frequency power source 2816 is connected to the substrate holder 2812 through a matching unit 2815.

The substrate holder 2812 has a function of holding a substrate 2811. For example, the substrate holder 2812 has a function of performing an electrostatic chuck or a mechanical chuck on the substrate 2811. Further, the substrate holder 2812 has a function of an electrode to which power is supplied by the high-frequency power source 2816. Further, the substrate holder 2812 includes a heating mechanism 2813 inside thereof and has a function of heating the substrate 2811.

As the vacuum pump 2817, for example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, a turbo molecular pump, or the like can be used. In addition, a cryotrap may be used in addition to the vacuum pump 2817. It is particularly preferable that the cryopump and the cryotrap be used to drain water efficiently.

As the heating means 2813, for example, a heating means that heats by a resistance heating element or the like may be used. Alternatively, a heating mechanism that heats by heat conduction or heat radiation of a medium such as a heated gas may be used. For example, RTA (Rapid Thermal Annealing: rapid thermal annealing) such as GRTA (Gas Rapid Thermal Annealing: gas rapid thermal annealing) or LRTA (Lamp Rapid Thermal Annealing: lamp rapid thermal annealing) may be used. GRTA is heat treated with a high temperature gas. An inert gas is used as the gas.

In addition, the gas supply 2801 may be connected to the refiner through a mass flow controller. As the gas, a gas having a dew point of-80℃or lower, preferably-100℃or lower is preferably used. For example, an oxygen gas, a nitrogen gas, and a rare gas (argon gas or the like) can be used.

As the dielectric plate 2809, for example, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (yttria), or the like may be used. Further, another protective layer may be formed on the surface of the dielectric plate 2809. As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like can be used. Since the dielectric plate 2809 is exposed to a particularly high density region of high density plasma 2810, which will be described later, damage can be reduced by providing a protective layer. As a result, the increase in particles and the like at the time of treatment can be suppressed.

The high frequency generator 2803 has a function of generating microwaves of, for example, 0.3GHz or more and 3.0GHz or less, 0.7GHz or more and 1.1GHz or less, or 2.2GHz or more and 2.8GHz or less. Microwaves generated by the high-frequency generator 2803 are transmitted to the mode converter 2805 through the waveguide 2804. In the mode converter 2805, the transmitted TE mode microwaves are converted into TEM mode microwaves. The microwaves are then transmitted to the slot antenna plate 2808 through the waveguide 2807. A plurality of slots are provided in the slot antenna plate 2808, and microwaves pass through the slots and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and a high-density plasma 2810 can be generated. The high-density plasma 2810 includes ions and radicals according to the kind of gas supplied from the gas supply source 2801. For example, the high density plasma 2810 includes oxygen radicals and the like.

At this time, by using ions and radicals generated in the high-density plasma 2810, quality of a film or the like over the substrate 2811 can be improved. In addition, it is sometimes preferable to bias the substrate 2811 side using a high-frequency power source 2816. As the high-frequency power source 2816, for example, RF (Radio Frequency) power sources having frequencies of 13.56MHz, 27.12MHz, and the like can be used. By applying a bias to the substrate side, ions in the high-density plasma 2810 can efficiently reach the deep portion of the opening of the film or the like over the substrate 2811.

For example, oxygen radical treatment using the high-density plasma 2810 can be performed in the process chamber 2706b or the process chamber 2706c by introducing oxygen from the gas supply source 2801.

Next, the process chambers 2706a and 2706d will be described with reference to a schematic cross-sectional view shown in fig. 28.

The processing chambers 2706a and 2706d are, for example, processing chambers capable of irradiating an object to be processed with electromagnetic waves. Note that the processing chamber 2706a differs from the processing chamber 2706d only in the kind of electromagnetic wave. Since the other structures of the processing chamber 2706a and the processing chamber 2706d are mostly the same, they will be described together.

The process chambers 2706a and 2706d include one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust 2830. Further, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the process chamber 2706a and the process chamber 2706d, and the like.

The gas supply 2821 is connected to the gas inlet 2823 through a valve 2822. Vacuum pump 2828 is connected to exhaust 2830 through valve 2829. The lamp 2820 is disposed opposite to the substrate holder 2825. The substrate holder 2825 has a function of holding the substrate 2824. In addition, the substrate holder 2825 includes a heating mechanism 2826 inside thereof and has a function of heating the substrate 2824.

As the lamp 2820, for example, a light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light can be used. For example, a light source having a function of emitting electromagnetic waves having a peak in a wavelength region of 10nm or more and 2500nm or less, 500nm or more and 2000nm or less, or 40nm or more and 340nm or less may be used.

For example, as the lamp 2820, a light source such as a halogen lamp, a metal halogen lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp can be used.

For example, part or all of electromagnetic waves emitted from the lamp 2820 are sucked by the substrate 2824, whereby the quality of a film or the like on the substrate 2824 can be improved. For example, defects may be generated or reduced, or impurities may be removed. In addition, in the case where defects are generated or reduced, or impurities are removed while the substrate 2824 is heated, defects can be efficiently generated or reduced, impurities can be removed, or the like.

Alternatively, for example, the substrate 2824 may be heated by heating the substrate holder 2825 with electromagnetic waves emitted from the lamp 2820. In this case, it is not necessary to include a heating mechanism 2826 inside the substrate holder 2825.

The vacuum pump 2828 may refer to the description regarding the vacuum pump 2817. The heating means 2826 may refer to the description of the heating means 2813. In addition, the gas supply source 2821 may refer to the description about the gas supply source 2801.

The microwave processing apparatus usable in the present embodiment is not limited to the above-described microwave processing apparatus, and a microwave processing apparatus 2900 shown in fig. 29 may be used. The microwave processing apparatus 2900 includes a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas tube 2806, a vacuum pump 2817, and a valve 2818. In addition, the microwave processing apparatus 2900 includes a substrate holder 2902 that supports a plurality of substrates 2811 (2811_1 to 2811—n, n being an integer of 2 or more) within the quartz tube 2901. The microwave processing apparatus 2900 may include a heating unit 2903 outside the quartz tube 2901.

The microwaves generated by the high-frequency generator 2803 are irradiated to the substrate disposed in the quartz tube 2901 through the waveguide 2804. The vacuum pump 2817 is connected to the exhaust port 2819 through a valve 2818, and the pressure inside the quartz tube 2901 can be adjusted. The gas supply source 2801 is connected to a gas pipe 2806 through a valve 2802, so that a desired gas can be introduced into the quartz pipe 2901. In addition, the substrate 2811 in the quartz tube 2901 can be heated to a desired temperature by the heating unit 2903. Alternatively, the gas supplied from the gas supply source 2801 may be heated by the heating unit 2903. The substrate 2811 can be subjected to heat treatment and microwave treatment simultaneously by the microwave treatment device 2900. In addition, microwave treatment may be performed after the substrate 2811 is heated. In addition, the substrate 2811 may be subjected to a microwave treatment and then to a heat treatment.

The substrates 2811_1 to 2811—n may be treated substrates forming a semiconductor device or a memory device, or a part of the substrates 2811_1 to 2811—n may be pseudo substrates. For example, the substrates 2811_1 and 2811_n may be pseudo substrates, and the substrates 2811_2 to 2811_n-1 may be handle substrates. In addition, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be pseudo substrates, and the substrates 2811_3 to 2811_n-2 may be processed substrates. By using the dummy substrate, a plurality of processed substrates can be uniformly processed at the time of microwave processing or heat processing, and unevenness between processed substrates can be reduced, which is preferable. For example, a dummy substrate is preferably disposed on a processing substrate closest to the high-frequency generator 2803 and the waveguide 2804, since the processing substrate can be prevented from being directly exposed to microwaves.

By using the above manufacturing apparatus, it is possible to suppress the contamination of impurities into the object to be treated and to improve the film quality.

< modification example of semiconductor device >

An example of a semiconductor device according to an embodiment of the present invention will be described below with reference to fig. 11A to 13D.

A in each drawing is a plan view of the semiconductor device. B in each drawing is a sectional view along a portion of a chain line A1-A2 in a in each drawing. C in the drawings is a sectional view of a portion along a dash-dot line A3-A4 in a in the drawings. D in each drawing is a sectional view of a portion along a chain line A5-A6 in a in each drawing. For clarity, some constituent elements are omitted from the plan view of a in each drawing.

Note that in the semiconductor devices shown in a to D in the drawings, the same reference numerals are given to structures having the same functions as those of the constituent elements of the semiconductor device shown in structural examples of the semiconductor device. Note that the material constituting the semiconductor device in this section may be the material described in detail in < structural example of the semiconductor device >.

< modification example 1 of semiconductor device >

The semiconductor device shown in fig. 11A to 11D is a modified example of the semiconductor device shown in fig. 1A to 1D. The semiconductor device shown in fig. 11A to 11D is different from the semiconductor device shown in fig. 1A to 1D in that: the insulator 282 is not provided. Accordingly, in the semiconductor device shown in fig. 11A to 11D, the insulator 283 is in contact with the top surface of the conductor 260, the top surface of the insulator 280, the uppermost portion of the insulator 254, the uppermost portion of the insulator 250, and the uppermost portion of the insulator 252.

For example, when a sufficient amount of oxygen can be supplied to the oxide 230 by the microwave treatment or the like shown in fig. 19 or 20, the region 230bc can be substantially i-shaped even if oxygen supply to the insulator 280 is not performed in the case where the insulator 282 is provided. In this case, as shown in fig. 11A to 11D, by adopting a structure in which the insulator 282 is not provided, the manufacturing process of the semiconductor device can be simplified, and improvement in productivity can be achieved.

< modification example 2 of semiconductor device >

The semiconductor device shown in fig. 12A to 12D is a modified example of the semiconductor device shown in fig. 1A to 1D. The semiconductor device shown in fig. 12A to 12D is different from the semiconductor device shown in fig. 1A to 1D in that: an oxide 243 (oxide 243a and oxide 243 b) is provided. Oxide 243a is disposed between oxide 230b and conductor 242a, and oxide 243b is disposed between oxide 230b and conductor 242 b. Here, the oxide 243a is preferably in contact with the top surface of the oxide 230b and the bottom surface of the conductor 242 a. The oxide 243b preferably contacts the top surface of the oxide 230b and the bottom surface of the conductor 242 b.

The oxide 243 preferably has a function of inhibiting oxygen permeation. It is preferable to dispose an oxide 243 having a function of suppressing oxygen permeation between the conductor 242 serving as a source electrode or a drain electrode and the oxide 230b because the resistance between the conductor 242 and the oxide 230b is reduced. By adopting such a structure, the electrical characteristics, field effect mobility, and reliability of the transistor 200 can be improved in some cases.

As the oxide 243, a metal oxide containing the element M can also be used. In particular, aluminum, gallium, yttrium or tin is preferably used as element M. The concentration of element M of oxide 243 is preferably higher than oxide 230 b. Gallium oxide may be used as the oxide 243. In addition, a metal oxide such as in—m—zn oxide may be used as the oxide 243. Specifically, the atomic ratio of In to element M In the metal oxide for oxide 243 is preferably larger than the atomic ratio of In to element M In the metal oxide for oxide 230 b. The thickness of the oxide 243 is preferably 0.5nm or more and 5nm or less, more preferably 1nm or more and 3nm or less, and still more preferably 1nm or more and 2nm or less. The oxide 243 preferably has crystallinity. In the case where the oxide 243 has crystallinity, release of oxygen in the oxide 230 can be appropriately suppressed. For example, in the case where the oxide 243 has a crystal structure such as hexagonal crystal, release of oxygen in the oxide 230 may be suppressed.

< modification example 3 of semiconductor device >

The semiconductor device shown in fig. 13A to 13D is a modified example of the semiconductor device shown in fig. 1A to 1D. The semiconductor device shown in fig. 13A to 13D is different from the semiconductor device shown in fig. 1A to 1D in that the insulator 283 is in contact with a portion of the top surface of the insulator 212. Accordingly, the transistor 200 is disposed in a region sealed by the insulator 283 and the insulator 212. With the above configuration, the hydrogen contained outside the sealed region can be suppressed from being mixed into the sealed region. In the transistor 200 shown in fig. 13A to 13D, the insulator 212 and the insulator 283 have a single-layer structure, but the present invention is not limited thereto. For example, the insulator 212 and the insulator 283 may each have a laminated structure of two or more layers.

The OS transistors such as the transistor 200 have small variations in electrical characteristics due to irradiation of radiation, that is, have high resistance to radiation, and thus can be suitably used even in an environment where radiation may be incident. For example, an OS transistor can be used appropriately in the case of use in a cosmic space. Specifically, an OS transistor can be used as a transistor constituting a semiconductor device provided in an aerospace plane, an artificial satellite, a space probe, or the like. Examples of the radiation include X-ray and neutron radiation. The space is, for example, a place having a height of 100km or more, but the space described in the present specification may include a thermal layer, an intermediate layer, and a stratosphere.

Alternatively, for example, an OS transistor may be used as a transistor constituting a semiconductor device provided in a nuclear power plant and a radioactive waste treatment field or a work robot of a treatment field. In particular, it can be suitably used as a transistor constituting a semiconductor device such as: the semiconductor device is provided in a remotely operated robot for remote operation such as removal of a reactor facility, extraction of nuclear fuel or fuel fragments, and field inspection in a space where a large amount of radioactive substances are contained.

Even in a high-temperature environment, the off-state current of the OS transistor such as the transistor 200 hardly increases. Specifically, the off-state current hardly increases even at ambient temperatures of not less than room temperature and not more than 200 ℃. In addition, even in a high-temperature environment, the on-state current of the OS transistor is not easily reduced. The semiconductor device including the OS transistor stably operates even under a high-temperature environment and has high reliability.

< application example of semiconductor device >

An example of a semiconductor device according to an embodiment of the present invention will be described below with reference to fig. 30.

Fig. 30A shows a top view of the semiconductor device 500. In fig. 30A, a direction parallel to the channel length direction of the transistor 200 is an x-axis, and a direction perpendicular to the x-axis is a y-axis. Fig. 30B is a cross-sectional view of a portion along the chain line A1-A2 in fig. 30A, which corresponds to a cross-sectional view of the transistor 200 in the channel length direction. Fig. 30C is a sectional view taken along the chain line A3-A4 in fig. 30A, which corresponds to the opening area 400 and the vicinity thereof. Note that in the plan view of fig. 30A, some constituent elements are omitted for clarity.

Note that in the semiconductor device shown in fig. 30A to 30C, the same reference numerals are given to structures having the same functions as those of the constituent elements of the semiconductor device shown in structural examples of the semiconductor device. Note that the material constituting the semiconductor device in this section may be the material described in detail in < structural example of the semiconductor device >.

The semiconductor device 500 shown in fig. 30A to 30C is a modified example of the semiconductor device shown in fig. 1A to 1D. The semiconductor device 500 shown in fig. 30A to 30C is different from the semiconductor device shown in fig. 1A to 1D in that: insulator 282 and insulator 280 are formed with an opening region 400. In addition, the semiconductor device shown in fig. 1A to 1D is different from the semiconductor device in that: a sealing portion 265 is formed so as to surround the plurality of transistors 200.

The semiconductor device 500 includes a plurality of transistors 200 and a plurality of opening regions 400 arranged in a matrix. In addition, a plurality of conductors 260 serving as gate electrodes of the transistors 200 are provided so as to extend in the y-axis direction. The opening region 400 is formed in a region that does not overlap with the oxide 230 and the conductor 260. Further, the sealing portion 265 is formed so as to surround the plurality of transistors 200, the plurality of conductors 260, and the plurality of opening regions 400. Note that the number, arrangement, and size of the transistor 200, the conductor 260, and the opening region 400 are not limited to those shown in fig. 30, and may be appropriately set according to the design of the semiconductor device 500.

As shown in fig. 30B and 30C, the sealing portion 265 is provided so as to surround the plurality of transistors 200, the insulator 216, the insulator 222, the insulator 275, the insulator 280, and the insulator 282. In other words, the insulator 283 is provided so as to cover the plurality of transistors 200, the insulator 216, the insulator 222, the insulator 275, the insulator 280, and the insulator 282. In addition, in the sealing portion 265, the insulator 283 is in contact with the top surface of the insulator 214. Further, an insulator 274 is provided between the insulator 283 and the insulator 285 above the sealing portion 265. The top surface of insulator 274 has a height substantially equal to the uppermost height of insulator 283. As the insulator 274, an insulator similar to the insulator 280 can be used.

By adopting such a structure, the plurality of transistors 200 can be surrounded by the insulator 283, the insulator 214, and the insulator 212. Here, one or more of the insulator 283, the insulator 214, and the insulator 212 is preferably used as the hydrogen blocking insulating film. Thereby, hydrogen contained outside the region of the seal portion 265 can be suppressed from entering the region of the seal portion 265.

As shown in fig. 30C, in the opening region 400, the insulator 282 has an opening. In the opening region 400, the insulator 280 may have a groove portion overlapping with the opening portion of the insulator 282. The depth of the groove of the insulator 280 may be as deep as the top surface of the insulator 275 is exposed, and may be, for example, about 1/4 to 1/2 of the maximum thickness of the insulator 280.

As shown in fig. 30C, the insulator 283 is in contact with the side surface of the insulator 282, the side surface of the insulator 280, and the top surface of the insulator 280 inside the opening region 400. In the opening region 400, a part of the insulator 274 may be formed so as to fit into a recess formed in the insulator 283. At this time, the top surface of the insulator 274 formed in the opening region 400 may be substantially equal to the uppermost surface of the insulator 283.

By performing the heat treatment in a state where such an opening region 400 is formed and exposed from the opening insulator 280 of the insulator 282, a part of oxygen contained in the insulator 280 can be diffused to the outside from the opening region 400 while oxygen is supplied to the oxide 230. Thereby, it is possible to supply ten oxygen from the insulator 280 containing oxygen detached by heating to a region serving as a channel formation region in the oxide semiconductor and the vicinity thereof, and it is possible to prevent the oxygen from being supplied excessively.

At this time, hydrogen contained in the insulator 280 may be bonded to oxygen, which is released to the outside through the opening region 400. Hydrogen bonded to oxygen is released as water. Accordingly, hydrogen contained in the insulator 280 can be reduced, and hydrogen contained in the insulator 280 can be reduced from entering the oxide 230.

In fig. 30A, the shape of the opening area 400 is substantially rectangular in plan view, but the present invention is not limited thereto. For example, the shape of the opening area 400 in a plan view may be rectangular, elliptical, circular, diamond-shaped, or a combination of these shapes. In addition, the area and arrangement pitch of the opening region 400 can be appropriately set according to the design of the semiconductor device including the transistor 200. For example, in a region where the density of the transistor 200 is low, the area of the opening region 400 may be enlarged or the arrangement pitch of the opening region 400 may be reduced. For example, in a region where the density of the transistor 200 is high, the area of the opening region 400 may be reduced or the arrangement pitch of the opening region 400 may be increased.

According to one aspect of the present invention, a novel transistor may be provided. According to one embodiment of the present invention, a semiconductor device with small non-uniformity in transistor characteristics can be provided. Further, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. Further, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Further, according to one embodiment of the present invention, a semiconductor device having a high on-state current can be provided. Further, according to one embodiment of the present invention, a semiconductor device having high field effect mobility can be provided. Further, according to one embodiment of the present invention, a semiconductor device having excellent frequency characteristics can be provided. Further, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Further, according to an embodiment of the present invention, a semiconductor device with low power consumption can be provided.

As described above, at least a part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with other embodiments and other examples described in this specification.

(embodiment 2)

In this embodiment, one embodiment of a semiconductor device will be described with reference to fig. 31 and 32. The semiconductor device described in this embodiment mode is an evaluation element (also referred to as TEG) capable of performing multipoint measurement.

Fig. 31 is a circuit diagram of a TEG900 that is an example of a semiconductor device according to an embodiment of the invention.

TEG900 includes transistor group TRA and peripheral circuit PC.

The transistor group TRA includes m×n (m, n are integers of 1 or more independently of each other) transistors (transistors Tr [1,1] to Tr [ m, n ] shown in fig. 31).

The peripheral circuit PC includes two multiplexers (multiplexer MUXX and multiplexer MUXY), m analog switches (analog switches ASX [1] to ASX [ m ]), and n analog switches (analog switches ASY [1] to ASY [ n ]). The analog switch is an electronic component that switches on/off of an analog signal according to an input control signal. Here, the control signal refers to an analog potential (binary voltage condition), and the analog signal refers to an analog potential (binary or higher voltage condition). In addition, the analog switch is also called a transmission gate.

The TEG900 is electrically connected to wirings WX, WY, DL, TGL, BGL, and SL.

The wiring WX is electrically connected to the multiplexer MUXX. The wiring WY is electrically connected to the multiplexer mux. In addition, the wiring BGL is electrically connected to the second gates of the transistors Tr [1,1] to Tr [ m, n ]. In addition, the wiring SL is electrically connected to one of the source and the drain of each of the transistors Tr [1,1] to Tr [ m, n ].

When the first gate and the second gate are electrically connected in each of the transistors Tr [1,1] to Tr [ m, n ], the TEG900 may not include the wiring BGL. In addition, when the transistors Tr [1,1] to Tr [ m, n ] are single-gate structure transistors, that is, transistors not including the second gate, the TEG900 may not include the wiring BGL.

The wiring WX is supplied with a control signal used in the multiplexer MUXX. In addition, the wiring WY is supplied with a control signal used in the multiplexer mux.

The respective first terminals of the analog switches ASX [1] to ASX [ m ] are electrically connected to the multiplexer MUXX. Further, the second terminals of the analog switches ASX [1] to ASX [ m ] are electrically connected to the wiring DL. In addition, a third terminal of the analog switch ASX [ i ] (i is an integer of 1 to m) is electrically connected to the other of the source and the drain of each of the transistors Tr [ i,1] to Tr [ i, n ].

The multiplexer MUXX has a function of controlling the on/off of each of the analog switches ASX [1] to ASX [ m ]. Specifically, the multiplexer MUXX has a function of turning on any one of the m analog switches ASX or turning off all the analog switches ASX according to a control signal received from the wiring WX. For example, the analog switch ASX is turned off when the potential of the signal supplied from the multiplexer MUXX is high, and is turned on when the potential of the signal supplied from the multiplexer MUXX is low. When the analog switch ASX [ i ] is turned on, the wiring DL is turned on with the other of the source and the drain of each of the transistors Tr [ i,1] to Tr [ i, n ]. At this time, the potential of the wiring DL is supplied to the other of the source and the drain of each of the transistors Tr [ i,1] to Tr [ i, n ].

The first terminals of the analog switches ASY [1] to ASY [ n ] are electrically connected to the multiplexer MUXY. Further, the second terminals of the analog switches ASY [1] to ASY [ n ] are electrically connected to the wiring TGL. The third terminal of the analog switch ASY [ j ] (j is an integer of 1 to n) is electrically connected to the first gate of each of the transistors Tr [ j,1] to Tr [ j, n ].

The multiplexer MUXY has a function of controlling the on/off of each of the analog switches ASY [1] to ASY [ n ]. Specifically, the multiplexer mux has a function of turning on any one of the n analog switches ASY or turning off all the analog switches ASY according to a control signal received from the wiring WY. For example, the analog switch ASY is turned on when the potential of the signal supplied from the multiplexer MUXY is high, and is turned off when the potential of the signal supplied from the multiplexer MUXY is low. Alternatively, the analog switch ASY is turned off when the potential of the signal supplied from the multiplexer MUXY is high, and is turned on when the potential of the signal supplied from the multiplexer MUXY is low. When the analog switch ASY [ j ] is turned on, the wiring TGL is turned on with the first gates of the transistors Tr [1, j ] to Tr [ m, j ], respectively. At this time, the potential of the wiring DL is supplied to the first gates of the transistors Tr [1, j ] to Tr [ n, j ], respectively.

By using TEG900 shown in fig. 31, a transistor to be measured can be selected from m×n transistors, and electrical characteristics can be measured. That is, TEG900 can be said to be a TEG capable of multipoint measurement.

Preferably, the multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are each independently configured using a CMOS (Complementary Metal Oxide Semiconductor ) circuit or a unipolar circuit, and more preferably, the multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are each configured using a CMOS circuit or a unipolar circuit.

In addition, it is preferable to stack a layer including the peripheral circuit PC and a layer including the transistor group TRA.

Fig. 32A shows a perspective view of TEG 900. TEG900 includes layers 910 and 920. Fig. 32B is a perspective view for explaining the structure of TEG900, showing layer 910 and layer 920 separately.

Layer 910 includes peripheral circuitry PC. In other words, layer 910 includes multiplexer MUXX, multiplexer MUXY, analog switch ASX, and analog switch ASY. In addition, layer 920 includes a transistor group TRA.

The layer 910 may be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, or the like, singly or in combination. As the semiconductor material, silicon, germanium, or the like can be used, for example. Further, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductor, and nitride semiconductor may be used. A transistor including silicon in a channel formation region is sometimes referred to as a Si transistor.

In addition, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like, which can be used for HEMTs (High Electron Mobility Transistor, high electron mobility transistors), can also be used.

The layer 920 may be formed using a semiconductor material such as an oxide semiconductor or silicon, which can be formed as a thin film. By using the thin film formation technique, the peripheral circuit PC included in the layer 910 and the transistor group TRA included in the layer 920 can be three-dimensionally arranged. Therefore, the occupation area of the TEG900 can be reduced.

Alternatively, the layer 920 may be formed over another substrate and then bonded to the layer 910.

For example, the peripheral circuit PC is configured using a CMOS circuit, and the transistor group TRA is configured using the transistor 200 described in embodiment 1. Specifically, the peripheral circuit PC is configured using Si transistors, and the transistor group TRA is configured using OS transistors. The layer including the Si transistor and the layer including the OS transistor can be formed in a monolithic manner, and thus by adopting this structure, wiring connecting the peripheral circuit and the OS transistor can be shortened, and electrical characteristics of a plurality of OS transistors can be measured with a short TAT (Turn Around Time). In addition, the pitch between the OS transistors can be reduced.

Alternatively, for example, the peripheral circuit PC and the transistor group TRA are configured using the transistor 200 described in embodiment 1. Specifically, the peripheral circuit PC and the transistor group TRA are configured using OS transistors. Layers including OS transistors may be stacked. Therefore, by stacking a layer including an OS transistor for the peripheral circuit PC and a layer including an OS transistor for the transistor group TRA, wiring connecting the peripheral circuit and the OS transistor can be shortened, and electrical characteristics of a plurality of OS transistors can be measured with a short TAT. In addition, the pitch between the OS transistors can be reduced.

The peripheral circuit PC and the transistor group TRA may be formed so as to be three or more. For example, some of the plurality of transistors included in the peripheral circuit PC may be formed using Si transistors, all of the other plurality of transistors included in the peripheral circuit PC may be formed using OS transistors, and the transistor group TRA may be formed using OS transistors. At this time, TEG900 may also have a layer including a Si transistor, a first layer including an OS transistor over the layer, and a second layer including an OS transistor over the first layer. The OS transistors included in the first layer are preferably used for all other transistors of the plurality of transistors included in the peripheral circuit PC, and the OS transistors included in the second layer are preferably used for the transistor group TRA. By adopting this structure, the occupation area of the TEG900 can be further reduced.

Alternatively, the peripheral circuit PC and the transistor group TRA may be formed in the same layer.

Embodiment 3

In this embodiment mode, one embodiment of a semiconductor device is described with reference to fig. 33 to 37.

[ storage device 1]

Fig. 33 shows an example of a semiconductor device (memory device) according to an embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. As the transistor 200, the transistor 200 described in the above embodiment mode can be used.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is low, the memory content can be maintained for a long period of time by using it for the memory device. In other words, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

In the semiconductor device shown in fig. 33, a wiring 1001 is electrically connected to a source of the transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, the wiring 1004 is electrically connected to a first gate of the transistor 200, and the wiring 1006 is electrically connected to a second gate of the transistor 200. Further, the other of the gate of the transistor 300 and the source and the drain of the transistor 200 is electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100.

Further, the memory devices shown in fig. 33 are arranged in a matrix, whereby a memory cell array can be configured.

< transistor 300>

The transistor 300 is disposed on the substrate 311, and includes: a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 constituted by a portion of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b serving as source regions or drain regions. Transistor 300 may be p-channel or n-channel.

Here, in the transistor 300 shown in fig. 33, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. The conductor 316 is provided so as to cover the side surfaces and the top surface of the semiconductor region 313 with an insulator 315 interposed therebetween. In addition, a material for adjusting the work function can be used for the conductor 316. Such a transistor 300 is also referred to as a FIN-type transistor because of the use of a convex portion of a semiconductor substrate. Further, an insulator having a mask for forming the convex portion may be provided so as to be in contact with the upper surface of the convex portion. Although the case where the protruding portion is formed by processing a part of the semiconductor substrate is described here, the semiconductor film having the protruding portion may be formed by processing an SOI substrate.

Note that the structure of the transistor 300 shown in fig. 33 is only an example, and is not limited to the above-described structure, and an appropriate transistor may be used according to a circuit structure or a driving method.

< capacitor 100>

The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 283 shown in the above embodiment.

For example, the conductor 112 and the conductor 110 provided on the conductor 246 may be formed simultaneously. Further, the conductor 112 is used as a plug or wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

In fig. 33, the conductor 112 and the conductor 110 have a single-layer structure, but the structure is not limited to this, and may have a laminated structure of two or more layers. For example, a conductor having high adhesion to a conductor having barrier properties and a conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

The insulator 130 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride, or the like, and may be stacked or formed in a single layer.

For example, a stacked structure of a material having a high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material is preferably used for the insulator 130. By adopting this structure, the capacitor 100 can include an insulator with a high dielectric constant (high-k) to ensure sufficient capacitance, and can include an insulator with a high dielectric strength to improve dielectric strength, so that electrostatic destruction of the capacitor 100 can be suppressed.

Note that as a high dielectric constant (high-k) material (a material having a high relative dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, a nitride containing silicon and hafnium, or the like can be given.

On the other hand, as a material having a high dielectric strength (a material having a low relative dielectric constant), there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, resin, and the like.

< wiring layer >

Wiring layers including interlayer films, wirings, plugs, and the like may be provided between the respective structures. Further, the wiring layer may be provided as a plurality of layers according to design. Here, in the conductor having a function of a plug or a wiring, a plurality of structures may be denoted by the same symbol. In this specification, the wiring and the plug electrically connected to the wiring may be one component. That is, a part of the electric conductor is sometimes used as a wiring, and a part of the electric conductor is sometimes used as a plug.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 300. Further, a conductor 328, a conductor 330, and the like electrically connected to the capacitor 100 or the transistor 200 are buried in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Further, the electric conductor 328 and the electric conductor 330 are used as plugs or wirings.

Further, an insulator used as an interlayer film may be used as a planarizing film covering the concave-convex shape thereunder. For example, planarization may be performed by a planarization process using a Chemical Mechanical Polishing (CMP) method or the like in order to improve the flatness of the top surface of the insulator 322.

Further, a wiring layer may be provided on the insulator 326 and the conductor 330. For example, in fig. 33, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Further, conductors 356 are formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 is used as a plug or wiring.

Similarly, the insulator 210, the insulator 212, the insulator 214, and the insulator 216 are filled with a conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like. Further, the conductor 218 is used as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. Further, an insulator 150 is provided on the conductor 120 and the insulator 130.

Here, like the insulator 241 in the above embodiment, the insulator 217 is provided so as to be in contact with the side surface of the conductor 218 used as a plug. The insulator 217 is provided in contact with the inner walls of openings formed in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. In other words, insulator 217 is disposed between conductor 218 and insulator 210, insulator 212, insulator 214, and insulator 216. The conductor 205 may be formed in parallel with the conductor 218, so the insulator 217 is sometimes formed in contact with the side surface of the conductor 205.

As the insulator 217, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, and the insulator 222, it is possible to suppress impurities such as water and hydrogen from entering the oxide 230 from the insulator 210, the insulator 216, and the like through the conductor 218. In particular, silicon nitride has high barrier properties against hydrogen, so that it is preferable. Further, oxygen contained in the insulator 210 or the insulator 216 can be prevented from being absorbed by the conductor 218.

The insulator 217 may be formed using the same method as the insulator 241. For example, silicon nitride is deposited using a PEALD process, and an opening to the conductor 356 may be formed using an anisotropic etch.

As an insulator which can be used as an interlayer film, there are oxides, nitrides, oxynitrides, metal oxides, metal oxynitrides, and the like having insulating properties.

For example, by using a material having a relatively low dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material is preferably selected according to the function of the insulator.

For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, and the like are preferably insulators having a low relative dielectric constant. For example, the insulator preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, resin, or the like. Alternatively, the insulator preferably has a stacked structure of silicon oxide, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, or silicon oxide having voids and resin. Since silicon oxide and silicon oxynitride have thermal stability, a stacked structure having thermal stability and low relative dielectric constant can be realized by combining them with a resin. Examples of the resin include polyesters, polyolefins, polyamides (nylon, aramid, etc.), polyimides, polycarbonates, and acrylic resins.

Further, the transistor using an oxide semiconductor is surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, whereby the electrical characteristics of the transistor can be stabilized. Accordingly, as the insulator 214, the insulator 212, the insulator 350, and the like, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.

As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or stacked layers. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide and the like, silicon oxynitride, silicon nitride and the like can be used.

As a conductor which can be used for wiring and a plug, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Further, a semiconductor having high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials may be used in a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. The wiring resistance can be reduced by using a low-resistance conductive material.

< wiring or plug provided with layer of oxide semiconductor >

Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In this case, an insulator having barrier properties is preferably provided between the insulator having the excess oxygen region and the conductor provided to the insulator having the excess oxygen region.

For example, in fig. 33, an insulator 241 is preferably provided between an insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the transistor 200 can have a structure sealed with an insulator having barrier properties.

That is, by providing the insulator 241, the excess oxygen of the insulator 280 can be suppressed from being absorbed by the conductor 240. Further, by having the insulator 241, diffusion of hydrogen as an impurity to the transistor 200 through the conductor 240 can be suppressed.

Further, as the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen, and oxygen is preferably used. For example, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or the like is preferably used. In particular, silicon nitride has high barrier properties against hydrogen, so that it is preferable. For example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

As in the above embodiment, the transistor 200 may be sealed with the insulator 212, the insulator 214, the insulator 282, and the insulator 283. By adopting the above-described structure, the incorporation of hydrogen contained in the insulator 274, the insulator 150, or the like into the insulator 280 or the like can be reduced.

Here, the conductor 240 penetrates the insulator 283 and the insulator 282, the conductor 218 penetrates the insulator 214 and the insulator 212, and the insulator 241 is provided in contact with the conductor 240 and the insulator 217 is provided in contact with the conductor 218 as described above. This can reduce the mixing of hydrogen into the inside of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 through the conductors 240 and 218. In this manner, the transistor 200 can be sealed with the insulator 212, the insulator 214, the insulator 282, the insulator 283, the insulator 241, and the insulator 217, and impurities such as hydrogen contained in the insulator 274 or the like can be reduced from being mixed in from the outside.

< cutting line >

Next, dicing lines (sometimes referred to as dicing lines, breaking lines, or cutting lines) provided when dividing a large-area substrate into a plurality of semiconductor devices having a chip shape for each semiconductor device will be described. As a dividing method, for example, after grooves (dicing lines) for dividing semiconductor modules are first formed in a substrate, the grooves are cut at the dicing lines, and a plurality of divided (divided) semiconductor devices are obtained.

Here, for example, as shown in fig. 33, it is preferable to design such that the region where the insulator 283 and the insulator 214 are in contact overlaps with the dicing line. That is, openings are provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216 in the vicinity of the region to be the dicing line provided at the edge of the memory cell including the plurality of transistors 200.

That is, in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, and the insulator 216, the insulator 214 is in contact with the insulator 283.

For example, openings may be formed in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214. By adopting such a structure, the insulator 212 is in contact with the insulator 283 in the openings provided in the insulator 282, the insulator 280, the insulator 275, the insulator 222, the insulator 216, and the insulator 214. At this time, the insulator 212 and the insulator 283 may be formed using the same material and the same method. By forming the insulator 212 and the insulator 283 using the same material and the same method, the compactability can be improved. For example, silicon nitride is preferably used.

By adopting this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if a substrate is divided into a plurality of chips for each circuit region where the semiconductor element shown in this embodiment mode is formed, impurities such as hydrogen and water are prevented from being mixed in from the side surface direction of the divided substrate and diffusing to the transistor 200.

Further, by adopting this structure, the excessive oxygen in the insulator 280 can be prevented from diffusing to the outside. Accordingly, the excess oxygen in the insulator 280 is efficiently supplied to the channel-forming oxide in the transistor 200. Due to this oxygen, oxygen vacancies of the oxide forming a channel in the transistor 200 can be reduced. Thus, the oxide forming the channel in the transistor 200 can be an oxide semiconductor having a low defect state density and stable characteristics. That is, the reliability can be improved while suppressing variation in the electrical characteristics of the transistor 200.

Note that, in the memory device shown in fig. 33, a planar shape is adopted as the shape of the capacitor 100, but the memory device shown in the present embodiment is not limited thereto. For example, as shown in fig. 34, a cylindrical shape may be used as the shape of the capacitor 100. The structure under the insulator 150 of the memory device shown in fig. 34 is the same as the semiconductor device shown in fig. 33.

The capacitor 100 shown in fig. 34 includes an insulator 150 on the insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in openings formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, a conductor 125, and an insulator 152 on the insulator 145. Here, at least a part of the conductors 115, 145, and 125 are disposed in openings formed in the insulators 150 and 142.

The conductor 115 is used as a lower electrode of the capacitor 100, the conductor 125 is used as an upper electrode of the capacitor 100, and the insulator 145 is used as a dielectric of the capacitor 100. The capacitor 100 has a structure in which the upper electrode and the lower electrode are opposed to each other through a dielectric in the openings of the insulator 150 and the insulator 142 not only on the bottom surface but also on the side surfaces, and thus the capacitance per unit area can be increased. The greater the depth of the opening, the greater the electrostatic capacitance of the capacitor 100. Thus, by increasing the capacitance per unit area of the capacitor 100, miniaturization or high integration of the semiconductor device can be advanced.

As the insulator 152, an insulator that can be used as the insulator 280 can be used. Further, as the insulator 142, an insulator which is used as an etching stop layer when forming an opening of the insulator 150 and which can be used for the insulator 214 is preferably used.

The openings formed in the insulators 150 and 142 may have a square shape, a polygonal shape other than a square shape, a polygonal shape with arc-shaped corners, or a circular shape such as an ellipse in plan view. Here, the area where the opening overlaps with the transistor 200 is preferably large in plan view. By adopting such a structure, the occupied area of the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

The conductor 115 is disposed in contact with openings formed in the insulator 142 and the insulator 150. The top surface of electrical conductor 115 preferably substantially coincides with the top surface of insulator 142. Further, the bottom surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably deposited by an ALD method, a CVD method, or the like, and for example, a conductor usable for the conductor 205 may be used.

Insulator 145 is disposed so as to cover conductor 115 and insulator 142. For example, the insulator 145 is preferably deposited by an ALD method, a CVD method, or the like. As the insulator 145, for example, silicon oxide, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride, or the like is used, and a stacked-layer structure or a single-layer structure may be employed. For example, an insulating film in which zirconia, alumina, and zirconia are sequentially stacked can be used as the insulator 145.

In addition, a material having a high dielectric strength such as silicon oxynitride or a high dielectric constant (high-k) material is preferably used for the insulator 145. Alternatively, a stacked structure of a material having high dielectric strength and a material having high dielectric constant (high-k) may be used.

Note that as a high dielectric constant (high-k) material (a material having a high relative dielectric constant), gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, a nitride containing silicon and hafnium, or the like can be given. By having such a high-k material, the capacitance of the capacitor 100 can be sufficiently ensured even if the insulator 145 is thickened. By thickening the insulator 145, leakage current generated between the conductor 115 and the conductor 125 can be suppressed.

On the other hand, as a material having high dielectric strength, there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, resin, and the like. For example, a silicon nitride (SiN) deposited by PEALD method may be used which is sequentially laminated _x ) Silicon oxide (SiO) deposited by PEALD method _x ) Silicon nitride (SiN) deposited by PEALD method _x ) Is provided. Alternatively, an insulating film in which zirconium oxide, silicon oxide deposited by an ALD method, and zirconium oxide are sequentially stacked may be used. By using such an insulator having high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

The conductor 125 is disposed so as to fill the openings formed in the insulator 142 and the insulator 150. Further, the conductor 125 is electrically connected to the wiring 1005 through the conductor 140 and the conductor 153. The conductor 125 is preferably deposited by an ALD method, a CVD method, or the like, and for example, a conductor usable for the conductor 205 may be used.

Further, the electric conductor 153 is provided on the insulator 154 and is covered with the insulator 156. The conductor 153 may be a conductor usable for the conductor 112, and the insulator 156 may be an insulator usable for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140, and is used as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[ storage device 2]

Fig. 35 shows an example of a semiconductor device (memory device) according to an embodiment of the present invention.

< structural example of memory device >

Fig. 35 is a cross-sectional view of a semiconductor apparatus including the memory device 290. The memory device 290 shown in fig. 35 includes a capacitor device 292 in addition to the transistor 200 shown in fig. 1A to 1D. Fig. 35 is a sectional view of the transistor 200 in the channel length direction.

The capacitor device 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 275 provided in contact with the top surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294 provided on the insulator 275. That is, the capacitive device 292 constitutes a MIM (Metal-Insulator-Metal) capacitor. Further, the conductor 242b which is one of a pair of electrodes included in the capacitor 292 may serve as the other of the source electrode and the drain electrode of the transistor. The dielectric layer included in the capacitor 292 may also serve as a protective layer provided in the transistor, that is, the insulator 271 and the insulator 275. Therefore, a part of the manufacturing process of the transistor can be used for the manufacturing process of the capacitor 292, so that a semiconductor device with high productivity can be obtained. Further, since one of the pair of electrodes included in the capacitor 292, that is, the conductor 242b serves as the other of the source electrode and the drain electrode of the transistor, the area in which the transistor and the capacitor are arranged can be reduced.

As the conductor 294, for example, a material usable for the conductor 242 may be used.

< modified example of memory device >

An example of a semiconductor device including the transistor 200 and the capacitor 292 according to one embodiment of the present invention, which is different from the semiconductor device shown in the above < structural example of a memory device >, will be described below with reference to fig. 36A, 36B, and 37. Note that in the semiconductor device shown in fig. 36A, 36B, and 37, the same reference numerals are given to structures having the same functions as those of the semiconductor device (see fig. 35) shown in the structure example of the memory device and the embodiment described above. In this section, the constituent materials of the transistor 200 and the capacitor device 292 can be those described in detail in the above embodiment mode and < structural example of a memory device >. In addition, although the memory device shown in fig. 35 is used in fig. 36A, 36B, 37, and the like, it is not limited thereto.

Modification example 1 of memory device

An example of a semiconductor device 600 including the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b according to one embodiment of the present invention will be described below with reference to fig. 36A.

Fig. 36A is a cross-sectional view in the channel length direction of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292 b. Here, the capacitor device 292a includes: a conductive body 242a; an insulator 271a on the conductor 242a; an insulator 275 in contact with the top surface of the insulator 271a, the side surface of the insulator 271a, and the side surface of the conductor 242a; and a conductor 294a on insulator 275. In addition, the capacitor device 292b includes: a conductor 242b; an insulator 271b on the conductor 242b; an insulator 275 in contact with the top surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b; and a conductor 294b on insulator 275.

As shown in fig. 36A, the semiconductor device 600 has an axisymmetric structure with the alternate long and short dash lines A3 to A4 serving as symmetry axes. The conductor 242c doubles as one of the source electrode and the drain electrode of the transistor 200a and one of the source electrode and the drain electrode of the transistor 200 b. Further, an insulator 271c is provided on the conductor 242 c. Further, the conductor 240 used as a plug serves to connect the conductor 246 used as a wiring with the transistor 200a and to connect the conductor 246 used as a wiring with the transistor 200 b. By adopting the above-described structure as a connection relationship of the two transistors, the two capacitance devices, the wiring, and the plug, a semiconductor device which can be miniaturized or highly integrated can be provided.

The structures and effects of the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b can be described with reference to the structure example of the semiconductor device shown in fig. 35.

Modification example 2 of memory device

The transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b are shown as structural examples of the semiconductor device in the above, but the semiconductor device shown in the present embodiment is not limited thereto. For example, as shown in fig. 36B, a semiconductor device 600 and a semiconductor device having the same structure as the semiconductor device 600 may be connected by a capacitor portion. In this specification, a semiconductor device including the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b is referred to as a cell. The structures of the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292b can be described with reference to the transistor 200a, the transistor 200b, the capacitor 292a, and the capacitor 292 b.

Fig. 36B is a cross-sectional view of a semiconductor device 600 including a transistor 200a, a transistor 200B, a capacitor 292a, and a capacitor 292B, and a cell having the same structure as the semiconductor device 600 is connected by a capacitor portion.

As shown in fig. 36B, the conductor 294B, which is used as one electrode of the capacitor device 292B included in the semiconductor device 600, doubles as one electrode of the capacitor device included in the semiconductor device 601 having the same structure as the semiconductor device 600. Although not shown, the conductor 294a, which is used as one electrode of the capacitor 292a included in the semiconductor device 600, also serves as one electrode of the capacitor of the semiconductor device adjacent to the left side of the semiconductor device 600, that is, in the A1 direction of fig. 36B. Further, the cell on the right side of the semiconductor device 601, i.e., in the A2 direction of fig. 36B, also has the same structure. In other words, a cell array (may also be referred to as a memory device layer) may be constituted. By adopting the structure of the cell array, the interval between adjacent cells can be reduced, and thus the projected area of the cell array can be reduced, and high integration can be achieved. Further, by arranging the structure of the cell array shown in fig. 36B in a matrix, a matrix-like cell array can be configured.

As described above, by forming the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b in the structure shown in this embodiment mode, the area of a cell can be reduced, and miniaturization or high integration of a semiconductor device including a cell array can be achieved.

The cell arrays may be stacked in addition to being arranged in a planar shape. Fig. 37 shows a cross-sectional view of a structure of a cell array 610 in which n layers are stacked. As shown in fig. 37, by stacking a plurality of cell arrays (cell arrays 610_1 to 610—n), cells can be integrally arranged without increasing the occupied area of the cell arrays. That is, a 3D cell array may be constructed.

Embodiment 4

In this embodiment mode, a memory device using a transistor using an oxide for a semiconductor (hereinafter, referred to as an OS transistor) and a capacitor (hereinafter, referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to fig. 38A, 38B, and 39A to 39H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charge and discharge of the capacitor. The OS memory device has excellent holding characteristics because the off-state current of the OS transistor is extremely low, and thus can be used as a nonvolatile memory.

< structural example of storage device >

Fig. 38A shows an example of the structure of the OS storage device. The memory device 1400 includes peripheral circuitry 1411 and an array 1470 of memory cells. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read out from the memory cell. Note that the wirings described above are wirings connected to memory cells included in the memory cell array 1470, and details thereof are described below. The amplified data signal is output to the outside of the memory device 1400 through the output circuit 1440 as the data signal RDATA. Further, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

The memory device 1400 is externally supplied with a low power supply Voltage (VSS) as a power supply voltage, a high power supply Voltage (VDD) for the peripheral circuit 1411, and a high power supply Voltage (VIL) for the memory cell array 1470. Further, a control signal (CE, WE, RES), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

The control logic circuit 1460 processes a control signal (CE, WE, RES) input from the outside to generate control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RES is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.

The memory cell array 1470 includes a plurality of memory cells MC arranged in rows and columns and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cells MC, the number of memory cells MC included in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cells MC, the number of memory cells MC included in one row, and the like.

In addition, although fig. 38A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, the present embodiment is not limited thereto. For example, as shown in fig. 38B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap with the memory cell array 1470.

Fig. 39A to 39H illustrate a configuration example of a memory cell which can be suitably used for the memory cell MC described above.

[DOSRAM]

Fig. 39A to 39C show circuit configuration examples of memory cells of the DRAM. In this specification and the like, a DRAM using a 1OS transistor 1 capacitor type memory cell is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory ). The memory cell 1471 shown in fig. 39A includes a transistor M1 and a capacitor CA. Further, the transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

A first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to the wiring BIL, a gate of the transistor M1 is connected to the wiring WOL, and a back gate of the transistor M1 is connected to the wiring BGL. A second terminal of the capacitor CA is connected to the wiring LL.

The wiring BIL is used as a bit line, and the wiring WOL is used as a word line. The wiring LL is used as a wiring for applying a prescribed potential to the second terminal of the capacitor CA. In writing and reading data, the wiring LL may be at the ground potential or at the low-level potential. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Here, the storage unit 1471 shown in fig. 39A corresponds to the storage device shown in fig. 35. That is, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor device 292.

Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration thereof may be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is not connected to the wiring BGL but connected to the wiring WOL as in the memory cell 1472 shown in fig. 39B. For example, the memory cell MC may be a memory cell including a transistor having a single gate structure, that is, a transistor M1 including no back gate, such as the memory cell 1473 shown in fig. 39C.

In the case where the semiconductor device described in the above embodiment mode is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. In other words, since the written data can be held by the transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Alternatively, the refresh operation of the memory cell may not be performed. Further, since the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

In addition, in the DOSRAM, when the sense amplifier is provided so as to overlap with the memory cell array 1470, the bit line can be shortened. Thereby, the bit line capacitance is reduced, so that the holding capacitance of the memory cell can be reduced.

[NOSRAM]

Fig. 39D to 39G show circuit configuration examples of gain cell type memory cells of the 2-transistor 1 capacitor. The memory cell 1474 shown in fig. 39D includes a transistor M2, a transistor M3, and a capacitor CB. In addition, the transistor M2 includes a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device including a gain cell type memory cell in which an OS transistor is used for the transistor M2 is sometimes referred to as a norram (Nonvolatile Oxide Semiconductor RAM ).

A first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to a first terminal of the capacitor CB.

The wiring WBL is used as a write bit line, the wiring RBL is used as a read bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a prescribed potential to the second terminal of the capacitor CB. In writing and reading data, it is preferable to apply a high-level potential to the wiring CAL. In addition, when data is held, a low-level potential is preferably applied to the wiring CAL. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

Here, the storage unit 1474 shown in fig. 39D corresponds to the storage device shown in fig. 33 and 34. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

Further, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration thereof may be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is not connected to the wiring BGL but connected to the wiring WOL as in the memory cell 1475 shown in fig. 39E. For example, the memory cell MC may be a memory cell including a transistor having a single gate structure, that is, a transistor M2 including no back gate, such as the memory cell 1476 shown in fig. 39F. For example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL as in the memory cell 1477 shown in fig. 39G.

In the case where the semiconductor device described in the above embodiment mode is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely low. Thus, since the written data can be held by the transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. Alternatively, the refresh operation of the memory cell may not be performed. Further, since the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

The transistor M3 may be a transistor including silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The field effect mobility of Si transistors is sometimes higher than that of OS transistors. Therefore, as the transistor M3 used as the readout transistor, a Si transistor can also be used. In addition, by using a Si transistor for the transistor M3, the transistor M2 can be provided so as to be stacked over the transistor M3, whereby the occupied area of the memory cell can be reduced, and the memory device can be highly integrated.

The transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, a circuit may be formed using only n-type transistors in the memory cell array 1470.

Further, fig. 39H shows an example of a gain cell type memory cell of a 3-transistor 1 capacitor. The memory cell 1478 shown in fig. 39H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is suitably set. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. The wiring GNDL is a wiring that supplies a low-level potential. Further, the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL, not to the wiring BIL.

The transistor M4 is an OS transistor including a back gate electrically connected to the wiring BGL. In addition, the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not include the back gate.

Further, the transistors M5 and M6 may be n-channel type Si transistors or p-channel type Si transistors, respectively. Alternatively, the transistors M4 to M6 may be all OS transistors. In this case, a circuit may be configured using only n-type transistors in the memory cell array 1470.

When the semiconductor device described in the above embodiment mode is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely low.

Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to the above-described structures. Further, the arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, removed, or added as necessary.

As described above, the structure, method, and the like shown in this embodiment can be implemented in appropriate combination with other structures, methods, and the like shown in other embodiments.

Embodiment 5

In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted is described with reference to fig. 40A and 40B. A plurality of circuits (systems) are mounted on the chip 1200. As such, a technology in which a plurality of circuits (systems) are integrated on one Chip is sometimes referred to as a System on Chip (SoC).

As shown in fig. 40A, the chip 1200 includes a CPU1211, a GPU1212, one or more analog computation portions 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

The chip 1200 is provided with bumps (not shown) connected to the first surface of the package substrate 1201 as shown in fig. 40B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, and the bumps 1202 are connected to the motherboard 1203.

Further, a storage device such as a DRAM1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment may be applied to the DRAM1221. Further, for example, the norsram shown in the above embodiment mode may be applied to the flash memory 1222.

The CPU1211 preferably has a plurality of CPU cores. Furthermore, the GPU1212 preferably has multiple GPU cores. Further, the CPU1211 and the GPU1212 may each have a memory that temporarily stores data. Alternatively, a memory commonly used by the CPU1211 and the GPU1212 may be provided on the chip 1200. The above-described norsram or DOSRAM may be applied to the memory. Furthermore, the GPU1212 is suitable for parallel computing of multiple data, which may be used for image processing or product-sum operations. By providing an image processing circuit or a product-sum operation circuit using the oxide semiconductor of the present invention as the GPU1212, image processing and product-sum operation can be performed with low power consumption.

Further, since the CPU1211 and the GPU1212 are provided on the same chip, wiring between the CPU1211 and the GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between memories possessed by the CPU1211 and the GPU1212, and operation result transfer from the GPU1212 to the CPU1211 after operation in the GPU1212 is completed can be performed at high speed.

The analog operation unit 1213 includes one or both of an a/D (analog/digital) conversion circuit and a D/a (digital/analog) conversion circuit. The product-sum operation circuit may be provided in the analog operation unit 1213.

The memory controller 1214 has a circuit used as a controller of the DRAM1221 and a circuit used as an interface of the flash memory 1222.

The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, an image capturing device, a controller, and the like. The controller includes a mouse, a keyboard, a controller for a game machine, and the like. As the interface, USB (Universal Serial Bus: universal serial bus), HDMI (High-Definition Multimedia Interface: high-definition multimedia interface) (registered trademark), or the like can be used.

The network circuit 1216 includes a network circuit such as a LAN (Local Area Network: local area network). In addition, a network security circuit may be provided.

The above-described circuits (systems) may be formed on the chip 1200 through the same manufacturing process. Thus, even if the number of circuits required for the chip 1200 increases, the chip 1200 can be manufactured at low cost without increasing the number of manufacturing steps.

The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU1212, the DRAM1221, and the flash memory 1222 may be referred to as a GPU module 1204.

The GPU module 1204 may reduce its size by having a chip 1200 using SoC technology. Furthermore, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, portable (portable) gaming devices, and the like, due to its high image processing capability. Further, by using a product-sum operation circuit using the GPU1212, a method of Deep Neural Network (DNN), convolutional Neural Network (CNN), recurrent Neural Network (RNN), auto encoder, deep Boltzmann Machine (DBM), deep Belief Network (DBN), or the like may be performed, whereby the chip 1200 may be used as an AI chip, or the GPU module 1204 may be used as an AI system module.

Embodiment 6

The present embodiment shows an example of an electronic component and an electronic device to which the storage device or the like described in the above embodiment is mounted.

< electronic Member >

First, an example of an electronic component in which a storage device 1720 is incorporated will be described with reference to fig. 41A and 41B.

Fig. 41A shows a perspective view of the electronic component 1700 and a substrate (circuit board 1704) on which the electronic component 1700 is mounted. The electronic component 1700 shown in fig. 41A includes a memory device 1720 within a mold 1711. In fig. 41A, a part of the electronic component 1700 is omitted to show the inside thereof. The electronic component 1700 includes a land 1712 on the outside of the mold 1711. The land 1712 is electrically connected to the electrode pad 1713, and the electrode pad 1713 is electrically connected to the memory device 1720 through a lead 1714. The electronic component 1700 is mounted on, for example, a printed circuit board 1702. The circuit board 1704 is completed by combining a plurality of such electronic components and electrically connecting them on the printed circuit board 1702, respectively.

Memory device 1720 includes a driver circuit layer 1721 and a memory circuit layer 1722.

Fig. 41B shows a perspective view of the electronic component 1730. Electronic component 1730 is an example of a SiP (System in package) or MCM (Multi Chip Module: multi-chip module). In the electronic component 1730, a package substrate 1732 (printed circuit board) is provided with a interposer 1731, and the interposer 1731 is provided with a semiconductor device 1735 and a plurality of memory devices 1720.

Electronic component 1730 shows an example in which storage 1720 is used as a high bandwidth memory (HBM: high Bandwidth Memory). Note that an integrated circuit (semiconductor device) such as CPU, GPU, FPGA can be used for the semiconductor device 1735.

The package substrate 1732 may use a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. As the board 1731, a silicon board, a resin board, or the like can be used.

The board 1731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different pitches of terminals. The plurality of wirings are constituted by a single layer or a plurality of layers. Further, the board 1731 has a function of electrically connecting an integrated circuit provided on the board 1731 with an electrode provided on the package substrate 1732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate (rewiring substrate)" or an "intermediate substrate". In addition, a through electrode may be provided in the interposer 1731, and the integrated circuit may be electrically connected to the package substrate 1732 through the through electrode. In addition, in the case of using a silicon interposer, a TSV (Through Silicon Via: through silicon via) may be used as the through electrode.

As the plug 1731, a silicon plug is preferably used. Since the silicon interposer does not need to be provided with active elements, it can be manufactured at lower cost than an integrated circuit. On the other hand, since the wiring formation of the silicon interposer can be performed in the semiconductor process, fine wirings which are difficult to form when using the resin interposer can be easily formed.

In HBM, many wires need to be connected in order to achieve a wide memory bandwidth. For this reason, it is required that fine wiring can be formed at high density on a board on which HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

In an SiP, MCM, or the like using a silicon interposer, degradation in reliability due to differences in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Further, since the surface flatness of the silicon interposer is high, a connection failure is not easily generated between the integrated circuit provided on the silicon interposer and the silicon interposer. Silicon interposer is particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged and disposed across the interposer.

Further, a heat sink (heat radiation plate) may be provided so as to overlap with the electronic component 1730. In the case of providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the board 1731 uniform. For example, in the electronic component 1730 shown in this embodiment, the height of the memory device 1720 is preferably matched with the height of the semiconductor device 1735.

In order to mount the electronic component 1730 on another substrate, the electrode 1733 may be provided at the bottom of the package substrate 1732. Fig. 41B shows an example in which the electrode 1733 is formed with a solder ball. The BGA (Ball Grid Array) can be mounted by providing solder balls in a matrix at the bottom of the package substrate 1732. In addition, the electrode 1733 may also be formed using a conductive needle. By providing conductive pins in a matrix form at the bottom of the package substrate 1732, PGA (Pin Grid Array) mounting can be achieved.

The electronic component 1730 may be mounted on other substrates by various mounting means, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array: staggered pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package: quad Flat package), QFJ (Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) may be employed.

Embodiment 7

In this embodiment, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device according to the above embodiment can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smart phone, an electronic book reader, a digital camera (including a video camera), a video recording/reproducing device, a navigation system, and the like). Note that herein, a computer includes a tablet computer, a notebook computer, a desktop computer, and a mainframe computer such as a server system. Alternatively, the semiconductor device according to the above embodiment is applied to various removable storage devices such as a memory card (e.g., SD card), a USB memory, and an SSD (solid state disk). Fig. 42A to 42E schematically show several structural examples of the removable storage device. For example, the semiconductor device shown in the above embodiment modes is processed into a packaged memory chip and used for various memory devices or removable memories.

Fig. 42A is a schematic diagram of a USB memory. USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device according to the above embodiment mode can be incorporated into a memory chip 1105 or the like.

Fig. 42B is an external schematic view of the SD card, and fig. 42C is a schematic view of the internal structure of the SD card. SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on a substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment modes can be incorporated into the memory chip 1114 or the like.

Fig. 42D is an external schematic view of the SSD, and fig. 42E is a schematic view of the internal structure of the SSD. SSD1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back surface side of the substrate 1153, the capacity of the SSD1150 can be increased. The semiconductor device shown in the above embodiment modes can be incorporated into a memory chip 1154 or the like.

Embodiment 8

The semiconductor device according to one embodiment of the present invention can be applied to a processor, a memory device, or a chip such as a CPU, a GPU, or the like. Fig. 43A to 43H show specific examples of an electronic device having a processor, such as a CPU, GPU, memory device, or chip according to one embodiment of the present invention.

< electronic device and System >

A GPU, a memory device, or a chip according to one embodiment of the present invention may be mounted on a wide variety of electronic devices. Examples of the electronic device include electronic devices having a large screen such as a television set, a display for a desktop or notebook type information terminal, a Digital Signage (Digital Signage), and a large-sized game machine such as a pachinko machine, and examples thereof include a Digital camera, a Digital video camera, a Digital photo frame, an electronic book reader, a mobile phone, a portable game machine, a portable information terminal, and a sound reproducing device. In addition, by providing a GPU, a memory device, or a chip according to one embodiment of the present invention in an electronic device, the electronic device can be provided with artificial intelligence.

The electronic device according to an embodiment of the present invention may include an antenna. By receiving the signal using the antenna, an image, information, or the like can be displayed on the display portion. Further, when the electronic device includes an antenna and a secondary battery, the antenna may be used for noncontact power transmission.

The electronic device according to one embodiment of the present invention may include a sensor (the sensor has a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, smell, or infrared ray).

The electronic device according to one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (still image, moving picture, character image, etc.) on the display section; a function of the touch panel; a function of displaying a calendar, date, time, or the like; executing functions of various software (programs); a function of performing wireless communication; a function of reading out a program or data stored in the storage medium; etc. Fig. 43A to 43H show examples of the electronic apparatus.

[ information terminal ]

Fig. 43A shows a mobile phone (smart phone) which is one of information terminals. The information terminal 5100 includes a housing 5101 and a display portion 5102, and the display portion 5102 includes a touch panel as an input interface and buttons are provided on the housing 5101.

By applying the chip of one embodiment of the present invention to the information terminal 5100, an application program using artificial intelligence can be executed. Examples of the application program using the user include an application program for recognizing a session to display the content of the session on the display portion 5102, an application program for recognizing characters or graphics inputted by the user to a touch panel provided in the display portion 5102 to display the characters or graphics on the display portion 5102, and an application program for performing biometric identification such as fingerprint or voiceprint.

Fig. 43B shows a notebook information terminal 5200. The notebook information terminal 5200 includes an information terminal main body 5201, a display portion 5202, and a keyboard 5203.

As with the information terminal 5100, by applying the chip according to one embodiment of the present invention to the notebook information terminal 5200, an application program using artificial intelligence can be executed. Examples of the application program using artificial intelligence include design support software, article collation software, and menu automatic generation software. In addition, novel artificial intelligence can be developed by using the notebook information terminal 5200.

Note that in the above example, fig. 43A and 43B show a smart phone and a notebook information terminal, respectively, as examples of electronic devices, but information terminals other than the smart phone and the notebook information terminal may be applied. Examples of information terminals other than smart phones and notebook type information terminals include PDAs (Personal Digital Assistant: personal digital assistants), desktop information terminals, and workstations.

[ Game machine ]

Fig. 43C illustrates a portable game machine 5300 as an example of the game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. By attaching the connection portion 5305 provided in the housing 5301 to another housing (not shown), the video output to the display portion 5304 can be output to another video display device (not shown). At this time, the housing 5302 and the housing 5303 can be used as the operation portions, respectively. Thus, a plurality of game players can play a game at the same time. The chips shown in the above embodiments may be embedded in chips or the like provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

In addition, fig. 43D shows a stationary game machine 5400 of one of the game machines. The stationary game machine 5400 is connected to the controller 5402 wirelessly or by wire.

By applying the GPU, the memory device, or the chip according to one embodiment of the present invention to a game machine such as the portable game machine 5300 and the stationary game machine 5400, a low-power-consumption game machine can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

Further, by applying the GPU or the chip according to one embodiment of the present invention to the portable game machine 5300, the portable game machine 5300 provided with artificial intelligence can be realized.

The progress of the game, the language of the creatures occurring in the game, the appearance of phenomena occurring in the game, and the like are originally defined by the program of the game, but by applying artificial intelligence to the portable game machine 5300, it is possible to realize the appearance of the program not limited to the game. For example, the presentation of the content of a game player question, the progress of a game, time, the change in the language of a character appearing on the game, etc. may be achieved.

Further, when a game requiring a plurality of game players is played using the portable game machine 5300, the anthropomorphic game players can be constituted by using artificial intelligence, whereby the artificial intelligence game players can be regarded as opponents, and one person can play a game played by a plurality of persons.

Although fig. 43C and 43D show a portable game machine and a stationary game machine as an example of the game machine, the game machine to which the GPU, the storage device, or the chip of one embodiment of the present invention is applied is not limited to this. Examples of the game machine to which the GPU, the memory device, or the chip according to one embodiment of the present invention is applied include a arcade game machine installed in an amusement facility (a game center, an amusement park, or the like), a ball pitching machine for ball striking practice installed in a sports facility, and the like.

[ mainframe computer ]

The GPU, the storage device, or the chip of one embodiment of the present invention may be applied to a mainframe computer.

Fig. 43E shows a supercomputer 5500 as an example of a mainframe computer. Fig. 43F shows a rack mount (rack mount) computer 5502 included in the super computer 5500.

The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. Note that a plurality of computers 5502 are housed in the chassis 5501. The computer 5502 is provided with a plurality of boards 5504, and GPUs, memory devices, or chips described in the above embodiments can be mounted on the boards.

The supercomputer 5500 is mainly a mainframe computer suitable for scientific computing. Since scientific calculation requires a huge operation at high speed, power consumption is large and heat generation of a chip is high. By applying the GPU, the storage, or the chip of one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby adverse effects on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

In fig. 43E and 43F, a super computer is shown as an example of a mainframe computer, but a mainframe computer to which a GPU, a storage device, or a chip of one embodiment of the present invention is applied is not limited thereto. Examples of a mainframe computer to which the GPU, the storage device, or the chip according to one embodiment of the present invention is applied include a computer (server) that provides a service, a mainframe computer (host), and the like.

[ moving object ]

The GPU, the memory device, or the chip according to one embodiment of the present invention can be applied to an automobile as a moving body and the periphery of a driver's seat of the automobile.

Fig. 43G is a view showing a front windshield surrounding an automobile interior of an example of a mobile body. Fig. 43G shows a display panel 5701 mounted on an instrument panel, a display panel 5702, a display panel 5703, and a display panel 5704 mounted on a pillar.

The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, and settings of an air conditioner. In addition, the user can appropriately change the display contents, layout, and the like displayed on the display panel according to the preference, and the designability can be improved. The display panels 5701 to 5703 can also be used as illumination devices.

By displaying an image captured by an imaging device (not shown) provided in the automobile on the display panel 5704, it is possible to compensate for a field of view (dead angle) blocked by the pillar. That is, by displaying an image captured by an imaging device provided outside the automobile, a dead angle can be compensated for, and safety can be improved. Further, by displaying an image that compensates for the invisible portion, the safety can be confirmed more naturally and more comfortably. The display panel 5704 can also be used as an illumination device.

Because the GPU, memory device or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automotive autopilot system. The chip may also be used in systems for navigation, hazard prediction, etc. In addition, information such as navigation and risk prediction may be displayed on the display panels 5701 to 5704.

Although an automobile is described as an example of the moving body in the above example, the moving body is not limited to an automobile. For example, as a mobile body, an electric car, a monorail, a ship, a flying object (a helicopter, an unmanned plane (unmanned plane), an airplane, a rocket), or the like can be given, and the chip according to one embodiment of the present invention can be applied to the mobile body to provide a system using artificial intelligence.

[ Electrical products ]

Fig. 43H shows an electric refrigerator-freezer 5800 which is an example of an electric product. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

By applying the chip according to one embodiment of the present invention to the electric refrigerator/freezer 5800, the electric refrigerator/freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 can be provided with a function of automatically generating a menu based on food stored in the electric refrigerator-freezer 5800 or a consumption period of the food, and a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food.

The electric refrigerator-freezer is described as an example of the electric appliance, but examples of the other electric appliance include a vacuum cleaner, a microwave oven, an electric rice cooker, a water heater, an IH cooker, a water dispenser, a cooling and heating air conditioner including an air conditioner, a washing machine, a clothes dryer, an audio-visual appliance, and the like.

The electronic device described in this embodiment mode, the function of the electronic device, the application example of artificial intelligence, the effect thereof, and the like can be implemented in appropriate combination with the description of other electronic devices.

Example 1

In this example, an aluminum oxide film was deposited on a silicon oxide film by a sputtering method, and the amount of oxygen released from the silicon oxide film was measured by a TDS (Thermal Desorption Spectrometry: thermal desorption spectroscopy) method.

Samples were manufactured as follows. First, a silicon oxide film is deposited on a silicon wafer by a thermal oxidation method, an aluminum oxide film is deposited on the silicon oxide film by an ALD method, and a silicon oxide film is deposited on the aluminum oxide film by a sputtering method. The film thickness of the silicon oxide film was six kinds of 10nm, 20nm, 30nm, 40nm, 60nm and 100 nm.

Next, an aluminum oxide film having a film thickness of 5nm was deposited on the silicon oxide film by sputtering. Here, different conditions are set at the time of depositing the aluminum oxide film. That is, the RF bias power is 0W/cm ² 、1.24W/cm ² 1.86W/cm ² Three of (3). Table 2 shows the correspondence of the film thickness of the silicon oxide film of samples a-1 to C-6 with the deposition conditions of the aluminum oxide film. 18 samples of samples A-1 through C-6 were produced in the manner described above.

TABLE 2

The alumina film was removed by wet etching after deposition of the alumina film, and the oxygen release amount of the silicon oxide film was measured by TDS method.

Fig. 44 shows a graph in which the oxygen release amounts of samples a-1 to C-6 are plotted. As shown in fig. 44, a trend of increasing the oxygen release amount with increasing the thickness of the silicon oxide film was observed, and it was found that the oxygen release amount was saturated at a certain level of the film thickness. In addition, it is known that: the lower the RF Bias power (Bias in Table 2) at the time of depositing the alumina film, the smaller the oxygen release amount, the RF Bias power was 0W/cm ² The oxygen release amount is less dependent on the thickness of the silicon oxide film and is easily saturated. Thus, by adjusting the deposition conditions of the aluminum oxide film deposited on the silicon oxide, the amount of oxygen injected into the silicon oxide can be controlled. For example, when alumina is used as the insulator 282 in the above embodiment, the amount of oxygen injected into the insulator 280 can be adjusted.

At least a part of the structures, methods, and the like shown in this embodiment can be implemented in appropriate combination with other embodiments and other embodiments described in this specification.

Example 2

In this example, crystallinity of the aluminum oxide film under deposition conditions of the aluminum oxide film was analyzed and examined by using a cross section STEM (Scanning Transmission Electoron Microscopy).

Samples were manufactured as follows. First, a silicon oxide film is deposited on a silicon wafer by a thermal oxidation method, a first aluminum oxide film is deposited on the silicon oxide film by an ALD method, a silicon oxynitride film is deposited on the first aluminum oxide film by a PECVD method, and a second aluminum oxide film is deposited on the silicon oxynitride film by a sputtering method. The deposition conditions of the second aluminum oxide film were as follows: gas conditions (O) ₂ flow/(O) ₂ +Ar) flow) of 50%, RF bias power of 0.31W/cm ² 、0.62W/cm ² 1.24W/cm ² Three of (3). Note that the film thickness of the second aluminum oxide film was unified to 40nm. At an RF bias power of 0.31W/cm ² 、0.62W/cm ² 1.24W/cm ² The samples produced below were sample D, sample E and sample F, respectively. Samples D through F were produced in the manner described above.

The sections of samples D through F were observed using STEM. Fig. 45A and 45B show the observation results. Fig. 45A is a cross-sectional STEM image of samples D through F. Fig. 45B is a diagram of measuring a film thickness having different crystallinity from the cross-sectional STEM image of fig. 45A. In fig. 45B, the vertical axis represents the film thickness [ nm ] of the second aluminum oxide film.

In fig. 45A, the range indicated by the arrow is an amorphous layer. As shown in fig. 45A and 45B, the film thickness of the crystalline layer of sample D was 17.2nm, and the film thickness of the amorphous layer was 17.1nm, each accounting for approximately half of the film thickness of the second aluminum oxide film. In addition, the whole of the sample E becomes an amorphous layer. The film thickness of the crystalline layer of sample F was 16.6nm, the film thickness of the amorphous layer was 9.9nm, and the film thickness of the low-density layer was 9.6nm. As described above, it can be seen that: by reducing the film thickness of the aluminum oxide film, the aluminum oxide film as a whole can be made amorphous irrespective of the RF bias power.

Example 3

In this example, the results of evaluating the hydrogen concentration in the laminated film before and after the heat treatment using an amorphous aluminum oxide film will be described.

[ production of sample ]

Here, two samples of the sample G1 and the sample G2, which were not subjected to the heat treatment, of the produced laminated film were produced.

Fig. 46A shows a stacked structure of the manufactured stacked film. As shown in fig. 46A, layers L1 to L7 are deposited in this order on a substrate (silicon wafer).

As the layer L1, a silicon oxide film deposited by thermally oxidizing the substrate surface is used. As the layer L2, a silicon nitride film deposited by a sputtering method is used. As the layer L3, an In-Ga-Zn oxide film (referred to as a metal oxide film In fig. 46A) deposited by a sputtering method was used. As the layer L4, a stacked film of an aluminum oxide film deposited by an ALD method and a silicon oxynitride film deposited by a CVD method is used as a gate insulating film. As the layer L5, a stacked film of a titanium nitride film and a tungsten film, which are deposited by CVD, respectively, is used as a gate electrode. As the layer L6, an aluminum oxide film deposited by a sputtering method was used. As the layer L7, a silicon nitride film deposited by a sputtering method was used.

Here, an aluminum oxide film used as the layer L6 was deposited in a thickness of 40nm by a sputtering method using an aluminum target. The deposition conditions of the alumina film were as follows: gas conditions (O) ₂ flow/(O) ₂ +Ar) flow) of 50%, RF bias power of 0.62W/cm ² . That is, the sample E integrally formed as an amorphous layer in the above-described embodiment was deposited under the same conditions.

Subsequently, sample G2 was subjected to a heating treatment at 400 ℃ for 8 hours under a nitrogen atmosphere.

In this way, samples G1 and G2 including the laminated film were produced.

[ of Hydrogen concentration ]

The hydrogen concentration in the laminated films of the samples G1 and G2 was evaluated. The hydrogen concentration was measured using secondary ion mass spectrometry (SIMS: secondary Ion Mass Spectrometry).

Fig. 46B shows SIMS analysis results of the samples G1 and G2. In fig. 46B, the horizontal axis represents the depth from the surface, and the vertical axis represents the concentration of hydrogen atoms per unit volume. In fig. 46B, a sample G1 and a sample G2 are indicated by a dotted line and a solid line, respectively. In fig. 46B, the ranges corresponding to the layers L2 to L7 are shown by arrows. Note that in fig. 46B, there is shown a gap between adjacent two arrows, because it is difficult to precisely determine the interface of two films in SIMS analysis.

When the layer L6 was observed, it was confirmed that the hydrogen concentration of the sample G2 was higher than that of the sample G1. On the other hand, when the layers L4 and L3 were focused, it was confirmed that the hydrogen concentration of the sample G2 was lower than that of the sample G1. Further, when the central portion of the layer L5 was focused on, it was confirmed that there was no large difference between the two samples.

As described above, the hydrogen concentration of the layer L4 and the layer L3 decreases due to the increase in the hydrogen concentration of the heat-treated layer L6, and thus it is estimated that the hydrogen in the layer L3 and the layer L4 diffuses into the layer L6 through the layer L5. In addition, no difference in hydrogen concentration was observed in the layer L5, and it was found that the layer L5 exhibited a property that hydrogen was very easily diffused (permeated).

As described above, it can be confirmed that: by stacking a metal oxide film, a gate insulating film, and a gate electrode and disposing an aluminum oxide film and a silicon nitride film deposited by sputtering on top of each other and performing heat treatment, hydrogen in the metal oxide film and the gate insulating film can be effectively reduced. Note that the aluminum oxide film is preferably in an amorphous state. By applying the above manufacturing method to a transistor using a metal oxide film as a semiconductor film for forming a channel, a transistor having both good electrical characteristics and high reliability can be realized.

Example 4

In this example, the layer state and the oxygen release amount of the silicon oxide film in the case of adopting a two-layer structure of different conditions as the aluminum oxide film were examined. The layer state was evaluated by STEM, and the oxygen release amount was evaluated by TDS.

Samples were manufactured as follows. First, a silicon oxide film is deposited on a silicon wafer by a thermal oxidation method, a first aluminum oxide film is deposited on the silicon oxide film by an ALD method, a silicon oxide film is deposited on the first aluminum oxide film by a sputtering method, a second aluminum oxide film is deposited on the silicon oxide film by a sputtering method, and a third aluminum oxide film is deposited on the second aluminum oxide film by a sputtering method.

The deposition conditions for the second aluminum oxide film of sample H were as follows: gas conditions (O) ₂ flow/(O) ₂ +Ar) flow) of 50%, RF bias power of 0W/cm ² And the film thickness was 5nm. In addition, the gas condition (O) ₂ flow/(O) ₂ +Ar) flow) of 50%, RF bias power of 0.31W/cm ² And the film thickness was 35nm.

The deposition conditions for the second aluminum oxide film of sample I were as follows: gas conditions (O) ₂ flow/(O) ₂ +Ar) flow) of 50%, RF bias power of 0W/cm ² And the film thickness was 5nm. In addition, the gas condition (O) ₂ flow/(O) ₂ +Ar) flow) of 50%, RF bias power of 0.62W/cm ² And the film thickness was 35nm.

Sample J is a monolayer of the second aluminum oxide film, and the deposition conditions are as follows: gas conditions (O) ₂ flow/(O) ₂ +Ar) flow) of 50%, RF bias power of 0W/cm ² And the film thickness was 5nm. Samples H through J were produced as above.

Samples H to J were cut, and one of them was observed in section by STEM. The second alumina film and the third alumina film were removed by wet etching (only the second alumina film was removed for sample J), and the oxygen release amount of the silicon oxide film was measured by TDS method.

Fig. 47A is a cross-sectional view using STEM. Fig. 47B is a graph showing the oxygen release amount of the silicon oxide film.

From the cross section STEM of fig. 47A, it was confirmed that when sample H had a laminated structure of the second aluminum oxide film and the third aluminum oxide film and sample I had a laminated structure of the second aluminum oxide film and the third aluminum oxide film, the entire layers of the second and third aluminum oxide films were amorphous.

As shown in fig. 47B, according to the evaluation of the oxygen release amount, in the case where sample H has a laminated structure of the second alumina film and the third alumina film and sample I has a laminated structure of the second alumina film and the third alumina film, the oxygen release amount was 1.1x10 ¹⁵ (moleculer/cm ² ) Up to 1.2X10 ¹⁵ (moleculer/cm ² ) All without great difference. In addition, in the case where sample J has a single-layer structure of the second aluminum oxide film, the oxygen release amount was 9.3X10 ¹⁴ (moleculer/cm ² ) Slightly reduced compared to samples H and I.

As described above, by thinning the second aluminum oxide film to 5nm, the amorphous state of the third aluminum oxide film can be maintained. In addition, even if the deposition conditions of the third aluminum oxide film are changed, the change in the oxygen supply amount is small, and therefore, the control of the oxygen supply amount is preferable because the deposition conditions of the second aluminum oxide film can be controlled.

Example 5

In this example, al addition to the surface of a metal oxide when alumina was formed on the metal oxide was evaluated. Specifically, a sample including a laminate including a metal oxide was produced, and a cross-sectional STEM image was acquired and EDX analysis was performed.

In this example, two samples (sample A1 and sample A2) were produced. The following describes the manufacturing method of the two samples.

As sample A1 and sample A2, a silicon oxide film having a film thickness of 10nm was deposited on a silicon substrate, a metal oxide having a film thickness of 20nm was deposited on the silicon oxide film, and a tantalum nitride film having a film thickness of 20nm was deposited on the metal oxide. Here, as the metal oxide, an oxide target material of In: ga: zn=1:1:1 [ atomic number ratio ] was used for deposition by a sputtering method. Next, the tantalum nitride film was removed by etching, and then washed with dilute hydrofluoric acid and heat treated.

After the heat treatment, as sample A1, an aluminum oxide film having a film thickness of 1nm was deposited on the metal oxide by ALD, and a silicon oxynitride film having a film thickness of 7nm was deposited on the aluminum oxide film. On the other hand, as sample A2, a silicon oxynitride film having a film thickness of 7nm was deposited on the above metal oxide.

Then, the samples A1 and A2 were subjected to a microwave treatment in an oxygen-containing atmosphere.

Samples A1 and A2 were produced in the above manner. Note that the metal oxide is a metal oxide which can be used for the oxide 230b described in embodiment mode 1, and the aluminum oxide film is an insulating film which can be used as an insulating film of the insulator 252 described in embodiment mode 1.

Cross-sectional STEM images were obtained for each of samples A1 and A2, and EDX analysis was performed. Fig. 48A shows a cross-sectional STEM image of sample A1, and fig. 48B and 48C show EDX results of the metal oxide surfaces and the vicinity thereof in samples A1 and A2, respectively. Fig. 48A shows a region surrounded by four corners, in which EDX analysis is performed. Note that EDX analysis at four positions was performed within one field of view, as shown in fig. 48A. In the present embodiment, two fields of view are obtained in the sample A1, and two fields of view are obtained in the sample A2. Accordingly, fig. 48B and 48C show EDX analysis results for eight positions, respectively.

According to fig. 48B and 48C, al was detected on the surface of the metal oxide of the sample A1 and the vicinity thereof. That is, it was found that Al was added to the surface of the metal oxide of the sample A1 and the vicinity thereof. On the other hand, al was not detected in sample A2. Therefore, it is known that Al is added to the surface of the metal oxide and the vicinity thereof by depositing an aluminum oxide film on the metal oxide by the ALD method. Note that it is presumed that the addition of Al to the surface of the metal oxide and the vicinity thereof occurs at the time of depositing the aluminum oxide film or in a process after depositing the aluminum oxide film.

This embodiment can be implemented in appropriate combination with the structures, methods, and the like shown in other embodiments and other embodiments.

Example 6

In this example, the film thickness dependence of alumina on oxygen permeation was evaluated. Specifically, samples (sample B1 to sample B4) including a laminate including alumina, and samples (sample B5 and sample B6) including a laminate not including alumina were manufactured and subjected to SIMS analysis.

First, the method for producing samples B1 to B6 will be described.

Each of the samples B1 to B6 was deposited with a first silicon oxide film (HCl-SiOx) having a film thickness of 100nm on a silicon substrate by a thermal oxidation treatment, and a first silicon oxynitride film (PECVD-SiON) having a film thickness of 100nm was deposited on the first silicon oxide film by a PECVD method. Note that HCl-SiOx is an oxide film formed using hydrogen chloride.

Next, an aluminum oxide film (ALD-AlOx) having a film thickness of 1nm was deposited on the first silicon oxynitride films of the samples B1 and B2 by the ALD method. Further, an aluminum oxide film having a film thickness of 3nm was deposited on the first silicon oxynitride films of the samples B3 and B4 by the ALD method. Next, each of samples B1 to B4 deposited a second silicon oxynitride film having a film thickness of 50nm on the aluminum oxide film by the PECVD method. On the other hand, a second silicon oxynitride film having a film thickness of 50nm was deposited on the above-mentioned first silicon oxynitride films of the samples B5 and B6. That is, the samples B5 and B6 do not include an aluminum oxide film between the first silicon oxynitride film and the second silicon oxynitride film.

Next, each of samples B1 to B6 was deposited on the second silicon oxynitride film by sputtering to a thickness of 50nm including ¹⁸ Second silicon dioxide film of O (SP-SiOx ] ¹⁸ O)). Next, a silicon nitride film having a film thickness of 20nm was deposited on the second silicon oxide film.

Next, the samples B2, B4, and B6 were subjected to heat treatment. The heat treatment was carried out at a temperature of 400℃for 8 hours under a nitrogen atmosphere. Note that the above-described heat treatment was not performed on the sample B1, the sample B3, and the sample B5.

Samples B1 to B6 were produced in the above manner.

SIMS analysis was performed on samples B1 to B6. Note that the analysis direction (Scan direction) of the SIMS analysis is a direction from the substrate side to the silicon nitride film. By performing the SIMS analysis, oxygen of samples B1 to B6 was obtained( ¹⁸ O) distribution.

FIGS. 49A to 49C show the oxygen of each sample ¹⁸ O) distribution results. In FIGS. 49A to 49C, the horizontal axis represents Depth (Depth) in the film thickness direction [ nm ]]The vertical axis represents ¹⁸ O concentration [ ] ¹⁸ O concentration)[atoms/cm ³ ]. Note that the first silicon oxynitride film (PECVD-SiON) is set to ¹⁸ Quantitative range of O (Quantitative range).

The dotted line shown in fig. 49A is the oxygen distribution of the sample B1, and the solid line shown in fig. 49A is the oxygen distribution of the sample B2. In addition, the dotted line shown in fig. 49B is the oxygen distribution of sample B3, and the solid line shown in fig. 49B is the oxygen distribution of sample B4. In addition, the dotted line shown in fig. 49C is the oxygen distribution of sample B5, and the solid line shown in fig. 49C is the oxygen distribution of sample B6.

According to FIG. 49B, samples B3 and B4 ¹⁸ O is distributed over the first silicon oxynitride film and under the first silicon oxynitride film. Therefore, it was found that when the film thickness of the alumina film was 3nm, the film thickness of the second silica film was as follows ¹⁸ O diffuses into the second silicon oxynitride film but does not diffuse into the first silicon oxynitride film. That is, it was found that an alumina film having a film thickness of 3nm was not easily permeable to oxygen.

From FIG. 49A, it is found that when the film thickness of the alumina film is 1nm, the film thickness of the second silica film ¹⁸ O permeates the second silicon oxynitride film and the aluminum oxide film and diffuses into the first silicon oxynitride film. That is, it was found that an alumina film having a film thickness of 1nm was permeable to oxygen. Therefore, when the film thickness of the alumina used for the insulator 252 described in embodiment 1 is 1nm or more and less than 3nm, it was confirmed that oxygen can be supplied to the oxide 230b through the gate insulating film.

Example 7

In this embodiment, layout dependence of electrical characteristics of the transistor is evaluated.

< layout dependence of electric characteristics of transistor 1>

In this section, two samples (a first sample and a second sample) of different structures of the transistor were manufactured and the electrical characteristics of the transistor were measured. Note that a transistor in the first sample is denoted as a transistor 701, and a transistor in the second sample is denoted as a transistor 702.

The transistor 701 and the transistor 702 correspond to the transistor 200 shown in fig. 6A. The design values of the L length and the W length of the transistors 701 and 702 are 60nm and 60nm, respectively.

The deposition conditions of the insulator 282a of the transistor 701 and the transistor 702 are different. Specifically, as the insulator 282a of the transistor 701, aluminum oxide having a film thickness of 5nm is deposited by a sputtering method. The deposition conditions for this alumina were as follows: the temperature was 200℃and the pressure was 0.4Pa, the oxygen flow rate ratio (O ₂ /(O ₂ +Ar)) was 83%, the power was 5kW, and the RF bias power was 1.86W/cm ² . On the other hand, as the insulator 282a of the transistor 702, alumina having a film thickness of 5nm was deposited by a sputtering method. The deposition conditions for this alumina were as follows: the temperature was 200℃and the pressure was 0.4Pa, the oxygen flow rate ratio (O ₂ /(O ₂ +Ar)) was 83%, the power was 5kW, and the RF bias power was 0.31W/cm ² . That is, the RF bias power of transistor 701 and transistor 702 are different when insulator 282a is deposited.

Note that the insulator 282b of the transistor 701 and the transistor 702 are deposited under the same conditions. Specifically, as the insulator 282b of the transistor 701 and the transistor 702, aluminum oxide having a film thickness of 35nm was deposited by a sputtering method. The deposition conditions for this alumina were as follows: the temperature was 200℃and the pressure was 0.4Pa, the oxygen flow rate ratio (O ₂ /(O ₂ +Ar)) was 83%, the power was 5kW, and the RF bias power was 0.62W/cm ² 。

Further, the above two samples each have two TEGs different in layout. Specifically, the number of transistors per unit area (also referred to as transistor density) of the two TEGs included in each of the two samples is different. Fig. 50 shows a top view of the two TEGs, a cross-sectional TEM image of the photographing transistor and its vicinity, and parameters.

The top view shown in fig. 50 shows a Layout (Layout) including 3×3 transistors (3×3 cells). Note that the section TE shown in fig. 50The M image is a cross-sectional view (Cross section in channel length direction) of the channel in the longitudinal direction. The parameter shown in fig. 50 is the transistor density (density) and the pattern density (TGEpattern density). In addition, as shown in FIG. 50, the transistor density of the two TEGs is 2.0 μm ^-2 8.4 μm ^-2 . The pattern density of the two TEGs was 6.6% and 17.6%.

The transistor density will be 2.0 μm ^-2 The TEG of the transistor 701 is designated as TEG711a, and the transistor density is 8.4 μm ^-2 The TEG of the configuration transistor 701 is denoted as TEG711b. In addition, the transistor density is 2.0 μm ^-2 The TEG of the transistor 702 is configured as TEG712a with a transistor density of 8.4 μm ^-2 The TEG of the configuration transistor 702 is denoted as TEG712b.

The Id-Vg characteristics are measured for transistors in TEG711a, TEG711b, TEG712a, and TEG712b.

Fig. 51A and 51B show Id-Vg characteristics of transistors in each TEG. In fig. 51A and 51B, the horizontal axis represents Vg [ V ], and the vertical axis represents Id [ a ]. The dotted line shown in fig. 51A represents the Id-Vg characteristic of the transistor 701 in the TEG711A, and the solid line shown in fig. 51A represents the Id-Vg characteristic of the transistor 701 in the TEG711 b. The dotted line shown in fig. 51B represents the Id-Vg characteristic of the transistor 702 in the TEG712a, and the solid line shown in fig. 51B represents the Id-Vg characteristic of the transistor 702 in the TEG712B.

Fig. 52A and 52B show cumulative probability distributions of threshold voltages (Vth) calculated from Id-Vg characteristics. Here, the threshold voltage (Vth) is defined as the gate voltage at which the drain current becomes 1 pA. In fig. 52A and 52B, vth [ V ] is on the horizontal axis, and cumulative probability (Cumulative probability) [% ] is on the vertical axis. The dotted line shown in fig. 52A represents the cumulative probability distribution of Vth of the transistor 701 in the TEG711a, and the solid line shown in fig. 52A represents the cumulative probability distribution of Vth of the transistor 701 in the TEG711 b. The dotted line shown in fig. 52B represents the cumulative probability distribution of Vth of the transistor 702 in the TEG712a, and the solid line shown in fig. 52B represents the cumulative probability distribution of Vth of the transistor 702 in the TEG712B.

As can be seen from fig. 51 and 52, vth of the transistor 701 in the TEG711b is smaller than that of the transistor 701 in the TEG711 a. In addition, it is known that Vth of the transistor 702 in the TEG712b is smaller than that of the transistor 702 in the TEG712 a.

As described above, the transistor density was found to be 2.0. Mu.m ^-2 Transistor density of 8.4 μm compared to transistors in TEG of (c) ^-2 The transistors in TEG of (c) drift in the negative direction. Therefore, it is found that the increase in the Id-Vg characteristic of a TEG with high transistor density shifts in the negative direction than a TEG with low transistor density. In addition, the rise is independent of RF bias power. This is presumably mainly because the channel formation region of the TEG with high transistor density has a large total area, a large oxygen consumption amount, and the insulator 280 has a small volume.

Further, it is understood that the increase in id—vg characteristics of the transistor 702 shifts to the negative direction as compared with the transistor 701. This indicates that the oxygen supply amount is insufficient, in agreement with the trend shown in fig. 44. Further, it is known that the difference in Vth due to the transistor density hardly changes under the RF bias power condition.

< layout dependence of electrical characteristics of transistors 2>

In this section, three samples (third sample to fifth sample) different in structure of the transistor were manufactured and the electrical characteristics of the transistor were measured. Note that the transistor in the third sample is denoted as a transistor 703, the transistor in the fourth sample is denoted as a transistor 704, and the transistor in the fifth sample is denoted as a transistor 705.

Transistors 703 to 705 correspond to the transistor 200 shown in fig. 6A. The design values of the L length and the W length of the transistors 703 to 705 are 60nm and 60nm, respectively.

As the insulator 252 of the transistor 703 and the transistor 704, aluminum oxide is formed by an ALD method. The deposition conditions for this alumina were as follows: the temperature was 300℃and H was used as the oxidant ₂ O. Note that in the transistor 705, the insulator 252 is not provided.

Further, the thickness of the insulator 252 of the transistor 703 and the transistor 704 is different. Specifically, the film thickness of the insulator 252 of the transistor 703 is 1nm, and the film thickness of the insulator 252 of the transistor 704 is 3nm. Note that the insulator 252 is not provided in the transistor 705, and for convenience of explanation, the film thickness of the insulator 252 of the transistor 705 is set to 0nm.

Further, each of the above three samples has two TEGs different in layout. Specifically, the three samples each have two TEGs with different transistor densities. The parameters of the two TEGs are the same as those shown in fig. 50. Transistor density of two TEGs is 2.0 μm ^-2 8.4 μm ^-2 。

The transistor density will be 2.0 μm ^-2 The TEG configuring the transistor 703 in such a way is denoted as TEG713a, and will be at a transistor density of 8.4 μm ^-2 The TEG configuring the transistor 703 is denoted as TEG713b. In addition, the transistor density is 2.0 μm ^-2 The TEG of the configuration transistor 704 is denoted as TEG714a, which will be at a transistor density of 8.4 μm ^-2 The TEG of the configuration transistor 704 is denoted as TEG714b. In addition, the transistor density is 2.0 μm ^-2 The TEG configuring transistor 705 in this manner will be referred to as TEG715a, with a transistor density of 8.4 μm ^-2 The TEG configuring transistor 705 is denoted as TEG715b.

The Id-Vg characteristics were measured for transistors in TEGs 713a, 713b, 714a, 714b, 715a and 715b.

Fig. 53A to 53C show Id-Vg characteristics of transistors in each TEG. In fig. 53A to 53C, the horizontal axis represents Vg [ V ], and the vertical axis represents Id [ a ]. The dotted line shown in fig. 53A represents the Id-Vg characteristic of the transistor 703 in the TEG713A, and the solid line shown in fig. 53A represents the Id-Vg characteristic of the transistor 703 in the TEG713b. The dotted line shown in fig. 53B represents the Id-Vg characteristic of the transistor 704 in the TEG714a, and the solid line shown in fig. 53B represents the Id-Vg characteristic of the transistor 704 in the TEG714B. The dotted line shown in fig. 53C represents the Id-Vg characteristic of the transistor 705 in the TEG715a, and the solid line shown in fig. 53C represents the Id-Vg characteristic of the transistor 705 in the TEG715b.

Fig. 54A to 54C show cumulative probability distributions of threshold voltages (Vth) calculated from Id-Vg characteristics. In fig. 54A to 54C, the horizontal axis represents Vth [ V ], and the vertical axis represents the cumulative probability (Cumulative probability) [% ]. The dotted line shown in fig. 54A represents the cumulative probability distribution of Vth of the transistor 703 in the TEG713a, and the solid line shown in fig. 54A represents the cumulative probability distribution of Vth of the transistor 703 in the TEG713b. The dotted line shown in fig. 54B represents the cumulative probability distribution of Vth of the transistor 704 in the TEG714a, and the solid line shown in fig. 54B represents the cumulative probability distribution of Vth of the transistor 704 in the TEG714B. The dotted line shown in fig. 54C represents the cumulative probability distribution of Vth of the transistor 705 in the TEG715a, and the solid line shown in fig. 54C represents the cumulative probability distribution of Vth of the transistor 705 in the TEG715b.

As is clear from fig. 54B, vth of the transistor 704 shifts in the negative direction even when the transistor density is low, and the variation in Vth is large. This is presumably because the insulator 252 suppresses diffusion of oxygen in the insulator 280 to the oxide 230b through the insulator 250. That is, it is presumed that the oxygen supply to the oxide 230b is insufficient and the i-type of the channel formation region is insufficient.

From fig. 54A and 54C, it can be assumed that the change in Vth caused by the transistor density of the transistor 703 is smaller than that of the transistor 705. It is presumed that this is because the formation of oxygen vacancies in the metal oxide is suppressed by adding Al to the metal oxide.

Fig. 55A to 55C show the relationship of Vth and Id-Vg characteristics of the transistors. Fig. 55A is a diagram showing a relationship between Vth and on-state current (Ion) of a transistor, fig. 55B is a diagram showing a relationship between Vth and S value of a transistor, and fig. 55C is a diagram showing a relationship between Vth and Linear mobility (Linear mobility) of a transistor. Note that the S value and linear mobility of the transistor are calculated with vd=0.1v.

The triangles shown in fig. 55A to 55C are the results of the transistors 703 in the TEG713a, the quadrangles shown in fig. 55A to 55C are the results of the transistors 703 in the TEG713b, the circles shown in fig. 55A to 55C are the results of the transistors 705 in the TEG715A, and the diamonds shown in fig. 55A to 55C are the results of the transistors 705 in the TEG715 b.

From fig. 55A to 55C, it can be seen whether there is no difference in the relationship between Vth and Id-Vg characteristics of the insulator 252.

< layout dependence of electrical characteristics of transistors 3>

In this section, a sample including a transistor is manufactured and the electrical characteristics of the transistor are measured.

The transistor in this sample corresponds to the transistor 200 shown in fig. 6A.

As the oxide 230b of the transistor, a metal oxide having a film thickness of 15nm was formed by a sputtering method. Note that as the formation of the metal oxide, an oxide target material of In: ga: zn=1:1:1.2 [ atomic number ratio ] was used. Further, as the insulator 252, alumina having a film thickness of 1nm was formed by an ALD method. Further, as the insulator 250, silicon oxide having a film thickness of 4nm was formed by an ALD method.

Note that the above-described samples include transistors having different design values of W length. Specifically, the transistor having a design value of 60nm for the W length (denoted as a transistor 706), the transistor having a design value of 200nm for the W length (denoted as a transistor 707), the transistor having a design value of 360nm for the W length (denoted as a transistor 708), and the transistor having a design value of 960nm for the W length (denoted as a transistor 709) are included. The design value of the L length of the transistors 706 to 709 is 60nm. The structures of the transistors 706 to 709 are the same except for the W length.

In addition, the above-described sample includes two TEGs and a single transistor which are different in layout. Specifically, the transistor densities of the two TEGs are different. More specifically, the transistor density of the two TEGs is 2.0 μm ^-2 8.4 μm ^-2 。

The transistor density will be 2.0 μm ^-2 The TEG configuring transistor 706 is denoted as TEG716a, and will be at a transistor density of 8.4 μm ^-2 The TEG of the configuration transistor 706 is denoted as TEG716b.

Id-Vg characteristics are measured for TEG716a and 716b and for individual transistors 706-709.

Fig. 56A shows the result of the Id-Vg characteristics of the transistor 706 in the TEG716A and the TEG716b. In FIG. 56A, the horizontal axis represents Vg [ V ], and the vertical axis represents Id [ A ]. The dotted line shown in fig. 56A represents the Id-Vg characteristic of the transistor 706 in the TEG716A, and the solid line shown in fig. 56A represents the Id-Vg characteristic of the transistor 706 in the TEG716b.

Fig. 56B shows the cumulative probability distribution of the threshold voltage (Vth) calculated from the Id-Vg characteristics. In fig. 56B, the horizontal axis represents Vth [ V ], and the vertical axis represents the cumulative probability (Cumulative probability) [% ]. The dotted line shown in fig. 56B represents the cumulative probability distribution of Vth of the transistor 706 in TEG716a, and the solid line shown in fig. 56B represents the cumulative probability distribution of Vth of the transistor 706 in TEG716B.

From fig. 56A and 56B, it can be seen that the difference caused by the transistor density is extremely small.

Fig. 57A shows the result of the Id-Vg characteristics of the single transistor 706 to the transistor 709. In FIG. 57A, the horizontal axis represents Vg [ V ], and the vertical axis represents Id [ A ]. The dotted line shown in fig. 57A indicates the Id-Vg characteristic of the transistor 706, the broken line shown in fig. 57A indicates the Id-Vg characteristic of the transistor 707, the dash-dot line shown in fig. 57A indicates the Id-Vg characteristic of the transistor 708, and the solid line shown in fig. 57A indicates the Id-Vg characteristic of the transistor 709.

Fig. 57B shows the cumulative probability distribution of the threshold voltage (Vth) calculated from the Id-Vg characteristics. In fig. 57B, the horizontal axis represents Vth [ V ], and the vertical axis represents cumulative probability (Cumulative probability) [% ]. The dotted line shown in fig. 57B represents the cumulative probability distribution of Vth of the transistor 706, the broken line shown in fig. 57B represents the cumulative probability distribution of Vth of the transistor 707, the dash-dot line shown in fig. 57B represents the cumulative probability distribution of Vth of the transistor 708, and the solid line shown in fig. 57B represents the cumulative probability distribution of Vth of the transistor 709.

According to fig. 57A and 57B, the difference between Vth of the transistor 709 and Vth of the transistor 706 is About 1V (About 1V).

In this section, TEG716b provided with opening region 400 described in embodiment 1 is manufactured. Note that by changing the number of the opening regions 400, the amount of oxygen supplied to the oxide 230b can be adjusted. For example, the larger the number of opening regions 400, the smaller the amount of oxygen supplied to the oxide 230b, and the more likely the Vth of the transistor shifts to the negative direction. In addition, for example, the smaller the number of the opening regions 400, the larger the amount of oxygen supplied to the oxide 230b, and the more easily Vth of the transistor shifts in the positive direction.

The Id-Vg characteristics are measured for transistors included in each of the plurality of TEGs 716b having different numbers of the opening regions 400.

Fig. 58A to 58C show the relationship of Vth and Id-Vg characteristics of the transistor 706 in the TEG716b provided with the opening region 400. Fig. 58A is a diagram showing a relationship between Vth of the transistor 706 and on-state current (Ion), fig. 58B is a diagram showing a relationship between Vth of the transistor 706 and S value, and fig. 58C is a diagram showing a relationship between Vth of the transistor 706 and linear mobility.

According to fig. 58A to 58C, the best electrical characteristics are obtained in the region where Vth of the transistor 706 is about 0.2V. That is, it is known that it is important to control Vth of the transistor to be within this region, and this control can be achieved by adjusting the amount of oxygen supplied to the oxide 230 b. In addition, it is known that it is effective to form the opening region 400 as one of methods of adjusting the amount of oxygen supplied to the oxide 230 b. In addition, according to fig. 58B, it was confirmed that Vth of the transistor 706 has a tendency of deterioration of the S value on both the negative side and the positive side. It is presumed that Vth drifts in the positive direction due to acceptor defects and Vth drifts in the negative direction due to donor defects.

Example 8

In this embodiment, a relationship between the oxidation susceptibility of a metal film and a metal nitride film, the deposition condition dependence of tantalum nitride, the Id-Vg characteristics of a transistor using tantalum nitride, the influence of stress in a metal oxide, the stress dependence of on-state current (Ion) of a transistor, and the ratio of the area of a channel formation region to the area of a source electrode or a drain electrode and on-state current will be described.

< easy Oxidation of Metal film and Metal nitride film >

In this section, the metal film and the metal nitride film were evaluated for their oxidation susceptibility. Specifically, a sample on which a metal film was deposited was subjected to heat treatment, and the metal film before heat treatment and the metal film after heat treatment were subjected to cross-sectional TEM observation. In the same manner, the sample on which the metal nitride film was deposited was subjected to heat treatment, and the metal nitride film before heat treatment and the metal nitride film after heat treatment were subjected to cross-sectional TEM observation.

First, 10 samples (sample C1, sample C2, sample D1, sample D2, sample E1, sample E2, sample F1, sample F2, sample G1, and sample G2) were produced. The following describes a method for manufacturing 10 samples.

All 10 samples were subjected to thermal oxidation treatment on a silicon substrate to form a silicon oxide film having a film thickness of 100nm (here, siO was used as a typical silicon oxide film ₂ To illustrate).

In samples C1 and C2, tungsten films having a film thickness of 20nm were deposited on the silicon oxide films by sputtering. In addition, in the samples D1 and D2, a tantalum film having a film thickness of 20nm was deposited on the silicon oxide film by sputtering. In the samples E1 and E2, a tantalum nitride film having a film thickness of 20nm was deposited on the silicon oxide film by sputtering. In the samples F1 and F2, a titanium film having a film thickness of 20nm was formed on the silicon oxide film by sputtering. In the samples G1 and G2, titanium nitride films having a film thickness of 20nm were deposited on the silicon oxide films by sputtering.

Next, the samples C2, D2, E2, F2, and G2 were subjected to heat treatment. The heat treatment was performed at a temperature of 400℃for 1 hour under an oxygen atmosphere. Note that the above-described heat treatment was not performed on the sample C1, the sample D1, the sample E1, the sample F1, and the sample G1.

10 samples were produced by the above method.

Cross-sectional TEM images were acquired for 10 samples produced.

Fig. 59A1 to 59C2, and 60A1 to 60B2 show acquired cross-sectional TEM images. Note that in fig. 59A1 to 59C2 and fig. 60A1 to 60B2, a carbon film (Ccoating) provided for acquiring a cross-sectional TEM image is observed on the metal film or the metal nitride film.

Fig. 59A1 is a cross-sectional TEM image of the sample C1, and fig. 59A2 is a cross-sectional TEM image of the sample C2. Fig. 59B1 is a cross-sectional TEM image of the sample D1, and fig. 59B2 is a cross-sectional TEM image of the sample D2. Fig. 59C1 is a cross-sectional TEM image of the sample E1, and fig. 59C2 is a cross-sectional TEM image of the sample E2. Fig. 60A1 is a cross-sectional TEM image of the sample F1, and fig. 60A2 is a cross-sectional TEM image of the sample F2. Fig. 60B1 is a cross-sectional TEM image of the sample G1, and fig. 60B2 is a cross-sectional TEM image of the sample G2.

According to FIG. 59A1, the film thickness of the tungsten (W) film before the heat treatment was 22nm.According to fig. 59A2, a part of the tungsten (W) film is oxidized (partially) by the heat treatment. The film thickness of the tungsten (W) film after heat treatment was 2.3nm, and tungsten oxide (WO _x X is a real number greater than 0) film thickness was 51nm.

According to FIG. 59B1, the film thickness of the tantalum (Ta) film before heat treatment was 18nm. According to fig. 59B2, the entire tantalum (Ta) film is oxidized (all oxidized) by the heat treatment. The film thickness of the tantalum (Ta) film after heat treatment was 0nm, and tantalum (TaO) was oxidized _x ) The film thickness of the film was 38.4nm.

According to FIG. 59C1, tantalum nitride (TaN _x ) The film thickness of the film was 19nm. According to FIG. 59C2, tantalum nitride (TaN _x ) A portion of the film is oxidized (partially) by the heat treatment. Tantalum nitride (TaN) _x ) The film thickness of the film was 17nm, and oxidized tantalum nitride (TaO _x N _y Y is a real number greater than 0) film thickness was 3.3nm.

According to FIG. 60A1, the film thickness of the titanium (Ti) film before heat treatment was 16nm. According to fig. 60A2, the entire titanium (Ti) film is oxidized (all oxidized) by the heat treatment. The film thickness of the titanium (Ti) film after heat treatment was 0nm, and oxidized Titanium (TiO) _x ) The film thickness of the film was 31nm.

According to FIG. 60B1, titanium nitride (TiN) _x ) The film thickness of the film was 16nm. According to FIG. 60B2, titanium nitride (TiN _x ) A portion of the film is oxidized (partially) by the heat treatment. Titanium nitride after heat Treatment (TiN) _x ) The film thickness of the film was 8.8nm, and oxidized titanium nitride (TiO _x N _y ) The film thickness of the film was 12nm.

Fig. 61 shows the film thickness of each film before heat treatment and the film thickness of each film after heat treatment of 10 samples produced. In FIG. 61, the vertical axis represents the film Thickness (Thickness) [ nm ] of each film, and the horizontal axis represents each film. Note that the film shown in fig. 61 is a Tungsten (tunesten) film, a Tantalum (Tantalum) film, a Tantalum Nitride (Tantalum nitiride) film, a Titanium (Titanium) film, or a Titanium Nitride (Titanium nitiride) film. The bar graph shown on the left side of each film is the film thickness of each film before heat treatment (As depo.), and the bar graph shown on the right side of each film is the film thickness of each film After heat treatment (After O2 analysis). The bar graph of the diagonal line indicates the film thickness of the metal film (metal) or the metal nitride film, and the white bar graph indicates the film thickness of the oxidized film (Oxide).

From the above, it is clear that the metal nitride films (tantalum nitride film and titanium nitride film) are not easily oxidized, and particularly that the tantalum nitride film is not easily oxidized.

< dependency of tantalum nitride deposition conditions >

Tantalum nitride, which has conductivity, is not stoichiometric and therefore may be oxidized. For example, tantalum nitride having a low nitrogen concentration is considered to be easily oxidized although having high conductivity. In this section, the dependence of the deposition conditions of tantalum nitride will be described.

First, three tantalum nitrides (first to third tantalum nitrides) having different deposition conditions are formed.

The first to third tantalum nitrides are formed at room temperature using a sputtering method and using a Ta-containing target in an atmosphere containing argon and nitrogen. As the same deposition conditions of the first to third tantalum nitrides, N ₂ The flow ratio was set to 25% and the pressure to 0.5Pa.

The first tantalum nitride was a single layer of tantalum nitride deposited with a DC power of 2.0kW and a film thickness of 20 nm. The second tantalum nitride was a single layer of tantalum nitride deposited with a DC power of 0.5kW and a film thickness of 20 nm. The third tantalum nitride was a single layer of tantalum nitride deposited with a DC power of 1.0kW and a film thickness of 20 nm.

The first tantalum nitride is sometimes referred to hereinafter as N-PoortANx. The second tantalum nitride is sometimes referred to as N-rich TaNx-1. In addition, the third tantalum nitride is sometimes referred to as N-rich TaNx-2.

[ composition and resistance value ]

Table 3 shows the Ratio (Ratio) and Resistivity (Resistivity) of three tantalum nitrides with different deposition conditions. Note that the ratio shown in table 3 is a ratio of nitrogen to tantalum (N/Ta), which is calculated by XPS.

TABLE 3

[ sheet resistance ]

Next, a sample containing any one of the first to third tantalum nitrides and a metal oxide was produced, and the sheet resistance of the metal oxide in the depth direction was measured. Fig. 62A shows a stacked structure of a sample used when measuring sheet resistance.

Here, a method for producing the above sample will be described. A quartz substrate was prepared, and a metal oxide having a film thickness of 100nm was formed on the quartz substrate by a sputtering method using an oxide target of In: ga: zn=1:1:1.2 [ atomic ratio ]. The metal oxide is IGZO having a CAAC structure.

Next, the flow ratio of the nitrogen gas to the oxygen gas was set to 4:1, and after heat treatment was performed at 450 ℃ for 1 hour, any one of the first to third tantalum nitrides was formed on the metal oxide. Then, the heating treatment was performed at 300℃for 1 hour under a nitrogen atmosphere.

In the above manner, a sample for measurement of sheet resistance was produced. Here, a sample containing the first tantalum nitride is referred to as a sample 920A, a sample containing the second tantalum nitride is referred to as a sample 920B, and a sample containing the third tantalum nitride is referred to as a sample 920C.

Next, a method for measuring sheet resistance in the depth direction of the metal oxide will be described.

Tantalum nitride of samples 920A through 920C was removed using a dry etching process. Next, a step of measuring the sheet resistance of the metal oxide of each sample is performed (step 1). Next, a step of etching a part of the metal oxide is performed (step 2). Next, a step of measuring the thickness of the residual film of the metal oxide is performed (step 3). After that, until the sheet resistance exceeds the upper limit of measurement of the measurer, i.e. reaches 6×10 ⁶ Repeating steps 1 to 3 until Ω/square.

In the above manner, the sheet resistance in the depth direction of the metal oxide can be measured. Note that even if the metal oxide of around 80nm of the sample 920A is etched, the sheet resistance does not reach the upper measurement limit (measurement limit).

Fig. 62B shows the distribution of sheet resistance in the depth direction of the metal oxide in each sample. In FIG. 62B, the horizontal axis represents the Depth (Depth) of the metal oxide from the surface [ nm ], and the vertical axis represents the sheet resistance of the metal oxide (Sheet Resistance of CAAC-IGZO) [ Ω/square ]. The diamonds shown in fig. 62B represent the distribution of sheet resistance of the sample 920A, the triangles shown in fig. 62B represent the distribution of sheet resistance of the sample 920B, and the circles shown in fig. 62B represent the distribution of sheet resistance of the sample 920C.

From fig. 62, it can be seen that by bonding any of the first to third tantalum nitrides to the metal oxide, the n-type layer diffuses into the metal oxide. In particular, it is known that the n-type layer diffuses the deepest when the metal oxide is bonded to the first tantalum nitride.

< Id-Vg Property 1>

In this section, transistors using the above-described first to third tantalum nitrides were manufactured, and Id-Vg characteristics of the transistors were measured. Note that the transistor manufactured in this section corresponds to the transistor 200 shown in fig. 2B.

Specifically, as the conductor 242 to be used as a source electrode or a drain electrode, any one of the first to third tantalum nitrides is used. Here, a transistor of the first tantalum nitride for the conductor 242 is referred to as a transistor 930A, a transistor of the second tantalum nitride for the conductor 242 is referred to as a transistor 930B, and a transistor of the third tantalum nitride for the conductor 242 is referred to as a transistor 930C.

The Id-Vg characteristics of transistors 930A through 930C are measured. Note that the design values of the L length of the transistor 930A to the transistor 930C, which measure the Id-Vg characteristics, are all 60nm, and the design values of the w length are all 25nm.

Fig. 63A to 63C show Id-Vg characteristics of the transistors 930A to 930C. In fig. 63A to 63C, the horizontal axis represents Vg [ V ], and the vertical axis represents Id [ a ]. Fig. 63A shows the Id-Vg characteristic of the transistor 930A, fig. 63B shows the Id-Vg characteristic of the transistor 930B, and fig. 63C shows the Id-Vg characteristic of the transistor 930C.

In addition, fig. 63D to 63F show cross-sectional TEM images of the transistors 930A to 930C. Note that the design values of the L length of the transistor 930A to the transistor 930C, which take cross-sectional TEM images, are all 60nm, and the design values of the w length are all 60nm.

As can be seen from fig. 63A, when first tantalum nitride (N-pore tanx) is used as the conductor 242, the transistor has normally-on characteristics. The above results are not contradictory to the results of FIG. 62B, i.e., the first tantalum nitride readily diffuses the N-type layer into the metal oxide as compared to the second tantalum nitride (N-rich TaNx-1) and the third tantalum nitride (N-rich TaNx-2).

In addition, ion of a transistor using the first tantalum nitride as the conductor 242 becomes low. This is presumably because the conductor 242 on the oxide 230b shown in fig. 63D is peroxidized (Oxidized TaNx).

When the second tantalum nitride is used as the conductor 242, the transistor has ON/OFF characteristics, but ON-state current is small.

When the third tantalum nitride is used as the conductor 242, the transistor has ON/OFF characteristics and ON-state current is larger than that of the transistor using the second tantalum nitride as the conductor 242.

< Id-Vg Property 2>

In this section, two transistors using the first tantalum nitride were fabricated and the Id-Vg characteristics of the transistors were measured. Note that one of the two transistors manufactured in this section corresponds to the transistor 200 shown in fig. 2B, and the other corresponds to the transistor shown in fig. 6B. One of the two transistors manufactured in this section is referred to as a transistor 930D and the other of the two transistors manufactured in this section is referred to as a transistor 930E.

In the transistor 930D, first tantalum nitride is used as the conductive body 242 serving as a source electrode or a drain electrode. The film thickness of the conductor 242 was 20nm.

In the transistor 930E, a second tantalum nitride is used as the conductor 242a1 and the conductor 242b1, and a first tantalum nitride is used as the conductor 242a2 and the conductor 242b 2. In other words, a second tantalum nitride (Inserted N-rich layer) is interposed between the metal oxide and the first tantalum nitride. Note that the film thicknesses of the conductor 242a1 and the conductor 242b1 are 1nm, and the film thicknesses of the conductor 242a2 and the conductor 242b2 are 19nm. Fig. 64C shows a schematic cross-sectional view of the transistor 930E.

Fig. 64A and 64B show Id-Vg characteristics of the transistor 930D and the transistor 930E. In fig. 64A and 64B, the horizontal axis represents Vg [ V ], and the vertical axis represents Id [ a ]. Fig. 64A shows the Id-Vg characteristic of the transistor 930D, and fig. 64B shows the Id-Vg characteristic of the transistor 930E.

As shown in fig. 64B, even if the first tantalum nitride (N-pore TaNx) is used as the upper layer (the conductors 242a2 and 242B 2) of the conductor 242, the second tantalum nitride (N-rich TaNx) of 1nm is provided as the lower layer (the conductors 242a1 and 242B 1) of the conductor 242, whereby the negative drift can be suppressed.

From the above, it is found that the interface between the metal oxide and the tantalum nitride has a large influence on the characteristics of the transistor.

< influence of stress in Metal oxide >

In the manufacturing process of a transistor, stress may affect the manufacturing process and the electrical characteristics of the transistor. In this section, the effect of stress in the metal oxide is described.

Table 4 shows the film compressive stress (Compressive stress) of the above metal oxide having a CAAC structure (denoted as CAAC-IGZO) containing the third tantalum nitride (denoted as N-rich TaNx-2).

TABLE 4

Film and method for producing the same	Compressive stress
		CAAC-IGZO	487MPa
N-rich TaNx-2	2,403MPa

As shown in table 4, the compression stress of the third tantalum nitride was higher than that of the metal oxide having the CAAC structure. Therefore, when the third tantalum nitride is formed on the metal oxide, the metal oxide is subjected to stress in a direction in which the metal oxide under the third tantalum nitride expands, and there is a possibility that the stress distorts the metal oxide.

As described in embodiment 1, it is presumed that oxygen vacancies are easily generated in the metal oxide due to the distortion. A large number of oxygen vacancies are formed under the third tantalum nitride and a donor is formed when hydrogen enters the oxygen vacancies.

From the above, it is presumed that when the third tantalum nitride is used for the conductor 242 of the transistor according to one embodiment of the present invention, a stable n-type region is formed in the vicinity of the conductor 242 by the metal oxide. Thus, ion of the transistor can be improved.

Note that, as the conductor to be applied to the conductor 242, the third tantalum nitride is shown, and it is preferable to use a conductor having a compressive stress larger than that of a metal oxide for the conductor 242.

< stress dependence of Ion of transistor >

In this section, the stress dependence of Ion of the transistor is described. Specifically, a transistor using conductors having different stresses for the source electrode and the drain electrode was manufactured, and the Id-Vg characteristics of the transistor were measured.

Four conductors (first to fourth conductors) having different stresses are formed by changing the deposition conditions and the laminated structure. Hereinafter, the first conductor, the second conductor, the third conductor, and the fourth conductor are sometimes referred to as Split1, split2, split3, and Split4, respectively.

The first conductor was composed of a Single layer (Single layer) of third tantalum nitride having a film thickness of 20 nm.

The second conductor is composed of a laminated structure of a third tantalum nitride having a film thickness of 5nm and a second tantalum nitride having a film thickness of 15 nm.

The third conductor is formed of a stacked structure of a third tantalum nitride having a film thickness of 5nm and a tantalum nitride having a film thickness of 15 nm. Note that tantalum nitride with a film thickness of 15nm was deposited under the following conditions: n (N) ₂ The flow ratio was 25%, the DC power was 1.0kW, and the pressure was 1.2Pa. The other deposition conditions were the same as those of the third tantalum nitride.

The fourth conductor is formed of a stacked structure of a third tantalum nitride having a film thickness of 5nm and titanium nitride having a film thickness of 15 nm. Note that titanium nitride was deposited by setting the substrate temperature to 400 ℃ by the CVD method.

Fig. 65 shows the stress of each of the first to fourth conductors. In FIG. 65, the vertical axis represents Stress (Stress) [ MPa ]. The electrical conductor has a Tensile stress (tension) when the stress is positive, and a Compressive stress (compression) when the pressure is negative.

As shown in fig. 65, the first to third conductors have compressive stress, and the fourth conductor has tensile stress.

Next, a transistor is manufactured using the first to fourth conductors. The transistor manufactured in this section corresponds to the transistor 200 shown in fig. 1B or fig. 6B. The conductor 242 of the transistor 200 is used as a source electrode or a drain electrode.

Hereinafter, a transistor using a first conductor as the conductor 242 is referred to as a transistor 950A, a transistor using a second conductor as the conductor 242 is referred to as a transistor 950B, a transistor using a third conductor as the conductor 242 is referred to as a transistor 950C, and a transistor using a fourth conductor as the conductor 242 is referred to as a transistor 950D.

Note that in the transistors 950A to 950D, third tantalum nitride is used as a lower layer of the conductor 242 which is in contact with the oxide 230 b. Therefore, it can be assumed that the interface reaction between the oxide 230b and the conductor 242 is not significantly different between the transistors 950A and 950D.

The Id-Vg characteristics of the transistors 950A to 950D are measured and Ion is calculated.

Fig. 66 shows the result of Ion for each transistor. In FIG. 66, the vertical axis represents Ion [ μA ]. Ion shown in fig. 66 was calculated as vg=vsh+2. V, vd =1. V, vbg =0v.

From fig. 66, a trend that Ion increases as the compressive stress of the conductor 242 increases was confirmed. Therefore, it is presumed that the carrier concentration in the oxide 230b in the vicinity of the conductor 242 becomes high.

< relation of area ratio of channel formation region to area of source electrode or drain electrode to on-state current >

Here, the results of investigation of the relationship between the on-state current Ion and the ratio of the area of the channel formation region to the area of the source electrode or the drain electrode will be described.

In this section, four transistors (the transistors 970A to 970D) are manufactured. The channel widths of the four transistors manufactured are different. Specifically, the channel width is designed as follows: the transistor 970A is 45nm, the transistor 970B is 60nm, the transistor 970C is 90nm, and the transistor 970D is 120nm. Note that the channel lengths of the four transistors are all designed to be 60nm. The four transistors have the same structure as the transistor 950A.

The area of the channel formation region is the area of the trench region. The area of the channel formation region is hereinafter referred to as A _Trench And the area of the source electrode or the drain electrode is denoted as A _S/Delectrode 。

The Id-Vg characteristics of the four transistors fabricated were measured. Note that in the measurement of the Id-Vg characteristics, the drain voltage Vd is set to 1.2V. Further, a threshold voltage Vth is calculated from the measured Id-Vg characteristics, and an on-state current Ion is calculated when the top gate voltage is Vth+1.0[ V ].

Fig. 67 shows the relationship between the on-state current and the ratio of the area of the channel formation region to the area of the source electrode or the drain electrode. In FIG. 67, the vertical axis represents the on-state current Ion [ A/μm ] of 1 μm per channel width]The horizontal axis represents the ratio (a) of the area of the channel formation region to the area of the source electrode or the drain electrode _Trench /A _S/Delectrode )。

The plots shown in black circles in fig. 67 are the results of the transistors 970A to 970D. Note that the plot represented by black diamonds in fig. 67 is illustrated with reference to the results of transistors reported by other companies. Specifically, the graph represented by black diamonds shows the result obtained when the drain voltage Vd is assumed to be 0.8V and the shape of the source electrode or the drain electrode is rectangular.

As can be seen from fig. 67, the on-state current Ion is large in all area ratios of the transistor having the same structure as the transistor 950A described above. Thus, it is assumed that by applying the third tantalum nitride to the conductor 242 of the transistor according to one embodiment of the present invention, a stable n-type region is formed in the vicinity of the conductor 242 by the metal oxide, and Ion of the transistor is improved. As described above, as the conductor 242 of the transistor according to one embodiment of the present invention, the third tantalum nitride is preferably used.

This embodiment can be implemented in combination with the structures, methods, and the like shown in other embodiments and other embodiments as appropriate

Example 9

In this example, the influence of the oxygen barrier property of the buffer layer and the presence or absence of the buffer layer on the Id-Vg characteristic will be described.

< oxygen Barrier Property >

In this section, the oxygen barrier property of the buffer layer was evaluated. Specifically, a sample including a buffer layer was manufactured, and SIMS analysis was performed on the sample.

Fig. 68A shows the stacked structure of the sample manufactured in this section.

Here, a method for producing the above sample will be described. A silicon oxide film having a film thickness of 100nm was formed on a silicon substrate (sipafer in fig. 68A) by a thermal oxidation treatment, a first silicon oxynitride film having a film thickness of 100nm was formed on the silicon oxide film by a PECVD method, and a Buffer layer having a film thickness of 10nm was formed on the first silicon oxynitride film. Note that the buffer layer was deposited using an oxide target of In: ga: zn=1:3:4 [ atomic number ratio ] by a sputtering method.

Then, a second silicon oxynitride film having a film thickness of 50nm is formed on the buffer layer by PECVD, and a film thickness of 50nm is deposited on the second silicon oxynitride film by PECVD to form a film comprising ¹⁸ Third silicon oxynitride film of O (in FIG. 68A ¹⁸ O addlayer), a silicon nitride film (not shown in fig. 68A) is deposited on the third silicon oxynitride film by a sputtering method.

Note that SiOx below the buffer layer shown in fig. 68A corresponds to a silicon oxide film and a first silicon oxynitride film. In addition, siOx located above the buffer layer shown in fig. 68A corresponds to the second silicon oxynitride film.

The above sample was divided into two. One of the samples divided into two was subjected to a heating treatment at 400℃for 8 hours under a nitrogen atmosphere. In addition, the other of the samples split into two was not subjected to heat treatment.

SIMS analysis was performed on both samples. Note that the analysis direction of this SIMS analysis is a direction from the substrate side toward the silicon nitride film. Obtaining oxygen from each sample by SIMS analysis ¹⁸ O) distribution.

FIG. 68B shows the oxygen in each sample ¹⁸ O) distribution results. In FIG. 68B, the horizontal axis represents Depth (Depth) in the film thickness direction [ nm]The vertical axis represents ¹⁸ O concentration [ ] ¹⁸ Oconcentration)[atoms/cm ³ ]. The dotted line shown in fig. 68B is the oxygen distribution of the sample (Before analysis) which is not subjected to the heat treatment, and the solid line shown in fig. 68B is the oxygen distribution of the sample (After analysis) which is subjected to the heat treatment.

As is clear from fig. 68B, the diffusion of oxygen was observed on the upper side of the buffer layer by performing the heat treatment, but the oxygen did not diffuse below the buffer layer. This confirms the oxygen barrier property of the buffer layer.

In a manufacturing process of a transistor in which a channel formation region includes a metal oxide, oxygen may be supplied to the channel formation region of the metal oxide from above and/or below in order to suppress an increase in carrier concentration of a channel. When oxygen is supplied from the lower side of the metal oxide, oxygen is supplied in large amounts to the interface of the metal oxide and the source electrode or the drain electrode. Thus, by providing a buffer layer having oxygen barrier properties under the metal oxide, oxygen can be prevented from being mixed into the metal oxide from the lower side.

< influence of the presence of buffer layer on Id-Vg characteristics >

In this section, the influence of the presence or absence of the buffer layer on the Id-Vg characteristics of the transistor is described.

In this section, a transistor including a buffer layer and a transistor not including a buffer layer are prepared. The two transistors correspond to the transistor 200 shown in fig. 1B, using a buffer layer as the oxide 230a. That is, the oxide 230 of the transistor including no buffer layer has a single-layer structure of the oxide 230 b.

As the oxide 230a of the transistor including the buffer layer, a metal oxide having a film thickness of 10nm was formed by a sputtering method. Oxide 230a uses In: ga: zn=1:3:4 [ atomic number ratio]With O as oxide target material ₂ Deposition was carried out at a flow rate of 100% and a temperature of 300 ℃.

In addition, a transistor including a buffer layer and a transistor not including a buffer layer were each formed as a metal oxide having a film thickness of 15nm by a sputtering method as the oxide 230 b. As the oxide 230b, in: ga: zn=1:1:1 [ atomic number ratio]With O as oxide target material ₂ Deposition was carried out at a flow rate of 100% and a temperature of 300 ℃.

The Id-Vg characteristics of the above transistors were measured.

Fig. 69A shows measurement results of Id-Vg characteristics of each transistor. In FIG. 69A, the horizontal axis represents Vgs [ V ] and the vertical axis represents Id [ A ]. The dotted line shown in fig. 69A represents the Id-Vg characteristic of the transistor including no buffer layer, and the solid line shown in fig. 69A represents the Id-Vg characteristic of the transistor including the buffer layer.

According to fig. 69A, ion of a transistor not including a buffer layer is small. On the other hand, the Ion of the transistor including the buffer layer is larger than the Ion of the transistor including no buffer layer. That is, it is known that Ion of the transistor increases by providing the buffer layer.

Fig. 69B shows a schematic view of oxygen supply to a metal oxide. As shown in fig. 69B, by providing the buffer layer, the amount of oxygen supplied to the metal oxide from below is reduced, and by supplying oxygen to the metal oxide from above in a self-aligned manner, good electrical characteristics can be obtained even in a micro transistor.

Example 10

In this example, crystallinity of a metal oxide and electrical characteristics of a transistor including the metal oxide were evaluated.

< crystallinity of Metal oxide >

In this section, the results of evaluating the crystallinity of the metal oxide will be described. Specifically, two metal oxides are prepared, plane TEM observation is performed and a Fast Fourier Transform (FFT) is performed on the observed plane TEM image.

First, two kinds of metal oxides (a first metal oxide and a second metal oxide) for evaluating crystallinity will be described. An oxide target of In: ga: zn=1:1:1 [ atomic number ratio ] is used and the first metal oxide is deposited by a sputtering method. An oxide target of In: ga: zn=1:1:1.2 [ atomic number ratio ] was used and a second metal oxide was deposited by sputtering. Hereinafter, the first metal oxide is sometimes referred to as conv.caac-IGZO and the second metal oxide is referred to as Zn-rich CAAC-IGZO.

Fig. 70A shows a planar TEM image of a first metal oxide, and fig. 70B shows a planar TEM image of a second metal oxide. Fig. 70C shows an FFT image of the first metal oxide, and fig. 70D shows an FFT image of the second metal oxide.

According to fig. 70C and 70D, in the FFT images of the first metal oxide and the second metal oxide, analysis spots derived from CAAC were confirmed on the ab plane. In addition, as shown in fig. 70D, in the FFT image of the second metal oxide, analysis spots derived from CAAC were clearly confirmed on the ab plane.

< electric Properties of Metal oxide-containing transistor >

In this section, the results of evaluating the electrical characteristics of a transistor including a metal oxide will be described. Specifically, a transistor including the above-described second metal oxide in a channel formation region was manufactured, and Id-Vg characteristics of the transistor were measured.

The design value of the L length of the transistor is 60nm, and the design value of the W length is 60nm.

The Id-Vg characteristics of the above transistors were measured at Vds of 1.2V. Note that the back gate voltage (Vbg) when the Id-Vg characteristic is measured is set to-6V, -4V, -2V, 0V, 2V, 4V, or 6V.

Fig. 71 shows the Id-Vg characteristics of the transistor. In FIG. 71, the horizontal axis represents Vg [ V ], and the vertical axis represents Id [ A ]. Note that fig. 71 shows a Detection limit (Detection limit) of Id in a chain line.

According to fig. 71, the ratio of on-state current to off-state current (I _on /I _off ) Is 10 ⁸ The above.

Further, the Id-Vg characteristics of the above-described transistor were measured at Vds of 1.2V and Vbg of 0V. Note that the temperature at the time of measuring Id-Vg characteristics was set to-40 ℃, 27 ℃, or 85 ℃.

Fig. 72 shows the Id-Vg characteristics of the transistor and the mutual track (gm) curve. In fig. 72, the horizontal axis represents Vg [ a ], the first vertical axis represents Id [ a ], and the second vertical axis represents gm [ μs ]. The dotted line shown in FIG. 72 shows the Id-Vg characteristic at a temperature of-40 ℃, the broken line shown in FIG. 72 shows the Id-Vg characteristic at a temperature of 27 ℃, and the solid line shown in FIG. 72 shows the Id-Vg characteristic at a temperature of 85 ℃. In fig. 72, the lower Detection limit (Id) is indicated by a dash-dot line.

In this transistor, the following results were obtained: vth is-0.11V at Id=1pA, S is 85mV/dec, gm is 5.3. Mu.S.

< non-uniformity in electrical characteristics of transistors >

In this section, TEGs capable of multipoint measurement described in embodiment 2 were manufactured, and the electric characteristics of the transistors were evaluated for unevenness.

In the TEG capable of multipoint measurement, the multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are all configured using CMOS circuits. That is, the peripheral circuits including the multiplexer MUXX, the multiplexer MUXY, the analog switch ASX, and the analog switch ASY are formed using Si transistors.

In addition, as the transistors Tr [1,1] to Tr [ m, n ], the transistor 200 described in embodiment mode 1 is manufactured. That is, the transistors Tr [1,1] to Tr [ m, n ] include a metal oxide in the channel formation region. Specifically, the first gate of the transistor Tr corresponds to the conductor 260 described in embodiment mode 1, the second gate of the transistor Tr corresponds to the conductor 205 described in embodiment mode 1, and the source or drain of the transistor Tr corresponds to the conductor 242a or the conductor 242b or the region 230ba or the region 230bb described in embodiment mode 1.

In addition, m and n are both 128. The channel length was 200nm and the channel width was 60nm, which were design values of the transistors.

A TEG including a transistor including the first metal oxide in a channel formation region is referred to as TEG960A, and a TEG including a transistor including the second metal oxide in a channel formation region is referred to as TEG960B.

Id-Vg characteristics of the transistors of TEG960A and TEG960B are measured, and threshold voltages (Vth), S values, gm, and Ion are calculated from the measured Id-Vg characteristics. Note that Vth is calculated using linear extrapolation.

Fig. 73A and 73B are graphs of Vth measured. Fig. 73A is a graph of Vth of TEG960A, and fig. 73B is a graph of Vth of TEG960B.

Fig. 74A to 74D show histograms of Vth, S values, gm, and Ion. Fig. 74A is a histogram of Vth of 16384 transistors in TEG960A or TEG960B, fig. 74B is a histogram of S values of 16384 transistors in TEG960A or TEG960B, fig. 74C is a histogram of gm of 16384 transistors in TEG960A or TEG960B, and fig. 74D is a histogram of Ion of 16384 transistors in TEG960A or TEG960B. In fig. 74A to 74D, the vertical axis represents Frequency (Frequency).

According to fig. 74a, the center value of Vth of the transistor in TEG960b is 3% higher than that of the transistor in TEG960A, and further has a normally-off characteristic. In addition, according to fig. 74B to 74d, the S value, gm, ion of the transistor in TEG960B are 3%, 9%, 7% better than the transistors in TEG960A, respectively.

Further, the full width at half maximum (FWHM) of Vth of the transistor in TEG960B is 117mV, and the full width at half maximum of Vth of the transistor in TEG960a is 121mV. This result corresponds to the fluctuation of the crystal orientation shown in fig. 70A to 70D.

Example 11

In this example, the transistor described in this embodiment mode was tried, and the electrical characteristics of the transistor were measured. In this embodiment, two transistors (a transistor 800A and a transistor 800B) are tried. As a design value of the transistor to be tested, the channel length of the transistor 800A was 60nm and the channel width was 60nm. The channel length of the transistor 800B is 200nm and the channel width is 60nm.

First, a method for manufacturing the transistor 800A and the transistor 800B is described. Note that the cross-sectional structures of the transistor 800A and the transistor 800B can be referred to fig. 1A to 1D. In addition, for details of the manufacturing method, reference is made to embodiment 1. Further, the transistor 800A has the same structure as the transistor 800B except that the design value of the channel length is different.

As the insulator 212, silicon nitride is used. As the insulator 214, alumina is used. As the insulator 216, silicon oxide is used. Note that the insulator 212, the insulator 214, and the insulator 216 are deposited by a pulsed DC sputtering method.

The conductor 205a is formed using a titanium nitride film. The conductor 205b is formed using a tungsten film. Note that the titanium nitride film and the tungsten film are deposited by a metal CVD method.

As the insulator 222, hafnium oxide deposited by an ALD method is used. As the insulator 224, silicon oxide deposited by a sputtering method is used.

As the oxide 230a, an In-Ga-Zn oxide (also referred to as IGZO) deposited by a DC sputtering method and having a film thickness of 10nm was used. Note that In depositing the oxide 230a, an oxide target of In: ga: zn=1:3:4 [ atomic ratio ] is used.

As the oxide 230b, an In-Ga-Zn oxide deposited by a DC sputtering method and having a film thickness of 15nm was used. Note that In depositing the oxide 230b, an oxide target of In: ga: zn=1:1:1 [ atomic ratio ] is used.

As the conductor 242a and the conductor 242b, a tantalum nitride film having a film thickness of 20nm deposited by a sputtering method was used. Note that, as the conductive films to be the conductors 242a and 242b, a metallic tantalum target is used for deposition under a nitrogen-containing atmosphere.

As the insulator 271a and the insulator 271b, a stacked body of a silicon nitride film and a silicon oxide film over the silicon nitride film is used. Note that as the silicon nitride film and the silicon oxide film, deposition is performed by a sputtering method.

As the insulator 275, a laminate of aluminum oxide deposited by a sputtering method and silicon nitride deposited by an ALD method on the aluminum oxide is used.

As the insulator 280, a silicon oxide film deposited by a sputtering method is used.

As the insulator 252, an aluminum oxide film deposited by an ALD method is used. As the insulator 250, a silicon oxide film deposited by CVD is used. As the insulator 254, a laminate of a hafnium oxide film deposited by an ALD method and a silicon nitride film deposited by an ALD method on the hafnium oxide film is used.

As the conductor 260a, a titanium nitride film deposited by a metal CVD method is used. As the conductor 260b, a tungsten film deposited by a metal CVD method is used.

As the insulator 282, alumina deposited by a sputtering method is used.

As the insulator 283, a stacked body of the first silicon nitride and the second silicon nitride over the first silicon nitride is used. Note that the first silicon nitride is deposited by a sputtering method. In addition, the second silicon nitride is deposited using an ALD method.

As the insulator 274, silicon oxynitride deposited by CVD is used. As the insulator 285, silicon oxide deposited by a sputtering method is used.

The insulator 241a and the insulator 241b are each a laminate of a first insulator and a second insulator. The first insulator is formed using an aluminum oxide film deposited by an ALD method, and the second insulator is formed using a silicon nitride film deposited by an ALD method.

The conductor 240a and the conductor 240b are each formed using a stacked film of a titanium nitride film and a tungsten film over the titanium nitride film. Note that as the titanium nitride film and the tungsten film, a CVD method is used for deposition.

In this manner, the transistor 800A and the transistor 800B are manufactured.

Fig. 75A is a schematic diagram showing the structure of a transistor to be tested. The transistor has the same structure as the transistor 200 shown in the above embodiment mode, and includes a top gate electrode, a gate insulating layer (top gate insulator) on the top gate electrode side, a back gate electrode, a gate insulating layer (also referred to as back gate insulating layer) on the back gate electrode side, an electrode (source/drain electrode) serving as a source or a drain, and the like. In addition, the transistor contains In-Ga-Zn oxide (CAAC-IGZO) having a CAAC structure In a channel formation region. In addition, the back gate insulating layer has a two-layered layer structure of a first layer (back gate insulator 1) and a second layer (back gate insulator 2) on the first layer.

Note that the top gate electrode shown in fig. 75A corresponds to the conductors 260a and 260b, the gate insulating layer on the top gate electrode side corresponds to the insulators 252, 250, and 254, the back gate electrode corresponds to the conductors 205A and 205b, the electrode used as a source or drain (source/drain electrode) corresponds to the conductor 242a or 242b, the first layer (back gate insulator 1) corresponds to the insulator 222, and the second layer (back gate insulator 2) corresponds to the insulator 224.

Fig. 75B is a cross-sectional view of the channel width direction of the transistor 800B in the test. Note that, as described above, the gate insulating layer (back gate insulator) on the back gate electrode side includes the first layer and the second layer having different cross-sectional shapes.

The channel width of the transistor 800B tested was found to be 37nm. Note that although not shown, the actual measurement value of the channel length of the transistor 800B is 247nm. The actual measurement value of the channel width of the transistor 800A was 38nm, and the actual measurement value of the channel length was 92nm.

Next, drain current-top gate voltage characteristics of the transistors (the transistor 800A and the transistor 800B) which were tested were measured.

The drain current-top gate voltage characteristics of the test transistors were measured as follows: the top gate voltage with respect to the source was varied from-2.5V to +2.5V, measured every 50mV, at a temperature of 27 ℃ in the measurement environment. Note that the back gate voltage Vbs with respect to the source when the drain current-top gate voltage characteristic is measured is-6V, -4V, -2V, 0V, 2V, 4V, or 6V. The drain voltage with respect to the source was 0.05V or 2.5V.

Fig. 76A and 76B show drain current-top gate voltage characteristics of the transistor 800A being tested. Fig. 77A and 77B show drain current-top gate voltage characteristics of the transistor 800B to be tested. In fig. 76A to 77B, the horizontal axis represents the top gate voltage Vgs [ V ] with respect to the source, and the vertical axis represents the drain current Id [ a ].

Note that fig. 76A and 77A show measurement results of drain current-top gate voltage characteristics at a drain voltage of 0.05V with respect to the source. Fig. 76B and 77B show measurement results of drain current-top gate voltage characteristics at a drain voltage of 2.5V with respect to the source.

From fig. 76A to 77B, it can be confirmed that the threshold voltage of the transistor being tested varies according to the back gate voltage Vbs with respect to the source.

In this embodiment, an evaluation element (also referred to as TEG) including the transistor 800A is tried. Note that, in the evaluation element, 60000 transistors 800A are connected in parallel.

The capacitance-top gate voltage characteristics of the test TEG are described with reference to fig. 78A to 78D.

Fig. 78A and 78B are diagrams illustrating the capacitance. G shown in fig. 78A and 78B denotes a top gate (also referred to as a first gate), S denotes a source, D denotes a drain, and BG denotes a back gate (also referred to as a second gate).

The capacitance Cgs shown in fig. 78A is the top gate-source capacitance. The capacitance Cgd shown in fig. 78A is the top gate-drain capacitance. In addition, the capacitance Cgb shown in fig. 78B is a top gate-back gate capacitance.

Here, the capacitance Cgc represents a combined capacitance of the capacitance Cgs and the capacitance Cgd. The capacitance Cgg represents the resultant capacitance of the capacitance Cgc and the capacitance Cgb.

The capacitance-top gate voltage characteristics of the TEG tested were measured at 50mV intervals by changing the top gate voltage with respect to the source from-2.5V to +2.5V under conditions of a source voltage and a drain voltage of 0.0V, a measurement frequency of 100kHz, and a temperature of the measurement environment of 27 ℃. Note that when the capacitance-top gate voltage characteristic is measured, the back gate voltage Vbs with respect to the source is set to-6V, -4V, -2V, 0V, 2V, 4V, or 6V.

Fig. 78C and 78D show the capacitance-top gate voltage characteristics of the test TEG. Specifically, fig. 78C shows the capacitance Cgc-top gate voltage Vgs characteristic of the test TEG, and fig. 78D shows the capacitance Cgg-top gate voltage Vgs characteristic of the test TEG.

In fig. 78C and 78D, the horizontal axis represents the top gate voltage Vgs [ V ]. In fig. 78C, the vertical axis represents the capacitance Cgc [ pF ] of the TEG including the transistor 800A. In fig. 78D, the vertical axis represents the capacitance Cgg [ pF ] of the TEG including the transistor 800A. That is, the capacitance-top gate voltage characteristics shown in fig. 78C and 78D can be said to be the capacitance-top gate voltage characteristics of the transistor 800A.

From fig. 78C and 78D, it can be seen that the back gate voltage can control the threshold voltage of the transistor.

[ description of the symbols ]

ASX: analog switch, ASY: analog switch, BGL: wiring, DL: wiring, MUXX: multiplexer, MUXY: multiplexer, PC: peripheral circuits, SL: wiring, TGL: wiring, tr: transistor, TRA: transistor group, WX: wiring, WY: wiring, 100: capacitor, 110: an electrical conductor, 112: electrical conductor, 115: electrical conductor, 120: electrical conductor, 125: conductor, 130: insulator, 140: conductor, 142: insulator, 145: insulator, 150: insulator, 152: insulator, 153: electrical conductor, 154: insulator, 156: insulator, 200: transistor, 200a: transistor, 200b: transistor, 205: conductor, 205a: conductor, 205b: electrical conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 217: insulator, 218: electrical conductor, 222: insulator, 224: insulator, 224A: insulating film, 230: oxide, 230a: oxide, 230A: oxide film, 230a1: oxide, 230a2: oxide, 230b: oxide, 230B: oxide film, 230ba: region, 230bb: region, 230bc: region, 230b1: oxide, 230b2: oxide, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242a1: conductor, 242a2: conductor, 242A: conductive film, 242b: conductor, 242b1: conductor, 242b2: conductor, 242B: conductive layer, 242c: conductor, 243: oxide, 243a: oxide, 243b: oxide, 246: conductor, 246a: conductor, 246b: an electrical conductor, 250: insulator, 250a: insulator, 250A: insulating film, 250b: insulator, 252: insulator, 252A: insulating film, 254: insulator, 254A: insulating film, 260: conductor, 260a: conductor, 260b: electrical conductor, 265: sealing part, 271: insulator, 271a: insulator, 271A: insulating film, 271b: insulator, 271B: insulating layer, 271c: insulator, 274: insulator, 275: insulator, 280: insulator, 282: insulator, 282a: insulator, 282b: insulator, 283: insulator, 285: insulator, 290: memory device, 292: capacity device, 292a: capacity device, 292b: capacity device, 294: conductor, 294a: conductor, 294b: conductor, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: electrical conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: an electrical conductor, 330: an electrical conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 400: open area, 500: semiconductor device, 600: semiconductor device, 601: semiconductor device, 610: cell array, 610—n: cell array, 610_1: cell array, 711a: TEG, 711b: TEG, 712a: TEG, 712b: TEG, 713a: TEG, 713b: TEG, 715a: TEG, 715b: TEG, 800A: transistor, 800B: transistor, 900: TEG, 910: layer, 920: layer, 960A: TEG, 960B: TEG, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring, 1100: USB memory, 1101: housing 1102: cover, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip 1150: SSD, 1151: shell, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate, 1202: bump 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog operation unit 1214: storage controller 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device, 1411: peripheral circuitry, 1420: row circuitry, 1430: column circuitry, 1440: output circuit, 1460: control logic, 1470: memory cell array 1471: memory cell, 1472: storage unit, 1473: storage unit, 1474: storage unit, 1475: storage unit, 1476: storage unit, 1477: storage unit, 1478: storage unit, 1700: electronic component, 1702: printed circuit board 1704: circuit board, 1711: mold, 1712: connection pad, 1713: electrode pads, 1714: lead wire, 1720: storage device, 1721: drive circuit layer, 1722: storage circuit layer, 1730: electronic component 1731: plugboard, 1732: package substrate, 1733: electrode, 1735: semiconductor device, 2700: manufacturing apparatus, 2701: atmospheric side substrate supply chamber 2702: atmospheric side substrate transfer chamber 2703a: load lock chamber 2703b: unloading the latch chamber, 2704: transfer chamber, 2706a: treatment chamber, 2706b: treatment chamber, 2706c: treatment chamber, 2706d: treatment chamber, 2761: cassette, 2762: alignment machine, 2763a: transfer robot, 2763b: transfer robot, 2801: gas supply source, 2802: valve, 2803: high frequency generator, 2804: waveguide, 2805: mode converter, 2806: gas tube, 2807: waveguide, 2808: slot antenna plate, 2809: dielectric plate 2810: high density plasma, 2811: substrate 2811—n: substrate, 2811—n-1: substrate, 2811—n-2: substrate, 2811_1: substrate, 2811_2: substrate, 2811_3: substrate, 2812: substrate holder, 2813: heating mechanism, 2815: matcher 2816: high frequency power supply, 2817: vacuum pump, 2818: valve, 2819: exhaust port, 2820: lamp, 2821: gas supply source, 2822: valve, 2823: gas inlet, 2824: substrate, 2825: substrate holder, 2826: heating mechanism, 2828: vacuum pump 2829: valve, 2830: exhaust port, 2900: microwave processing apparatus, 2901: quartz tube, 2902: substrate holder 2903: heating unit, 5100: information terminal 5101: housing 5102: display unit, 5200: notebook information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game machine, 5301: housing, 5302: housing, 5303: housing, 5304: display unit, 5305: connection part, 5306: operation key, 5400: stationary gaming machine, 5402: controller, 5500: supercomputer, 5501: frame, 5502: computer, 5504: substrate, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5802: refrigerating chamber door, 5803: a freezing chamber door.

Claims

1. A semiconductor device, comprising:

an oxide;

a first conductor, a second conductor, and a first insulator on the oxide;

a second insulator on the first conductor and on the second conductor;

a third insulator on the first insulator;

a third electrical conductor on the third insulator; and

a fourth insulator on the second insulator and on the third conductor,

wherein the fourth insulator is in contact with the top surface of the second insulator and the top surface of the third conductor,

the first insulator has regions respectively contacting the top surface of the oxide, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator,

the oxide comprises indium, gallium, aluminum, and zinc,

the first insulator and the fourth insulator both comprise aluminum and oxygen,

the fourth insulator has an amorphous structure,

the oxide has a concentration gradient in which the concentration of aluminum increases from the bottom surface of the oxide to the top surface of the oxide.

2. The semiconductor device according to claim 1,

wherein the fourth insulator comprises a first laminate,

The first laminate includes a first layer and a second layer on the first layer,

and the first layer has a region with a film thickness of 3.0nm or more and 8.0nm or less.

3. The semiconductor device according to claim 1 or 2,

wherein the first conductor and the second conductor each comprise a second laminate,

the second laminate includes a third layer and a fourth layer on the third layer,

the third layer and the fourth layer both comprise tantalum and nitrogen,

and the third layer has a region having a film thickness of 1.0nm or more and 3.0nm or less.

4. A semiconductor device, comprising:

an oxide;

a first conductor, a second conductor, and a first insulator on the oxide;

a second insulator on the first conductor and on the second conductor;

a third insulator on the first insulator;

a third electrical conductor on the third insulator;

a fourth insulator on the second insulator and on the third conductor; and

a fourth conductor and a fifth insulator under the oxide,

The fourth conductor has a region overlapping the third conductor with the oxide interposed therebetween,

the fifth insulator is located between the fourth conductor and the oxide,

the oxide comprises indium, gallium, aluminum, and zinc,

the first insulator and the fourth insulator both comprise aluminum and oxygen,

the fourth insulator has an amorphous structure,

5. The semiconductor device according to claim 4,

wherein the fourth insulator comprises a first laminate,

6. The semiconductor device according to claim 4 or 5,

the third layer and the fourth layer both comprise tantalum and nitrogen,

7. A semiconductor device, comprising:

an oxide;

a first conductor, a second conductor, and a first insulator on the oxide;

a second insulator on the first conductor and on the second conductor;

a third insulator on the first insulator;

a third electrical conductor on the third insulator; and

a fourth insulator on the second insulator and on the third conductor,

the oxide includes a first metal oxide layer and a second metal oxide layer on the first metal oxide layer,

the first metal oxide layer contains at least one of indium, element Mb, and zinc,

the second metal oxide layer comprises aluminum and at least one of indium, elemental Mb, and zinc,

the element Mb is one or more selected from gallium, yttrium and tin,

the first insulator and the fourth insulator both comprise aluminum and oxygen,

The fourth insulator has an amorphous structure,

8. The semiconductor device according to claim 7,

wherein the fourth insulator comprises a first laminate,

9. The semiconductor device according to claim 7 or 8,

the third layer and the fourth layer both comprise tantalum and nitrogen,