CN117615166A - Network code stream recovery method, system, medium and FPGA chip - Google Patents
Network code stream recovery method, system, medium and FPGA chip Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/231—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion
- H04N21/23106—Content storage operation, e.g. caching movies for short term storage, replicating data over plural servers, prioritizing data for deletion involving caching operations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/242—Synchronization processes, e.g. processing of PCR [Program Clock References]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/25—Management operations performed by the server for facilitating the content distribution or administrating data related to end-users or client devices, e.g. end-user or client device authentication, learning user preferences for recommending movies
- H04N21/266—Channel or content management, e.g. generation and management of keys and entitlement messages in a conditional access system, merging a VOD unicast channel into a multicast channel
- H04N21/2662—Controlling the complexity of the video stream, e.g. by scaling the resolution or bitrate of the video stream based on the client capabilities
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
- H04N21/4331—Caching operations, e.g. of an advertisement for later insertion during playback
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/45—Management operations performed by the client for facilitating the reception of or the interaction with the content or administrating data related to the end-user or to the client device itself, e.g. learning user preferences for recommending movies, resolving scheduling conflicts
- H04N21/462—Content or additional data management, e.g. creating a master electronic program guide from data received from the Internet and a Head-end, controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
- H04N21/4621—Controlling the complexity of the content stream or additional data, e.g. lowering the resolution or bit-rate of the video stream for a mobile client with a small screen
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Abstract
The application relates to a network code stream recovery method, a system, a medium and an FPGA chip, which belong to the technical field of broadcast television, and the method comprises the following steps: receiving TS code stream input by a network interface and synchronizing the code stream; caching the TS code stream according to preset caching time, and acquiring a current caching value; acquiring an original code rate of the TS code stream according to the TS code stream; obtaining a cache difference value according to the current cache value and the initial cache value; determining an adjusting parameter according to the buffer difference value, and adjusting the original code rate of the TS code stream to obtain an output code rate; and reading the TS code stream from the buffer memory according to the output code rate and outputting the TS code stream. The method eliminates the influence caused by various network jitter and PCR deviation, ensures the stable output of code rate, effectively reduces the occurrence of picture blocking, asynchronous audio and video and even incapable decoding caused by partial hardware decoder in the decoding process, and ensures smoother and stable code stream recovery process.
Description
Technical Field
The present application relates to the field of broadcast television technologies, and in particular, to a network code stream recovery method, system, medium, and FPGA chip.
Background
With the rapid development of networks and video coding technologies, the demand for video transmission is increasing. From traditional cable television, satellite television to the internet live broadcast and on demand platform today, video content has become an integral part of people's daily lives. However, with the popularization of high-resolution videos such as high definition, 4K, 8K and the like, and the emergence of emerging applications such as real-time interaction, virtual reality and the like, the requirements on the quality and the real-time performance of video transmission are also increasing. Therefore, how to achieve high quality video transmission has become a focus of industry attention.
In this context, stability of the network transport stream becomes a critical issue. Due to the complexity and instability of the network environment, the transmitted code stream has larger jitter, which seriously affects the performance and user experience of the decoding end. In order to solve this problem, it is common practice to design a buffer at the receiving end, count the average code rate for a certain period of time, and output according to the code rate. The method can alleviate the influence caused by code stream jitter to a certain extent, but simultaneously exposes another problem: PCR accuracy problems.
PCR (Program Clock Reference) is a key parameter in video coding that is used to synchronize the clocks of the encoder and decoder. Due to jitter in network transmission, a certain deviation between the PCR received by the decoding end and the PCR transmitted by the actual encoding end may occur, and this deviation may cause a situation that part of the hardware decoder is stuck or even cannot decode during the decoding process.
Disclosure of Invention
In order to eliminate the influence caused by network jitter and code stream variation and simultaneously reduce the situation that part of hardware decoders are stuck or even cannot be decoded in the decoding process, the application provides a network code stream recovery method, a system, a medium and an FPGA chip.
In a first aspect, the present application provides a network code stream recovery method, which adopts the following technical scheme:
a network code stream recovery method includes:
receiving TS code stream input by a network interface and synchronizing the code stream;
caching the TS code stream according to preset caching time, and acquiring a current caching value;
acquiring an original code rate of the TS code stream according to the TS code stream;
obtaining a cache difference value according to the current cache value and the initial cache value;
determining an adjusting parameter according to the buffer difference value, and adjusting the original code rate of the TS code stream to obtain an output code rate;
and reading the TS code stream from the buffer memory according to the output code rate and outputting the TS code stream.
By adopting the technical scheme, the adjusting parameters are determined according to the cache difference value, the output code rate is adjusted, the recovery of the received code stream is realized based on the code stream cache, the influence caused by various network jitters and PCR deviation is eliminated, the stable output of the code rate is ensured, the situations that part of hardware decoders produce picture jamming, asynchronous audio and video and even incapable of decoding in the decoding process are effectively reduced, and the code stream recovery process is smoother and stable.
Optionally, the step of performing code stream synchronization includes:
according to the synchronization byte 0x47, TS packet synchronization is carried out on the received TS code stream;
and converting the TS code stream from a network clock to a write buffer clock and storing the TS code stream in an asynchronous FIFO buffer area.
By adopting the technical scheme, the function of carrying out packet synchronization on the TS code stream and converting the TS code stream into a TS clock domain is realized, and the asynchronous FIFO buffer area is used for carrying out clock conversion, so that the video playing performance can be improved, the delay and the blocking phenomenon are reduced, and the transmission quality and the reliability are improved.
Optionally, the step of obtaining the original code rate of the TS code stream according to the TS code stream includes:
acquiring a PCR count value carried by each PCR packet in the TS code stream according to a PCR PID and a PCR_flag mark;
acquiring the number of TS packets between every two adjacent PCR packets;
obtaining the time interval of every two adjacent PCR packets according to the PCR count value carried by each PCR packet;
dividing the total bit number of the TS packet number between every two adjacent PCR packets by the time interval of every two adjacent PCR packets to obtain the original code rate of the TS code stream.
By adopting the technical scheme, the original code rate of the TS code stream is accurately calculated according to the PCR count value carried by each PCR packet in the TS code stream, so that errors and uncertainties possibly existing in the traditional method are avoided.
Optionally, the step of determining the initial cache value includes:
and determining an initial buffer value according to the preset buffer time and the original code rate of the TS code stream.
By adopting the technical scheme, the initial buffer value is calculated according to the preset buffer time and the original code rate of the TS code stream, and then the initial buffer value is used as a parameter to be transmitted to a corresponding code block or function so as to carry out subsequent processing and operation.
Optionally, the step of determining the adjustment parameter according to the cache difference value includes:
based on a PID algorithm, respectively calculating a proportional control parameter, an integral control parameter and a differential control parameter according to the cache difference value;
adding the proportional control parameter, the integral control parameter and the differential control parameter to obtain an adjustment parameter;
and adjusting the original code rate of the TS code stream according to the adjustment parameter to obtain an output code rate.
By adopting the technical scheme, the PID algorithm is used for adjusting the original code rate, so that the code stream recovery process is smoother and more stable, and the high-quality recovery of the code stream is ensured.
In a second aspect, the present application provides a network code stream recovery system, which adopts the following technical scheme:
a network code stream recovery system for use in the network code stream recovery method of the first aspect, the system comprising:
the network TS code stream input module is used for receiving TS code streams input by the network interface;
the code stream synchronization module is used for carrying out code stream synchronization on the TS code stream;
the write cache control module is used for configuring preset cache time;
the buffer module is used for buffering the TS code stream according to preset buffer time;
the code rate acquisition module is used for acquiring the original code rate of the TS code stream according to the TS code stream;
the adjusting parameter determining module is used for obtaining the current cache value of the cache module, obtaining a cache difference value according to the current cache value and the initial cache value, and determining an adjusting parameter according to the cache difference value;
the code rate adjusting module is used for adjusting the original code rate of the TS code stream according to the adjusting parameter to obtain an output code rate;
the read cache control module is used for reading the TS code stream from the cache according to the output code rate;
and the ASI output module is used for outputting the TS code stream read in the buffer memory.
By adopting the technical scheme, the recovery of the received code stream is realized based on the code stream buffer, the influence caused by various network jitters and PCR deviation is eliminated, the stable output of the code rate is ensured, and the situations that part of hardware decoders produce picture blocking, audio and video are asynchronous and even cannot be decoded in the decoding process are effectively reduced.
Optionally, the buffer module adopts a DDR buffer.
Through adopting above-mentioned technical scheme, DDR register is a computer memory module, has adopted DDR technique, can make the memory module carry out data transmission twice in the same clock cycle to improve the transmission speed of memory. DDR buffer is generally used in personal computers, servers and other devices requiring high-speed memory, and is mainly characterized by high transmission rate, low delay and low power consumption, and the performance of the computer can be improved by improving the memory bandwidth, so that a processor can access data more quickly, and the calculation speed is increased.
Optionally, the adjustment parameter determining module adopts a PID controller.
By adopting the technical scheme, the PID controller is a closed-loop control algorithm widely applied to an industrial control system, is totally called as a proportional-integral-derivative controller, and adjusts the output of the controller according to the proportional, integral and derivative values of the deviation value respectively, so that the controlled object is accurately controlled.
In a third aspect, the present application provides a computer readable storage medium, which adopts the following technical scheme:
a computer readable storage medium storing a computer program capable of being loaded by a processor and executing any one of the methods of the first aspect.
In a fourth aspect, the present application provides a computer device, which adopts the following technical scheme:
an FPGA chip comprising the network code stream restoration system of the second aspect.
By adopting the technical scheme, the method for adjusting the code rate based on the code stream buffer memory is realized by adopting FPGA hardware, fully utilizes the flexibility and the programmability of an FPGA platform, and effectively reduces the code stream jitter and the PCR precision problem in network transmission.
In summary, the present application includes the following beneficial technical effects: the method has the advantages that the adjustment parameters are determined according to the buffer difference value, the output code rate is adjusted, the recovery of the received code stream is realized based on the code stream buffer, the influence caused by various network jitter and PCR deviation is eliminated, the stable output of the code rate is ensured, the situations that a part of hardware decoders produce picture jamming, asynchronous audio and video and even cannot be decoded in the decoding process are effectively reduced, and the code stream recovery process is smoother and stable.
Drawings
Fig. 1 is a first flow chart of a network code stream recovery method according to an embodiment of the present application.
Fig. 2 is a second flow chart of a network code stream recovery method according to an embodiment of the present application.
Fig. 3 is a third flow chart of a network code stream recovery method according to an embodiment of the present application.
Fig. 4 is a fourth flowchart of a network code stream recovery method according to an embodiment of the present application.
Fig. 5 is a block diagram of a network code stream recovery system according to one embodiment of the present application.
Fig. 6 is a test block diagram of the network code stream recovery system in practical application.
Reference numerals illustrate: 101. a network TS code stream input module; 102. a code stream synchronization module; 103. a write cache control module; 104. a cache module; 105. a code rate acquisition module; 106. an adjustment parameter determination module; 107. a code rate adjusting module; 108. a read cache control module; 109. and an ASI output module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to fig. 1 to 6 and the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The embodiment of the application discloses a network code stream recovery method.
Referring to fig. 1, a network code stream recovery method includes:
step S101, receiving TS code stream input by a network interface and synchronizing the code stream;
the code stream synchronization means that TS packets of TS code streams input by a network interface are synchronized, and the input code streams are converted from a network clock to a write buffer clock through an asynchronous FIFO, so that the received TS code streams are ensured to be consistent with the local buffer clock, the video playing performance is improved, and the delay and the blocking phenomenon are reduced.
Step S102, caching TS code stream according to preset caching time, and obtaining a current caching value;
the method comprises the steps that in order to adapt to different network environments and video content changes, preset caching time is preset and adjusted according to network environment conditions, and the preset caching time is the data of how many data frames need to be cached; the current buffer value is the data amount or the data packet number stored in the buffer in the preset buffer time.
It will be appreciated that when new TS code stream data arrives, it is written into the buffer of the FPGA chip, and when the buffer is full, the earliest data frame is removed from the buffer to make room for new data frames to be written.
Step S103, according to the TS code stream, the original code rate of the TS code stream is obtained;
the original code rate of the TS code stream refers to data flow used by the video file in unit time, and is also called code flow rate or sampling rate;
step S104, obtaining a cache difference value according to the current cache value and the initial cache value;
performing difference calculation on the current cache value and the initial cache value to obtain a cache difference value; the initial buffer value can be calculated according to the preset buffer time and the original code rate of the TS code stream;
in some embodiments, the step of determining the initial cache value comprises: and determining an initial buffer value according to the preset buffer time and the original code rate of the TS code stream.
Specifically, the initial buffer value= (original code rate × buffer time)/8;
the unit of the original code rate is bits per second (bps), the unit of the buffer time is seconds(s), and 8 is 8 bits.
It should be noted that, the preset buffering time can be flexibly adjusted according to the actual requirement, so as to adjust the initial buffering value, so as to adapt to different network environments and video content changes. And calculating to obtain an initial buffer value according to the preset buffer time and the original code rate of the TS code stream, and transmitting the initial buffer value as a parameter to a corresponding code block or function so as to carry out subsequent processing and operation.
It will be appreciated that the calculation of the cache difference may help the system to better adapt to different network environments and transmission conditions. For example, in the case of a large change in network bandwidth, the adjustment parameters of the code rate can be quickly adjusted by calculating the buffer difference value, so as to maintain a constant output code rate.
In addition, the buffer difference value can be used for detecting and correcting errors and jitter in the system, so that the robustness and reliability of the system are improved.
Step S105, determining an adjusting parameter according to the buffer difference value, and adjusting the original code rate of the TS code stream to obtain an output code rate;
and determining an adjusting parameter to be adjusted according to the buffer difference by using a PID algorithm, and adjusting to obtain an output code rate value according to the adjusting parameter, wherein the output code rate value is used for guiding the subsequent code stream recovery operation so as to adapt to different network environments and transmission conditions.
And step S106, reading the TS code stream from the buffer memory according to the output code rate and outputting the TS code stream.
The read TS code stream data is output to the target equipment or the display screen through an ASI interface, so that the functions of video playing or monitoring and the like can be realized.
In the embodiment, the PID algorithm is utilized to adjust the output code rate, the recovery of the received code stream is realized based on the code stream buffer, the influence caused by various network jitters and PCR deviation is eliminated, the stable output of the code rate is ensured, the situations that a part of hardware decoders produce picture jamming, asynchronous audio and video and even incapable of decoding in the decoding process are effectively reduced, and the code stream recovery process is smoother and more stable.
Referring to fig. 2, as an embodiment of step S101, the step of performing the code stream synchronization includes:
step S201, TS packet synchronization is carried out on a received TS code stream according to the synchronization byte 0x 47;
the sync byte 0x47 is a sync byte specified in DVB TS, and is used to detect whether the code stream is synchronized, and as a special byte sequence, the sync byte 0x47 is used to identify the start position of the TS packet.
It will be appreciated that by scanning each TS packet in the TS stream, this particular byte sequence can be detected, thereby determining the start position of each TS packet to achieve synchronization of the TS packets.
Step S202, converting TS code stream from network clock to write buffer clock, and storing into asynchronous FIFO buffer.
The clock domain is converted through the asynchronous FIFO (First In First Out) buffer area, so that the subsequent write cache operation is convenient.
In the above embodiment, the function of packet synchronization and conversion of the TS code stream into the TS clock domain is realized, and the clock conversion is performed by using the asynchronous FIFO buffer area, so that the video playing performance can be improved, the delay and the blocking phenomenon are reduced, and the transmission quality and the reliability are improved.
Referring to fig. 3, as an embodiment of step S103, the step of obtaining the original code rate of the TS code stream from the TS code stream includes:
step S301, according to the PCR PID and the PCR_flag mark, obtaining a PCR count value carried by each PCR packet in the TS code stream;
in the TS code stream, each data packet comprises a PID for identifying the content of the data packet, and the PCR PID is used for distinguishing the data packet containing the PCR information; the pcr_flag flag is located at the header of the data packet and indicates whether the current data packet contains PCR information.
Step S302, acquiring the number of TS packets between every two adjacent PCR packets;
counting the number of TS packets between every two PCR packets, starting counting when the PCR packets are found, accumulating 1 by one TS packet, stopping the current counting and starting the next round of counting until the next PCR packet is found, wherein the current counting is the number of TS packets.
Step S303, obtaining the time interval of every two adjacent PCR packets according to the PCR count value carried by each PCR packet;
specifically, firstly calculating a counting difference value carried by each two adjacent PCR packets, and then dividing the counting difference value by a 27M system clock to obtain the time interval of the two adjacent PCR packets;
the difference value of each PCR packet relative to the previous PCR packet can be calculated according to the PCR count value carried by each PCR packet, so that the count difference value carried by each two adjacent PCR packets can be obtained;
in addition, a 27M system clock refers to 27 mega system clock cycles per second. In the digital television and digital video fields, the system clock is a time reference for synchronizing and decoding data packets. In the TS (Transport Stream) code stream PCR (Program Clock Reference) is a time stamp for representing the data packet, which is typically updated at a rate of 27M system clock cycles per second.
Specifically, the count difference carried by each two adjacent PCR packets can be converted into a time interval by dividing by a 27M system clock;
step S304, dividing the total bit number of TS packet number between every two adjacent PCR packets by the time interval of every two adjacent PCR packets to obtain the original code rate of TS code stream.
The original code rate can help to know the overall quality of the TS code stream and provide reference data for subsequent processing analysis.
In the embodiment, the original code rate of the TS code stream is accurately calculated according to the PCR count value carried by each PCR packet in the TS code stream, so that errors and uncertainties possibly existing in the traditional method are avoided.
Referring to fig. 4, as an embodiment of step S105, the step of determining the adjustment parameter according to the cache difference value includes:
step S401, based on a PID algorithm, respectively calculating a proportional control parameter, an integral control parameter and a differential control parameter according to the cache difference value;
the buffer difference value is used as an error value to respectively calculate a proportional control parameter, an integral control parameter and a differential control parameter;
specifically, the calculation formula of the proportional control parameter P is: p=kp×e (t) Wherein Kp is the proportional gain, e (t) Buffer the difference (error value);
the calculation formula of the integral control parameter I is as follows: i=ki +.e (t) dt, where Ki is the integral gain, +.e (t) dt is the buffer difference e (t) Is a combination of the integration of (2);
the differential control parameter D is calculated by the formula d=kd_de (t) Dt, where Kd is the differential gain, de (t) Dt is the buffer difference e (t) Is a derivative of (a).
Step S402, adding the proportional control parameter, the integral control parameter and the differential control parameter to obtain an adjustment parameter;
wherein, the adjusting parameter pid=p+i+d, namely the sum of the proportional control parameter, the integral control parameter and the differential control parameter;
step S403, the original code rate of the TS code stream is adjusted according to the adjustment parameters, and the output code rate is obtained.
It should be noted that, because the obtained current buffer value is dynamically adjusted, the buffer difference value is also dynamically adjusted, the adjustment parameters are automatically determined based on the PID algorithm, and the output code rate is continuously adjusted, so that the method can adapt to different network environments and transmission conditions through continuously iterating the above steps.
In the embodiment, the PID algorithm is used for adjusting the original code rate, so that the code stream recovery process is smoother and more stable, and the high-quality recovery of the code stream is ensured.
In addition, the calculation formula of the adjustment parameter corresponds to a position type PID controller, and as a further embodiment, the adjustment parameter may be determined by an incremental type PID controller based on the error of two adjacent controls: specifically, the calculation formula is as follows: deltaU (t) =Kp*（e (t) -e (t-1) ）+Ki*e (t) + Kd*（e (t) -2*e (t-1) +e (t-2) ) Wherein DeltaU (t) To adjust the parameters, kp, ki, kd are proportional gain, integral gain, differential gain, e (t) For caching the difference.
It can be understood that, because the process of buffer reading and outputting the TS code stream is involved, the incremental PID controller can better cope with the problem of control performance degradation caused by buffer delay and other factors, and the incremental PID controller can consider the error of adjacent control twice when calculating the control quantity, so that the incremental PID controller can better adapt to the influence caused by buffer delay.
The embodiment of the application also discloses a network code stream recovery system.
Referring to fig. 5, a network code stream recovery system for executing the above network code stream recovery method, the network code stream recovery system includes:
a network TS code stream input module 101, configured to receive a TS code stream input by a network interface;
the code stream synchronization module 102 is configured to perform code stream synchronization on the TS code stream;
a write cache control module 103, configured to configure a preset cache time;
the buffer module 104 is configured to buffer the TS code stream according to a preset buffer time;
the buffer module 104 may adopt a DDR buffer, which is a memory module of a computer, and adopts DDR technology, so that the memory module can perform data transmission twice in the same clock cycle, thereby improving the transmission speed of the memory. DDR buffer is generally used in personal computers, servers and other devices requiring high-speed memory, and is mainly characterized by high transmission rate, low delay and low power consumption, and the performance of the computer can be improved by improving the memory bandwidth, so that a processor can access data more quickly, and the calculation speed is increased.
The code rate acquisition module 105 is used for acquiring the original code rate of the TS code stream according to the TS code stream;
the adjustment parameter determining module 106 is configured to obtain a current cache value of the cache module 104, obtain a cache difference value according to the current cache value and the initial cache value, and determine an adjustment parameter according to the cache difference value;
wherein, the adjusting parameter determining module 106 may employ a PID controller; the PID controller is a closed-loop control algorithm widely applied to an industrial control system, is totally called as a proportional-integral-derivative controller, and adjusts the output of the controller according to the proportional, integral and derivative values of the deviation value respectively, so that the controlled object is accurately controlled.
The code rate adjusting module 107 is configured to adjust an original code rate of the TS code stream according to the adjustment parameter, to obtain an output code rate;
the read buffer control module 108 is configured to read the TS stream from the buffer according to the output code rate;
the ASI output module 109 is configured to output the TS code stream read in the buffer.
In the embodiment, the PID algorithm is utilized to adjust the output code rate, the recovery of the received code stream is realized based on the code stream buffer, the influence caused by various network jitters and PCR deviation is eliminated, the stable output of the code rate is ensured, the situations that a part of hardware decoders produce picture jamming, asynchronous audio and video and even incapable of decoding in the decoding process are effectively reduced, and the code stream recovery process is smoother and more stable.
The network code stream recovery system of the embodiment of the application can realize any one of the above-mentioned network code stream recovery methods, and the specific working process of each module in the network code stream recovery system can refer to the corresponding process in the above-mentioned method embodiment.
In several embodiments provided herein, it should be understood that the provided methods and systems may be implemented in other ways. For example, the system embodiments described above are merely illustrative; for example, a division of a module is merely a logical function division, and there may be another division manner in actual implementation, for example, multiple modules may be combined or may be integrated into another system, or some features may be omitted or not performed.
The embodiment of the application also discloses a computer readable storage medium.
A computer readable storage medium storing a computer program capable of being loaded by a processor and executing any one of the network code stream restoration methods described above.
Wherein a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device; program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
The embodiment of the application also discloses an FPGA chip.
An FPGA chip comprises the network code stream recovery system.
The network code stream recovery system is realized by adopting FPGA hardware, and the method for adjusting the code rate based on the code stream cache fully utilizes the flexibility and the programmability of an FPGA platform, and effectively reduces the code stream jitter and the PCR precision in network transmission.
Referring to fig. 6, an actual test case of the present application is shown, when the network encoder outputs a code stream to the server, the network code stream recovery system of the present application receives a network code stream from the server, processes the network code stream, and accesses the dektec code stream meter through the ASI interface, and the actual test result is that the output code rate is stable and no PCR error report exists.
Therefore, the method has good effect in practical application, is applied to practical products such as decoders, transmission boards and the like, has good stability through dektec code flow meter test, is low in transformation cost, and is expected to become one of key technologies in the future video transmission field.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing description of the preferred embodiments of the present application is not intended to limit the scope of the application, in which any feature disclosed in this specification (including abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.
Claims (10)
1. The network code stream recovery method is characterized by comprising the following steps:
receiving TS code stream input by a network interface and synchronizing the code stream;
caching the TS code stream according to preset caching time, and acquiring a current caching value;
acquiring an original code rate of the TS code stream according to the TS code stream;
obtaining a cache difference value according to the current cache value and the initial cache value;
determining an adjusting parameter according to the buffer difference value, and adjusting the original code rate of the TS code stream to obtain an output code rate;
and reading the TS code stream from the buffer memory according to the output code rate and outputting the TS code stream.
2. The method for recovering network code stream according to claim 1, wherein said step of performing code stream synchronization comprises:
according to the synchronization byte 0x47, TS packet synchronization is carried out on the received TS code stream;
and converting the TS code stream from a network clock to a write buffer clock and storing the TS code stream in an asynchronous FIFO buffer area.
3. The network code stream restoration method according to claim 1, wherein the step of obtaining the original code rate of the TS code stream from the TS code stream comprises:
acquiring a PCR count value carried by each PCR packet in the TS code stream according to a PCR PID and a PCR_flag mark;
acquiring the number of TS packets between every two adjacent PCR packets;
obtaining the time interval of every two adjacent PCR packets according to the PCR count value carried by each PCR packet;
dividing the total bit number of the TS packet number between every two adjacent PCR packets by the time interval of every two adjacent PCR packets to obtain the original code rate of the TS code stream.
4. A method of recovering a network code stream according to claim 3, wherein the step of determining an initial buffer value comprises:
and determining an initial buffer value according to the preset buffer time and the original code rate of the TS code stream.
5. A method of recovering a network code stream according to any one of claims 1 to 4, wherein the step of determining the adjustment parameter based on the buffered difference value comprises:
based on a PID algorithm, respectively calculating a proportional control parameter, an integral control parameter and a differential control parameter according to the cache difference value;
adding the proportional control parameter, the integral control parameter and the differential control parameter to obtain an adjustment parameter;
and adjusting the original code rate of the TS code stream according to the adjustment parameter to obtain an output code rate.
6. A network code stream restoration system for performing the network code stream restoration method of any one of claims 1 to 5, the system comprising:
the network TS code stream input module (101) is used for receiving TS code streams input by the network interface;
the code stream synchronization module (102) is used for carrying out code stream synchronization on the TS code stream;
a write cache control module (103) for configuring a preset cache time;
the buffer memory module (104) is used for buffering the TS code stream according to preset buffer memory time;
the code rate acquisition module (105) is used for acquiring the original code rate of the TS code stream according to the TS code stream;
the adjusting parameter determining module (106) is used for obtaining the current cache value of the cache module, obtaining a cache difference value according to the current cache value and the initial cache value, and determining an adjusting parameter according to the cache difference value;
the code rate adjusting module (107) is used for adjusting the original code rate of the TS code stream according to the adjusting parameter to obtain an output code rate;
the read cache control module (108) is used for reading the TS code stream from the cache according to the output code rate;
and the ASI output module (109) is used for outputting the TS code stream read in the buffer memory.
7. The network code stream restoration system according to claim 6, wherein the buffer module (104) employs a DDR buffer.
8. The network code stream restoration system according to claim 6, wherein said adjustment parameter determination module (106) employs a PID controller.
9. A computer-readable storage medium, characterized by: a computer program stored which can be loaded by a processor and which performs the method according to any one of claims 1 to 5.
10. An FPGA chip, characterized in that: a network code stream restoration system comprising any of claims 6 to 8.
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