CN117613091A - Structure for improving surface potential of field effect transistor and preparation method - Google Patents

Structure for improving surface potential of field effect transistor and preparation method Download PDF

Info

Publication number
CN117613091A
CN117613091A CN202311605645.3A CN202311605645A CN117613091A CN 117613091 A CN117613091 A CN 117613091A CN 202311605645 A CN202311605645 A CN 202311605645A CN 117613091 A CN117613091 A CN 117613091A
Authority
CN
China
Prior art keywords
insulator layer
semiconductor layer
electrode
source electrode
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311605645.3A
Other languages
Chinese (zh)
Inventor
夏奕东
杜兵峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University
Original Assignee
Nanjing University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University filed Critical Nanjing University
Priority to CN202311605645.3A priority Critical patent/CN117613091A/en
Publication of CN117613091A publication Critical patent/CN117613091A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a structure for improving the surface potential of a field effect transistor and a preparation method thereof. The structure of the semiconductor device comprises an insulator layer, a semiconductor layer, a gate electrode, a drain electrode and a source electrode, wherein the insulator layer is arranged between the gate electrode and the semiconductor layer to isolate the gate electrode from the semiconductor layer, and the source electrode, the drain electrode and the semiconductor layer are in contact; the source electrode of the field effect transistor is simultaneously contacted with the semiconductor layer and the insulator layer, so that MIM parts formed by the source electrode, the insulator layer and the gate electrode and MISM parts formed by the source electrode, the insulator layer, the semiconductor layer and the gate electrode form a parallel circuit. The invention is a structure which allows the insulator layer to generate reversible transformation of blocking-transporting charges, can promote the surface potential of a transistor, and can realize the promotion of sub-threshold voltage swing and intrinsic gain performance under low gate voltage.

Description

Structure for improving surface potential of field effect transistor and preparation method
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a structure for improving the surface potential of a field effect transistor and a preparation method thereof.
Background
Field effect transistors (Field-effect Transistor, hereinafter referred to as transistors) are basic units and core elements of the modern electronics industry, and their operating principles are:by varying the gate voltage V gs The (electric field) regulates the conduction of the channel. When the channel is opened, at the source-drain voltage V ds Driven downward carrier directional motion to generate source leakage current I ds . The application range mainly comprises a switching device, signal modulation, amplification and the like. The electrical performance parameters of the transistor as a switching device are mainly sub-threshold voltage swing (Subthreshold Swing, SS), threshold voltage (V th )、I OFF Current, as well as on-off current ratio, mobility, etc., the transfer I of a transistor can be measured by an electrical performance characterization experiment ds -V gs And output curve I ds -V ds Obtained. Where SS is defined as the minimum voltage required for every order of magnitude increase in current, ss=dv gs /dlogI ds ＝(dV gs /dψ s )(dψ s /dlogI ds ) The unit is mV/decade, which characterizes the switching speed of the device, wherein psi s Is the voltage drop across the semiconductor, i.e., the surface potential. At the same time the SS value also affects the minimum achievable voltage value of the transistor, i.e. affects the power consumption and miniaturization of the device, requiring as small a value as possible. For an amplifying circuit, intrinsic gain A i Is an important parameter, which characterizes the modulation capacity of the signal, and consists of transconductance g m And an output resistor r o Where transconductance is defined as g m ＝dI ds /dV gs ＝(dI ds /dψ s )(dψ s /dV gs ) The output resistance is defined as r o ＝dV ds /dI ds . As can be seen from the above, SS and A i Is directly regulated and controlled by the grid voltage.
As the physical size of transistors continues to decrease, smaller operating voltages are required to address challenges in performance, heat dissipation capability, and power consumption. In addition, the transistor is close to the off state at low gate voltage, the current is small, the output resistance is large, and the improvement of the intrinsic gain is facilitated. However, maintaining high performance at low gate voltages faces a number of difficulties, subject to the constraints of the device operating mechanism and the physical properties of the material.
In terms of the working mechanism, an insulator layer-semiconductor layer in the transistor forms a series capacitor, and the channel is regulated and controlled through series capacitance, namely a field effect. In the traditionIn cognition, the insulator layer mainly plays a role in blocking charge transport and the capacitance is substantially constant, which results in that a part of the voltage must be split off by the insulator layer, i.e. the gate voltage cannot be used for the channel regulation all and makes dV gs /dψ s >1. In terms of material physical properties, the charge in the transistor that constitutes the source current is mainly from the electrode, i.e. the source electrode. However, boltzmann distributes electrons in the metal to dψ s /dlogI ds A limit was set at 60mV/decade at room temperature. The two co-operate to result in SS not less than 60mV/decade at room temperature. From transconductance g m The expression of (1) can know the distribution mode of grid voltage and limit A at the same time i Is improved.
In the existing mechanism, changing the electron source can realize SS <60mV/decade (K.Gopalakrishnan, P.B.Griffin, J.D.Plummer, impact Ionization MOS (I-MOS) -Part I: device and Circuit formulas IEEE Trans. Electron Dev.52,69-76, 2005) or larger gain (S.S. Lee and A.Nathan, subthreshold Schottky-barreer thin-film transistors with ultralow power and high intrinsic gain.science 354,302-304, 2016), but has no effect on reducing the gate voltage; the ferroelectric is adopted as an insulator, so that the direct regulation and control of a channel can be realized theoretically, but the participation of inversion of ferroelectric polarization (ferroelectric domain) is needed, and the problems of extra energy source and voltage matching are introduced.
From an analysis of the transistor operating mechanism and factors affecting SS and Ai performance, it is known that the default insulator acts primarily to block charge transfer and that the capacitance is substantially constant, prohibiting improvement in transistor performance. Studies in 2015 reported that an insulator layer can act as a charge transport in a metal-insulator-semiconductor-metal (MISM) structure (E.K.Lee, J.Lee, J.H.Kim, K.H.Lim, J.S.Byun, J.Ko, Y.D.Kim, Y.Park, Y.S.Kim, direct electron injection into an oxide insulator using a cathode buffer layer. Nat. Commun.6,6785, 2015). In a metal-insulator-metal (MIM) structure, the insulator still serves as a charge blocking task. But are limited by the charge transport mechanism, the reversible transition of the insulator layer blocking-transporting charge cannot be achieved in a single MIM or MISM device, nor can the performance of the transistor be improved.
Disclosure of Invention
The present invention has for its object to solve the above problems a structure allowing a reversible transformation of the blocking-transporting charges of the insulator layer and for raising the surface potential of the transistor to achieve a low gate voltage V gs Lower boost sub-threshold voltage swing (SS) and eigengain (a i ) Performance. It is another object of the present invention to provide a method of making the above structure.
The invention adopts the technical scheme that:
a structure for improving surface potential of a field effect transistor comprises an insulator layer, a semiconductor layer, a gate electrode, a drain electrode and a source electrode, wherein the insulator layer is arranged between the gate electrode and the semiconductor layer to isolate the gate electrode from the semiconductor layer, and the source electrode, the drain electrode and the semiconductor layer are in contact; the source electrode is simultaneously contacted with the semiconductor layer and the insulator layer, so that MIM parts formed by the source electrode, the insulator layer and the gate electrode and MISM parts formed by the source electrode, the insulator layer, the semiconductor layer and the gate electrode form a parallel circuit.
Further, the field effect transistor is of a bottom gate staggered type, a bottom gate coplanar type, a top gate staggered type or a top gate coplanar type.
Further, the gate electrode adopts heavily doped p-Si as the gate electrode.
Further, the thickness of the insulator layer is 2-200nm.
Further, the thickness of the source electrode and the drain electrode is 2-300nm.
Further, the area of the source electrode and the drain electrode is 10nm 2 -1000μm 2 。
Further, the coverage area of the source electrode in contact with the semiconductor layer and the insulator layer is 2nm 2 -900μm 2 。
The invention also provides a preparation method of the structure for improving the surface potential of the field effect transistor, which comprises the following steps:
step 1, growing an insulator layer on a gate electrode, and cleaning;
step 2, growing a semiconductor layer above the insulator layer, and then performing thermal annealing treatment in an atmospheric environment;
and 3, depositing a metal film on the surface of the structure subjected to the thermal annealing treatment in the step 2 to serve as a source electrode and a drain electrode, wherein the source electrode is simultaneously contacted with the semiconductor layer and the insulator layer, so that MIM parts formed by the source electrode, the insulator layer and the gate electrode and MISM parts formed by the source electrode, the insulator layer, the semiconductor layer and the gate electrode form a parallel circuit.
Further, in the step 2, the temperature of the thermal annealing treatment is 200-600 ℃.
Further, in the step 2, the time of the thermal annealing treatment is 0.5 to 3 hours.
Current prior art regulation of the SS value and intrinsic gain of a transistor is mainly achieved by changing the electron source, which results in two consequences: 1) Small SS values or large a i Not necessarily obtained at small gate voltages, 2) small SS values and large a i Cannot be achieved at the same time at the same gate voltage. The invention can raise the surface potential of the transistor and realize low grid voltage V by dividing MIM part and MISM part into parallel structure and allowing the insulator layer to generate reversible transformation of blocking-transporting charge gs Lower boost sub-threshold voltage swing (SS) and eigengain (a i ) Performance. The embodiment of the invention preferably realizes that the subthreshold voltage swing breaks through the Boltzmann limit at the small gate voltage of 0.3V, namely, 36mV/decade is achieved, and the intrinsic gain is more than 10000.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the surface potential enhancement of a transistor of the present invention; dotted line and real lineThe lines represent the partial voltage V on the insulator and semiconductor layers of the transistor, respectively ins Sum phi s The dotted line is dV gs /dψ s Case=1. Voltage division from V in conventional transistors gs =0v starting; while the insulator layer and semiconductor partial pressure of the transistor are changed from V gs ＝V 1 Initially, the double arrow indicates V 1 The surface potential increases.
FIG. 2 is a schematic diagram of the structures of MIM, MISM and MI/SM (a) and (b) the current-voltage (I-V) curves across the terminals in example 1 of the present invention.
Fig. 3 is a transfer characteristic curve of the transistor with the MISM structure in example 2 of the present invention.
FIG. 4 is a transfer characteristic curve of the MI/SM structure transistor of example 3 of the present invention.
FIG. 5 shows (a) transistor output characteristic curves, (b) output resistance (r) o ) And transconductance (g) m ) And (c) an intrinsic gain versus gate voltage curve.
Fig. 6 is a graph showing transfer characteristics of a transistor having an MI/SM structure without annealing IGZO in example 4 of the present invention.
Detailed Description
The invention will now be discussed with reference to several example implementations. It should be understood that these implementations are discussed only to enable one of ordinary skill in the art to better understand and thus practice the invention, and are not meant to imply any limitation on the scope of the invention.
The invention provides a structure for enabling an insulator layer to conduct electron transmission and block transformation, and aims to improve the performance of a transistor at low grid voltage. The principle of voltage distribution to transistors is shown in fig. 1. For a conventional transistor, the capacitance of the insulator layer is constant, the channel is regulated when the gate voltage is applied to the transistor, and the voltage on the channel cannot be greater than the gate voltage due to the voltage division effect of the insulator layer, as shown by the dotted line in fig. 1, and SS cannot be less than 60mV/decade. When the transport-blocking transition of charges occurs in the insulator layer by proper structural design, the capacitance of the insulator layer also changes, making it possible to enhance the surface potential. As in V gs ＝V 1 The transition occurs: at V 1 The front insulator layer allows charge to pass through, i.e., the device is not a transistor and the semiconductor layer is not under field effect (series capacitance) regulation; v (V) 1 The insulator recovers the charge blocking layer effect, the device is a transistor and the semiconductor layer is subjected to field effect (series capacitance) regulation, as shown in solid lines in fig. 1, but the gate voltage applied to the transistor is now not from 0, but V 1 This results in: 1) Compared with the traditional transistor, more gate voltages are used for regulating and controlling the semiconductor layer, so that the high performance can be kept while the gate voltage is reduced; 2) A large surface potential increment, even greater than the gate voltage increment, i.e. dV gs /dψ s <1, as indicated by the double arrow.
In the present invention, a transistor includes an insulator layer, a semiconductor layer, a gate electrode, a drain electrode, and a source electrode, the insulator layer being disposed between the gate electrode and the semiconductor layer to isolate the gate electrode from the semiconductor layer, the source electrode, the drain electrode, and the semiconductor layer being in contact. The source electrode of the transistor is in contact with both the semiconductor layer and the insulator layer such that the source electrode-insulator-gate electrode (MIM) portion and the source electrode-insulator-semiconductor-gate electrode (MISM) portion form a parallel circuit. When charge is transferred from the MIM portion, the insulator in the MISM portion blocks electron transport; the insulator in the MISM section allows electron transport when charge is transported from the MISM section. As the voltage changes, the energy level matching in the MIM and MISM structures changes, i.e., the height of the barrier that the charge needs to cross through the MIM or MISM portion changes, while the charge tends to pass through the path where the barrier is lower. However, for MIM and MISM structures, the barrier change is not the same and can therefore be used to control charge transport via MIM or MISM structures, i.e. to achieve transport-blocking transitions of the insulator layer to the charge in the MISM structure.
The field effect transistor may be of bottom gate staggered, bottom gate coplanar, top gate staggered or top gate coplanar type. The electrode of the field effect transistor can be metal, conductive nitride or conductive oxide material, semiconductor material such as n-type heavily doped high-conductivity silicon or p-type heavily doped high-conductivity silicon, or flexible substrate with conductive coating.
The insulator layer film can be an insulator such as silicon dioxide, aluminum oxide and the like, and has the function of converting the transmission and blocking of electrons so as to improve the regulation capability of the transistor, and can also be a polymer insulator such as PMMA (polymethyl methacrylate), P (VDF-TrFE) and the like.
The semiconductor layer may be an element, a compound, or the like, which functions to provide a movable carrier (electron or hole) and has a carrier concentration.
Example 1
To verify the specific effect of the insulator layer on charge transport, first a device was prepared with the structure shown in fig. 2 (a), respectively, comprising three structures: i metal-insulator-metal (MIM), ii metal-insulator-semiconductor-metal (MISM), and iii metal-insulator/semiconductor-metal (MI/SM) structures of the present invention. To be used for<100>Heavily doped p-Si with the crystal orientation is used as a gate electrode, and the resistivity is less than 0.005 omega-cm; taking silicon dioxide with the thickness of 90nm which is grown by thermal oxidation as a gate insulator layer; for MISM and MI/SM, indium gallium zinc oxide (InGaZnO) at 100nm 4 IGZO) is an n-type semiconductor layer; a100 nm gold film was used as the source and drain electrodes. The source electrode area was 10 μm×50 μm, and the source electrode contact area covering the semiconductor layer and the insulator layer was 5 μm×50 μm.
The specific preparation process comprises the following steps:
thermal oxidation of SiO at 90nm 2 The covered p-Si substrate is sequentially ultrasonically cleaned by acetone, ethanol and deionized water for 10 minutes respectively, and is dried by a nitrogen gun for standby. Using a magnetron sputtering method, IGZO of 100nm was grown on the above p-Si substrate, followed by thermal annealing treatment in an atmospheric environment at 400℃for 1 hour. Finally, a gold film was deposited using direct current sputtering at 100nm.
Analysis by X-ray photoelectron spectrometer shows that IGZO-SiO after annealing treatment 2 The energy level matching changes. The interface barrier is reduced by 0.5eV after annealing compared to not performing the annealing treatment.
Performing electrical performance test on the prepared device by using a Keithley 4200 (4200-SCS) semiconductor analysis system, and analyzing performance parameters such as output characteristics and transfer characteristics of the device by testing the response relation between current and applied voltage;
FIG. 2 (b) shows two endsCurrent-voltage (I-V) characteristic of the device: for MIM structure, the current is maintained at 10 - 11 Below A, exhibits good insulating properties, namely SiO 2 Blocking the transport of electrons; for MISM structure, current is 10 at-15 to 0V -9 A and increases to 10 at a positive voltage of 15V -5 A, shows rectifying characteristics, and a rectifying ratio of 10 5 Indicating SiO 2 The transportation of electrons is participated; whereas for MI/SM structures, the current magnitude is close to MIM structures in the test voltage interval (-15 to 15V). But experienced a significant increase before 0.2V (indicated by circles) and then quickly recovered to MIM levels, indicating SiO 2 The layer acts as carrier transport in the 0.2V preceding interval, while the other intervals block carrier transport, i.e. a transition of carrier transport to blocking is achieved at 0.2V.
Example 2
Examples 2 and 1 differ in that the transfer characteristic of the test transistor, i.e., the three-terminal device test. The transfer characteristic curve of the transistor prepared with the MISM structure is shown in fig. 3: leakage current I gs That is, the current of the two-terminal MISM structure is close to the current of the two terminals of the MISM in FIG. 2 (b), indicating that the insulator layer in the three-terminal device allows charge transport; and I ds And I gs Proximity. Three terminal device I indicating MISM structure ds A significant portion is due to electrons at the interface that fail across the domain interface, directional movement at source drain voltage, and not channel opening in the capacitive control of the transistor. In other words, this time is not a transistor.
Example 3
Examples 3 and 2 differ in that the MI/SM structures of the present invention are used and subjected to a thermal annealing process. The transfer characteristic diagram for the characterization transistor here shows that: i gs Shows the same trend of change of the current at the two ends of MI/SM in the graph (b) of FIG. 2, and the current is respectively subjected to increase and dip (shown by circles) before and after 0.2V, namely the insulator layer is subjected to transport-blocking transition of electrons at 0.2V; i ds At 0.2V, jump-up process is carried out from 10 -13 10 to 0.3V -10 A, i.e. a voltage step of 0.1V, achieves 10 3 Corresponding to an SS value of 36mV/decade. Since the electron source is not changed,the improvement in SS performance is due to the enhancement of the surface potential caused by the transport-blocking transition of charge by the insulator layer.
Fig. 5 is an output characteristic, an output resistance and a transconductance derived based on the output characteristic and the transfer characteristic, and an eigengain obtained from the transconductance and the output resistance. The intrinsic gain exceeds 10000 at 0.3V.
The performance of the embodiment at 0.3V can meet the requirements of the field effect transistor and the large scale integrated circuit for the operation voltage of 0.5V and below.
Example 4
Examples 4 and 3 differ in that MI/SM structures are used but no thermal annealing treatment. The transfer characteristic is shown in fig. 6: i gs The current is maintained at substantially 10 -11 Below a, there is no significant current increase and decrease process (shown by circles), i.e., the insulator layer is always blocking the transport of charge. The transistor prepared by the method is a traditional transistor, and is specifically expressed as I ds Slowly increasing, SS is much greater than 60mV/decade.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention, but rather to enable any modification, equivalents, improvements and the like to be made within the spirit and principles of the invention.

Claims (10)

1. A structure for improving surface potential of a field effect transistor comprises an insulator layer, a semiconductor layer, a gate electrode, a drain electrode and a source electrode, wherein the insulator layer is arranged between the gate electrode and the semiconductor layer to isolate the gate electrode from the semiconductor layer, and the source electrode, the drain electrode and the semiconductor layer are in contact; the MIM part formed by the source electrode, the insulator layer and the gate electrode and the MISM part formed by the source electrode, the insulator layer, the semiconductor layer and the gate electrode form a parallel circuit.
2. The structure of claim 1, wherein the field effect transistor is bottom gate staggered, bottom gate coplanar, top gate staggered, or top gate coplanar.
3. The structure of claim 1, wherein the gate electrode is heavily doped with p-Si.
4. A structure for raising surface potential of field effect transistor according to claim 1, wherein the thickness of the insulator layer is 2-200nm.
5. A structure for raising surface potential of field effect transistor according to claim 1, wherein the thickness of source and drain electrodes is 2-300nm.
6. The structure for increasing surface potential of field effect transistor according to claim 1, wherein the source electrode and drain electrode have an area of 10nm 2 -1000μm 2 。
7. The structure of claim 6, wherein the contact area of the source electrode with the semiconductor layer and the insulator layer is 2nm 2 -900μm 2 。
8. A method of fabricating a structure for enhancing the surface potential of a field effect transistor as recited in claim 1, comprising the steps of:
step 1, growing an insulator layer on a gate electrode, and cleaning;
step 2, growing a semiconductor layer above the insulator layer, and then performing thermal annealing treatment in an atmospheric environment;
and 3, depositing a metal film on the surface of the structure subjected to the thermal annealing treatment in the step 2 to serve as a source electrode and a drain electrode, wherein the source electrode is simultaneously contacted with the semiconductor layer and the insulator layer, so that MIM parts formed by the source electrode, the insulator layer and the gate electrode and MISM parts formed by the source electrode, the insulator layer, the semiconductor layer and the gate electrode form a parallel circuit.
9. The method according to claim 8, wherein the thermal annealing treatment is performed at a temperature of 200 to 600 ℃.
10. The method according to claim 9, wherein in the step 2, the time of the thermal annealing treatment is 0.5 to 3 hours.
CN202311605645.3A 2023-11-28 2023-11-28 Structure for improving surface potential of field effect transistor and preparation method Pending CN117613091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311605645.3A CN117613091A (en) 2023-11-28 2023-11-28 Structure for improving surface potential of field effect transistor and preparation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311605645.3A CN117613091A (en) 2023-11-28 2023-11-28 Structure for improving surface potential of field effect transistor and preparation method

Publications (1)

Publication Number Publication Date
CN117613091A true CN117613091A (en) 2024-02-27

Family

ID=89945869

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311605645.3A Pending CN117613091A (en) 2023-11-28 2023-11-28 Structure for improving surface potential of field effect transistor and preparation method

Country Status (1)

Country Link
CN (1) CN117613091A (en)

Similar Documents

Publication Publication Date Title
US7339187B2 (en) Transistor structures
US7888207B2 (en) Transistor structures and methods for making the same
US11765907B2 (en) Ferroelectric memory device and operation method thereof
CN108831928B (en) Two-dimensional semiconductor material negative capacitance field effect transistor and preparation method thereof
US11980042B2 (en) Method for enhancing the performance of pentacene organic field-effect transistor and the structure of pentacence organic field-effect transistor
Jin et al. Experimental study on the role of polarization switching in subthreshold characteristics of HfO 2-based ferroelectric and anti-ferroelectric FET
US9412769B2 (en) Transistor, method of manufacturing the transistor, and electronic device including the transistor
JP5701015B2 (en) Driving method of semiconductor device
CN117613091A (en) Structure for improving surface potential of field effect transistor and preparation method
KR101605338B1 (en) Transistor with negative capacitor using topological insulator process for the preferation of the same
Kao et al. The TEOS CVD oxide deposited on phosphorus in situ doped polysilicon with rapid thermal annealing
US11575093B2 (en) Pentacene organic field-effect transistor with n-type semiconductor interlayer and its application
CN113871535B (en) Organic thin film transistor and preparation method thereof
TWI833965B (en) Non-volatile memory device and method of operation
US20230118661A1 (en) Space-free vertical field effect transistor including active layer having vertically grown crystal grains
KR20150059681A (en) Thin film transistor having double channel layers
WO2022190817A1 (en) Method for forming ferroelectric thin film and semiconductor device provided with same
Song et al. Investigation of Vertical Channel IGZO-TFT Based on PVD-IGZO
Cheng et al. A SOI based dopant-free MOSFET for logic and memory application
KR20240019943A (en) Thin film transistor with improved threshold voltage and stability
Jiang et al. Long-Term Recovery Behavior in InSnZnO Thin-Film Transistors after Negative Bias Stress
KR20240019942A (en) Method for manufacturing indium oxide thin film transistor doped with molybdenum oxide
Kishore et al. Impact of Bias Temperature Stress on IGZO/Ni/IGZO Steep Subthreshold Vertical Current Driver Fabricated at Room Temperature
Yang et al. High-Voltage a-IGZO Thin Film Transistor with the Symmetrical Stair Gate-Dielectric Structure
CN114141882A (en) Field effect transistor device structure for reducing energy consumption by utilizing point defect doping

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination