CN117613086A - LDMOS (laterally diffused metal oxide semiconductor) based on hemispherical insulation layer for improving HCI (hydrogen chloride) and preparation method - Google Patents

LDMOS (laterally diffused metal oxide semiconductor) based on hemispherical insulation layer for improving HCI (hydrogen chloride) and preparation method Download PDF

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CN117613086A
CN117613086A CN202311356263.1A CN202311356263A CN117613086A CN 117613086 A CN117613086 A CN 117613086A CN 202311356263 A CN202311356263 A CN 202311356263A CN 117613086 A CN117613086 A CN 117613086A
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ldmos
layer
hemispherical
field plate
etching
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黄伟宗
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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Abstract

The invention discloses an LDMOS (laterally diffused metal oxide semiconductor) based on hemispherical insulation layer improved HCI (hydrogen chloride) and a preparation method thereof, wherein the LDMOS comprises the following steps: a groove is formed in the upper layer of the N-drift layer; the distance between the bottom of the groove and the bottom surface of the polysilicon field plate is h2; the bottom of the groove is positioned right below the side wall surface of the polysilicon field plate; the trench is deposited with an insulating material. According to the invention, the STI below the polysilicon field plate is arranged in a hemispherical shape, so that the thickness of the STI at the strongest bottom of the edge electric field of the polysilicon field plate is thicker than that of other places, the generation of sharp corner strong electric field is avoided by the hemispherical design structure, the device damage caused by the LDMOS hot carrier injection effect is improved, and the reliability of the LDMOS is improved.

Description

LDMOS (laterally diffused metal oxide semiconductor) based on hemispherical insulation layer for improving HCI (hydrogen chloride) and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to an LDMOS (laterally diffused metal oxide semiconductor) based on a hemispherical insulating layer for improving HCI (hydrogen chloride) and a preparation method thereof.
Background
When the carriers acquire a large amount of energy from the outside, they can become hot carriers. For example, under the action of a strong electric field, carriers drift continuously along the direction of the electric field and accelerate continuously, so that great kinetic energy can be obtained, and the carriers become hot carriers. For MOS devices, when the feature size of the MOS device is small, a strong electric field can be generated even at voltages other than higher voltages, resulting in the tendency for hot carriers to occur. Therefore, in small-sized MOS devices as well as large-scale integrated circuits, hot carriers are liable to occur.
The hot carriers are carriers with high energy, which kinetic energy is higher than the average thermal movement energy, i.e. the movement speed of the hot carriers is also high. The hot carrier can induce the degradation of the MOS device, the phenomenon is caused by the injection of high-energy electrons and holes into the gate oxide layer, and interface states and oxide layer trapping charges can be generated in the injection process, so that the oxide layer is damaged. As the damage level increases, the current-voltage characteristics of the MOS device change. When the MOS device parameters change beyond a certain limit, the MOS device will fail.
The HCI, hot carrier injection effect, refers to the phenomenon of electrical performance degradation caused by injection of high-energy electrons or holes in a semiconductor device, and is a major key problem affecting the reliability of the LDMOS, and also affecting the service life of the LDMOS. The hot carrier injection effect is that ionization collision probability is increased due to the position of the strong electric field of the LDMOS device, so that the hot carrier overcomes the interface potential of silicon and silicon dioxide to tunnel into the oxide layer, and the oxide layer of the LDMOS device is damaged. Such damage can cause a change in the charge density of the oxide layer, which in turn affects the electrical performance of the device, causing drift or degradation of the device electrical parameters.
Disclosure of Invention
In order to solve at least one technical problem, the invention aims to provide an LDMOS (laterally diffused metal oxide semiconductor) based on a hemispherical insulating layer for improving HCI and a preparation method thereof, wherein the shape of an STI below a polycrystalline silicon field plate is set to be hemispherical, so that the thickness of the STI at the strongest bottom of an edge electric field of the polycrystalline silicon field plate is thicker than that of the STI at other places, and the hemispherical design structure also avoids the generation of sharp corner strong electric fields, improves device damage caused by the injection effect of hot carriers of the LDMOS, and improves the reliability of the LDMOS.
The aim of the invention is realized by adopting the following technical modes:
in a first aspect, the present invention provides an LDMOS based on a hemispherical insulation layer improved HCI, comprising: a groove is formed in the upper layer of the N-drift layer;
the distance between the bottom of the groove and the bottom surface of the polysilicon field plate is h2;
the bottom of the groove is positioned right below the side wall surface of the polysilicon field plate;
the trench is deposited with an insulating material.
Preferably, the method further comprises: a polysilicon field plate;
the polysilicon field plate is positioned above the P-body layer, the N-drift layer and the trench and is adjacent to the P-body layer and the N-drift layer.
Preferably, the grooves are formed by a plurality of sections of cambered surfaces.
Preferably, the width of the groove ranges from 0.5 to 10um.
Preferably, the insulating material comprises: siO2.
Preferably, the cross section of the groove is semicircular.
Preferably, the distance h2 between the bottom of the groove and the bottom surface of the polysilicon field plate ranges from 0.25 um to 5um.
In a second aspect, the present invention provides a method for manufacturing an LDMOS based on a hemispherical insulation layer improved HCI, comprising:
etching the upper layer of the N-drift layer to form a hemispherical groove;
depositing silicon dioxide in the groove to form a hemispherical insulating layer;
depositing a polysilicon field plate;
etching the polysilicon field plate;
and forming a P-body layer, an N+ layer and a P+ layer by ion implantation on the N-drift layer.
Preferably, the forming of the hemispherical trench by etching the upper layer of the N-drift layer is specifically: and defining an etching area of the hemispherical groove by using a photoetching method, and then etching the upper layer of the N-drift layer by using an isotropic etching method to form the hemispherical groove.
Preferably, the etching polysilicon field plate specifically comprises: the region to be etched is defined by photolithography, and the polysilicon field plate is etched by polysilicon etching.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the STI below the polysilicon field plate is arranged in a hemispherical shape, so that the thickness of the STI at the strongest bottom of the edge electric field of the polysilicon field plate is thicker than that of other places, the generation of sharp corner strong electric field is avoided by the hemispherical design structure, the device damage caused by the LDMOS hot carrier injection effect is improved, and the reliability of the LDMOS is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings that are required to be used in the embodiments or the background of the present application.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 is a schematic structural diagram of an LDMOS based on a hemispherical insulation layer improved HCI according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for preparing an LDMOS based on a hemispherical insulation layer improved HCI according to an embodiment of the invention.
Description of the embodiments
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
When the carriers acquire a large amount of energy from the outside, they can become hot carriers. For example, under the action of a strong electric field, carriers drift continuously along the direction of the electric field and accelerate continuously, so that great kinetic energy can be obtained, and the carriers become hot carriers. For MOS devices, when the feature size of the MOS device is small, a strong electric field can be generated even at voltages other than higher voltages, resulting in the tendency for hot carriers to occur. Therefore, in small-sized MOS devices as well as large-scale integrated circuits, hot carriers are liable to occur. The hot carriers are carriers with high energy, which kinetic energy is higher than the average thermal movement energy, i.e. the movement speed of the hot carriers is also high. The hot carrier can induce the degradation of the MOS device, the phenomenon is caused by the injection of high-energy electrons and holes into the gate oxide layer, and interface states and oxide layer trapping charges can be generated in the injection process, so that the oxide layer is damaged. As the damage level increases, the current-voltage characteristics of the MOS device change. When the MOS device parameters change beyond a certain limit, the MOS device will fail. The HCI, hot carrier injection effect, refers to the phenomenon of electrical performance degradation caused by injection of high-energy electrons or holes in a semiconductor device, and is a major key problem affecting the reliability of the LDMOS, and also affecting the service life of the LDMOS. The hot carrier injection effect is that ionization collision probability is increased due to the position of the strong electric field of the LDMOS device, so that the hot carrier overcomes the interface potential of silicon and silicon dioxide to tunnel into the oxide layer, and the oxide layer of the LDMOS device is damaged. Such damage can cause a change in the charge density of the oxide layer, which in turn affects the electrical performance of the device, causing drift or degradation of the device electrical parameters.
According to the invention, the STI below the polysilicon field plate is arranged in a hemispherical shape, so that the thickness of the STI at the strongest bottom of the edge electric field of the polysilicon field plate is thicker than that of other places, the generation of sharp corner strong electric field is avoided by the hemispherical design structure, the device damage caused by the LDMOS hot carrier injection effect is improved, and the reliability of the LDMOS is improved.
Example 1
There is provided an LDMOS based on a hemispherical insulation layer improved HCI, comprising: a groove is formed in the upper layer of the N-drift layer;
the distance from the bottom of the groove to the bottom surface of the polysilicon field plate is h2;
the bottom of the groove is positioned right below the side wall surface of the polysilicon field plate;
the trench is deposited with an insulating material.
The reliability of the LDMOS is an important index for measuring the performance of the LDMOS device when the LDMOS is applied to the field of high-voltage power, and the strong field effect of the LDMOS has to be carefully considered due to the existence of high voltage of a drain and the reduction of the size of the LDMOS device, and the strong field directly causes the hot carrier injection effect of the LDMOS device.
Hot carrier: when channel electrons pass through the strong field region, the electrons acquire additional energy from the electric field, and the energy balance between the electrons and the crystal lattice is broken, i.e. the additional energy cannot be transmitted to the crystal lattice. These high energy carriers are called hot carriers. With respect to the structure of the LDMOS, what generates hot carriers in the LDMOS device and can affect the gate current is at the PN junction near the drift region.
In the strong field region, since there are more high-energy electrons than in other regions, another main phenomenon, impact ionization, is caused. The high energy electrons strike the lattice, creating additional electron-hole pairs. The newly added electrons become part of the drain current, and the generated holes have various sites. Wherein a majority of the current flows to the substrate, which becomes the substrate current, and a fraction of zero flows to the gate and source. Hot carriers entering the gate can generate oxide charges and interface traps, resulting in degradation of the performance of the LDMOS device, especially threshold voltage drift, transconductance degradation, etc., which affect the lifetime of the LDMOS device.
The amount of hot carriers can be reflected by the substrate current. The magnitude of the substrate current is determined by the drain current and the field strength and the collision coefficient, and it can be seen that the collision ionization phenomenon preferentially occurs in the region where the field strength and the current concentrate. The bird's beak area under the field plate of the LDMOS and the drain area are all where the current is concentrated. The beak region under the field plate is where the current is dense and when the field strength is large enough, the secondary electron-hole pairs generated by the high velocity carriers striking the lattice will increase substantially, i.e. the impact ionization intensity of the region is enhanced.
In this embodiment, a trench is formed in the upper layer of the N-drift layer, the bottom of the trench is located directly below the sidewall surface of the polysilicon field plate, the distance between the bottom of the trench and the bottom surface of the polysilicon field plate is h2, and the thickness h2 of the bottom of the polysilicon field plate, where the electric field is strongest, is thickest, so as to reduce the hot carrier injection effect at the bottom of the polysilicon field plate edge.
According to the invention, the STI below the polysilicon field plate is arranged in a hemispherical shape, so that the thickness of the STI at the strongest bottom of the edge electric field of the polysilicon field plate is thicker than that of other places, the generation of sharp corner strong electric field is avoided by the hemispherical design structure, the device damage caused by the LDMOS hot carrier injection effect is improved, and the reliability of the LDMOS is improved.
Preferably, the method further comprises: a polysilicon field plate;
the polysilicon field plate is located over and adjacent to the P-body layer, the N-drift layer, and the trench.
The field plate is an electric field optimization technology widely applied to the transverse power device, and the technology increases the field plate and improves the voltage resistance of the LDMOS device under the condition that the on-resistance of the LDMOS device is not changed. When electric lines exist on the surface of the drift region, the electric lines terminate on the surface charge of the LDMOS device and are influenced by the electric field on the surface of the LDMOS device, and the shape of the surface of the drift region and the distribution of the electric field are changed, so that the breakdown voltage of the LDMOS device is changed. The field plate technology is used for covering a field plate on the surface of the LDMOS device, and changing the breakdown voltage of the LDMOS device by changing the voltage of the field plate.
By introducing two vertical field plates which are symmetrical in the center in the oxide groove, the aims of improving the breakdown voltage of the device and reducing the on-resistance of the device can be achieved. Two vertical field plates in the device are connected one to the gate and one to the drain. In the off state, the vertical field plate introduces a high electric field into the oxidation trench, two new electric field peaks are formed near the surface of the trench, and the whole electric field of the device is optimized. The auxiliary depletion effect caused by the gate field plate helps the drift region to reach a higher doping concentration. In the on state, the concentration of the doped region is higher, so that the specific on resistance of the device is smaller, the contradiction relation between the breakdown voltage and the specific on resistance of the device is relieved to a certain extent, and the performance of the device is improved. Besides being connected with the electrode through being embedded in the groove, the field plate technology can be directly used on the electrode to optimize and adjust the surface electric field of the LDMOS device, and the performance of the LDMOS device is improved. The field plate technology is connected with different electrodes to form different field plates, such as a source field plate, a gate field plate and a drain field plate.
Preferably, the grooves are formed by a plurality of arcuate surfaces.
In LDMOS devices, the strong field region is typically located at the edge or tip of the region. In some embodiments, the cross-section of the STI trench is trapezoidal in shape, with an increased curvature at one end surface of the sidewall surface of the trapezoid, resulting in a strong electric field on the sidewall surface of the trapezoid, where hot carrier injection damage is more likely to occur. In this embodiment, the trench located right below the sidewall surface of the polysilicon field plate is formed by multi-end arc surfaces, so that the generation of sharp-angle strong electric fields is avoided, and the hot carrier injection effect of the LDMOS device is improved.
Preferably, the width of the trench ranges from 0.5 to 10um.
Preferably, the insulating material comprises: siO2.
In some embodiments, the insulating material of the trench may be silicon dioxide, other oxides deposited by high density plasma deposition, undoped silicate glass, or other insulating materials. Silicon dioxide is advantageous as an insulating material for the trenches. The silicon dioxide has good high temperature resistance, high temperature manufacturing can be carried out in the manufacturing process, and the silicon dioxide is lower in cost than other insulating materials, so that the use of the silicon dioxide as the insulating material is beneficial to saving the cost.
Preferably, the grooves are semi-circular in cross section.
In some embodiments, the cross-sectional shape of the groove may be semi-elliptical or semi-circular. The cross section of the groove is arranged in a semicircular shape, so that the improvement effect on the strong electric field of the LDMOS device is good, meanwhile, the groove can be etched more conveniently and accurately, and the manufacturing and labor cost of the groove are saved.
Preferably, the distance h2 of the bottom of the trench from the bottom surface of the polysilicon field plate ranges from 0.25 to 5um.
The shape and size of the trench can affect the current in the drift region, thereby affecting the performance of the LDMOS device, for example, improper design of the trench can obstruct the current path from the source to the drain, resulting in impact ionization and hot carriers, and both interface states and hot carriers generated by the impact ionization can affect the performance of the LDMOS device. The proper size and shape of the trench can enable the drift region to be completely exhausted, and the breakdown voltage of the LDMOS device can be improved. In this embodiment, the width of the trench is in the range of 0.5-10um, and the distance h2 from the bottom of the trench to the bottom surface of the polysilicon field plate is in the range of 0.25-5um.
Example 2
The preparation method of the LDMOS based on the hemispherical insulation layer improved HCI comprises the following steps:
s100, etching the upper layer of the N-drift layer to form a hemispherical groove;
s200, silicon dioxide is deposited in the groove to form a hemispherical insulating layer;
the STI process overcomes the limitations of the LOCOS process, and its superior performance is achieved by integrating a complex series of processes, mainly including etching, filling and chemical mechanical polishing planarization of trenches. In the formation of trenches, the STI process generally uses Si3N4 as an isolation mask, and in order to prevent the stress of Si3N4 from causing defects in the silicon substrate, a thin layer of Si02 is used as a buffer layer to relieve the stress between Si3N4 and the silicon substrate. SiN4 acts as a polish stop during the subsequent cmp planarization process. Its thickness determines the step height of the active region and field region and its optimization should be chosen to ensure that the step height after cmp planarization is sufficient to allow cleaning and etching prior to gate oxide growth. In some embodiments, 20nm of SiO2 is grown as a buffer layer at 1000℃ in an atmosphere of O2 and HCI, then 200nm of Si3N4 is deposited using LPCVD process, followed by annealing at 800℃ in an atmosphere of N2 for 30min. And photoetching by taking the photoresist as an etching mask after Si3N4 annealing. The trench is formed by reactive ion etching the silicon substrate. Factors that affect etching are mainly temperature, pressure, RF power, etching gas, and components thereof. The most critical of the etching process is controlling the shape of the trench, which affects the trench filling.
The main step in trench filling is to deposit SiO2, which is typically higher than the etch rate of the grown SiO2, which can lead to loss of field SiO2 during surface cleaning prior to gate SiO2 formation. The etch rate of the deposited SiO2 can be reduced by a densification process, such as annealing at 800-1050℃, to reduce the etch rate of the fill medium to a rate close to that of thermally grown SiO2. In some embodiments, PECVD TEOS SiO2 is used as a trench filling medium, and a LPCVD process is used to deposit 15nm of SiO2 and 15nm of Si3N4 before the SiO2 is used to fill the trench, so as to protect the corners of the trench from damage during chemical mechanical polishing planarization, and the trench is annealed in an atmosphere of N2 at 900 ℃ after filling to reduce the corrosion rate of the SiO2.
CMP planarization is considered to be the most central part of the STI process, which utilizes a combination of chemistry and machinery to planarize the surface of the silicon wafer. The difficulty with the CMP process is that its planarization effect is related to the pattern size of the wafer surface. After CMP, after SiN4 is exposed on the wide active region, overpolishing tends to occur in the wide isolation region and the narrow active region, resulting in a dishing phenomenon, which may cause non-uniformity in step height between the active region and the field region after Si3N4 removal, and may even damage the silicon substrate at the narrow active region. In some embodiments, after CMP, the exposed Si3N4 is removed using hot phosphoric acid, and finally a sacrificial oxide layer is grown on the wafer surface and rinsed away to further remove defects and damage to the wafer surface, ready for gate oxidation and polysilicon gate formation.
S300, depositing a polysilicon field plate;
s400, etching the polysilicon field plate;
deposition processes are classified into Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). CVD refers to a process of chemically depositing a coating on the surface of a wafer, typically by applying energy to a gas mixture. Assuming that the substance (a) is deposited on the wafer surface, two gases (B and C) that can generate the substance (a) are first input to the deposition apparatus, and then energy is applied to the gases to cause the gases B and C to chemically react.
PVD (physical vapor deposition) coating techniques are mainly divided into three categories: vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The main methods of physical vapor deposition are: vacuum evaporation, sputter coating, arc plasma coating, ion coating, molecular beam epitaxy, and the like. The corresponding vacuum coating equipment comprises a vacuum evaporation coating machine, a vacuum sputtering coating machine and a vacuum ion coating machine.
Etching is a process of selectively removing unwanted material from the surface of a silicon wafer by chemical or physical means, and is a generic term for stripping and removing material by solution, reactive ions or other mechanical means. The etching technology is mainly divided into dry etching and wet etching. The dry etching mainly uses the reaction gas and the plasma for etching; the wet etching mainly uses chemical reagents to chemically react with the etched material for etching.
Ion beam etching is a physical dry etching process. Thereby, argon ions are irradiated onto the surface with an ion beam of about 1 to 3 keV. Due to the energy of the ions, they strike the material of the surface. The wafer is vertically or obliquely directed into the ion beam and the etching process is absolutely anisotropic. The selectivity is low because it is not different for each layer. The gas and abraded material are evacuated by the vacuum pump, but since the reaction products are not gaseous, particles can deposit on the wafer or chamber walls. All materials can be etched in this way and the wear on the vertical walls is low due to the vertical radiation.
Plasma etching is an absolute chemical etching process and has the advantage that the wafer surface is not damaged by accelerated ions. The method is used to remove the entire film (e.g., backside cleaning after thermal oxidation) because the etch profile is isotropic due to the movable particles of the etch gas. One type of reactor used for plasma etching is a downstream reactor. So that the plasma is ignited at a high frequency of 2.45GHz by impact ionization, the location of which is separated from the wafer.
The etch rate depends on the pressure, the power of the high frequency generator, the process gas, the actual gas flow and the wafer temperature. Anisotropy increases with an increase in high-frequency power, a decrease in pressure, and a decrease in temperature. The uniformity of the etching process depends on the gas, the distance between the two electrodes and the material of the electrodes. If the distance is too small, the plasma cannot be unevenly dispersed, resulting in non-uniformity. If the distance of the electrodes is increased, the etch rate is reduced because the plasma is distributed in the enlarged volume. Carbon has proven to be the material of choice for electrodes. Since fluorine and chlorine also attack carbon, the electrodes produce a uniformly strained plasma and the wafer edge is affected by the same effect as the wafer center. The selectivity and etch rate are largely dependent on the process gas. For silicon and silicon compounds, fluorine gas and chlorine gas are mainly used.
S500, forming a P-body layer, an N+ layer and a P+ layer by ion implantation on the upper layer of the N-drift layer.
+ is heavily doped (high doping concentration), -is lightly doped (low doping concentration), P-type doped group IIIA element, for example: boron, aluminum, gallium, indium, thallium. N-type doping with group VA elements such as nitrogen, phosphorus, arsenic, antimony, bismuth and permalloy. Heavily doped semiconductors can be used to fabricate high performance electronic devices with a doping concentration of 10 19 cm -3 The above methods for preparing p+ doping include a diffusion method and an ion implantation method. The diffusion method mixes impurity ions with a semiconductor material, and then heats the mixture to a high temperature to diffuse the impurity ions into the semiconductor material, and the ion implantation accelerates the impurity ions to a high speed and then injects the impurity ions into the semiconductor material. Lightly doped semiconductors refer to semiconductor materials that are made by adding a low concentration of impurity atoms in the preparation of the semiconductor material. The doped impurity atoms can alter the electrical properties of the semiconductor material, thereby improving its performance and functionality. In lightly doped semiconductors, the concentration of impurity atoms incorporated is typically lower than the intrinsic concentration of the semiconductor material (intrinsic concentration refers to the concentration of impurity atoms in a pure semiconductor). The impurity atoms to be incorporated must also have a lattice size and an electronic structure similar to those of the semiconductor material atoms to ensure that they can be smoothly bonded to and move in the semiconductor material. After doping impurity atoms, the electrical properties of the lightly doped semiconductor will change accordingly. The most important of these is the improvement in conductivity. This is because the added impurity atoms may form additional free electrons or holes in the semiconductor, resulting in enhanced conductivity properties of the semiconductor material. In addition, it is lightThe doped semiconductor can also change the forbidden bandwidth, carrier mobility, optical absorption spectrum and other properties of the semiconductor material, so that the application of the semiconductor material in the fields of electronics, optoelectronics, chemistry and the like is expanded. The lightly doped semiconductor is prepared by ion implantation, fusion diffusion and other technologies. The ion implantation is to accelerate the doping element to a high speed by a high voltage electric field, then bombard the semiconductor surface, and implant it into the semiconductor lattice. The fusion diffusion is to place the semiconductor chip on the doped material block, then heat to high temperature, and the doped atoms are fused and diffused into the semiconductor material. In practical application, lightly doped semiconductors are widely applied to the fields of circuits, solar cells, nano materials and the like. For example, after silicon is doped with aluminum element, n-type silicon can be formed, the conductivity of which is remarkably improved, and the silicon can be used for manufacturing a p-n junction solar cell. In addition, the lightly doped semiconductor can also be used for preparing microelectronic devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFET), low noise power amplifiers and the like. In the field of nanotechnology, the lightly doped semiconductor can be used for preparing various photoelectron and biochemical sensors, and has wide application prospect.
Preferably, the forming of the hemispherical trench by etching the upper layer of the N-drift layer is specifically: and defining an etching area of the hemispherical groove by using a photoetching method, and then etching the upper layer of the N-drift layer by using an isotropic etching method to form the hemispherical groove.
Preferably, the etching of the polysilicon field plate is specifically: the region to be etched is defined by photolithography, and the polysilicon field plate is etched by polysilicon etching.
Photolithography is one method of patterning photoresist. This step uses exposure and development to pattern geometric structures on the photoresist layer, and then transfers the pattern on the photomask to the substrate by an etching process. A metal layer of only a few nanometers thick is arranged on a silicon substrate by a metallization process. And then coating a photoresist on the metal layer. The photoresist layer may be dissolved by a specific solution after exposure. The photoresist is selectively exposed by passing a specific light wave through the photomask to irradiate the photoresist. The irradiated areas are then dissolved away using a developer solution, so that the pattern on the photomask appears on the photoresist. Some properties of the remaining portion of the photoresist will also typically be improved by baking measures. After the above steps are completed, a selective etching or ion implantation process can be performed on the substrate, and the undissolved photoresist will protect the substrate from being changed during these processes. After the etching or ion implantation is completed, the final step of photolithography, i.e., photoresist removal, is performed to facilitate further steps in the manufacture of semiconductor devices.
Photoresist: photosensitive materials used in photolithography are called photoresists and are largely classified into positive photoresists and negative photoresists. The non-illuminated portions of the positive photoresist will remain after development, while the photosensitive portions of the negative photoresist will remain after development. The photoresist needs to be sensitive to not only specified light but also to maintain stable properties during subsequent metal etching and the like. Different photoresists typically have different photosensitive properties, some photosensitive to all ultraviolet spectra, some photosensitive to specific spectra only, and some photosensitive to X-rays or electron beams. The photoresist needs to be stored in a special light shielding vessel.
Photolithography can be classified into projection exposure, proximity exposure, and contact exposure according to the method of exposure. Projection exposure is an exposure method in which a pattern on a reticle is projected onto a substrate using a lens or a mirror. In the exposure method, the damage to the mask plate can be completely avoided due to the fact that the distance between the mask plate and the silicon wafer is far. In projection exposure, only a small portion of the wafer is exposed at a time, and then the entire wafer is exposed using scanning and step and repeat methods to improve resolution. The close exposure has a small gap between the silicon wafer and the mask plate during exposure, the gap is generally between 10 and 25um, and the gap can greatly reduce the damage to the mask plate. The resolution of proximity exposures is low, typically between 2-4um, and the main advantage of proximity exposure over projection exposure is higher production efficiency. In the contact exposure technique, a silicon wafer coated with photoresist is in direct contact with a mask. Because of the close contact between the photoresist and the reticle, a relatively high resolution can be obtained. However, contact exposure also has drawbacks, the main problem of which is the ease of damage to the reticle and photoresist.
By adding the developing solution after the exposure process is finished, the photosensitive area of the positive photoresist and the non-photosensitive area of the negative photoresist are dissolved in the developing solution. After this step, the pattern in the photoresist layer can be visualized. In order to improve the resolution, almost every photoresist has a special developer to ensure a high quality developing effect. The photoresist stripping method includes wet photoresist stripping, which is divided into removing photoresist by using an organic solvent and oxidizing carbon element of the photoresist into carbon dioxide by using an inorganic solvent, and dry photoresist stripping, which is to strip the photoresist by using plasma.
According to the invention, the STI below the polysilicon field plate is arranged in a hemispherical shape, so that the thickness of the STI at the strongest bottom of the edge electric field of the polysilicon field plate is thicker than that of other places, the generation of sharp corner strong electric field is avoided by the hemispherical design structure, the device damage caused by the hot carrier injection effect of the LDMOS device is improved, and the reliability of the LDMOS device is improved.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity. In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disk (digital versatile disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
Those of ordinary skill in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by a computer program to instruct related hardware, the program may be stored in a computer readable storage medium, and the program may include the above-described method embodiments when executed. And the aforementioned storage medium includes: a read-only memory (ROM) or a random access memory (random access memory, RAM), a magnetic disk or an optical disk, or the like.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. An LDMOS based on a hemispherical insulation layer to improve HCI, comprising: a groove is formed in the upper layer of the N-drift layer;
the distance between the bottom of the groove and the bottom surface of the polysilicon field plate is h2;
the bottom of the groove is positioned right below the side wall surface of the polysilicon field plate;
the trench is deposited with an insulating material.
2. An LDMOS based on a hemispherical insulator improved HCI as claimed in claim 1, further comprising: a polysilicon field plate;
the polysilicon field plate is positioned above the P-body layer, the N-drift layer and the trench and is adjacent to the P-body layer and the N-drift layer.
3. An LDMOS based on a hemispherical insulator improved HCI as claimed in claim 1, wherein the trench is comprised of a multi-segment arc.
4. An LDMOS based on a hemispherical insulator improved HCI as claimed in claim 1, wherein the width of the trench ranges from 0.5 to 10um.
5. An LDMOS based on a hemispherical insulator improved HCI as in claim 1, wherein the insulator material comprises: siO2.
6. An LDMOS for improving HCI based on a hemispherical insulator layer as in claim 1, wherein the trench is semi-circular in cross section.
7. An LDMOS for improving HCI based on a hemispherical insulator layer as in claim 1, wherein the bottom of the trench is at a distance h2 from the bottom surface of the polysilicon field plate in the range of 0.25-5um.
8. The preparation method of the LDMOS based on the hemispherical insulation layer improved HCI is characterized by comprising the following steps of:
etching the upper layer of the N-drift layer to form a hemispherical groove;
depositing silicon dioxide in the groove to form a hemispherical insulating layer;
depositing a polysilicon field plate;
etching the polysilicon field plate;
and forming a P-body layer, an N+ layer and a P+ layer by ion implantation on the N-drift layer.
9. The LDMOS of claim 8 wherein said etching of the N-drift layer upper layer to form hemispherical trenches is specifically: and defining an etching area of the hemispherical groove by using a photoetching method, and then etching the upper layer of the N-drift layer by using an isotropic etching method to form the hemispherical groove.
10. The LDMOS of claim 8 wherein said etched polysilicon field plate is specifically: the region to be etched is defined by photolithography, and the polysilicon field plate is etched by polysilicon etching.
CN202311356263.1A 2023-10-19 2023-10-19 LDMOS (laterally diffused metal oxide semiconductor) based on hemispherical insulation layer for improving HCI (hydrogen chloride) and preparation method Pending CN117613086A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117855283A (en) * 2024-03-08 2024-04-09 粤芯半导体技术股份有限公司 LDMOS device and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117855283A (en) * 2024-03-08 2024-04-09 粤芯半导体技术股份有限公司 LDMOS device and preparation method thereof
CN117855283B (en) * 2024-03-08 2024-05-17 粤芯半导体技术股份有限公司 LDMOS device and preparation method thereof

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