CN117608947A - Fault testing system and method for memory - Google Patents
Fault testing system and method for memory Download PDFInfo
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- CN117608947A CN117608947A CN202410094844.0A CN202410094844A CN117608947A CN 117608947 A CN117608947 A CN 117608947A CN 202410094844 A CN202410094844 A CN 202410094844A CN 117608947 A CN117608947 A CN 117608947A
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- 238000011990 functional testing Methods 0.000 claims abstract description 9
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides a fault test system of a memory, which comprises: the multi-functional test main board is configured to be in communication connection with a plurality of memories to be tested, wherein a programmable processor is arranged on the multi-functional test main board and is used for carrying out corresponding interface resource allocation so as to generate a multi-channel communication protocol; the host end is used for transmitting a plurality of different test files with continuous numbers to the corresponding memory to be tested through the multi-channel communication protocol; the memory to be tested is used for testing according to the corresponding test file so as to generate a corresponding test result; the programmable processor is also used for generating a test log according to the test result; the host end is also used for analyzing and counting the test log to generate a fault test report. The fault test system and the fault test method for the memory can improve the fault test efficiency of the memory.
Description
Technical Field
The present invention relates to the field of electronic storage technologies, and in particular, to a fault test system and method for a memory.
Background
Embedded memory (Embedded Multi Media Card, eMMC) and universal flash memory (Universal Flash Storage, UFS) are widely used in electronic products such as televisions, set-top boxes, tablet computers, and cell phones. The eMMC memory is composed of an ARM CPU as a controller plus a NAND Flash, where the ARM CPU runs controller software, commonly referred to as Firmware (Firmware).
Because the eMMC memory includes a plurality of memory particles, and the memory needs to be subjected to fault test before leaving the factory, so as to screen out memory particles with differences, thereby classifying the fault types of the memory. However, the existing test system has low classification accuracy for the fault type of the memory and low test efficiency, and thus, there is a need for improvement.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a system and a method for testing a memory failure, which improve the problem of low testing efficiency of the existing testing system.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a fault test system of a memory, comprising:
the multi-functional test main board is configured to be in communication connection with a plurality of memories to be tested, wherein a programmable processor is arranged on the multi-functional test main board and is used for carrying out corresponding interface resource allocation according to the types of the memories to be tested so as to generate a multi-channel communication protocol; and
the host end is in communication connection with the programmable processor and is used for transmitting a plurality of different test files with continuous numbers to the corresponding memory to be tested through the multi-channel communication protocol;
the memory to be tested is used for testing according to the corresponding test file so as to generate a corresponding test result;
the programmable processor is also used for generating a test log according to the test result;
the host end is also used for analyzing and counting the test log to generate a fault test report.
In an embodiment of the present invention, when the programmable processor determines that the test of the memory to be tested passes, the programmable processor generates a test success log, uploads the test success log to the host, and continues to test the next test file.
In an embodiment of the present invention, the programmable processor is further configured to determine whether all of the other test files are tested;
if all the other test files are tested, uploading all the test success logs generated correspondingly to the host end, and reselecting other memories to be tested for testing;
if all the other test files are not tested, continuing to test and repeating the judgment until all the other test files are tested.
In an embodiment of the present invention, when the programmable processor determines that the memory under test fails, the programmable processor generates a test failure log and uploads the test failure log to the host.
In an embodiment of the present invention, the host side is further configured to analyze and classify the test log, and generate a fault summary list.
In an embodiment of the present invention, the host is further configured to perform probability distribution statistics on the fault summary list, so as to generate a fault test report.
The invention also provides a fault test method of the memory, comprising the following steps:
according to the type of the memory to be tested, carrying out corresponding interface resource allocation on the programmable processor to generate a multi-channel communication protocol;
the host end transmits a plurality of different test files with continuous numbers to the corresponding memory to be tested through the multi-channel communication protocol;
the memory to be tested is tested according to the corresponding test file, and a corresponding test result is generated;
the programmable processor generates a test log according to the test result; and
and the host end analyzes and performs statistical processing on the test log to generate a fault test report.
In one embodiment of the present invention, the step of generating the test log by the programmable processor according to the test result includes:
when the programmable processor determines that the memory to be tested passes the test, the programmable processor generates a test success log, uploads the test success log to the host end and continues the test of the next test file;
and when the programmable processor determines that the memory to be tested fails to pass, the programmable processor generates a test failure log and uploads the test failure log to the host side.
In an embodiment of the present invention, when the programmable processor determines that the test of the memory to be tested passes, the programmable processor generates a test success log, uploads the test success log to the host, and continues to perform the test of the next test file, including:
judging whether all other test files are tested;
if all the other test files are tested, uploading all the test success logs generated correspondingly to the host end, and reselecting other memories to be tested for testing;
if all the other test files are not tested, continuing to test and repeating the judgment until all the other test files are tested.
In an embodiment of the present invention, the step of generating the fault test report by the host end performing analysis and statistics processing on the test log includes:
analyzing and classifying the test logs to generate a fault summary list;
and carrying out probability distribution statistics on the fault summary list to generate a fault test report.
As described above, the invention provides a system and a method for testing faults of a memory, which can rapidly and comprehensively screen abnormal faults of the memory or memory particles, improve the classification precision of the fault test of the memory, and further improve the test efficiency of the memory.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory failure test system according to the present invention;
FIG. 2 is a schematic diagram of a user interface of the host side in FIG. 1;
FIG. 3 is a flow chart of a method for testing a memory failure according to the present invention;
fig. 4 is a schematic flow chart of step S40 in fig. 3;
fig. 5 is a schematic flow chart of step S41 in fig. 4;
fig. 6 is a schematic flow chart of step S50 in fig. 3.
Description of element numbers:
100. a fault test system; 110. a multifunctional test motherboard; 111. a memory to be tested; 112. a power module; 113. a programmable processor; 1131. a programmable logic unit; 1132. interconnecting resource units; 114. a serial bus unit;
120. a host end; 121. a user interface.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides a fault test system for a memory, which can be used for real-time testing of the difference of storage particles in the memory, so as to accurately classify the fault type of the memory, thereby improving the fault test efficiency of the memory. The fault testing system 100 may include, but is not limited to, a multi-function test motherboard 110 and a host side 120, and the multi-function test motherboard 110 is communicatively connected to the host side 120. Wherein the multi-function test motherboard 110 may be configured for communicative connection with a plurality of memories under test (Device Under Test, DUT) 111, and at least one memory granule may be disposed within each memory under test 111.
Referring to fig. 1, a plurality of Power modules (PWR) 112 may be further disposed in the multi-functional test motherboard 110, and the Power modules 112 are electrically connected to the memory 111 to be tested to supply Power to the memory 111 to be tested. For example, two power modules 112 may be disposed in the multifunctional test motherboard 110, and the two power modules 112 may be disposed at symmetrical ends of the multifunctional test motherboard 110, respectively, for supplying power to the memory 111 to be tested, and the two power modules 112 may be PWR1 and PWR2, respectively. However, the multifunctional test motherboard 110 is also provided with a programmable processor (Field-Programmable Gate Array, FPGA) 113, and the programmable processor 113 is electrically connected to the power module 112. The programmable processor 113 may be respectively connected to the memory 111 to be tested and the host 120 in a communication manner, so as to simulate various working modes of a multi-channel communication protocol of the memory 111 to be tested according to abundant interface resources, and accurately interconnect and interact with the memory 111 to be tested, thereby realizing effective device testing. For example, programmable processor 113 may simulate the Clock protocol (Clock), reset protocol (RST), DATA transfer protocols (DATA 0-DATA 7), and optional protocols (DATA Strobe) of memory under test 111, thereby generating a multi-channel communication protocol. The programmable processor 113 is a programmable processor that can be programmed to perform complex logic functions OR to make simple logic gates such as AND, OR, AND NOT gates, etc., as desired.
Referring to fig. 1, further, the programmable processor 113 may include a plurality of programmable logic units (Programmable Logic Unit, PLU) 1131, an interconnection resource unit (Interconnect Resources, IR) 1132, and a plurality of communication interfaces. The programmable logic unit 1131 is configured to perform corresponding interface resource allocation on the communication interface according to the type of the memory 111 to be tested, so as to generate a multi-channel communication protocol. The programmable logic unit 1131 may be further connected to the host 120 through a communication interface for receiving a plurality of different test files with serial numbers sent by the host 120, and transmitting the test files to the corresponding memory 111 to be tested through a multi-channel communication protocol for testing. After the memory 111 to be tested receives the test file, it can test according to the test file, and returns the test result to the programmable logic unit 1131 through the communication interface, and the programmable logic unit 1131 can generate a test log according to the test result.
Referring to fig. 1, further, test results may include, but are not limited to, a PASS test result (PASS) and a FAIL test result (FAIL), and test logs may include, but are not limited to, a test success log and a test failure log. When the programmable logic unit 1131 in the programmable processor 113 determines that the test of the memory 111 under test passes, the programmable logic unit 1131 may generate a test success log, upload the test success log to the host 120, and control the memory 111 under test to continue with the test of the next test file. In addition, the programmable logic unit 1131 is also configured to determine whether all other test files are tested. If all the tests of the other test files are completed, the programmable logic unit 1131 may upload all the test success logs generated correspondingly to the host 120, and after receiving the test success logs, the host 120 may reselect the other memories 111 to be tested for testing. If all the other test files are not tested, continuing to test and repeating the judgment until all the other test files are tested. When the programmable logic unit 1131 within the programmable processor 113 determines that the memory under test 111 fails the test, the programmable processor 113 may generate a test failure log and upload it to the host 120.
Referring to fig. 1, it should be further noted that the interconnection resource unit 1132 may be used to connect the programmable logic unit 1131, and the interconnection resources may include look-up tables (LUTs), flip-flops (Flip-flops), and routing resources for connecting various logic gates or functional blocks. By flexibly configuring these interconnected resources, highly complex functions, such as digital signal processing algorithms or data transfer operations, can be implemented. The communication interface may include, but is not limited to, an input interface and an output interface. The communication interface may be in communication connection with the memory 111 to be tested, and the communication interface is in bidirectional communication connection with the memory 111 to be tested, so as to send the test file to the memory 111 to be tested, and receive the test result of the memory 111 to be tested. In addition, by configuring the interface resource of the programmable processor 113, the programmable processor 113 can perform multi-channel communication protocol test like the memory 111 to be tested, so that one programmable processor 113 can be simultaneously connected with a plurality of memories 111 to be tested in a bidirectional communication manner.
Referring to fig. 1, the multifunctional test motherboard 110 further includes a serial bus unit (Universal Serial Bus, USB) 114, and the serial bus unit 114 can be respectively connected to the programmable processor 113 and the host 120 in a bidirectional communication manner, so as to realize data communication between the programmable processor 113 and the host 120. For example, the serial bus unit 114 may receive the test file sent by the host 120, send the test file to the programmable processor 113, and send the test file to the memory 111 to be tested through the programmable processor 113 for testing. In addition, after the to-be-tested memory 111 sends the test result to the programmable processor 113, the programmable processor 113 may generate a corresponding test log according to the test result, and upload the test log to the database of the host 120 for processing through the serial bus unit 114.
Referring to fig. 1, the host 120 may be communicatively connected to the programmable processor 113 in the multi-functional test motherboard 110, so as to issue a plurality of different test files with consecutive numbers to the corresponding memories 111 under test through a multi-channel communication protocol. However, the host 120 is also configured to receive the test log uploaded by the programmable processor 113, and perform analysis and statistics on the test log to generate a fault test report. The Test files may be sequentially defined as Test Pattern-1 to Pattern-x according to the numbers, i.e., the host 120 may sequentially issue the Test Pattern-1 to Pattern-x to the corresponding memory 111 to be tested for testing. In addition, the test file can be a test instruction, a test item or a test program, namely the test file is not particularly limited, as long as the test file can comprehensively cover the application scene of the application end of the actual client platform, and good products can be quickly and accurately screened out in the production line in advance. For example, test files Test Pattern-1 through Test Pattern-8 may be a basic command Test file, a tuning Test file, an initialization Test file, a specific environment Test file, a read-write Test file, a firmware update Test file, a power-down resume Test file, and a sleep/wake-up Test file, respectively.
Referring to fig. 1 and 2, further, the host 120 may be a computer (Personal Computer, PC), but not limited thereto, and may be other servers. The host side 120 is further configured to analyze and categorize the test log, generate a fault summary list, and perform probability distribution statistics on the fault summary list to generate a fault test report, where the fault summary list is shown in table 1. The fault summary list may include, but is Not limited to, a PASS result (PASS), a FAIL result (FAIL), and a Not Application (NA) result of the test file. A User Interface (UI) 121 may be disposed on the host side 120, and the User Interface 121 may include, but is not limited to, a memory to be tested selection module, a test file selection module, an image selection module, an analysis classification module, a test status module, and a distribution statistics module. That is, the corresponding module on the user interface 121 of the host 120 may be selected to implement the corresponding test of the memory 111 to be tested, thereby implementing the accurate fault classification of the memory 111 to be tested and improving the fault test efficiency.
Table 1: and (5) a fault summary list.
Referring to fig. 3, the present invention further provides a fault testing method for a memory, which can be applied to the fault testing system to perform fault testing on the memory and accurately classify the fault testing result. The fault test method corresponds to the fault test system in the embodiment one by one, and the fault test method may include the following steps:
and step S10, according to the type of the memory to be tested, carrying out corresponding interface resource allocation on the programmable processor so as to generate a multi-channel communication protocol.
Step S20, the host computer side transmits a plurality of different test files with continuous numbers to the corresponding memories to be tested through a multi-channel communication protocol.
And step S30, testing the memory to be tested according to the corresponding test file, and generating a corresponding test result.
And S40, the programmable processor generates a test log according to the test result.
And S50, the host computer side analyzes and performs statistical processing on the test log to generate a fault test report.
Referring to fig. 1 and 3, in an embodiment of the present invention, when step S10 is performed, the programmable processor 113 may be specifically communicatively connected to the memory under test 111 and the host 120, so as to simulate various operation modes of the multi-channel communication protocol of the memory under test 111 according to its abundant interface resources, and accurately interconnect and interact with the memory under test 111, thereby implementing effective device testing. For example, programmable processor 113 may simulate the Clock protocol (Clock), reset protocol (RST), DATA transfer protocols (DATA 0-DATA 7), and optional protocols (DATA Strobe) of memory under test 111, thereby generating a multi-channel communication protocol. The programmable processor 113 is a programmable processor that can be programmed to perform complex logic functions OR to make simple logic gates such as AND, OR, AND NOT gates, etc., as desired.
Referring to fig. 1 and 3, in an embodiment of the present invention, when step S20 is performed, the host 120 is specifically configured to be communicatively connected to the programmable processor 113 in the multi-functional test motherboard 110, so as to issue a plurality of different test files with consecutive numbers to the corresponding to-be-tested memories 111 through the multi-channel communication protocol. The Test files may be sequentially defined as Test Pattern-1 to Pattern-x according to the numbers, i.e., the host 120 may sequentially issue the Test Pattern-1 to Pattern-x to the corresponding memory 111 to be tested for testing. In addition, the test file can be a test instruction, a test item or a test program, namely the test file is not particularly limited, as long as the test file can comprehensively cover the application scene of the application end of the actual client platform, and good products can be quickly and accurately screened out in the production line in advance. For example, test files Test Pattern-1 through Test Pattern-8 may be a basic command Test file, a tuning Test file, an initialization Test file, a specific environment Test file, a read-write Test file, a firmware update Test file, a power-down resume Test file, and a sleep/wake-up Test file, respectively.
Referring to fig. 1 and 3, in one embodiment of the present invention, when step S30 is performed, the test results may include, but are not limited to, a test passing result and a non-test passing result, and the memory under test 111 may upload the test results to the programmable processor 113.
Referring to fig. 1 and 4, in one embodiment of the present invention, when step S40 is performed, specifically, step S40 may include the following steps:
and S41, when the programmable processor determines that the test of the memory to be tested passes, the programmable processor generates a test success log, uploads the test success log to the host end and continues the test of the next test file.
And step S42, when the programmable processor determines that the memory to be tested fails to pass the test, the programmable processor generates a test failure log and uploads the test failure log to the host side.
Referring to fig. 1 and 5, in one embodiment of the present invention, when step S41 is performed, specifically, step S41 may include the following steps:
step S411, judging whether all the other test files are tested.
And step S412, if all the other test files are tested, uploading all the test success logs generated correspondingly to the host end, and reselecting other memories to be tested for testing.
And step 413, if all the other test files are not tested, continuing the test, and repeating the judgment until all the other test files are tested.
In one embodiment of the present invention, when step S42 is performed, specifically, when the programmable logic unit 1131 in the programmable processor 113 determines that the test of the memory 111 under test passes, the programmable logic unit 1131 may generate a test success log, upload the test success log to the host 120, and control the memory 111 under test to continue to test the next test file. In addition, the programmable logic unit 1131 is also configured to determine whether all other test files are tested. If all the tests of the other test files are completed, the programmable logic unit 1131 may upload all the test success logs generated correspondingly to the host 120, and after receiving the test success logs, the host 120 may reselect the other memories 111 to be tested for testing. If all the other test files are not tested, continuing to test and repeating the judgment until all the other test files are tested. When the programmable logic unit 1131 in the programmable processor 113 determines that the memory under test 111 fails, the programmable processor 113 may generate a test failure log and upload the test failure log to the host 120 for analysis and statistics.
Referring to fig. 1 and 6, in one embodiment of the present invention, when step S50 is performed, specifically, step S50 may include the following steps:
and S51, analyzing and classifying the test logs to generate a fault summary list.
And S52, carrying out probability distribution statistics on the fault summary list to generate a fault test report.
In one embodiment of the present invention, when step S50 is performed, the analysis statistical process of the test log may be implemented by the host side 120 to generate a fault test report. The host 120 may be a computer (Personal Computer, PC), but is not limited thereto, and may be other servers. The host computer 120 is further configured to analyze and classify the test log, generate a fault summary list, and perform probability distribution statistics on the fault summary list to generate a fault test report. A User Interface (UI) 121 may be disposed on the host side 120, and the User Interface 121 may include, but is not limited to, a memory to be tested selection module, a test file selection module, an analysis classification module, a test status module, and a distribution statistics module. That is, the corresponding module on the user interface 121 of the host 120 may be selected to implement the corresponding test of the memory 110 to be tested, thereby implementing the accurate classification of the faults of the memory to be tested and improving the efficiency of the fault test.
In summary, by the system and the method for testing the faults of the memory, which are provided by the invention, the automatic screening of the memory can be realized, the memory or the storage particles with abnormal faults can be rapidly and comprehensively screened according to the fault test report, the classification precision of the fault test of the memory is improved, and the test efficiency of the memory is further improved.
In the description of the present specification, the descriptions of the terms "present embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A fault testing system for a memory, comprising:
the multi-functional test main board is configured to be in communication connection with a plurality of memories to be tested, wherein a programmable processor is arranged on the multi-functional test main board and is used for carrying out corresponding interface resource allocation according to the types of the memories to be tested so as to generate a multi-channel communication protocol; and
the host end is in communication connection with the programmable processor and is used for transmitting a plurality of different test files with continuous numbers to the corresponding memory to be tested through the multi-channel communication protocol;
the memory to be tested is used for testing according to the corresponding test file so as to generate a corresponding test result;
the programmable processor is also used for generating a test log according to the test result;
the host end is also used for analyzing and counting the test log to generate a fault test report.
2. The memory fault test system of claim 1, wherein when the programmable processor determines that the memory under test passes, the programmable processor generates a test success log, uploads it to the host side, and proceeds with testing of a next test file.
3. The memory fault testing system of claim 2, wherein the programmable processor is further configured to determine whether all other test files are tested;
if all the other test files are tested, uploading all the test success logs generated correspondingly to the host end, and reselecting other memories to be tested for testing;
if all the other test files are not tested, continuing to test and repeating the judgment until all the other test files are tested.
4. The memory failure test system of claim 1, wherein the programmable processor generates a test failure log and uploads it to the host side when the programmable processor determines that the memory under test fails.
5. The system of claim 1, wherein the host side is further configured to perform an analysis and categorization process on the test log to generate a fault summary list.
6. The system of claim 1, wherein the host is further configured to perform probability distribution statistics on the fault summary list to generate a fault test report.
7. A method for testing a memory for faults, comprising:
according to the type of the memory to be tested, carrying out corresponding interface resource allocation on the programmable processor to generate a multi-channel communication protocol;
the host end transmits a plurality of different test files with continuous numbers to the corresponding memory to be tested through the multi-channel communication protocol;
the memory to be tested is tested according to the corresponding test file, and a corresponding test result is generated;
the programmable processor generates a test log according to the test result; and
and the host end analyzes and performs statistical processing on the test log to generate a fault test report.
8. The method of claim 7, wherein the step of generating a test log from the test results by the programmable processor comprises:
when the programmable processor determines that the memory to be tested passes the test, the programmable processor generates a test success log, uploads the test success log to the host end and continues the test of the next test file;
and when the programmable processor determines that the memory to be tested fails to pass, the programmable processor generates a test failure log and uploads the test failure log to the host side.
9. The method according to claim 8, wherein when the programmable processor determines that the test of the memory under test passes, the programmable processor generates a test success log, uploads the test success log to the host side, and proceeds with the test of the next test file, comprising:
judging whether all other test files are tested;
if all the other test files are tested, uploading all the test success logs generated correspondingly to the host end, and reselecting other memories to be tested for testing;
if all the other test files are not tested, continuing to test and repeating the judgment until all the other test files are tested.
10. The method for testing a memory according to claim 7, wherein the step of generating the fault test report by performing an analysis and statistics process on the test log by the host side includes:
analyzing and classifying the test logs to generate a fault summary list;
and carrying out probability distribution statistics on the fault summary list to generate a fault test report.
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| CN202410094844.0A CN117608947B (en) | 2024-01-24 | 2024-01-24 | Fault testing system and method for memory |
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| CN202410094844.0A CN117608947B (en) | 2024-01-24 | 2024-01-24 | Fault testing system and method for memory |
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