CN117608868A - Clock generator, parameter adjustment method, system, device and medium - Google Patents

Clock generator, parameter adjustment method, system, device and medium Download PDF

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Publication number
CN117608868A
CN117608868A CN202410097172.9A CN202410097172A CN117608868A CN 117608868 A CN117608868 A CN 117608868A CN 202410097172 A CN202410097172 A CN 202410097172A CN 117608868 A CN117608868 A CN 117608868A
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frequency
target
clock signal
clock
frequency divider
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CN117608868B (en
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王代刚
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a clock generator, a parameter adjusting method, a parameter adjusting system, a parameter adjusting device and a parameter adjusting medium, relates to the field of clocks, and is used for solving the problem that the frequency of a clock signal generated by the clock generator is not adjustable. The scheme comprises a reference clock source and a clock processing circuit provided with a first frequency divider, wherein the first frequency divider is used for adjusting the frequency division coefficient of the first frequency divider according to a first target configuration instruction sent by a user; the clock processing circuit is used for carrying out frequency adjustment on the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider to obtain a target clock signal. The clock generator of the invention realizes flexible adjustment of the CPU clock to improve the performance of the CPU by allowing the user to adjust the frequency division coefficient and adjusting the frequency according to the requirement of the user, thereby meeting the user customization requirements of the server over-frequency application and the like and improving the advantages of the server product in competition.

Description

Clock generator, parameter adjustment method, system, device and medium
Technical Field
The present invention relates to the field of clocks, and in particular, to a clock generator, a parameter adjustment method, a parameter adjustment system, a parameter adjustment device, and a medium.
Background
Under the condition that the schemes of the competitive products of the CPU (Central Processing Unit ) of the current server manufacturers are consistent, improving the CPU performance becomes a key for enhancing the competitiveness of the server products. In this case, the most direct and effective way is to raise the operating frequency of the CPU, i.e. to use the CPU over-frequently. However, the standardized clock generator chip collocated with the CPU of the current platform can only output fixed standard frequency points, and cannot moderately adjust the CPU clock according to the requirements so as to improve the performance of the CPU.
Because the output frequency of the conventional standardized clock generator chip cannot be flexibly adjusted, the output frequency cannot be adjusted within an allowable range to meet the user customization requirements of server over-frequency application and the like, the flexible improvement of CPU performance is limited, and the server product is limited to play a larger advantage in competition.
Disclosure of Invention
The invention aims to provide a clock generator, a parameter adjusting method, a parameter adjusting system, a parameter adjusting device and a parameter adjusting medium, which are used for realizing flexible adjustment of a CPU clock to improve the performance of the CPU when the clock generator is applied to the CPU by allowing a user to adjust a frequency dividing coefficient and adjusting the frequency according to the requirement of the user, and can meet the user customization requirements of server over-frequency application and the like so as to improve the advantages of server products in competition.
In order to solve the above technical problems, the present invention provides a clock generator, including:
a reference clock source for outputting a reference clock signal at a first frequency;
the clock processing circuit is provided with a first frequency divider and is connected with the reference clock source;
the first frequency divider is used for adjusting the frequency division coefficient of the first frequency divider according to a first target configuration instruction sent by a user;
the clock processing circuit is used for carrying out frequency adjustment on the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider to obtain a target clock signal.
In one embodiment, the clock processing circuit further comprises:
the phase-locked loop circuit is connected with the reference clock source, and the first frequency divider is connected with the phase-locked loop circuit;
the phase-locked loop circuit is used for carrying out frequency adjustment on the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider to obtain the target clock signal.
In one embodiment, the phase-locked loop circuit is specifically configured to multiply the frequency of the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider, so as to obtain a first clock signal after frequency multiplication;
The clock processing circuit further includes:
the frequency dividing circuit is connected with the phase-locked loop circuit;
the frequency dividing circuit is used for dividing the frequency of the first clock signal by a preset multiple to obtain the target clock signal.
In one embodiment, the clock processing circuit further comprises a reference frequency divider provided with a reference frequency division coefficient, and the phase-locked loop circuit comprises a phase comparator, a loop filter and a voltage-controlled oscillator;
the input end of the reference frequency divider is connected with the reference clock source, the input end of the phase comparator is respectively connected with the output end of the reference frequency divider and the output end of the first frequency divider, the output end of the phase comparator is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, and the output end of the loop filter is connected with the input end of the first frequency divider;
the reference frequency divider divides the frequency of the reference clock signal according to the reference frequency division coefficient, the phase comparator determines a clock error according to the clock signal output by the reference frequency divider and the clock signal output by the first frequency divider and inputs the clock error to the voltage-controlled oscillator, and the voltage-controlled oscillator adjusts the control voltage of the voltage-controlled oscillator according to the clock error so as to adjust the frequency of the first clock signal of the clock signal output by the voltage-controlled oscillator.
In one embodiment, when the number of the phase-locked loop circuits is plural, the plural phase-locked loop circuits are connected to the plural first frequency dividers in a one-to-one correspondence.
In one embodiment, further comprising:
the first configuration register is connected with the first frequency divider and is used for storing a first target frequency division coefficient corresponding to the first target configuration instruction;
the first frequency divider is specifically configured to adjust its frequency division coefficient to the first target frequency division coefficient according to the first target frequency division coefficient in the first configuration register.
In one embodiment, the frequency dividing circuit includes:
and the integer frequency divider is connected with the phase-locked loop circuit and is used for dividing the frequency of the first clock signal by a preset integer multiple to obtain the target clock signal.
In one embodiment, the division factor of the integer divider is correspondingly adjusted according to a second target configuration instruction sent by the user.
In one embodiment, the frequency dividing circuit further comprises:
the second configuration register is connected with the integer frequency divider and is used for storing a second target frequency division coefficient corresponding to the second target configuration instruction, and the second target frequency division coefficient is an integer;
The integer frequency divider is specifically configured to adjust its frequency division coefficient to the second target frequency division coefficient according to the second target frequency division coefficient in the second configuration register.
In one embodiment, the frequency dividing circuit includes:
and the decimal frequency divider is connected with the phase-locked loop circuit and is used for dividing the frequency of the first clock signal by preset decimal times to obtain the target clock signal.
In one embodiment, the division factor of the fractional divider is correspondingly adjusted according to a third target configuration instruction sent by the user.
In one embodiment, the frequency dividing circuit further comprises:
the third configuration register is connected with the fractional frequency divider and is used for storing a third target frequency division coefficient corresponding to the third target configuration instruction, and the third target frequency division coefficient is a fractional number;
the fractional frequency divider is specifically configured to adjust its frequency division coefficient to the third target frequency division coefficient according to the third target frequency division coefficient in the third configuration register.
In one embodiment, the clock processing circuit further comprises:
and the first multiplexer is connected with the integer frequency divider and the fractional frequency divider and is used for conducting a channel corresponding to the integer frequency divider or the fractional frequency divider according to user requirements so as to output a target clock signal output by the integer frequency divider or the fractional frequency divider.
In one embodiment, the first multiplexer is specifically configured to select, according to configuration information input by a user, a channel corresponding to the integer frequency divider or the fractional frequency divider to be turned on, and if the frequency of the clock signal output by the first multiplexer is the target frequency corresponding to the target clock signal, directly take the clock signal output by the first multiplexer as the target clock signal; if the frequency of the clock signal output by the frequency divider reaches a frequency threshold, selecting a channel corresponding to the fractional frequency divider to conduct so that the fractional frequency divider adjusts the frequency of the clock signal output by the frequency divider to the target frequency;
the configuration information input by the user is determined according to the target frequency, and the frequency threshold is any value within a preset range of the target frequency.
In one embodiment, the clock processing circuit further includes a phase adjustment phase-locked loop circuit having an input for inputting a clock signal of another device, the phase adjustment phase-locked loop circuit being configured to perform a detector adjustment on a phase of the clock signal of the other device to output a clock signal synchronized with the target clock signal.
In one embodiment, further comprising:
And the second multiplexer is connected with the integer frequency divider, the fractional frequency divider and the phase adjustment phase-locked loop circuit and is used for conducting a channel corresponding to the integer frequency divider, the fractional frequency divider or the phase adjustment phase-locked loop circuit according to user requirements so as to output a clock signal output by the integer frequency divider, the fractional frequency divider or the phase adjustment phase-locked loop circuit.
In order to solve the technical problem, the invention also provides a parameter adjusting method of the clock generator, which is applied to the clock generator and comprises the following steps:
acquiring a first target configuration instruction sent by a user;
analyzing the first target configuration instruction to obtain a first target frequency division coefficient;
and adjusting the frequency division coefficient of the first frequency divider to be the first target frequency division coefficient, so that the clock processing circuit carries out frequency adjustment on the reference clock signal of the first frequency based on the first target frequency division coefficient to obtain a target clock signal.
In one embodiment, the clock generator further comprises a first configuration register coupled to the first frequency divider; analyzing the first target configuration instruction to obtain a first target frequency division coefficient, and then further comprising:
Writing the first target frequency division coefficient into the first configuration register;
adjusting the frequency division coefficient of the first frequency divider to the first target frequency division coefficient comprises:
and refreshing the first target frequency division coefficient stored in the first configuration register to the first frequency divider when a parameter refreshing instruction is received.
In order to solve the technical problem, the invention also provides a parameter adjusting system of the clock generator, which is applied to the clock generator and comprises:
the instruction acquisition unit is used for acquiring a first target configuration instruction sent by a user;
the analysis unit is used for analyzing the first target configuration instruction to obtain a first target frequency division coefficient;
and the parameter adjusting unit is used for adjusting the frequency dividing coefficient of the first frequency divider to the first target frequency dividing coefficient so that the clock processing circuit can carry out frequency adjustment on the reference clock signal with the first frequency based on the first target frequency dividing coefficient to obtain a target clock signal.
In order to solve the technical problem, the invention also provides a parameter adjusting device of the clock generator, which comprises:
a memory for storing a computer program;
And the processor is used for realizing the steps of the parameter adjustment method of the clock generator when executing the computer program.
In order to solve the above technical problem, the present invention further provides a computer readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method for adjusting parameters of a clock generator described above.
The invention provides a clock generator, a parameter adjusting method, a parameter adjusting system, a parameter adjusting device and a parameter adjusting medium, relates to the field of clocks, and solves the problem that the frequency of a clock signal generated by the clock generator is not adjustable. The scheme comprises a reference clock source and a clock processing circuit provided with a first frequency divider, wherein the first frequency divider is used for adjusting the frequency division coefficient of the first frequency divider according to a first target configuration instruction sent by a user; the clock processing circuit is used for carrying out frequency adjustment on the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider to obtain a target clock signal. Therefore, the clock generator of the invention realizes flexible adjustment of the CPU clock to improve the performance of the CPU by allowing the user to adjust the frequency division coefficient and adjusting the frequency according to the requirement of the user, and can meet the user customization requirements of the server over-frequency application and the like to improve the advantage of the server product in competition.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a clock generator according to the present invention;
fig. 2 is a schematic diagram of a phase-locked loop circuit according to the present invention;
FIG. 3 is a schematic diagram of a chip of a clock generator according to the present invention;
FIG. 4 is a flowchart of a method for adjusting parameters of a clock generator according to the present invention;
fig. 5 is a flowchart of a parameter adjusting system of a clock generator according to the present invention.
Detailed Description
The core of the invention is to provide a clock generator, a parameter adjusting method, a system, a device and a medium, which allow a user to adjust a frequency division coefficient and adjust the frequency according to the requirement of the user, so that when the clock is applied to a CPU, the CPU clock is flexibly adjusted to improve the performance of the CPU, the customized requirements of the server such as over-frequency application and the like can be met, and the advantage of the server product in competition is improved.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the present invention provides a clock generator including:
a reference clock source 11 for outputting a reference clock signal of a first frequency;
a clock processing circuit 12 provided with a first frequency divider 13, connected to the reference clock source 11;
the first frequency divider 13 is used for adjusting the frequency division coefficient of the first frequency divider according to a first target configuration instruction sent by a user;
the clock processing circuit 12 is configured to perform frequency adjustment on the reference clock signal with the first frequency according to the frequency division coefficient of the first frequency divider 13, so as to obtain a target clock signal.
This embodiment describes a clock generator comprising the following components: a reference clock source 11, a first frequency divider 13 and a clock processing circuit 12. The clock generator aims to flexibly adjust the CPU clock to improve the performance of the CPU, and meet the user customization requirements of server over-frequency application and the like so as to enhance the advantages of server products in competition.
First, the clock generator comprises a reference clock source 11 for outputting a reference clock signal of a first frequency, which can be used as a reference signal for subsequent frequency adjustment. Next, the clock generator further comprises a clock processing circuit 12 provided with a first frequency divider 13, the clock processing circuit 12 being connected to the reference clock source 11, the first frequency divider 13 being capable of adjusting its frequency division factor according to a first target configuration command sent by a user, and the frequency of the reference clock signal of the first frequency being capable of being changed by changing the frequency division factor. Finally, the clock processing circuit 12 uses the frequency division coefficient of the first frequency divider 13 to perform frequency adjustment on the reference clock signal of the first frequency, so as to obtain the target clock signal, and thus the target clock signal can be flexibly adjusted according to the requirement of the user, so as to achieve the improvement of the performance of the CPU clock.
Through the design, the clock generator allows a user to adjust the frequency division coefficient and adjusts the frequency according to the requirement of the user, so that the user customization requirements of the server over-frequency application and the like are met. This provides a flexible way to boost the performance of the CPU and enhance the advantages of server products in competition.
In one embodiment, clock processing circuit 12 includes: the phase-locked loop circuit is connected with the reference clock source 11, and the first frequency divider 13 is connected with the phase-locked loop circuit; the phase-locked loop circuit is used for performing frequency adjustment on the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider 13 to obtain a target clock signal.
The embodiment describes a specific implementation manner of a clock generator, and mainly adds a phase-locked loop circuit to perform frequency adjustment on a reference clock signal with a first frequency to obtain a target clock signal. In this embodiment, the clock processing circuit 12 includes a phase-locked loop circuit connected to the reference clock source 11, and the first frequency divider 13 is connected to the phase-locked loop circuit, which can frequency-adjust the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider 13, thereby obtaining the target clock signal. A phase locked loop circuit is a circuit that can be used to generate a stable high frequency clock signal or extract a specific frequency from an existing clock signal, has self-adaptation and stability, and can perform accurate frequency adjustment on an input clock signal within a certain range. By adding the phase-locked loop circuit in the clock generator, the frequency of the reference clock signal can be adjusted more accurately, and a more stable and accurate target clock signal can be obtained, which is helpful for improving the performance of the CPU and meeting the user customization demands of the server over-frequency application and the like.
In one embodiment, the pll circuit is specifically configured to multiply the reference clock signal of the first frequency according to the division coefficient of the first frequency divider 13 to obtain a first clock signal after frequency multiplication; the clock processing circuit 12 further includes: the frequency dividing circuit is connected with the phase-locked loop circuit; the frequency dividing circuit is used for dividing the frequency of the first clock signal by a preset multiple to obtain a target clock signal.
In this embodiment, the pll circuit is specifically configured to multiply a reference clock signal of a first frequency to obtain a first clock signal after frequency multiplication; correspondingly, the clock processing circuit 12 further includes a frequency dividing circuit, which is connected to the phase-locked loop circuit and is configured to divide the frequency of the multiplied first clock signal by a preset multiple, so as to obtain the target clock signal. In such an embodiment, the phase-locked loop circuit first multiplies the reference clock signal to obtain a high frequency first clock signal. Then, the frequency dividing circuit divides the high-frequency first clock signal by a preset multiple to obtain a target clock signal required by a user. By such a design, the clock generator can more flexibly generate the target clock signal according with the requirements of users. The phase-locked loop circuit provides a frequency multiplication function, and can boost an input clock signal to a higher frequency, and the frequency division circuit can divide the frequency of the high-frequency clock signal according to the required frequency according to the configuration of a user so as to obtain an accurate target clock signal. The mode of the embodiment provides higher flexibility and customizable, and can meet the clock signal generation requirements in more different scenes; therefore, it has wide application prospect in high-performance computing, communication equipment and other fields requiring high-frequency clock signals.
As shown in fig. 2, in one embodiment, the clock processing circuit further includes a reference frequency divider provided with a reference frequency division coefficient, and the phase-locked loop circuit includes a phase comparator, a loop filter, and a voltage-controlled oscillator; the input end of the reference frequency divider is connected with the reference clock source 11, the input end of the phase comparator is respectively connected with the output end of the reference frequency divider and the output end of the first frequency divider 13, the output end of the phase comparator is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, and the output end of the loop filter is connected with the input end of the first frequency divider 13; the reference frequency divider divides the frequency of the reference clock signal according to the reference frequency division coefficient, the phase comparator determines a clock error according to the clock signal output by the reference frequency divider and the clock signal output by the first frequency divider 13 and inputs the clock error to the voltage-controlled oscillator, and the voltage-controlled oscillator adjusts the control voltage of the voltage-controlled oscillator according to the clock error so as to adjust the frequency of the first clock signal of the clock signal output by the voltage-controlled oscillator.
The present embodiment mainly describes specific components and operation principles of a phase-locked loop circuit, which in this embodiment includes a phase comparator, a loop filter, and a voltage-controlled oscillator. The input of the reference frequency divider is connected to a reference clock source 11 for dividing the reference clock signal. The input end of the phase comparator is respectively connected with the output end of the reference frequency divider and the output end of the first frequency divider 13, and is used for comparing the phase difference of two input clock signals so as to determine the clock error. The output signal of the phase comparator is transmitted to the input end of the loop filter, and is input to the input end of the voltage-controlled oscillator after being filtered. The voltage-controlled oscillator adjusts its own control voltage according to the clock error to adjust the frequency of the output clock signal.
Specifically, the reference frequency divider divides the input reference clock signal, and the phase comparator compares the clock signal output from the reference frequency divider with the clock signal output from the first frequency divider 13 in phase. If the phase difference of the two input signals is greater than 0, the period of the reference clock signal is longer than the period of the first clock signal, and the phase comparator outputs a positive clock error; conversely, if the two input signals have a phase difference less than 0, indicating that the period of the reference clock signal is shorter than the period of the first clock signal, the phase comparator outputs a negative clock error. The clock error signal is filtered by the loop filter and then transmitted to the input end of the voltage-controlled oscillator. The voltage-controlled oscillator adjusts its own control voltage according to the clock error signal to adjust the frequency of the output clock signal. When the clock error is positive, the voltage-controlled oscillator increases the control voltage to increase the frequency of the output clock signal; conversely, when the clock error is negative, the voltage controlled oscillator reduces the control voltage to reduce the frequency of the output clock signal.
Here, assuming that the frequency of the clock signal output from the reference clock source 11 is f0, the frequency of the clock signal after passing through the reference frequency divider (reference frequency division coefficient is M) is fm, the frequency division coefficient of the first frequency divider 13 is N, the frequency of the clock signal after dividing the clock signal (frequency is f) output from the voltage-controlled oscillator is fn, when the loop is locked, fm=fn is present, since fm=f0/M, fn=f/N is present, f= (n×f0)/M is present, and signals of different frequencies can be output by changing the frequency division coefficient N of the first frequency divider 13.
In this way, the phase-locked loop circuit can adjust the frequency of the output clock signal according to the phase difference between the reference clock signal and the clock signal output by the first frequency divider 13, so as to realize accurate timing of the target clock signal, and the phase-locked loop circuit in this embodiment has better stability and accuracy.
In one embodiment, when the number of the phase-locked loop circuits is plural, plural phase-locked loop circuits are connected to plural first frequency dividers 13 in one-to-one correspondence.
In this embodiment, when the number of phase-locked loop circuits is plural, the plural phase-locked loop circuits are connected to the plural first frequency dividers in one-to-one correspondence. I.e. each phase-locked loop circuit is provided with a first frequency divider 13 connected to itself. This means that more complex clock signal generation and frequency adjustment can be achieved in the clock generator by using multiple phase locked loop circuits. Each phase-locked loop circuit can be independently frequency-adjusted, so that a plurality of target clock signals with different frequencies can be generated simultaneously. The design can provide more flexible and diversified clock signal output for different application scenes, and meets wider use requirements.
In addition, the arrangement of a plurality of phase-locked loop circuits can also improve the stability and reliability of the clock generator. Even if one phase-locked loop circuit has a problem or a fault, other phase-locked loop circuits can still work normally, and continuous and stable output of clock signals is ensured. Therefore, the design of the embodiment not only provides more clock signal output options, but also enhances the reliability and stability of the clock generator and improves the reliability of the clock generator in practical application.
In one embodiment, further comprising: a first configuration register, connected to the first frequency divider 13, for storing a first target frequency division coefficient corresponding to the first target configuration instruction; the first frequency divider 13 is specifically configured to adjust its frequency division coefficient to a first target frequency division coefficient according to the first target frequency division coefficient in the first configuration register.
This embodiment describes a specific implementation in a clock generator comprising a first configuration register and a first frequency divider 13. In this embodiment, the first configuration register is connected to the first frequency divider 13, and is configured to store a first target frequency division coefficient corresponding to the first target configuration instruction, where the first target frequency division coefficient is a frequency division ratio between a target frequency specified in the configuration instruction sent by the user and the reference clock frequency, and by adjusting the frequency division coefficient of the first frequency divider 13, accurate control of the target clock signal can be achieved.
Specifically, when the user sends the first target configuration instruction, the instruction includes a frequency division ratio between the target frequency and the reference clock frequency. This frequency division ratio is stored in a first configuration register for subsequent use. The first frequency divider 13 adjusts its own frequency division coefficient to a corresponding target frequency division coefficient according to the first target frequency division coefficient stored in the first configuration register. By changing the frequency division coefficient, the first frequency divider 13 can divide the input reference clock signal, thereby obtaining the target clock signal.
By combining the first configuration register and the first frequency divider 13, the clock generator can adjust the frequency division coefficient of the first frequency divider 13 according to the configuration instruction sent by the user, so that accurate frequency adjustment of the target clock signal is realized, and the flexibility and the customizability enable the clock generator to meet various requirements in different application scenes.
In one embodiment, a frequency dividing circuit includes: and the integer frequency divider is connected with the phase-locked loop circuit and is used for dividing the frequency of the first clock signal by a preset integer multiple to obtain a target clock signal.
In this embodiment, the frequency divider circuit includes an integer divider coupled to a phase-locked loop circuit. The integer frequency divider is used for dividing the first clock signal by a preset integer multiple so as to obtain a target clock signal. Specifically, the integer divider may perform an integer division operation on the first clock signal according to a preset integer division coefficient, so as to obtain the target clock signal, where the frequency of the target clock signal is an integer multiple of the frequency of the first clock signal. The design of the integer divider ensures accurate control and adjustment of the clock signal to meet specific application requirements. The function of the integer frequency divider is to adjust the frequency of the clock signal to adapt to specific application situations, such as the fields of communication systems, digital signal processing and the like.
In one embodiment, the division factor of the integer divider is correspondingly adjusted according to the second target configuration instruction sent by the user.
In such an embodiment, the division factor of the integer divider is correspondingly adjusted in accordance with the second target configuration instruction sent by the user. In other words, the user can change the frequency of the target clock signal by sending a specific instruction to adjust the division factor of the integer divider. This design allows for a more flexible configuration of the clock generator, and the user can dynamically adjust the division factor of the integer divider as needed to achieve the desired target clock signal. The configuration mode can be suitable for different application scenes, and the applicability and flexibility of the clock generator are improved.
In one embodiment, the frequency dividing circuit further comprises: the second configuration register is connected with the integer frequency divider and used for storing a second target frequency division coefficient corresponding to the second target configuration instruction, and the second target frequency division coefficient is an integer; the integer frequency divider is specifically configured to adjust its frequency division coefficient to a second target frequency division coefficient according to the second target frequency division coefficient in the second configuration register.
In this embodiment, the frequency dividing circuit further includes a second configuration register connected to the integer divider and configured to store a second target frequency division coefficient corresponding to the second target configuration instruction. The second target frequency division coefficient is an integer, and the integer frequency divider adjusts its own frequency division coefficient by using the second target frequency division coefficient in the second configuration register to realize the setting of the second target frequency division coefficient. In other words, when the user sends the second target configuration instruction, the integer divider automatically adjusts its own frequency division coefficient according to the second target frequency division coefficient stored in the second configuration register, so as to obtain the target clock signal meeting the user requirement. Therefore, a user can adjust the frequency division coefficient of the clock generator by sending a configuration instruction so as to meet different application requirements, and the flexibility and the adjustability enable the clock generator to be more suitable for different application scenes.
In one embodiment, a frequency dividing circuit includes: and the fractional frequency divider is connected with the phase-locked loop circuit and is used for dividing the frequency of the first clock signal by preset fractional times to obtain a target clock signal.
In this embodiment, the frequency dividing circuit may further be provided with a fractional frequency divider, where the fractional frequency divider is connected to the phase-locked loop circuit, and the fractional frequency divider is configured to divide the first clock signal by a preset fractional multiple to obtain the target clock signal. This means that the fractional divider can make a frequency adjustment of a non-integer multiple of the clock signal, thereby enabling finer clock frequency adjustments.
In practical applications, the fractional divider can implement a tiny frequency adjustment by setting a fractional division coefficient to meet specific clock requirements. For example, when the frequency of the clock signal needs to be fine-tuned to match other system components, the fractional divider may provide finer tuning capabilities so that the target clock signal can accurately meet the system requirements.
In one embodiment, the division factor of the fractional divider is correspondingly adjusted according to a third target configuration instruction sent by the user.
In this embodiment, the division coefficient of the fractional divider is correspondingly adjusted according to the third target configuration instruction sent by the user. In other words, the fractional divider may adjust the division factor according to a configuration instruction sent by a user to achieve precise control over the target clock signal. The design enables the clock generator to dynamically adjust the frequency of the output clock signal according to the requirements of users, thereby meeting different application scenes and requirements.
In one embodiment, the frequency dividing circuit further comprises: the third configuration register is connected with the fractional frequency divider and is used for storing a third target frequency division coefficient corresponding to the third target configuration instruction, and the third target frequency division coefficient is fractional; the fractional frequency divider is specifically configured to adjust its frequency division coefficient to a third target frequency division coefficient according to the third target frequency division coefficient in the third configuration register.
In this embodiment, the frequency dividing circuit includes a fractional frequency divider and a third configuration register, where the fractional frequency divider is connected to the phase-locked loop circuit and is used to divide the first clock signal by a preset fractional multiple to obtain the target clock signal, and the third configuration register is connected to the fractional frequency divider and is used to store a third target frequency division coefficient corresponding to a third target configuration instruction sent by a user, where the parameter is a fractional value. The fractional frequency divider is specifically configured to adjust its frequency division coefficient to a third target frequency division coefficient according to the third target frequency division coefficient in the third configuration register.
In other words, the user can request the clock generator to output a specific target clock signal by sending a third target configuration instruction, and the frequency adjustment of the target clock signal is realized by the fractional divider, and by adjusting the third target frequency division coefficient in the third configuration register, the user can precisely control the frequency division coefficient of the fractional divider, thereby obtaining the target clock signal meeting the requirement, and the design can meet the specific requirement of the user on the output frequency of the clock generator, and improves the flexibility and applicability of the clock generator.
In one embodiment, the first multiplexer is specifically configured to select a channel corresponding to the integer frequency divider or the fractional frequency divider for conduction according to the input configuration information, and if the frequency of the clock signal output by the first multiplexer is the target frequency corresponding to the target clock signal, the clock signal output by the first multiplexer is directly used as the target clock signal; if the frequency of the clock signal output by the frequency divider reaches the frequency threshold, selecting a channel corresponding to the fractional frequency divider to conduct so that the fractional frequency divider adjusts the frequency of the clock signal output by the frequency divider to the target frequency; the configuration information input by the user is determined according to the target frequency, and the frequency threshold is any value within a preset range of the target frequency.
In this embodiment, the target frequency of the target clock signal is first determined according to the user requirement, and then configuration information is determined according to the target frequency, so as to configure the first multiplexer, and the first multiplexer is triggered to select the integer frequency divider or the fractional frequency divider to conduct the channel, so that the integer frequency divider or the fractional frequency divider performs frequency division processing on the clock signal output by the phase-locked loop circuit, and when the frequency of the clock signal output by the first multiplexer is exactly the target frequency, the clock signal is directly output by the first multiplexer without adjustment; however, if the frequency of the clock signal output by the first multiplexer cannot be exactly adjusted to the target frequency, but is at the frequency threshold value within the target frequency range, the frequency of the clock signal is finely adjusted by switching to the fractional divider at this time, so that the frequency of the clock signal reaches the target frequency.
That is, configuring the first multiplexer to select either the gated integer divider output or the fractional divider output based on the configuration information is essentially a selective adjustment of the step size. It should be noted that, whether the user selects a large step adjustment mode (i.e., selecting an integer divider output) or a small step adjustment mode (i.e., selecting a fractional divider output) at the beginning, the user automatically switches to the small step adjustment mode (i.e., selecting the fractional divider output) once the frequency threshold is exceeded, so as to prevent that a larger adjustment step near the upper limit of the target frequency adjustment will easily cause the frequency to exceed the standard.
In one embodiment, the clock processing circuit 12 further includes a phase-adjusting phase-locked loop circuit having an input for inputting the clock signal of the other device, and the phase-adjusting phase-locked loop circuit is configured to perform detector adjustment on the phase of the clock signal of the other device to output the clock signal synchronized with the target clock signal.
The phase adjustment phase-locked loop circuit has the main functions of keeping the output clock signal and the target clock signal synchronous by comparing the phase difference between the clock signals of other devices and the target clock signal and performing feedback adjustment according to the phase difference. The specific operation is as follows: the phase adjustment phase-locked loop circuit receives clock signals and target clock signals of other devices as inputs; by comparing the phase differences of the two signals, the phase-locked loop circuit can calculate the phase offset; the phase-locked loop circuit generates an error signal according to the phase offset and inputs the error signal as a feedback signal to the phase adjustment circuit; the phase adjusting circuit adjusts the phase of the clock signals of other devices according to the error signal so as to keep synchronous with the target clock signal; the adjusted clock signal output is used as a target clock signal of a clock generator and can be used for driving other circuits or devices. The clock generator can realize the phase synchronization of clock signals of other devices through the operation of the phase-adjusting phase-locked loop circuit, and the time sequence consistency and coordination among all systems are ensured. This is important for application scenarios where multiple clock signals are required to co-operate, such as in communication systems, data transmission or in measurement instruments where synchronous sampling is required.
In one embodiment, further comprising: the second multiplexer is connected with the integer frequency divider, the fractional frequency divider and the phase adjustment phase-locked loop circuit and is used for conducting a corresponding channel of the integer frequency divider or the fractional frequency divider or the phase adjustment phase-locked loop circuit according to user requirements so as to output a clock signal output by the integer frequency divider or the fractional frequency divider or the phase adjustment phase-locked loop circuit. In short, the second multiplexer may switch different clock signal paths according to the user's requirement, so as to select the clock signal output by the integer divider, the fractional divider or the phase-adjusting phase-locked loop circuit. Such a design allows a user to select different clock signal processing paths according to specific requirements to obtain a target clock signal that meets specific requirements.
As shown in fig. 3, one embodiment of the present invention is described as follows: the clock generator chip is a CK440Q clock generator, and the embodiment is mainly a clock generator chip which is further improved on the CK440Q clock generator chip so as to realize that the clock generator chip can be compatible with CK440Q standard requirements, the output clock signal frequency is adjustable within a reasonable range, and the clock generator chip can meet the requirement of over-frequency application of server products. Specifically, in this embodiment, frequency dividers with adjustable frequency division coefficients are added to both SSC PLL (Spread Spectrum Clock Phase-Locked Loop) and pft_pi+filter_pll, so as to meet the requirement of adjustable frequency division coefficients. The first multiplexer on the left side is used for selecting which clock signal is input, when the xin_clkin input signal is input, the clock signal of the path is selected to be input to the SSC PLL, when the pft_in (Platform Time Input, the platform time input) is input to a chip transmitted by another chip, the pft_pi+filter_pll (this module is the phase adjustment phase-locked loop circuit described In the above embodiment) detects the phase, and the clock signal is synchronously locked and then output, and at this time, the clock signal output by the pft_pi+filter_pll is used by the multiplexer on the left side to be transmitted to the SSC PLL. A fractional divider and an integer divider are also provided in the chip to increase the frequency range of the outputtable clock signal, and in addition, a multiplexer is used to select the clock signal of the desired frequency for output. The clock signal may be multiplexed according to the requirement, which is not limited in this embodiment.
In order to solve the above technical problems, as shown in fig. 4, the present invention further provides a method for adjusting parameters of a clock generator, which is applied to the clock generator, and includes:
s11: acquiring a first target configuration instruction sent by a user;
in this embodiment, first, a first target configuration instruction sent by a user needs to be acquired. The user may send the configuration instructions in various ways, such as by way of a software interface input, an external interface transmission, etc. The configuration instructions may include a target division factor that the user wishes to adjust, such as a target clock signal that the user wishes to have a particular frequency. After the configuration instruction is obtained, subsequent analysis and processing can be performed.
Through the step, the parameters of the clock generator can be adjusted in real time according to the user demands, so that the clock generator outputs a target clock signal meeting the user demands.
S12: analyzing the first target configuration instruction to obtain a first target frequency division coefficient;
in this step, the clock generator receives the first target configuration instruction sent by the user and parses the first target configuration instruction into a corresponding first target frequency division coefficient. Specifically, the clock generator analyzes and processes the instruction according to the format and content of the instruction to obtain the value of the first target frequency division coefficient to be set. This value will be used in subsequent operations to adjust the divider's divide ratio to achieve the user-specified target clock frequency.
S13: and adjusting the frequency division coefficient of the first frequency divider to be a first target frequency division coefficient, so that the clock processing circuit carries out frequency adjustment on the reference clock signal of the first frequency based on the first target frequency division coefficient to obtain a target clock signal.
In this step, the first target division factor resolved according to the first target configuration instruction sent by the user will be used to adjust the division factor of the first frequency divider. With this adjustment, the clock processing circuit can frequency adjust the reference clock signal according to the new frequency division coefficient to generate the target clock signal. Therefore, the frequency output of the clock generator can be adjusted according to the requirements of users, and accurate control and adjustment of clock signals are realized.
In one embodiment, the clock generator further comprises a first configuration register coupled to the first divider; analyzing the first target configuration instruction to obtain a first target frequency division coefficient, and then further comprising:
writing a first target frequency division coefficient into a first configuration register;
adjusting the division factor of the first frequency divider to a first target division factor includes:
and refreshing the first target frequency division coefficient stored in the first configuration register to the first frequency divider when the parameter refreshing instruction is received.
In this embodiment, specific implementation steps of a parameter adjustment method of a clock generator are described. The clock generator also comprises a first configuration register connected with the first frequency divider, and after the first target frequency division coefficient is obtained through analysis, the frequency division coefficient is written into the first configuration register; and then when a parameter refreshing instruction is received, refreshing the first target frequency division coefficient stored in the first configuration register into the first frequency divider, thereby realizing dynamic adjustment and updating of the parameters of the clock generator.
The parameter adjustment method can enable a user to realize parameter adjustment of the clock generator by sending the configuration instruction, and achieves flexibility and customizability of the clock generator. Meanwhile, by combining the configuration register and the parameter refreshing instruction, the real-time updating and dynamic adjustment of parameters are realized, and the real-time performance and stability of the clock generator are improved.
In order to solve the above technical problems, as shown in fig. 5, the present invention further provides a parameter adjustment system of a clock generator, which is applied to the clock generator, and includes:
an instruction obtaining unit 51, configured to obtain a first target configuration instruction sent by a user;
the parsing unit 52 is configured to parse the first target configuration instruction to obtain a first target frequency division coefficient;
The parameter adjusting unit 53 is configured to adjust the frequency division coefficient of the first frequency divider to a first target frequency division coefficient according to the first target frequency division coefficient, so that the clock processing circuit performs frequency adjustment on the reference clock signal with the first frequency based on the first target frequency division coefficient to obtain the target clock signal.
In one embodiment, further comprising:
the writing unit is used for writing the first target frequency division coefficient into the first configuration register;
and the parameter adjusting unit is specifically used for refreshing the first target frequency division coefficient stored in the first configuration register into the first frequency divider when the parameter refreshing instruction is received, so that the clock processing circuit carries out frequency adjustment on the reference clock signal of the first frequency based on the first target frequency division coefficient to obtain the target clock signal.
In one embodiment, further comprising:
the instruction sending unit is used for sending the parameter refreshing instruction to the clock generator at intervals of preset time.
For the description of the parameter adjustment system of the clock generator, refer to the above embodiment, and the description of the present invention is omitted herein.
In order to solve the technical problem, the invention also provides a parameter adjusting device of the clock generator, which comprises:
A memory for storing a computer program;
and the processor is used for realizing the steps of the parameter adjustment method of the clock generator when executing the computer program.
For the description of the parameter adjusting device of the clock generator, refer to the above embodiment, and the description of the present invention is omitted herein.
In order to solve the technical problem, the invention also provides a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the steps of the parameter adjustment method of the clock generator are realized when the computer program is executed by a processor.
For the description of the computer-readable storage medium, refer to the above embodiments, and the disclosure is not repeated here.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (21)

1. A clock generator, comprising:
a reference clock source for outputting a reference clock signal at a first frequency;
the clock processing circuit is provided with a first frequency divider and is connected with the reference clock source;
the first frequency divider is used for adjusting the frequency division coefficient of the first frequency divider according to a first target configuration instruction sent by a user;
the clock processing circuit is used for carrying out frequency adjustment on the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider to obtain a target clock signal.
2. The clock generator of claim 1, wherein the clock processing circuit further comprises:
The phase-locked loop circuit is connected with the reference clock source, and the first frequency divider is connected with the phase-locked loop circuit;
the phase-locked loop circuit is used for carrying out frequency adjustment on the reference clock signal of the first frequency according to the frequency division coefficient of the first frequency divider to obtain the target clock signal.
3. The clock generator of claim 2, wherein the phase-locked loop circuit is specifically configured to multiply the reference clock signal of the first frequency according to a division coefficient of the first frequency divider to obtain a multiplied first clock signal;
the clock processing circuit further includes:
the frequency dividing circuit is connected with the phase-locked loop circuit;
the frequency dividing circuit is used for dividing the frequency of the first clock signal by a preset multiple to obtain the target clock signal.
4. The clock generator of claim 2, wherein the clock processing circuit further comprises a reference frequency divider provided with a reference frequency division factor, the phase locked loop circuit comprising a phase comparator, a loop filter, and a voltage controlled oscillator;
the input end of the reference frequency divider is connected with the reference clock source, the input end of the phase comparator is respectively connected with the output end of the reference frequency divider and the output end of the first frequency divider, the output end of the phase comparator is connected with the input end of the loop filter, the output end of the loop filter is connected with the input end of the voltage-controlled oscillator, and the output end of the loop filter is connected with the input end of the first frequency divider;
The reference frequency divider divides the frequency of the reference clock signal according to the reference frequency division coefficient, the phase comparator determines a clock error according to the clock signal output by the reference frequency divider and the clock signal output by the first frequency divider and inputs the clock error to the voltage-controlled oscillator, and the voltage-controlled oscillator adjusts the control voltage of the voltage-controlled oscillator according to the clock error so as to adjust the frequency of the first clock signal of the clock signal output by the voltage-controlled oscillator.
5. The clock generator of claim 2, wherein when the number of the phase-locked loop circuits is plural, the plural phase-locked loop circuits are connected in one-to-one correspondence with the plural first frequency dividers.
6. The clock generator of claim 1, further comprising:
the first configuration register is connected with the first frequency divider and is used for storing a first target frequency division coefficient corresponding to the first target configuration instruction;
the first frequency divider is specifically configured to adjust its frequency division coefficient to the first target frequency division coefficient according to the first target frequency division coefficient in the first configuration register.
7. The clock generator of claim 3, wherein the frequency divider circuit comprises:
And the integer frequency divider is connected with the phase-locked loop circuit and is used for dividing the frequency of the first clock signal by a preset integer multiple to obtain the target clock signal.
8. The clock generator of claim 7, wherein the division factor of the integer divider is correspondingly adjusted based on a second target configuration instruction sent by a user.
9. The clock generator of claim 8, wherein the frequency divider circuit further comprises:
the second configuration register is connected with the integer frequency divider and is used for storing a second target frequency division coefficient corresponding to the second target configuration instruction, and the second target frequency division coefficient is an integer;
the integer frequency divider is specifically configured to adjust its frequency division coefficient to the second target frequency division coefficient according to the second target frequency division coefficient in the second configuration register.
10. The clock generator of claim 7, wherein the frequency divider circuit further comprises:
and the decimal frequency divider is connected with the phase-locked loop circuit and is used for dividing the frequency of the first clock signal by preset decimal times to obtain the target clock signal.
11. The clock generator of claim 10, wherein the division factor of the fractional divider is correspondingly adjusted based on a third target configuration instruction sent by a user.
12. The clock generator of claim 11, wherein the frequency divider circuit further comprises:
the third configuration register is connected with the fractional frequency divider and is used for storing a third target frequency division coefficient corresponding to the third target configuration instruction, and the third target frequency division coefficient is a fractional number;
the fractional frequency divider is specifically configured to adjust its frequency division coefficient to the third target frequency division coefficient according to the third target frequency division coefficient in the third configuration register.
13. The clock generator of claim 10, wherein the clock processing circuit further comprises:
and the first multiplexer is connected with the integer frequency divider and the fractional frequency divider and is used for conducting a channel corresponding to the integer frequency divider or the fractional frequency divider according to user requirements so as to output a target clock signal output by the integer frequency divider or the fractional frequency divider.
14. The clock generator of claim 13, wherein the first multiplexer is specifically configured to select, according to configuration information input by a user, a channel corresponding to the integer frequency divider or the fractional frequency divider to be turned on, and if a frequency of a clock signal output by the first multiplexer is a target frequency corresponding to the target clock signal, directly take the clock signal output by the first multiplexer as the target clock signal; if the frequency of the clock signal output by the frequency divider reaches a frequency threshold, selecting a channel corresponding to the fractional frequency divider to conduct so that the fractional frequency divider adjusts the frequency of the clock signal output by the frequency divider to the target frequency;
The configuration information input by the user is determined according to the target frequency, and the frequency threshold is any value within a preset range of the target frequency.
15. The clock generator of claim 13, wherein the clock processing circuit further comprises a phase-adjusting phase-locked loop circuit having an input for inputting a clock signal of another device, the phase-adjusting phase-locked loop circuit for detecting and adjusting a phase of the clock signal of the other device to output a clock signal synchronized with the target clock signal.
16. The clock generator of claim 15, further comprising:
and the second multiplexer is connected with the integer frequency divider, the fractional frequency divider and the phase adjustment phase-locked loop circuit and is used for conducting a channel corresponding to the integer frequency divider, the fractional frequency divider or the phase adjustment phase-locked loop circuit according to user requirements so as to output a clock signal output by the integer frequency divider, the fractional frequency divider or the phase adjustment phase-locked loop circuit.
17. A method for adjusting parameters of a clock generator, applied to the clock generator as claimed in any one of claims 1 to 16, the method for adjusting parameters of the clock generator comprising:
Acquiring a first target configuration instruction sent by a user;
analyzing the first target configuration instruction to obtain a first target frequency division coefficient;
and adjusting the frequency division coefficient of the first frequency divider to be the first target frequency division coefficient, so that the clock processing circuit carries out frequency adjustment on the reference clock signal of the first frequency based on the first target frequency division coefficient to obtain a target clock signal.
18. The method of parameter tuning of a clock generator of claim 17, wherein the clock generator further comprises a first configuration register coupled to the first divider; analyzing the first target configuration instruction to obtain a first target frequency division coefficient, and then further comprising:
writing the first target frequency division coefficient into the first configuration register;
adjusting the frequency division coefficient of the first frequency divider to the first target frequency division coefficient comprises:
and refreshing the first target frequency division coefficient stored in the first configuration register to the first frequency divider when a parameter refreshing instruction is received.
19. A parameter adjustment system for a clock generator, applied to a clock generator as claimed in any one of claims 1 to 16, the parameter adjustment system for a clock generator comprising:
The instruction acquisition unit is used for acquiring a first target configuration instruction sent by a user;
the analysis unit is used for analyzing the first target configuration instruction to obtain a first target frequency division coefficient;
and the parameter adjusting unit is used for adjusting the frequency dividing coefficient of the first frequency divider to the first target frequency dividing coefficient so that the clock processing circuit can carry out frequency adjustment on the reference clock signal with the first frequency based on the first target frequency dividing coefficient to obtain a target clock signal.
20. A parameter adjustment device for a clock generator, comprising:
a memory for storing a computer program;
processor for implementing the steps of the method for parameter adjustment of a clock generator according to any of the claims 17-18 when executing a computer program.
21. A computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the steps of the method for adjusting parameters of a clock generator according to any one of claims 17-18.
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CN113078991A (en) * 2021-03-03 2021-07-06 北京紫光青藤微系统有限公司 Frequency calibration system, method and transponder
CN114448432A (en) * 2022-01-29 2022-05-06 上海燧原科技有限公司 Phase-locked loop frequency modulation system, frequency division control method, device, equipment and medium
CN116185127A (en) * 2023-02-28 2023-05-30 龙芯中科技术股份有限公司 Frequency division method, device, chip, equipment and medium for clock signal

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022778A (en) * 2014-06-24 2014-09-03 瑞斯康达科技发展股份有限公司 Analog phase-locked loop circuit and signal processing method thereof
CN113078991A (en) * 2021-03-03 2021-07-06 北京紫光青藤微系统有限公司 Frequency calibration system, method and transponder
CN114448432A (en) * 2022-01-29 2022-05-06 上海燧原科技有限公司 Phase-locked loop frequency modulation system, frequency division control method, device, equipment and medium
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