CN117596871A

CN117596871A - Method for manufacturing dynamic random access memory

Info

Publication number: CN117596871A
Application number: CN202311491888.9A
Authority: CN
Inventors: 张钦福; 许艺蓉; 冯立伟
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2023-11-09
Filing date: 2023-11-09
Publication date: 2024-02-23

Abstract

A method of manufacturing a dynamic random access memory, comprising: providing a substrate, forming a plurality of bit lines arranged at intervals on the substrate, and forming side wall structures on two sides of the bit lines, wherein the side wall structures comprise a first side wall, a second side wall and a third side wall. Then forming a contact structure, and removing part of the second side wall by taking the contact structure as a barrier to form a gap. And then forming a fourth side wall in the gap. By the above process, the barrier capability of the sidewall structure during the subsequent process can be enhanced.

Description

Method for manufacturing dynamic random access memory

Technical Field

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a dynamic random access memory.

Background

The dynamic random access memory (dynamic random access memory, DRAM) is a volatile memory, and includes an array area (array area) formed by a plurality of memory cells (memory cells) and a peripheral area (peripheral area) formed by a control circuit. Each memory cell is composed of a transistor (transducer) and a capacitor (capacitor) electrically connected with the transistor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. Control circuitry controls access of data to each memory cell by addressing each memory cell through Word Lines (WL) and Bit Lines (BL) that span the array region and are electrically connected to each memory cell.

To obtain higher density chips, the structure of memory cells has been developed toward three-dimensional (three-dimensional) technology, such as buried word line (wordline) and stacked capacitor (stacked capacitor) technology. The stacked capacitor technology is to set the capacitor of the memory unit above the substrate and realize the electrical connection with the transistor in the substrate in the vertical direction through the connection pad structure, thereby saving the substrate area occupied by the capacitor and conveniently obtaining larger capacitance by increasing the height of the electrode plate of the capacitor. How to obtain good electrical connection quality and maintain electrical isolation between memory cells at the same time is an important technical problem faced in the art to achieve higher concentration.

Disclosure of Invention

One of the objectives of the present invention is to provide a method for manufacturing a DRAM, which forms a multi-layered sidewall structure on both sides of a bit line, maintains a proper opening width between bit lines, and ensures a process margin to separate connection pad structures from each other so as to improve abnormal defects between the connection pad structures.

An embodiment of the invention provides a method for manufacturing a dynamic random access memory. Firstly, a substrate is provided, a plurality of bit lines which are arranged at intervals are formed on the substrate, and then side wall structures which comprise a first side wall, a second side wall and a fourth side wall are formed on two sides of the bit lines. Then, a contact structure is formed and arranged between the bit lines, the top surfaces of the bit lines and the side wall structures are exposed, and then the contact structure is used as a barrier, and part of the second side wall is removed to form a gap. Then, forming a third sidewall, conformally covering the bit line and the contact structure, filling the gap, and removing part of the third sidewall until the top surface of the bit line and the contact is exposed.

Drawings

The accompanying drawings provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 8 are schematic views illustrating steps of manufacturing a dynamic random access memory according to an embodiment of the invention.

FIG. 9 is a schematic cross-sectional view of a DRAM according to an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a DRAM according to an embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a DRAM according to an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a DRAM according to an embodiment of the present invention.

Wherein reference numerals are as follows:

102. substrate and method for manufacturing the same

104. Isolation structure

106. Insulating layer

122. Semiconductor layer

124. Interface layer

126. Metal layer

128. Hard mask layer

130. Sidewall structure

132. First side wall

133. Buried insulating layer

134. A second side wall

136. A third side wall

138. Fourth side wall

140. Contact structure

152. Barrier layer

154. Structure of connection pad

156. Insulation structure

106a silicon oxide layer

106b silicon nitride layer

106c silicon oxide layer

130a sidewall structure

138a fourth sidewall material layer

138b bottom surface

138c cap portion

138d interlayer part

154a plug portion

154b pad portion

AR active region

BL bit line

D1 Depth of

DA dotted line frame

E1 Etching process

E2 Etching back process

H1 Height of (1)

M1 conductive layer

R1 dent

R2 grooving

S1 gap

S2 air gap

SC storage node contact hole

V direction

WL word line

In the X direction

Y direction

In the Z direction

Detailed Description

The following description sets forth the preferred embodiments of the present invention and, together with the accompanying drawings, provides a further understanding of the invention, as well as details of the structure and advantages to be achieved, to those skilled in the art to which the invention pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the invention to accomplish other embodiments.

For ease of understanding and simplicity of illustration, the various illustrations in this disclosure depict only a portion of the DRAM and are not drawn to scale. Furthermore, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the present disclosure. As used herein, the terms "about" and "relative" refer to the portions of the article that are in turn, and thus, are intended to refer to the same elements as those illustrated in the figures.

For ease of illustration and to aid in understanding the semiconductor structure of the present invention, a spatial reference direction such as X, Y, Z, V is shown, wherein X, Y and the Z direction are parallel to the substrate surface and the X and Y directions are perpendicular to each other and are different from the Z direction. The V-direction is perpendicular to the substrate surface.

Fig. 1 to 8 are schematic views illustrating steps of fabricating a dynamic random access memory according to an embodiment of the invention, wherein fig. 1 is a plan view, and fig. 2 to 8 are schematic cross-sectional views along a line AA' in fig. 1. Referring to fig. 1 and 2, first, a substrate 102, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, is provided, but is not limited thereto. The substrate 102 includes an isolation structure 104 and a plurality of active regions AR defined by the isolation structure 104. The isolation structure 104 may comprise a single layer or multiple layers of dielectric material, and suitable dielectric materials may comprise, for example, silicon oxide (SiO) ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen doped silicon carbide (NDC), low-k dielectric materials such as, but not limited to, fluorosilicate glass (fluorinated silica glass, FSG), silicon oxycarbide oxide (SiCOH), spin-on-glass (spin-on glass), porous low-k dielectric materials (porius low-k dielectric material), organic polymer dielectric materials, or combinations thereof. The active regions AR are separated from each other by the isolation structures 104, and each have a long strip shape with a long axis extending along the Z direction. Active area ARAre staggered with each other to form an active area array. The substrate 102 further includes a plurality of buried word lines WL extending in the Y direction and arranged at intervals in the X direction, respectively, and cut through each active region AR to divide each active region AR into two end portions and one middle portion.

Please continue to refer to fig. 1 and 2. Next, an insulating layer 106 is formed on the substrate 102, and then an etching process is performed to remove a portion of the insulating layer 106, the substrate 102, and the material of the isolation structure 104, thereby forming a recess R1 on the substrate 102, which penetrates the insulating layer 106 and exposes the middle portion of the active region AR and the top surface of the isolation structure 104 on both sides thereof. Next, a bit line material stack (not shown) is formed to entirely cover the substrate 102 and fill the recess R1, and an etching process is performed to remove an excess portion of the bit line material stack, thereby obtaining a plurality of bit lines BL. The bit lines BL extend along the X-direction and are spaced apart along the Y-direction, respectively, and are in direct contact with the active regions AR exposed from the recesses R1.

According to an embodiment of the present invention, as shown in fig. 2, the insulating layer 106 may be a composite layer, such as an ONO composite layer formed by a silicon oxide layer 106a, a silicon nitride layer 106b and a silicon oxide layer 106c, but is not limited thereto. The bit line BL has a multi-layer structure, for example, comprising, in order from bottom to top, a semiconductor layer 122, an interface layer 124, a metal layer 126, and a hard mask layer 128. The material of the semiconductor layer 122 may include, but is not limited to, single crystal silicon (crystalline silicon), polycrystalline silicon (polysilicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable semiconductor materials.

The material of the interface layer 124 may include a metal, a metal silicide, or a metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The material of the metal layer 126 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or a compound, alloy, and/or composite layer of the foregoing metal materials, but is not limited thereto. The hard mask layer 128 may include a dielectric material, such as silicon oxide (SiO) ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination thereof, but is not limited thereto. According to an embodiment of the inventionFor example, the material of the semiconductor layer 122 includes polysilicon, the material of the interface layer 124 includes cobalt silicide (CoSi), the material of the metal layer 126 includes tungsten (W), and the material of the hard mask layer 128 includes silicon nitride (SiN).

Please refer to fig. 3. Next, sidewall structures 130 self-aligned to sidewalls of the bit lines BL are formed on both sides of the bit lines BL, and storage node contact holes SC aligned to outer sides of the sidewall structures 130 and respectively recessed into ends of the active regions AR, wherein the storage node contact holes SC are separated from each other by an inter-contact isolation (SCISO, not shown) region along a Y direction (refer to fig. 1). Then, a contact material layer (not shown) is formed to entirely cover the substrate 102 and fill the storage node contact holes SC, and then an etching or planarization process is used to remove the contact material layer outside the storage node contact holes SC until the top surfaces of the bit lines BL and the sidewall structures 130 are exposed, thereby obtaining contact structures 140 respectively located in the storage node contact holes SC.

Please continue to refer to fig. 3. The sidewall structure 130 has a multi-layer structure, at least including a first sidewall 132, a second sidewall 134, a third sidewall 136, and a buried insulating layer 133, wherein the first sidewall 132 is along the sidewall of the bit line BL and the surface of the recess R1, and the buried insulating layer 133 is located on the first sidewall 132 at the bottom of the sidewall structure 130 and fills the recess R1. The second sidewall 134 is sandwiched between the first sidewall 132 and the third sidewall 136, and bottom ends of the second sidewall 134 and the third sidewall 136 respectively contact the top surface of the buried insulating layer 133. The sidewall structures 130 may be formed by multiple thin film deposition and etching processes, which are not described in detail herein for simplicity of illustration. The first sidewall 132, the second sidewall 134, the third sidewall 136, and the buried insulating layer 133 each include a dielectric material, such as silicon oxide (SiO) ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination thereof, but is not limited thereto. According to an embodiment of the invention, the material of the first and third sidewalls 132 and 136 comprises silicon nitride (SiN), and the material of the second sidewall 134 comprises silicon oxide (SiO) ₂ ) The material of the buried insulating layer 133 includes silicon nitride (SiN). According to one embodiment of the present invention, as shown in FIG. 3, the first sidewall 132 is in direct contact with the bit line BL, and the third sidewall 136 and the buried insulating layer 133 are in contact with the contactsThe structure 140 is in direct contact. The contact structure 140 is located between the bit lines BL, separated from direct contact with the bit line BL by the sidewall structure 130 on both sides, and in direct contact with the end of the active region AR at the bottom. The material of the contact structure 140 may include, but is not limited to, single crystal silicon (crystalline silicon), poly silicon (polysilicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable semiconductor materials. According to an embodiment of the present invention, the material of the contact structure 140 includes phosphorus doped Silicon (SiP).

Please refer to fig. 4. An etching process E1 is then performed with the contact structure 140 and the bit line BL as a barrier, and a portion of the second sidewall 134 is selectively removed to form a space S1 between the contact structure 140 and the bit line BL. According to an embodiment of the present invention, the first sidewall 132 and the third sidewall 136 remain on both sides of the space S1, and the sidewalls of the contact structure 140 and the bit line BL are not exposed. The depth D1 of the void S1 is preferably about 1/2 to 1/3 of the height H1 of the bit line BL, wherein the height H1 is defined by the portion of the bit line BL located on the insulating layer 106. According to an embodiment of the present invention, the bottom end of the void S1 is slightly higher than the top surface of the metal layer 126 or is substantially flush with the top surface of the metal layer 126.

In embodiments of the present invention, "about" may refer to a value that does not float up or down by more than 10%. In some alternative embodiments, the depth of the void is approximately between 1/2 and 1/3 of the height of the bit line, which may mean that the depth of the void is at least 1/3× (1-10%) and at most 1/2× (1+10%) of the height of the bit line.

Please refer to fig. 5 and 6. In an embodiment of the invention, the sidewall structure may further comprise a fourth sidewall. Next, a fourth sidewall material layer 138a is formed, which conformally covers the top surfaces of the bit line BL and the contact structure 140 and fills the space S1, and then the unnecessary fourth sidewall material layer 138a outside the space S1 is etched away until the top surfaces of the bit line BL and the contact structure 140 are exposed, thereby obtaining a fourth sidewall 138 disposed in the space S1. The material of the fourth sidewall 138 (i.e., the material of the fourth sidewall material layer 138 a) is different from the material of the second sidewall 134. In accordance with an embodiment of the present invention, the material of the fourth sidewall 138 is preferably a material having a high blocking capability for the etch back process E2 (refer to fig. 7), such as silicon nitride (SiN). As shown in fig. 6, the first sidewall 132, the third sidewall 136, the buried insulating layer 133, and the second sidewall 134 and the fourth sidewall 138 interposed between the first sidewall 132 and the third sidewall 136 together constitute a sidewall structure 130a.

Wherein, the "co-form" in the embodiments of the present invention means that the continuous structural shape is constructed by utilizing the similarity and correlation factors of the morphological aspects between two shapes or multiple shapes.

In some alternative embodiments, the fourth sidewall material layer 138a conformally covers the top surfaces of the bit lines BL and the contact structures 140, may refer to the structural shape of the fourth sidewall material layer 138a, is configured to the structural shape of the upper surfaces or side surfaces of the bit lines BL and the contact structures 140, and covers the bit lines BL and the contact structures 140 in a continuous structure.

By forming the multi-layer sidewall structure on both sides of the bit lines in the above embodiments, a proper opening width between the bit lines can be maintained, and the blocking capability of the sidewall structure during the subsequent process can be enhanced. For example, in the process of forming the connection pad structures, it is possible to further improve the abnormal defects between the connection pad structures by ensuring a process margin to separate the connection pad structures from each other, thereby obtaining good electrical connection quality while maintaining electrical isolation between the memory cells, achieving higher integration density of the semiconductor device.

Please refer to fig. 7. An etch back process E2 is then performed to remove a portion of the contact structure 140 and expose an upper portion of the storage node contact hole SC. According to an embodiment of the present invention, after the etch back process E2, the top surface 140a of the contact structure 140 remaining at the lower portion of the storage node contact hole SC is lower than the bottom surface 138b of the fourth sidewall 138 or is interposed between the top surface and the bottom surface of the metal layer 126.

Please refer to fig. 8. Next, a barrier layer 152 is formed to conformally cover the top surface 140a of the contact structure 140, the sidewalls of the storage node contact hole SC, and the top surfaces of the sidewall structure 130a and the bit line BL, and then a conductive layer M1 is formed on the barrier layer 152 and fills the storage node contact hole SC. Then, an etching process is performed to form a trench R2 passing through the conductive layer M1 and the barrier layer 152 toThe conductive layer M1 and the barrier layer 152 are segmented into connection pad structures 154 that respectively fill the storage node contact holes SC and are separated from each other. Subsequently, an insulating material is filled into the slot R2 to form an insulating structure 156. The material of the barrier layer 152 may include, but is not limited to, conductive barrier materials such as titanium and/or titanium nitride (TiN), tantalum (Ta), and/or tantalum oxide (TaN). The material of the conductive layer M1 may include a metal such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys of the foregoing materials, and/or composite layers, but is not limited thereto. According to an embodiment of the present invention, the material of the barrier layer 152 includes titanium nitride (TiN), and the material of the conductive layer M1 includes tungsten (W). The material of the insulating structure 156 may include silicon oxide (SiO ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen doped silicon carbide (NDC), low-k dielectric materials such as, but not limited to, fluorosilicate glass (fluorinated silica glass, FSG), silicon oxycarbide oxide (SiCOH), spin-on-glass (spin-on glass), porous low-k dielectric materials (porius low-k dielectric material), organic polymer dielectric materials, or combinations thereof. According to an embodiment of the present invention, the material of the insulating structure 156 includes silicon nitride (SiN).

The location of the insulating structure 156 (i.e., the location of the slot R2) determines the shape of the connection pad structure 154. As shown in fig. 8, the insulating structure 156 is offset from the bit line BL in the vertical direction (i.e., V direction), and the bottom is located on the sidewall structure 130a and the connection pad structure 154 on one side of the bit line BL and below the top surface of the bit line BL. The connection pad structure 154 can be divided into a lower portion, which is also called a plug portion 154a, and an upper portion, which is also called a pad portion 154b, which are integrally formed. In detail, as shown in fig. 8, the plug portion 154a is interposed between the bit lines BL, and is in contact and electrically connected to the contact structure 140. The pad portion 154b is a position where a bottom electrode (not shown) of the stacked capacitor is disposed, and is connected to the plug portion 154a, and extends laterally toward the top of the bit line BL on one side of the plug portion 154a, and directly contacts the third sidewall 136, the fourth sidewall 138, the first sidewall 132, and the top surface of the bit line BL. With this design, the surface area and alignment uniformity of the pad 154b can be improved, which provides a larger process window for the bottom electrode (not shown) manufacturing process, and improves the electrical connection quality with the bottom electrode (not shown).

In order to increase the surface area of the pad portion 154b to increase the area Cheng Yuliang of the bottom electrode (not shown) and to increase the cross-sectional area of the connection between the plug portion 154a and the pad portion 154b to decrease the resistance, the width of the insulating structure 156 (i.e., the width of the recess R2) is limited to have a gradually decreasing size, however, if the sidewall structure 130a is excessively removed during the etch-back process E2 (refer to fig. 7) and the thickness is insufficient, this may result in the position of the barrier layer 152 overlying the sidewall structure 130a deviating from the position where the recess R2 is expected to cut, and thus may not be completely cut off, resulting in bridging and leakage between the pad structures 154. The present invention improves the leakage problem between the connection pad structures 154 by selecting a material (e.g., silicon nitride) with a higher barrier capability for the etch-back process E2 to replace a portion of the second sidewall 134 to form the sidewall structure 130a, which has a higher barrier capability for the etch-back process E2, so as to maintain the predetermined thickness after the etch-back process E2, and ensure that the barrier layer 152 on the sidewall structure 130a can be located within the process margin range of the notch R2 position to be completely cut off by the notch R2.

The following description will be made with respect to different embodiments of the present invention, and for simplicity of description, the following description mainly describes different parts of each embodiment, and the same parts will not be repeated. In addition, like parts in the various embodiments of the present invention are designated by like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 9, a schematic cross-sectional view of a dram according to another embodiment of the present invention is shown, which is different from the embodiment shown in fig. 8 in that an air gap S2 is included between the bottom end of the fourth sidewall 138 and the top end of the second sidewall 134 of the dram according to the present embodiment.

Please refer to fig. 10 and 11, which are schematic cross-sectional views of a dram according to other embodiments of the present invention. The present invention can adjust the overall impedance of the pad structure 154 by adjusting the etching parameters of the etching back process E2 (refer to fig. 7) to remove the top portions of the first sidewall 132, the fourth sidewall 138 and the third sidewall 136, thereby changing the cross-sectional shape of the junction of the plug portion 154a and the pad portion 154b of the pad structure 154. For example, as shown in fig. 10, the tops of the first, fourth and third sidewalls 132, 138 and 136 form a gradually decreasing continuous slope, and the portion of the pad structure 154 located on the continuous slope thus has a sloped arcuate profile. As shown in fig. 11, the top portions of the first, fourth and third sidewalls 132, 138 and 136 sequentially form a stepped profile that is gradually lowered, and the portion of the pad structure 154 located in the stepped profile thus also has a stepped profile.

Referring to fig. 12, a cross-sectional view of a dynamic random access memory according to another embodiment of the invention is shown, which is different from the embodiment shown in fig. 8 in that a pre-etch process is additionally performed before the etching process E1 of fig. 4, to etch back the contact structure 140, the first sidewall 132, the second sidewall 134 and the third sidewall 136 to a level lower than the top surface of the bit line BL, thereby exposing the upper sidewall of the bit line BL. In particular, the upper sidewall may refer to a sidewall of the bit line BL on a side remote from the active region or the isolation structure. Next, an etching process E1 shown in fig. 4 is performed to selectively remove a portion of the second sidewall 134 to form a space S1 between the contact structure 140 and the bit line BL, and then, a fourth sidewall material layer 138a is formed to conformally cover the top surface and the upper sidewall of the bit line BL and the top surface of the contact structure 140 and to fill the space S1. Then, the excess fourth sidewall material layer 138a is etched away until the top surfaces of the bit line BL and the contact structure 140 are exposed, resulting in a fourth sidewall 138 comprising a cap portion 138c on the upper sidewall of the bit line BL and covering the top surfaces of the first sidewall 132 and the third sidewall 136, and a sandwich portion 138d between the first sidewall 132 and the third sidewall 136 (i.e. in the space S1). Wherein the cap portion 138c may cover an upper sidewall of a portion of the bit line BL. Subsequently, the steps of fig. 7 to 8 are performed again to form a connection pad structure 154 and an insulating structure 156. The cap portion 138c can serve as a blocking structure to protect the underlying sidewall structure 130a during the etch-back process E2 of fig. 7, further reducing the thickness loss of the sidewall structure 130a, ensuring that the sidewall structure 130a has a sufficient thickness after the etch-back process E2, thereby helping to achieve electrical isolation between the bit line BL and the storage node contact hole SC, and improving or avoiding the shorting problem between the bit line BL and the storage node contact hole SC.

In view of the above, the multi-layered sidewall structure of the present invention is less prone to be excessively thinned during the etching back step of the contact structure, and can maintain a proper opening width between bit lines, so as to ensure that the process margin for manufacturing the separation structure can separate the connection pad structures from each other, thereby improving the abnormal defects between the connection pad structures.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of manufacturing a dynamic random access memory, comprising:

providing a substrate;

forming a plurality of bit lines which are arranged at intervals on the substrate;

forming a side wall structure on two sides of the bit line, wherein the side wall structure comprises a first side wall, a second side wall and a third side wall;

forming a contact structure arranged between the bit lines and exposing the top surfaces of the bit lines and the side wall structures;

removing part of the second side wall by taking the contact structure as a barrier to form a gap;

forming a fourth sidewall material layer conformally covering the bit line and the contact structure and filling the void; and

and removing part of the fourth side wall material layer until the top surfaces of the bit lines and the contacts are exposed, so as to obtain the fourth side wall located in the gap.

2. The method of manufacturing a dynamic random access memory of claim 1, wherein an air gap is included between a top surface of the remaining second sidewall and a bottom surface of the fourth sidewall.

3. The method of manufacturing a dynamic random access memory of claim 1, wherein the first sidewall, the third sidewall, and the fourth sidewall comprise a nitride material, and the second sidewall comprises an oxide material.

4. The method of claim 1, wherein the depth of the void is between 1/2 and 1/3 of the height of the bit line.

5. The method of manufacturing a dynamic random access memory according to claim 1, further comprising:

etching back the contact structure until the top surface of the contact structure is lower than the bottom surface of the fourth side wall; and

and forming a connection pad structure on the contact structure, wherein the connection pad structure is in direct contact with the third side wall, the fourth side wall, the first side wall and the top surface of the bit line.

6. The method of claim 5, wherein after etching back the contact structure, the top surfaces of the first sidewall, the fourth sidewall, and the third sidewall form a continuous slope that decreases gradually.

7. The method of claim 5, wherein after etching back the contact structure, the top surface of the first sidewall, the top surface of the fourth sidewall, and the top surface of the third sidewall form a stepped profile that decreases in sequence.

8. The method of claim 5, wherein the connection pad structure comprises a plug portion between the bit lines and a pad portion over the plug portion and the bit lines, and the plug portion and the pad portion are integrally formed.

9. The method of claim 1, further comprising, prior to removing a portion of the second sidewall:

and etching back the contact structure, the first side wall, the second side wall and the third side wall to be lower than the top surface of the bit line, so as to expose the upper side wall of the bit line.

10. The method of claim 9, wherein the fourth sidewall includes a cap portion on the upper sidewall of the bit line and an interlayer portion in the void.