CN117595862B - Phase-locked loop circuit, system and method for determining phase-locked loop locking time - Google Patents
Phase-locked loop circuit, system and method for determining phase-locked loop locking time Download PDFInfo
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- CN117595862B CN117595862B CN202410078580.XA CN202410078580A CN117595862B CN 117595862 B CN117595862 B CN 117595862B CN 202410078580 A CN202410078580 A CN 202410078580A CN 117595862 B CN117595862 B CN 117595862B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
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Abstract
The invention discloses a phase-locked loop circuit, a phase-locked loop system and a method for determining locking time of the phase-locked loop, and relates to the technical field of integrated circuit testing. The clock generator is connected with the clock buffer and used for acquiring a clock signal corresponding to the current modulation depth; the clock buffer is connected with the phase-locked loop plug-in unit; the controller is connected with the clock buffer and the phase-locked loop plug-in unit respectively. According to the invention, the controller is used for grabbing signals to obtain accurate first time and second time, so that deviation is avoided compared with the PLL locking time determined by the current manual grabbing time, the accuracy of grabbing signals and the accuracy of subsequently evaluating locking capacity are improved, the delay time is reduced, and the grabbing efficiency is improved. In addition, the locking scene covered by the invention is comprehensive and the normal circuit system is ensured by corresponding different preset locking scenes under different modulation depths.
Description
Technical Field
The present invention relates to the field of integrated circuit testing technology, and in particular, to a phase-locked loop circuit, a system and a method for determining locking time of a phase-locked loop.
Background
With the current higher clock frequencies of digital signals, there is a concomitant increase in the requirements for signal setup, hold time, and clock jitter within the circuitry. The purpose of reducing electromagnetic radiation peak value is achieved by reducing the amplitude of the clock at the fundamental frequency and odd harmonics in a spread spectrum clock (Spread Spectrum Clock, SSC) mode.
However, the SSC clock introduces extra jitter during the processing, and in general, if jitter occurs, the phase-locked loop (Phase Locked Loops, PLL) will control the frequency and phase of the oscillation signal in the loop by using the externally input reference signal, so as to realize automatic tracking of the output signal frequency to the input signal frequency, and determine the locking time of the phase-locked loop. Aiming at the current PLL locking time determining process, signals are manually grasped to calculate, delay or grasping inaccuracy exists in the manual grasping process, so that deviation exists between the PLL locking time calculation and the actual PLL locking time, and in addition, a locking scene corresponding to the locking time determining process is single, so that deviation exists in subsequent locking capacity evaluation and the coverage scene is single.
Therefore, how to improve the accuracy and locking capability of PLL locking time to ensure that the circuitry works properly is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a phase-locked loop circuit, a phase-locked loop system and a phase-locked loop locking time determining method, which are used for solving the technical problems that the deviation of the PLL locking time and single locking scene are caused by delay and inaccuracy caused by manually grabbing signals in the current PLL locking time determining process.
In order to solve the technical problems, the invention provides a phase-locked loop circuit, which comprises a clock generator, a clock buffer and a phase-locked loop plug-in;
The clock generator is connected with the clock buffer and is used for acquiring a clock signal corresponding to the current modulation depth;
the clock buffer is connected with the phase-locked loop plug-in unit;
The controller is respectively connected with the clock buffer and the phase-locked loop plug-in unit, and is used for controlling the time of the clock buffer for sending the clock signal and the time of the phase-locked loop plug-in unit for resetting to obtain first time and second time respectively according to a preset locking scene, and determining the locking time corresponding to the preset locking scene according to the first time and the second time.
In one aspect, the controller is connected to the clock buffer, and includes:
The first end of the controller is connected with the enabling end of the clock buffer;
the first output end of the clock buffer is connected with the second end of the controller.
In another aspect, the controller is coupled to the phase-locked loop plug-in, and includes:
the third end of the controller is connected with the reset end of the phase-locked loop plug-in unit;
And the interrupt signal end of the phase-locked loop plug-in unit is connected with the fourth end of the controller.
On the other hand, the device also comprises a switch unit;
the switch unit is respectively connected with the controller and the clock generator;
the controller is also used for controlling the current modulation depth output by the switch unit correspondingly.
In another aspect, the switching unit includes a first switch, a second switch, a first resistor, and a second resistor;
the first end of the first switch is connected with the first end of the first resistor; the second end of the first resistor is connected with a power supply;
The second end of the first switch is connected with the first end of the second resistor and is connected with the enabling end of the clock generator;
the second end of the second resistor is connected with the first end of the second switch; the second end of the second switch is grounded;
the fifth end of the controller is connected with the control end of the first switch, and the sixth end of the controller is connected with the control end of the second switch.
In another aspect, the switching unit includes a third switch, a fourth switch, a fifth switch, a sixth switch, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;
The first end of the third resistor is connected with the first end of the third switch, the first end of the fourth resistor is connected with the first end of the fourth switch, and the second end of the third resistor and the second end of the fourth resistor are both connected with a power supply;
the second end of the third switch is respectively connected with the first end of the fifth resistor and the enabling end of the clock generator, the first end of the fifth switch is connected with the second end of the fifth resistor, and the second end of the fifth switch is grounded;
the second end of the fourth switch is respectively connected with the first end of the sixth resistor and the enabling end of the clock generator, the first end of the sixth switch is connected with the second end of the sixth resistor, and the second end of the sixth resistor is grounded;
And the seventh end, the eighth end, the ninth end and the tenth end of the controller are correspondingly connected with the control end of the third switch, the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch respectively.
In another aspect, the phase-locked loop plug-in is a phase-locked loop chip.
In order to solve the technical problems, the invention also provides a phase-locked loop system which comprises the phase-locked loop circuit.
In order to solve the above technical problems, the present invention further provides a method for determining a locking time of a phase-locked loop, which is applied to the phase-locked loop circuit, including:
Acquiring a clock signal corresponding to the current modulation depth output by a clock generator;
acquiring a preset locking scene;
According to the preset locking scene, controlling the time for the clock buffer to send the clock signal and the time for the phase-locked loop plug-in to be reset to obtain first time and second time respectively;
and determining the locking time corresponding to the preset locking scene according to the first time and the second time.
In one aspect, the preset locking scenario is a scenario in which the clock signal output by the clock buffer has reached the pll plug-in and the pll plug-in is not yet started, and the time for controlling the clock buffer to send the clock signal and the time for resetting the pll plug-in respectively obtain a first time and a second time, including:
acquiring the time of the clock buffer to transmit the clock signal;
determining the first time fed back to a controller according to the time of the clock buffer sending the clock signal;
Acquiring preset resetting time of the phase-locked loop plug-in, wherein the resetting time is longer than the time of the clock buffer for sending the clock signal;
and determining the second time fed back to the controller according to the preset reset time.
On the other hand, the preset locking scenario is a scenario that the clock signal output by the clock buffer does not reach the phase-locked loop plug-in and the phase-locked loop plug-in is started, and the time for controlling the clock buffer to send the clock signal and the time for resetting the phase-locked loop plug-in respectively obtain a first time and a second time, including:
acquiring a preset reset time of the phase-locked loop plug-in;
determining the second time fed back to the controller according to the preset reset time;
Acquiring the time of the clock buffer for transmitting the clock signal, wherein the time of the clock buffer for transmitting the clock signal is longer than the preset reset time;
The first time fed back to the controller is determined according to the time when the clock buffer transmits the clock signal.
On the other hand, the determining, according to the first time and the second time, the lock time corresponding to the preset lock scene includes:
When the preset locking scene is a scene that the clock signal output by the clock buffer has reached the phase-locked loop plug-in and the phase-locked loop plug-in is not started, taking the absolute value time determined after the difference value processing of the second time and the first time as first locking time, wherein the first locking time comprises the non-starting time of the phase-locked loop plug-in;
And when the preset locking scene is a scene that the clock signal output by the clock buffer does not reach the phase-locked loop plug-in and the phase-locked loop plug-in is started, taking the absolute value time determined after the difference value processing of the second time and the first time as the second locking time.
On the other hand, when the number of phase-locked loop plug-ins is one, after determining the first locking time or the second locking time, the method further includes:
obtaining a locking score corresponding to a locking time interval;
determining whether the first locking time or the second locking time is located in each target time interval of the locking time interval;
and determining a corresponding locking score according to each target time interval to serve as the locking capacity corresponding to the first locking time or the second locking time.
In another aspect, the types of the current modulation depth include a first modulation depth, a second modulation depth, and a third modulation depth, where the first modulation depth is greater than the second modulation depth, and the second modulation depth is greater than the third modulation depth, and when the number of phase-locked loop plugins is plural and the model numbers of the phase-locked loop plugins are different, after determining the first locking time or the second locking time, the method further includes:
when the current modulation depth is the first modulation depth, acquiring each first locking time or each second locking time corresponding to each phase-locked loop plug-in;
Screening out the minimum locking time corresponding to the first locking time or the second locking time in the first locking time or the second locking time of the phase-locked loop plug-ins, and taking the phase-locked loop plug-in corresponding to the minimum locking time as a target phase-locked loop plug-in;
If the first locking time or the second locking time is the same in the respective locking time, modulating the first modulation depth to the second modulation depth to serve as the new current modulation depth;
And returning to the step of acquiring the first locking time or the second locking time corresponding to each phase-locked loop plug-in until a target phase-locked loop plug-in is selected.
In another aspect, the determining the type of the current modulation depth includes:
Acquiring an input and output state of a switch unit corresponding to the controller, wherein the input and output state is a level state corresponding to connection of the controller and the switch unit;
acquiring an enabling state and a clock state list corresponding to the connection of the controller to the clock buffer;
And determining the type of the current modulation depth according to the clock state list, the input and output states and the enabling state.
The invention provides a phase-locked loop circuit, wherein a clock generator is connected with a clock buffer and is used for acquiring a clock signal corresponding to the current modulation depth; the clock buffer is connected with the phase-locked loop plug-in unit; the controller is connected with the clock buffer and the phase-locked loop plug-in unit respectively.
The method has the advantages that the controller controls the time for the clock buffer to send the clock signal and the sequence of the reset time of the phase-locked loop plug-in based on the clock signal corresponding to the current modulation depth and different preset locking scenes so as to test the first time and the second time which are correspondingly obtained under the different locking scenes, and then determines the locking time corresponding to the preset locking scenes according to the difference value of the first time and the second time. According to the invention, the controller is used for grabbing signals to obtain accurate first time and second time, so that deviation is avoided compared with the PLL locking time determined by the current manual grabbing time, the accuracy of grabbing signals and the accuracy of subsequently evaluating locking capacity are improved, the delay time is reduced, and the grabbing efficiency is improved. In addition, the locking scene covered by the invention is comprehensive and the normal circuit system is ensured by corresponding different preset locking scenes under different modulation depths.
Secondly, the controller is connected with the clock buffer and the phase-locked loop plug-in unit, the time sequence of the clock signal sent to the phase-locked loop plug-in unit is realized by controlling the enabling end of the clock buffer, the input clock signal is detected, the first time of the clock sent to the phase-locked loop plug-in unit is recorded, the starting completion time of the phase-locked loop plug-in unit is controlled successively by releasing the resetting time of the phase-locked loop plug-in unit, and the simulation of the two locking scenes mentioned in the embodiment is realized to determine the corresponding locking time so as to facilitate the subsequent evaluation of the locking capability of the phase-locked loop; the controller is used for realizing automatic adjustment and switching of the output of SSC clocks of various different types, and the degree of automatic testing is improved. The controller controls the level state of the SSC mode control pin of the clock generator by configuring the pin state of the connection switch unit, so as to realize the type switching of the output clock model; the phase-locked loop chip is made into an insert (interface) form, and the insert of the phase-locked loop chip of different manufacturers is consistent with the interface definition of the motherboard, so that only the insert needs to be replaced when batch verification is carried out, and the detaching and welding efficiency is improved; the first time and the second time are determined through two different locking scene settings, so that the locking time under the corresponding locking scene can be determined conveniently; calculating corresponding locking time based on different locking scenes so as to evaluate locking capability of the phase-locked loop plug-in to different mode input clocks according to the determined locking time; and the phase-locked loop plug-in with stronger locking capability is mapped through the length of the locking time based on the evaluation of the locking capability determined by the locking time corresponding to each locking scene under different locking depths of the plurality of phase-locked loop plug-ins, so that the evaluation accuracy of the locking capability is improved.
In addition, the invention also provides a phase-locked loop system and a method for determining the locking time of the phase-locked loop, which have the same beneficial effects as the phase-locked loop circuit.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a block diagram of a phase-locked loop circuit according to an embodiment of the present invention;
fig. 2 is a block diagram of another phase-locked loop circuit according to an embodiment of the present invention;
fig. 3 is a block diagram of a phase-locked loop circuit according to another embodiment of the present invention;
fig. 4 is a flowchart of a method for determining a lock time of a phase-locked loop according to an embodiment of the present invention;
fig. 5 is a flowchart of another method for determining a lock time of a pll according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The invention provides a phase-locked loop circuit, a phase-locked loop system and a phase-locked loop locking time determining method, which are used for solving the technical problems that the PLL locking time has deviation and a single locking scene due to delay and inaccuracy caused by manually grabbing signals in the current PLL locking time determining process.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Electromagnetic interference (Electromagnetic Interference, EMI) tends to cause degradation in circuit performance in circuitry. In the method for reducing the EMI, the clock is spread, the energy concentrated in a narrow frequency band range is dispersed to a set wide frequency range by a frequency modulation method, and the purpose of reducing the electromagnetic radiation peak value of the system is achieved by reducing the amplitude (energy) of the clock in a fundamental frequency and an odd harmonic. For applications where clock accuracy is sensitive, the extra jitter of the SSC clock is emphasized, and when the SSC is turned on or the modulation depth reaches a certain level, the PLL is caused to have a longer locking time or cannot be locked, which affects the normal operation of the circuit system.
When the PLL locking time is tested, signals can be grabbed in a manual grabbing mode, grabbing delay and inaccurate grabbing situations can occur in the grabbing process, and therefore deviation occurs in calculation of the locking time. In addition, when testing PLL locking time, the locking scenario considered is relatively single, only one locking scenario is considered, different locking scenarios can appear in corresponding locking time calculation, and only one locking scenario is used for calculating locking time, so that a certain degree of deviation can exist in subsequent locking capability assessment. The phase-locked loop circuit provided by the invention can solve the technical problems.
Fig. 1 is a block diagram of a phase-locked loop circuit according to an embodiment of the present invention, and as shown in fig. 1, the phase-locked loop circuit includes a clock generator 1, a clock buffer 2, and a phase-locked loop plug-in 3;
the clock generator 1 is connected with the clock buffer 2 and is used for acquiring a clock signal corresponding to the current modulation depth;
the clock buffer 2 is connected with the phase-locked loop plug-in 3;
The controller 4 is respectively connected with the clock buffer 2 and the phase-locked loop plug-in unit 3, and is used for controlling the time of the clock buffer 2 for sending the clock signal and the time of the phase-locked loop plug-in unit 3 for resetting to obtain a first time and a second time respectively according to a preset locking scene, and determining the locking time corresponding to the preset locking scene according to the first time and the second time.
Specifically, the clock generator is configured to obtain a clock signal corresponding to the current modulation depth, where the clock signal in this embodiment may be an SSC clock signal or a non-SSC clock signal. In addition, when the clock signal is an SSC clock signal, the corresponding modulation depth may be configured, and the configuration process in this embodiment is not limited and may be set according to the actual situation. The modulation depth is typically in the range of 0 to-0.5%, and the specific current modulation depth may be the current state determined by switching between different states, or may be a specific modulation depth directly given, which is not limited herein.
In general, the model of the clock generator determines the magnitude of the received modulation depth, and therefore, the model of the clock generator is not limited, and can be determined according to the set magnitude of the modulation depth.
The clock generator is connected with the clock buffer, the clock buffer is connected with the phase-locked loop plug-in unit, and the clock buffer is used for sending a clock signal to the phase-locked loop plug-in unit through the clock buffer so as to test the locking time. The test lock time is determined by a controller connected to the clock buffer and to the phase-locked loop plug-in. The controller controls the time of the clock buffer to send the clock signal and the time of the phase-locked loop plug-in to be reset based on different preset locking scenes so as to simulate different locking scenes. Specifically, the time of the clock buffer sending the clock signal is controlled to obtain the first time, and the time of the phase-locked loop plug-in unit resetting is controlled to obtain the second time. And determining the corresponding locking time of each preset locking scene according to the first time and the second time. It will be appreciated that the controller may be a micro control unit (Microcontroller Unit, MCU) or other processor, without limitation.
Since the pll plug-in usually needs to load configuration, there may be a locked scenario in which the input clock has arrived but the pll plug-in configuration is not started to complete, or a locked scenario in which the pll plug-in configuration has been started to complete but the input clock has not arrived, and the controller controls related signals to implement control of the two locked scenarios, so as to obtain locking times under different locked scenarios. In addition, based on the locking time under different corresponding locking scenes under the current modulation depth, the evaluation of the influence of SSC on the phase-locked loop under different locking scenes is realized.
The phase-locked loop circuit provided by the embodiment of the invention is characterized in that a clock generator is connected with a clock buffer and is used for acquiring a clock signal corresponding to the current modulation depth; the clock buffer is connected with the phase-locked loop plug-in unit; the controller is connected with the clock buffer and the phase-locked loop plug-in unit respectively. The controller controls the time of the clock buffer for transmitting the clock signal and the sequence of the resetting time of the phase-locked loop plug-in based on the clock signal corresponding to the current modulation depth and different preset locking scenes so as to test the first time and the second time which are correspondingly obtained under the different locking scenes, and then determines the locking time corresponding to the preset locking scene according to the difference value of the first time and the second time. According to the invention, the controller is used for grabbing signals to obtain accurate first time and second time, so that deviation is avoided compared with the PLL locking time determined by the current manual grabbing time, the accuracy of grabbing signals and the accuracy of subsequently evaluating locking capacity are improved, the delay time is reduced, and the grabbing efficiency is improved. In addition, the locking scene covered by the invention is comprehensive and the normal circuit system is ensured by corresponding different preset locking scenes under different modulation depths.
In some embodiments, the controller is coupled to the clock buffer, comprising:
The first end of the controller is connected with the enabling end of the clock buffer;
The first output end of the clock buffer is connected with the second end of the controller.
As shown in fig. 1, a first terminal (first pin) of the controller 4 is connected to an Enable terminal (Output Enable (OE) pin) of the clock buffer 2, for controlling a time when the clock buffer 2 transmits a clock signal. The first Output end of the clock buffer 2 is connected to a second end (second pin) of the controller 4, and is used for sending the clock buffer 2 to a first time obtained by time feedback of the phase-locked loop plug-in 3, where the first pin and the second pin of the controller 4 are Input Output (IO) pins.
In some embodiments, the controller is coupled to a phase-locked loop plug-in, comprising:
the third end of the controller is connected with the reset end of the phase-locked loop plug-in unit;
the interrupt signal end of the phase-locked loop plug-in unit is connected with the fourth end of the controller.
Specifically, the third end of the controller is connected with the reset end of the phase-locked loop plug-in and is used for controlling the resetting time of the phase-locked loop plug-in. The interrupt signal end of the phase-locked loop plug-in unit is connected with the fourth end of the controller, and the time from the interrupt signal received by the controller to the fourth end determines the second time, provided that the controller is required to control the phase-locked loop plug-in unit to provide the reset time so as to obtain the second time.
The clock buffer is connected with the phase-locked loop plug-in unit based on that the second output end of the clock buffer is connected with the clock input end of the phase-locked loop plug-in unit.
The controller is connected with the clock buffer, the controller is connected with the phase-locked loop plug-in, the time sequence of sending clock signals to the phase-locked loop plug-in is realized by controlling the enabling end of the clock buffer, the input clock signals are detected, the first time of sending the clock to the phase-locked loop plug-in is recorded, the starting completion time of the phase-locked loop plug-in is controlled successively by releasing the resetting time of the phase-locked loop plug-in, and the simulation of the two locking scenes mentioned in the embodiment is realized to determine the corresponding locking time so as to facilitate the subsequent assessment of the locking capability of the phase-locked loop.
In some embodiments, the phase-locked loop circuit further comprises a switching unit;
the switch unit is respectively connected with the controller and the clock generator;
The controller is also used for controlling the current modulation depth of the corresponding output of the switch unit.
Specifically, the switching unit may be a transistor, or may be another switch, and the like, which is not limited herein. For the switch unit, the switch unit is used for outputting the corresponding clock signal type, the switch unit is connected with the controller and the clock generator, and the controller controls the current modulation depth of the switch unit corresponding to the output so as to realize the output of the corresponding clock signal type. The switch unit is connected with the clock generator, and is specifically connected with an enabling end (SSC_EN) of the clock generator.
Different clock signal types, namely different orders of modulation depth, can be set corresponding to the switch units, the number of switches in the corresponding switch units is not limited, in general, one switch corresponds to one modulation depth, three modulation depths can be realized by voltage division processing of two switches, and the output level comprises a high level, a low level and an intermediate level. The controller controls the level state of the clock generator by configuring the pin state of the switch unit, so as to realize different types of switching of the output clock signals.
In some embodiments, the switching unit includes a first switch, a second switch, a first resistor, and a second resistor;
the first end of the first switch is connected with the first end of the first resistor; the second end of the first resistor is connected with a power supply;
the second end of the first switch is connected with the first end of the second resistor and is connected with the enabling end of the clock generator;
the second end of the second resistor is connected with the first end of the second switch; the second end of the second switch is grounded;
The fifth end of the controller is connected with the control end of the first switch, and the sixth end of the controller is connected with the control end of the second switch.
Fig. 2 is a block diagram of another phase-locked loop circuit according to an embodiment of the present invention, as shown in fig. 2, a first end of a first switch SW1 of a switch unit 5 is connected to a first end of a first resistor R1; the second end of the first resistor R1 is connected with a power supply; the second end of the first switch SW1 is connected with the first end of the second resistor R2 and is connected with the enabling end of the clock generator 1; the second end of the second resistor R2 is connected with the first end of the second switch SW 2; the second terminal of the second switch SW2 is grounded; the fifth end of the controller 4 is connected to the control end of the first switch SW1, and the sixth end of the controller 4 is connected to the control end of the second switch SW 2.
The current phase-locked loop circuit implements three level states of the SSC mode of the clock generator, high, low and intermediate levels, respectively. For different level states, corresponding modulation depths are preset, and table 1 is a table of three clock types controlled and output by the controller, as shown in table 1, the three states of the controller correspond to the three modulation depths, and IO5 and IO6 of the controller correspond to the fifth pin and the sixth pin.
Three clock type tables for table 1 controller control output
。
As shown in fig. 2, the controller 4 controls the first terminal of the first switch SW1 to be at a high level, and controls the first terminal and the second terminal of the first switch SW1 to be at a low level. If the enable terminal of the clock generator 1 is high, the first terminal and the second terminal of the second switch SW2 need to be non-conductive, and the level transmitted to the enable terminal of the clock generator 1 is high of the power supply. If the enable terminal of the clock generator 1 is low, the first switch SW1 is not turned on and the second switch SW2 is turned on. If the enable terminal of the clock generator 1 is at the intermediate level, the first switch SW1 and the second switch SW2 are all turned on to assume a voltage division state.
In some embodiments, if more modulation depths are considered, the switching unit includes a third switch, a fourth switch, a fifth switch, a sixth switch, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;
The first end of the third resistor is connected with the first end of the third switch, the first end of the fourth resistor is connected with the first end of the fourth switch, and the second end of the third resistor and the second end of the fourth resistor are both connected with a power supply;
the second end of the third switch is respectively connected with the first end of the fifth resistor and the enabling end of the clock generator, the first end of the fifth switch is connected with the second end of the fifth resistor, and the second end of the fifth switch is grounded;
The second end of the fourth switch is connected with the first end of the sixth resistor and the enabling end of the clock generator respectively, the first end of the sixth switch is connected with the second end of the sixth resistor, and the second end of the sixth resistor is grounded;
The seventh end, the eighth end, the ninth end and the tenth end of the controller are correspondingly connected with the control end of the third switch, the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch respectively.
Fig. 3 is a block diagram of a phase-locked loop circuit according to another embodiment of the present invention, as shown in fig. 3, a first end of a third resistor R3 is connected to a first end of a third switch SW3, a first end of a fourth resistor R4 is connected to a first end of a fourth switch SW4, and a second end of the third resistor R3 and a second end of the fourth resistor R4 are both connected to a power supply; the second end of the third switch SW3 is respectively connected with the first end of the fifth resistor R5 and the enabling end of the clock generator 1, the first end of the fifth switch SW5 is connected with the second end of the fifth resistor R5, and the second end of the fifth switch SW5 is grounded; the second end of the fourth switch SW4 is respectively connected with the first end of the sixth resistor R6 and the enabling end of the clock generator 1, the first end of the sixth switch SW6 is connected with the second end of the sixth resistor R6, and the second end of the sixth resistor R6 is grounded; the seventh end, the eighth end, the ninth end and the tenth end of the controller 4 are correspondingly connected to the control end of the third switch SW3, the control end of the fourth switch SW4, the control end of the fifth switch SW5 and the control end of the sixth switch SW6, respectively.
Table 2 is a table of five clock types that the controller controls to output, and as shown in table 2, the five states of the controller correspond to the five modulation depths.
Table 2 five clock type tables for controller control outputs
。
Accordingly, the types of the switches in the switch unit may be the same or different, and the type of each switch may be SN74LVC1G66, other types, or the like, and the present invention is not limited thereto. For statistical convenience, the same type of switch is used in this embodiment. In combination with the above embodiment, the specific model of the clock generator may be CK440Q, or may be another model.
The embodiment realizes automatic adjustment and switching of the SSC clock output of various different types through the controller, and improves the degree of automation test. The controller controls the level state of the SSC mode control pin of the clock generator by configuring the pin state of the connecting switch unit, so that the type switching of the output clock model is realized.
Different manufacturers correspond to different packaging forms of the phase-locked loop chip, and the disassembling and welding efficiency can be directly affected when batch verification is carried out. Thus, in some embodiments, the phase-locked loop plug-in is a phase-locked loop chip.
Specifically, the phase-locked loop chip is made into an insert (interposer) form, and the insert and the interface definition of the motherboard of the phase-locked loop chip of different manufacturers are consistent, so that only the insert needs to be replaced when batch verification is performed, and the detaching and welding efficiency is improved.
Furthermore, the present invention also provides a phase-locked loop system, which includes the phase-locked loop circuit, and referring to the above circuit embodiment, the present invention is not repeated herein, and has the same beneficial effects as the phase-locked loop circuit.
Fig. 4 is a flowchart of a method for determining a locking time of a phase-locked loop according to an embodiment of the present invention, as shown in fig. 4, where the method is applied to the phase-locked loop circuit, and the method includes:
s11: acquiring a clock signal corresponding to the current modulation depth output by a clock generator;
S12: acquiring a preset locking scene;
S13: according to a preset locking scene, controlling the time of a clock buffer for sending a clock signal and the resetting time of a phase-locked loop plug-in unit to obtain first time and second time respectively;
s14: and determining the locking time corresponding to the preset locking scene according to the first time and the second time.
Specifically, the clock signal corresponding to the current modulation depth output by the clock generator is obtained, and the current modulation depth in this embodiment may be set directly, or may be obtained by switching among a plurality of modulation depths to a target modulation depth, which is not limited herein. Upon acquisition of the target modulation depth by the handoff, in some embodiments, the determination of the type of current modulation depth includes:
acquiring an input and output state of a switch unit corresponding to the controller, wherein the input and output state is a level state corresponding to the connection of the controller and the switch unit;
acquiring an enabling state and a clock state list corresponding to the clock buffer connected with the controller;
The type of the current modulation depth is determined according to the clock state list, the input and output states and the enabling state.
It will be appreciated that the switching unit may refer to the different switch arrangements of fig. 2 and 3 in the above embodiments. In this embodiment, the input/output state of the corresponding switch unit of the controller, that is, the level state of the control switch unit, is obtained, and the type of the current modulation depth can be mapped based on the clock state list according to the enable state of the enable terminal (ssc_en) corresponding to the clock buffer connected to the controller, and the mapping process is not limited herein, and may be table 1 and table 2 in the above embodiment.
In step S12, different preset locking scenes are required to be set in the embodiment, and it is to be noted that different locking scenes cannot be performed in parallel, and setting of one locking scene to one locking scene is required, that is, only one locking scene can be used to determine the corresponding locking time at a time.
As shown in fig. 1, according to a preset locking scene, the time sequence between the time when the clock reaches the phase-locked loop plug-in and the starting time of the phase-locked loop plug-in is controlled. The time at which the clock buffer sends the clock signal is controlled, the valid clock input can be detected, and the time is recorded as a first time, which is the time at which the clock is sent into the phase-locked loop plug-in. And controlling the reset time of the phase-locked loop plug-in, detecting the output time of the interrupt signal, recording the time as second time, and judging that the phase-locked loop plug-in is locked by considering that the phase-locked loop plug-in finishes locking the input clock signal after detecting the effective high level sent by the phase-locked loop plug-in, and judging that the phase-locked loop plug-in fails to lock if the interrupt signal is invalid. In the case of locking being completed, locking times corresponding to the first time and the second time are determined.
The method for determining the locking time of the phase-locked loop provided by the embodiment of the invention comprises the steps that a controller controls the time of a clock buffer for sending the clock signal and the sequence of the reset time of a phase-locked loop plug-in unit based on a clock signal corresponding to the current modulation depth and different preset locking scenes so as to test first time and second time which are correspondingly obtained under the different locking scenes, and then determines the locking time corresponding to the preset locking scenes according to the difference value of the first time and the second time. According to the invention, the controller is used for grabbing signals to obtain accurate first time and second time, so that deviation is avoided compared with the PLL locking time determined by the current manual grabbing time, the accuracy of grabbing signals and the accuracy of subsequently evaluating locking capacity are improved, the delay time is reduced, and the grabbing efficiency is improved. In addition, the locking scene covered by the invention is comprehensive and the normal circuit system is ensured by corresponding different preset locking scenes under different modulation depths.
In some embodiments, the preset locked scenario is a scenario in which a clock signal output by a clock buffer has arrived at a phase-locked loop plug-in and the phase-locked loop plug-in is not yet started, and the time for controlling the clock buffer to send the clock signal and the time for resetting the phase-locked loop plug-in to obtain a first time and a second time respectively, including:
Acquiring time of a clock buffer sending a clock signal;
determining a first time fed back to the controller according to the time of the clock buffer sending the clock signal;
Acquiring a preset reset time of a phase-locked loop plug-in, wherein the reset time is longer than the time of a clock buffer for sending a clock signal;
And determining a second time fed back to the controller according to the preset reset time.
Specifically, in this embodiment, for a first time and a second time determined in a locked scenario, in the locked scenario, considering that the clock signal has reached the pll plug-in and the pll plug-in has not been started, the first time is before the second time, so the reset time is longer than the time when the clock buffer sends the clock signal, and after the time when the clock buffer sends the clock signal, the controller receives the signal at the first output end of the clock buffer, that is, the time fed back to the controller. And after the second time is set by the reset time, feeding back an interrupt signal of the phase-locked loop plug-in to the controller.
In some embodiments, the preset locking scenario is a scenario in which a clock signal output by a clock buffer does not reach a phase-locked loop plug-in and the phase-locked loop plug-in is started, and the time for controlling the clock buffer to send the clock signal and the time for resetting the phase-locked loop plug-in respectively obtain a first time and a second time, including:
acquiring a preset reset time of a phase-locked loop plug-in;
determining a second time fed back to the controller according to the preset reset time;
acquiring time for a clock buffer to transmit a clock signal, wherein the time for the clock buffer to transmit the clock signal is longer than preset reset time;
the first time to be fed back to the controller is determined according to the time at which the clock buffer transmits the clock signal.
Specifically, in this embodiment, for a first time and a second time determined in another locking scenario, in the locking scenario, considering that the clock signal does not reach the pll plug-in and the pll plug-in is started, the second time is before the first time, so the time for the clock buffer to send the clock signal is longer than the preset reset time. The determination of the first time and the second time is the same as the determination of the first time and the second time in the other lock scene in the above embodiment.
In this embodiment, the first time and the second time are determined through two different locking scene settings, so as to determine the locking time in the corresponding locking scene later.
In some embodiments, determining the lock time corresponding to the preset lock scene according to the first time and the second time in step S14 includes:
when a preset locking scene is a scene that a clock signal output by a clock buffer reaches a phase-locked loop plug-in and the phase-locked loop plug-in is not started, taking absolute value time determined after difference value processing is carried out on second time and first time as first locking time, wherein the first locking time comprises the non-starting time of the phase-locked loop plug-in;
And when the preset locking scene is a scene that the clock signal output by the clock buffer does not reach the phase-locked loop plug-in and the phase-locked loop plug-in is started, taking the absolute value time determined after the difference value processing of the second time and the first time as the second locking time.
Specifically, considering that the two time parameters of the first time and the second time are different in different locking scenes, the absolute value processing is performed to obtain the corresponding first locking time or second locking time after the difference value processing is performed to determine the time. In this embodiment, only the lock time of the pll card corresponding to the evaluation capability is determined, and the time is a positive number, so that a time parameter is obtained by an absolute value.
The embodiment calculates the corresponding locking time based on different locking scenes, so as to evaluate the locking capability of the phase-locked loop plug-in to different mode input clocks according to the determined locking time.
In some embodiments, when the number of phase-locked loop plugins is one, after determining the first lock time or the second lock time, further includes:
obtaining a locking score corresponding to a locking time interval;
determining each target time interval of which the first locking time or the second locking time is positioned in the locking time interval;
and determining a corresponding locking score according to each target time interval to serve as the locking capacity corresponding to the first locking time or the second locking time.
Specifically, when the locking capability is evaluated, there may be different phase-locked loop plug-ins of different manufacturers, when the number of the phase-locked loop plug-ins is one, after determining the first locking time or the second locking time, the locking score corresponding to the locking time interval is obtained in advance, and the corresponding locking score is obtained as the locking capability corresponding to the first locking time or the second locking time according to the matching of the first locking time or the second locking time with the corresponding locking time interval (the target time interval).
The embodiment provides a method for determining locking capability and simplifying evaluation when the number of phase-locked loop plug-ins is one.
In some embodiments, if there are multiple types of current modulation depth (the first modulation depth, the second modulation depth, and the third modulation depth), the first modulation depth is greater than the second modulation depth, the second modulation depth is greater than the third modulation depth, and the number of phase-locked loop plugins is multiple, after determining the first lock time or the second lock time, the method further includes:
When the current modulation depth is the first modulation depth, acquiring each first locking time or each second locking time corresponding to each phase-locked loop plug-in unit;
Screening out the minimum locking time corresponding to the first locking time or the second locking time in the first locking time or the second locking time of the phase-locked loop plug-ins, and taking the phase-locked loop plug-in corresponding to the minimum locking time as a target phase-locked loop plug-in;
if the first locking time or the second locking time is the same in the respective locking time, modulating the first modulation depth to the second modulation depth to serve as a new current modulation depth;
And returning to the step of acquiring each first locking time or each second locking time corresponding to each phase-locked loop plug-in until the target phase-locked loop plug-in is selected.
Specifically, under the condition that the current modulation depth is the first modulation depth, acquiring a first locking time and a second locking time under each phase-locked loop plug-in corresponding to the first modulation depth. For example, the number of phase-locked loop plugins is 5, and based on the fact that each phase-locked loop plugin comprises two locking scenes, 5 first locking times and 5 second locking times can be obtained. And finding the minimum locking time in the 5 first locking times or the 5 second locking times, and taking the corresponding phase-locked loop plug-in as a target phase-locked loop plug-in. It can be understood that, according to the decision basis of the locking capability being stronger as the locking time is shorter, the target pll card in this embodiment is the pll card with the strongest locking capability among all pll cards.
If the 5 first locking times are the same or the 5 second locking times are the same, the first modulation depth is modulated to the second modulation depth to serve as a new current modulation depth, the target phase-locked loop plug-in is continuously selected, if the corresponding first locking times are the same or the corresponding second locking times are the same under the second modulation depth, the first modulation depth is continuously modulated to the third modulation depth, the target phase-locked loop plug-in is continuously selected, and if the first modulation depth is not selected, the phase-locked loop plug-in capability is considered to be equivalent.
Assume that taking 2 phase-locked loop plugins as an example, taking a lock time in one lock scene, the evaluation time at different modulation depths is as shown in the evaluation schedule of different modulation depths of table 3:
table 3 evaluation schedule for different modulation depths
。
If the lock cannot be completed, the evaluation time value is infinity.
When modulation depth=0, if T1> T2, the capability of the phase-locked loop plug-in 2 is stronger, whereas if T1< T2, the capability of the phase-locked loop plug-in 1 is stronger; ending the evaluation flow.
If ti=t2, the modulation depth is adjusted to-0.3%, and if T3> T4, the capability of the phase-locked loop plug-in 2 is stronger, otherwise if T3< T4, the capability of the phase-locked loop plug-in 1 is stronger; ending the evaluation flow.
If t3=t4, the modulation depth is adjusted to-0.5%, and if T5> T6, the capability of the phase-locked loop plug-in 2 is stronger, otherwise if T5< T6, the capability of the phase-locked loop plug-in 1 is stronger; ending the evaluation flow.
If t5=t6, the phase-locked loop plug-in 1 and the phase-locked loop plug-in 2 are considered to be comparable in capability.
In addition, the evaluation of the corresponding locking capability may be determined by other methods, for example, by a specific mathematical algorithm or a corresponding weight score, which is not limited herein, and may be set according to practical situations.
According to the evaluation of the locking capability based on the locking time determination corresponding to each locking scene under different locking depths of the plurality of phase-locked loop plug-ins, the phase-locked loop plug-ins with high locking capability are mapped through the length of the locking time, and the evaluation accuracy of the locking capability is improved.
Fig. 5 is a flowchart of another method for determining a lock time of a phase-locked loop according to an embodiment of the present invention, as shown in fig. 5, the method includes:
s21: the controller configures the switching states (high level, low level and intermediate level) of the analog switching unit;
s22: when the switch state is low level, determining that the clock signal is a non-spread spectrum clock signal;
S23: when the switch state is the intermediate level, determining that the clock signal is a spread spectrum clock signal and the corresponding modulation depth is-0.3%;
s24: when the switch state is high level, determining that the clock signal is a spread spectrum clock signal and the corresponding modulation depth is-0.5%;
s25: the controller configures the level corresponding to the time when the clock buffer sends the clock signal to be output to the enabling end of the clock buffer;
S26: if the feedback time of the clock buffer sending the clock signal is detected to be effective, recording the feedback time as the first time;
s27: the controller configures the level corresponding to the resetting time of the phase-locked loop plug-in unit and outputs the level to the phase-locked loop plug-in unit;
S28: if the feedback time obtained by the resetting of the phase-locked loop plug-in is detected to be effective, recording the feedback time as a second time;
s29: for different types of input time, corresponding locking time is determined according to the first time and the second time.
Specifically, in step S21, the controller configures the control terminal of the switching unit to realize three types of clock signal outputs in the spread spectrum mode. In step S25, the time configuration of the clock buffer to send the clock signal is obtained, in step S27, the time for resetting the phase-locked loop plug-in is obtained, and in step S28, if the interrupt detection is invalid, it is determined that the phase-locked loop plug-in cannot lock the input clock. It should be noted that, the steps S25 and S26 and the steps S27 and S28 are used in combination to simulate the two preset locking scenarios in the above embodiment.
The phase-locked loop circuit, the phase-locked loop system and the method for determining the locking time of the phase-locked loop provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Claims (15)
1. A phase-locked loop circuit, characterized in that the phase-locked loop circuit comprises a clock generator, a clock buffer and a phase-locked loop plug-in;
The clock generator is connected with the clock buffer and is used for acquiring a clock signal corresponding to the current modulation depth;
the clock buffer is connected with the phase-locked loop plug-in unit;
The controller is respectively connected with the clock buffer and the phase-locked loop plug-in unit and is used for controlling the time for the clock buffer to send the clock signal and the time for the phase-locked loop plug-in unit to be reset to obtain first time and second time respectively according to a preset locking scene, and determining the locking time corresponding to the preset locking scene according to the first time and the second time;
The determining, according to the first time and the second time, a locking time corresponding to the preset locking scene includes:
And performing absolute value processing on the time determined after the difference value processing on the first time and the second time to obtain corresponding locking time.
2. The phase-locked loop circuit of claim 1, wherein the controller is coupled to the clock buffer, comprising:
The first end of the controller is connected with the enabling end of the clock buffer;
the first output end of the clock buffer is connected with the second end of the controller.
3. The phase-locked loop circuit of claim 2, wherein the controller is coupled to the phase-locked loop plug-in, comprising:
the third end of the controller is connected with the reset end of the phase-locked loop plug-in unit;
And the interrupt signal end of the phase-locked loop plug-in unit is connected with the fourth end of the controller.
4. A phase locked loop circuit as claimed in any one of claims 1 to 3, further comprising a switching unit;
the switch unit is respectively connected with the controller and the clock generator;
the controller is also used for controlling the current modulation depth output by the switch unit correspondingly.
5. The phase-locked loop circuit of claim 4, wherein the switching unit comprises a first switch, a second switch, a first resistor, and a second resistor;
the first end of the first switch is connected with the first end of the first resistor; the second end of the first resistor is connected with a power supply;
The second end of the first switch is connected with the first end of the second resistor and is connected with the enabling end of the clock generator;
the second end of the second resistor is connected with the first end of the second switch; the second end of the second switch is grounded;
the fifth end of the controller is connected with the control end of the first switch, and the sixth end of the controller is connected with the control end of the second switch.
6. The phase-locked loop circuit of claim 4, wherein the switching unit comprises a third switch, a fourth switch, a fifth switch, a sixth switch, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;
The first end of the third resistor is connected with the first end of the third switch, the first end of the fourth resistor is connected with the first end of the fourth switch, and the second end of the third resistor and the second end of the fourth resistor are both connected with a power supply;
the second end of the third switch is respectively connected with the first end of the fifth resistor and the enabling end of the clock generator, the first end of the fifth switch is connected with the second end of the fifth resistor, and the second end of the fifth switch is grounded;
the second end of the fourth switch is respectively connected with the first end of the sixth resistor and the enabling end of the clock generator, the first end of the sixth switch is connected with the second end of the sixth resistor, and the second end of the sixth resistor is grounded;
And the seventh end, the eighth end, the ninth end and the tenth end of the controller are correspondingly connected with the control end of the third switch, the control end of the fourth switch, the control end of the fifth switch and the control end of the sixth switch respectively.
7. The phase-locked loop circuit of claim 1, wherein the phase-locked loop plug-in is a phase-locked loop chip.
8. A phase locked loop system comprising a phase locked loop circuit as claimed in any one of claims 1 to 7.
9. A method for determining a lock time of a phase locked loop, applied to the phase locked loop circuit of any one of claims 1 to 7, comprising:
Acquiring a clock signal corresponding to the current modulation depth output by a clock generator;
acquiring a preset locking scene;
According to the preset locking scene, controlling the time for the clock buffer to send the clock signal and the time for the phase-locked loop plug-in to be reset to obtain first time and second time respectively;
Determining the locking time corresponding to the preset locking scene according to the first time and the second time;
The determining, according to the first time and the second time, a locking time corresponding to the preset locking scene includes:
And performing absolute value processing on the time determined after the difference value processing on the first time and the second time to obtain corresponding locking time.
10. The method of determining a locked time of a pll according to claim 9, wherein the preset locked scenario is a scenario in which the clock signal output by the clock buffer has reached the pll plug-in and the pll plug-in has not been started, and the time for the clock buffer to send the clock signal and the time for the pll plug-in to be reset respectively obtain a first time and a second time, including:
acquiring the time of the clock buffer to transmit the clock signal;
determining the first time fed back to a controller according to the time of the clock buffer sending the clock signal;
Acquiring preset resetting time of the phase-locked loop plug-in, wherein the resetting time is longer than the time of the clock buffer for sending the clock signal;
and determining the second time fed back to the controller according to the preset reset time.
11. The method of determining a locked loop time according to claim 9, wherein the preset locked scenario is a scenario in which the clock signal output by the clock buffer does not reach the pll plug-in and the pll plug-in is started, and the time for controlling the clock buffer to send the clock signal and the time for resetting the pll plug-in obtain a first time and a second time, respectively, including:
acquiring a preset reset time of the phase-locked loop plug-in;
determining the second time fed back to the controller according to the preset reset time;
Acquiring the time of the clock buffer for transmitting the clock signal, wherein the time of the clock buffer for transmitting the clock signal is longer than the preset reset time;
The first time fed back to the controller is determined according to the time when the clock buffer transmits the clock signal.
12. The method for determining a lock time of a phase locked loop according to claim 10 or 11, wherein the determining the lock time corresponding to the preset lock scene according to the first time and the second time includes:
When the preset locking scene is a scene that the clock signal output by the clock buffer has reached the phase-locked loop plug-in and the phase-locked loop plug-in is not started, taking the absolute value time determined after the difference value processing of the second time and the first time as first locking time, wherein the first locking time comprises the non-starting time of the phase-locked loop plug-in;
And when the preset locking scene is a scene that the clock signal output by the clock buffer does not reach the phase-locked loop plug-in and the phase-locked loop plug-in is started, taking the absolute value time determined after the difference value processing of the second time and the first time as the second locking time.
13. The method of determining a lock time of a phase locked loop according to claim 12, further comprising, after determining the first lock time or the second lock time, when the number of phase locked loop plugins is one:
obtaining a locking score corresponding to a locking time interval;
determining whether the first locking time or the second locking time is located in each target time interval of the locking time interval;
and determining a corresponding locking score according to each target time interval to serve as the locking capacity corresponding to the first locking time or the second locking time.
14. The method for determining a lock time of a pll according to claim 12, wherein the type of the current modulation depth includes a first modulation depth, a second modulation depth, and a third modulation depth, the first modulation depth is greater than the second modulation depth, the second modulation depth is greater than the third modulation depth, and when the number of pll plugins is plural and the types of the pll plugins are different, after determining the first lock time or the second lock time, further comprising:
when the current modulation depth is the first modulation depth, acquiring each first locking time or each second locking time corresponding to each phase-locked loop plug-in;
Screening out the minimum locking time corresponding to the first locking time or the second locking time in the first locking time or the second locking time of the phase-locked loop plug-ins, and taking the phase-locked loop plug-in corresponding to the minimum locking time as a target phase-locked loop plug-in;
If the first locking time or the second locking time is the same in the respective locking time, modulating the first modulation depth to the second modulation depth to serve as the new current modulation depth;
And returning to the step of acquiring the first locking time or the second locking time corresponding to each phase-locked loop plug-in until a target phase-locked loop plug-in is selected.
15. The method of claim 14, wherein the determining the type of the current modulation depth comprises:
Acquiring an input and output state of a switch unit corresponding to the controller, wherein the input and output state is a level state corresponding to connection of the controller and the switch unit;
acquiring an enabling state and a clock state list corresponding to the connection of the controller to the clock buffer;
And determining the type of the current modulation depth according to the clock state list, the input and output states and the enabling state.
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| CN102111148A (en) * | 2009-12-29 | 2011-06-29 | 海力士半导体有限公司 | Delay locked loop and method for driving the same |
| CN114546028A (en) * | 2022-02-23 | 2022-05-27 | 浙江赛思电子科技有限公司 | Verification method, device and medium for adpll clock chip |
| CN115714597A (en) * | 2022-11-18 | 2023-02-24 | 山东云海国创云计算装备产业创新中心有限公司 | Universal PLL clock control circuit and SOC chip |
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