CN117595856A - Analog multiplexer and electronic equipment - Google Patents

Analog multiplexer and electronic equipment Download PDF

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Publication number
CN117595856A
CN117595856A CN202311848851.7A CN202311848851A CN117595856A CN 117595856 A CN117595856 A CN 117595856A CN 202311848851 A CN202311848851 A CN 202311848851A CN 117595856 A CN117595856 A CN 117595856A
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China
Prior art keywords
transistor
signal
analog
bootstrap
voltage
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Chinese (zh)
Inventor
陈崴
熊良勇
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Fuzhou Maling Microelectronics Technology Co ltd
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Fuzhou Maling Microelectronics Technology Co ltd
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Priority to CN202311848851.7A priority Critical patent/CN117595856A/en
Publication of CN117595856A publication Critical patent/CN117595856A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Electronic Switches (AREA)

Abstract

The invention discloses an analog multiplexer and an electronic device, comprising: a plurality of analog signal input terminals for receiving input analog signals; a channel selection signal input terminal for receiving an input channel selection signal; the bootstrap voltage generator is used for generating bootstrap voltage after receiving the voltage signal; the signal output end is used for outputting the sampled signal; the multi-path analog switch comprises sampling MOS tubes MN4 inside, wherein the source electrode of each sampling MOS tube MN4 in each path of analog switch is connected to an analog signal input end, the drain electrode of each sampling MOS tube MN4 in the multi-path analog switch is connected to a signal output end, and the grid electrode and the source electrode of each sampling MOS tube MN4 in each path of analog switch are respectively controlled by the channel selection signals and then are connected with two ends of bootstrap voltage of the bootstrap voltage generator. The on-resistance of the analog switch is irrelevant to an input signal, so that the analog switch has high sampling linearity.

Description

Analog multiplexer and electronic equipment
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to an analog multiplexer and an electronic device.
Background
An analog Multiplexer (Multiplexer) is an electronic device or circuit that combines multiple input signals into one output signal. Its function is to transmit multiple signals simultaneously on a limited communication link to increase the efficiency of signal transmission. An analog multiplexer typically has a plurality of inputs and an output. It selects the input signal to be transmitted according to the control signal of the input signal through a certain control logic and forwards it to the output terminal. In this way, multiple input signals can share the same communication link, and the effect of simultaneous transmission is achieved.
Analog multiplexers may be used in a variety of applications such as transmission of audio and video signals, data communications and telecommunications networks, and the like. In the audio and video arts, an analog multiplexer may combine multiple audio or video signals into a composite signal that is then transmitted over a single communication link. In data communications, an analog multiplexer may combine multiple data signals into a composite signal to improve the efficiency of data transmission. In a telecommunications network, an analog multiplexer may combine a plurality of telephone signals into a composite signal to enable sharing of telephone lines. An analog multiplexer is an electronic device or circuit for combining multiple input signals and enabling simultaneous transmission, playing an important role in a variety of communication applications.
The on-resistance of the analog switch in a conventional analog multiplexer is related to the input signal, and the sampling linearity is not sufficient.
Disclosure of Invention
Therefore, it is necessary to provide an analog multiplexer and an electronic device, which solve the problems of insufficient sampling linearity and insufficient on-resistance of an analog switch related to an input signal in the existing analog multiplexer.
To achieve the above object, the present invention provides an analog multiplexer comprising:
a plurality of analog signal input terminals for receiving input analog signals;
a channel selection signal input terminal for receiving an input channel selection signal;
the bootstrap voltage generator is used for generating bootstrap voltage after receiving the voltage signal;
the signal output end is used for outputting the sampled signal;
the multi-path analog switch comprises sampling MOS tubes MN4 inside, wherein the source electrode of each sampling MOS tube MN4 in each path of analog switch is connected to an analog signal input end, the drain electrode of each sampling MOS tube MN4 in each path of analog switch is connected to a signal output end, the grid electrode and the source electrode of each sampling MOS tube MN4 in each path of analog switch are respectively controlled by the channel selection signals and then are connected with two ends of bootstrap voltage of the bootstrap voltage generator, the sampling MOS tube MN4 of one path of analog switch is selected by the channel selection signals to be conducted, the conducted sampling MOS tube MN4 samples the analog signal input end connected with the sampling MOS tube MN4, and the sampling signals are output at the signal output end.
In some embodiments, the bootstrap voltage generator includes a bootstrap circuit enable terminal, a first voltage output terminal and a second voltage output terminal, where the bootstrap circuit enable terminal is configured to receive an enable signal or a disable signal, the bootstrap circuit enable terminal receives the enable signal and then charges the first voltage output terminal and the second voltage output terminal so that a voltage is provided between the first voltage output terminal and the second voltage output terminal, and the bootstrap circuit enable terminal receives the disable signal and then removes the charge to maintain a voltage difference between the first voltage output terminal and the second voltage output terminal.
In some embodiments, the bootstrap voltage generator further includes a capacitor C1, a transistor MN10, and a transistor MN11, two ends of the capacitor C1 are respectively connected to the first voltage output terminal and the second voltage output terminal, the bootstrap circuit enabling terminal is connected to the control terminals of the transistor MN10 and the transistor MN11, one end of the capacitor C1 is connected to a power supply through the transistor MN10, the other end of the capacitor C1 is grounded through the transistor MN11, the transistors MN10 and MN11 are turned on after the bootstrap circuit enabling terminal receives the enabling signal so that the capacitor C1 is charged, and the transistors MN10 and MN11 are turned off after the bootstrap circuit enabling terminal receives the disabling signal so that the capacitor C1 maintains a charged state and generates a voltage difference between the first voltage output terminal and the second voltage output terminal.
In some embodiments, the bootstrap circuit further comprises a sampling control signal terminal and a logic gate unit, wherein the sampling control signal terminal and the bootstrap circuit enable terminal are respectively connected to an input terminal of the logic gate unit, and an output terminal of the logic gate unit outputs the enable signal or the disable signal.
In some embodiments, the logic gate unit is a nand gate unit.
In some embodiments, the bootstrap voltage generator further includes a transistor MP10, a transistor MP11, a capacitor C2, and a capacitor C3, the bootstrap circuit enable terminal is connected to one end of the capacitor C2 and one end of the capacitor C3, the input terminal of the transistor MP10 and the input terminal of the transistor MP11 are connected to a power supply, the control terminal of the transistor MP10 is connected to the output terminal of the transistor MP11, the other end of the capacitor C3, and the control terminal of the transistor MN10, and the control terminal of the transistor MP11 is connected to the output terminal of the transistor MP10 and the other end of the capacitor C2.
In some embodiments, the analog switch further includes a MOS transistor MN3, a gate of the MOS transistor MN3 is connected to a gate of the sampling MOS transistor MN4, a drain of the MOS transistor MN3 is connected to an analog signal input end and a source of the sampling MOS transistor MN4, the source of the MOS transistor MN3 is connected to one end of the bootstrap voltage, and the gate of the MOS transistor MN3 and the gate of the sampling MOS transistor MN4 are controlled by the channel selection signal and then connected to the other end of the bootstrap voltage generator.
In some embodiments, the circuit further includes a transistor MP0, a transistor MN0, a transistor MP1, a transistor MN5, a transistor MP2, a transistor MN2, and an inverter INV0, the channel selection signal input terminal is connected to a gate of the transistor MP0, a gate of the transistor MN0, and an input terminal of the inverter INV0, a source of the transistor MP0 is connected to a source of the transistor MP1 and the other end of the bootstrap voltage, a drain of the transistor MP0 is connected to a gate of the transistor MP1, a drain of the transistor MN0, and a drain of the transistor MN1 is connected to a gate of the transistor MN1 and a drain of the transistor MN5, a gate of the MOS transistor MN3, a gate of the sampling MOS transistor MN4, a source of the transistor MN1 is connected to a source of the MOS transistor MN3 and one end of the bootstrap voltage, a source of the transistor MN5 is connected to a drain of the transistor MN2, a gate of the transistor MP2 and a gate of the inverter 0 are connected to a drain of the transistor MN2, and a source of the transistor MN2 are connected to a source of the transistor MN2 and a ground.
In some embodiments, a channel selection logic unit is further included for converting the channel selection input signal into a channel selection signal.
The invention also provides an electronic device comprising a plurality of signal inputs, a selection output and an analog multiplexer as described in any one of the examples, the plurality of signal inputs being connected to a plurality of analog signal inputs of the analog multiplexer, respectively, the selection output being connected to a signal output of the analog multiplexer.
Compared with the prior art, the technical scheme introduces the bootstrap voltage generator into the analog multiplexer circuit, and when the analog switch is conducted to sample an input signal, the gate-source voltage of the analog switch is kept unchanged, so that the on-resistance of the analog switch is irrelevant to the input signal, and the analog multiplexer circuit has high sampling linearity and is particularly suitable for being used as an analog multiplexer of an analog-digital converter. And the control of the multipath analog switch can be realized by using one path of bootstrap voltage generator circuit, so that the cost of the circuit scale is greatly reduced compared with the traditional bootstrap switch circuit.
Drawings
FIG. 1 is a schematic diagram of an overall circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a bootstrap voltage generator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an analog switch circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of an embodiment of an analog switch of the present invention when turned off;
fig. 5 is a schematic circuit diagram of an analog switch according to an embodiment of the invention when turned on.
Detailed Description
In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of the phrase "in various places in the specification are not necessarily all referring to the same embodiment, nor are they particularly limited to independence or relevance from other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the technical features mentioned in the embodiments may be combined in any manner to form a corresponding implementable technical solution.
Unless defined otherwise, technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application pertains; the use of related terms herein is for the description of specific embodiments only and is not intended to limit the present application.
In the description of the present application, the term "and/or" is a representation for describing a logical relationship between objects, which means that there may be three relationships, e.g., a and/or B, representing: there are three cases, a, B, and both a and B. In addition, the character "/" herein generally indicates that the front-to-back associated object is an "or" logical relationship.
In this application, terms such as "first" and "second" are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual number, order, or sequence of such entities or operations.
Without further limitation, the use of the terms "comprising," "including," "having," or other like terms in this application is intended to cover a non-exclusive inclusion, such that a process, method, or article of manufacture that comprises a list of elements does not include additional elements but may include other elements not expressly listed or inherent to such process, method, or article of manufacture.
As understood in the patent prosecution guidelines, in the present application, the expressions "greater than", "less than", "exceeding" and the like are understood to not include the present number; the expressions "above", "below", "within" and the like are understood to include this number. Furthermore, in the description of the embodiments of the present application, the meaning of "a plurality of" is two or more (including two), and similarly, the expression "a plurality of" is also to be understood as such, for example, "a plurality of groups", "a plurality of" and the like, unless specifically defined otherwise.
In the description of the embodiments of the present application, spatially relative terms such as "center," "longitudinal," "transverse," "length," "width," "thickness," "up," "down," "front," "back," "left," "right," "vertical," "horizontal," "vertical," "top," "bottom," "inner," "outer," "clockwise," "counter-clockwise," "axial," "radial," "circumferential," etc., are used herein as terms of orientation or positional relationship based on the specific embodiments or figures, and are merely for convenience of description of the specific embodiments of the present application or ease of understanding of the reader, and do not indicate or imply that the devices or components referred to must have a particular position, a particular orientation, or be configured or operated in a particular orientation, and therefore are not to be construed as limiting of the embodiments of the present application.
Unless specifically stated or limited otherwise, in the description of the embodiments of the present application, the terms "mounted," "connected," "affixed," "disposed," and the like are to be construed broadly. For example, the "connection" may be a fixed connection, a detachable connection, or an integral arrangement; the device can be mechanically connected, electrically connected and communicated; it can be directly connected or indirectly connected through an intermediate medium; which may be a communication between two elements or an interaction between two elements. The specific meanings of the above terms in the embodiments of the present application can be understood by those skilled in the art to which the present application pertains according to the specific circumstances.
Referring to fig. 1 to 5, the present invention provides an analog multiplexer, as shown in fig. 1, comprising: the analog signal input terminals AMUX_IN < N > are used for receiving input analog signals and are N+1 paths of analog input signals. A channel selection signal input terminal CHSEL < M:0> for receiving an input channel selection signal; if one of the paths of the signals is enabled, for example, the 0 th path is enabled to be high level, the channel is conducted. The bootstrap voltage generator is used for generating bootstrap voltage after receiving the voltage signal; the signal output end AMUX_OUT is used for outputting the sampled signal; the multi-path analog switch (analog switch 1 to analog switch N) internally comprises sampling MOS tubes MN4, and the source electrode of the sampling MOS tube MN4 in each path of analog switch is connected to an analog signal input end, namely the analog signal input end is used as a signal source of the sampling MOS tube MN 4. The drain electrode of the sampling MOS tube MN4 in the multipath analog switch is connected to the signal output end, namely the sampling MOS tube MN4 can output the signal of the analog signal input end when being conducted. The gate and the source of the sampling MOS tube MN4 in each path of analog switch are respectively controlled by the channel selection signals and then connected with the two ends of the bootstrap voltage generator, namely the channel selection signals control whether the two ends of the bootstrap voltage generator are connected with the gate and the source of the sampling MOS tube MN 4. The channel selection signal selects one path of sampling MOS tube MN4 of the analog switch to be conducted, bootstrap voltage is loaded to the grid electrode and the source electrode of the sampling MOS tube MN4 at the moment, the conducted sampling MOS tube MN4 samples an analog signal input end connected with the sampling MOS tube MN4, and a sampling signal is output at the signal output end.
The bootstrap voltage generator is introduced into the analog multiplexer circuit, when the analog switch is conducted, the bootstrap voltage generated by the bootstrap voltage generator is loaded to the grid electrode and the source electrode of the sampling MOS tube MN4, so that the sampling MOS tube MN4 is conducted, and when an input signal is sampled, the grid-source voltage of the sampling MOS tube of the analog switch is kept unchanged through the bootstrap voltage, so that the on-resistance of the analog switch is irrelevant to the input signal, and the analog multiplexer circuit has high sampling linearity and is particularly suitable for being used as an analog multiplexer of an analog-digital converter. And the control of the multipath analog switch can be realized by using one path of bootstrap voltage generator circuit, so that the cost of the circuit scale is greatly reduced compared with the traditional bootstrap switch circuit. The invention has simple implementation scheme and good process universality, is particularly suitable for single chip integration and is also suitable for constructing discrete devices.
In some embodiments, as shown in FIGS. 1 and 2, the bootstrap voltage generator includes a bootstrap enable terminal VBOOST_EN, a first voltage output terminal V BOOSTP And a second voltage output terminal V BOOSTP The bootstrap circuit enabling end is used for receiving an enabling signal or a disabling signal, the bootstrap circuit enabling end charges after receiving the enabling signal so that voltage is arranged between the first voltage output end and the second voltage output end, and the bootstrap circuit enabling end removes charging after receiving the disabling signal so as to keep the voltage difference between the first voltage output end and the second voltage output end. The bootstrap voltage generator may be controlled to charge and generate a voltage through the bootstrap circuit enable terminal vboost_en.
The bootstrap voltage generator mainly has the following principle: the bootstrap voltage generator mainly consists of a capacitor and a switch. When the switch is closed, the capacitor begins to charge, accumulating charge on its plates. When the switch is open, the capacitor is isolated and cannot be discharged by other circuitry. During charging of the capacitor, the positive electrode of the voltage source is connected to one plate of the capacitor, while the other plate of the capacitor is connected to the negative electrode. Thus, positive charge is accumulated on the plates of the capacitor during charging, and the voltage across the plates of the capacitor is also gradually increased. When the switch is open, the capacitor is isolated and cannot be discharged by other circuitry. At this time, since the voltage between the two poles of the capacitor still exists, it can be used as a voltage generating higher than the power supply voltage. This is because the electric field of the capacitor is able to store energy, and after the switch is opened, the capacitor releases the stored energy, thereby generating a higher voltage.
In some embodiments, as shown in fig. 2, the bootstrap voltage generator further includes a capacitor C1, a transistor MN10, and a transistor MN11, two ends of the capacitor C1 are respectively connected to the first voltage output terminal and the second voltage output terminal, the bootstrap circuit enable terminal is connected to the control terminals of the transistor MN10 and the transistor MN11, one end of the capacitor C1 is connected to the power supply through the transistor MN10, the other end of the capacitor C1 is grounded through the transistor MN11, the transistor MN10 and the transistor MN11 are turned on after the bootstrap circuit enable terminal receives the enable signal so that the capacitor C1 is charged, and the transistor MN10 and the transistor MN11 are turned off after the bootstrap circuit enable terminal receives the disable signal so that the capacitor C1 maintains a charged state and generates a voltage difference between the first voltage output terminal and the second voltage output terminal. The transistor can generate isolated charged capacitor to realize output of capacitor voltage, namely output of bootstrap voltage.
In order to realize the control of the bootstrap voltage generator through the sampling control signal terminal CLKS, the bootstrap voltage generator further comprises a sampling control signal terminal CLKS and a logic gate unit NAND0, wherein the sampling control signal terminal and the bootstrap circuit enabling terminal are respectively connected to one input terminal of the logic gate unit, and the output terminal of the logic gate unit outputs the enabling signal or the disabling signal. In this embodiment, the sampling control signal terminal CLKS and the bootstrap circuit enabling terminal vboost_en can be integrated through the sampling control signal terminal CLKS and the logic gate unit NAND0, and when sampling is required, the sampling control signal terminal CLKS is enabled, so that charging is performed.
In some embodiments, the logic gate unit is a nand gate unit. In this way, the sampling control signal end CLKS and the bootstrap circuit enabling end vboost_en are both high level and then generate low level, and then the bootstrap voltage generator internal inverter drives the transistor to conduct, so as to charge. Control is achieved in which charging is only performed when the level is high at the same time.
As a specific embodiment, as shown in fig. 2, the bootstrap voltage generator further includes a transistor MP10, a transistor MP11, a capacitor C2 and a capacitor C3, the bootstrap circuit enable terminal is connected to one end of the capacitor C2 and one end of the capacitor C3, the input terminal of the transistor MP10 and the input terminal of the transistor MP11 are connected to a power supply, the control terminal of the transistor MP10 is connected to the output terminal of the transistor MP11, the other end of the capacitor C3 and the control terminal of the transistor MN10, and the control terminal of the transistor MP11 is connected to the output terminal of the transistor MP10 and the other end of the capacitor C2. More detailed implementation referring to fig. 2, the present embodiment may better ensure the operation of the bootstrap voltage generator.
In the embodiment of fig. 2, vboost_en is an enable signal of the bootstrap voltage generator circuit, when vboost_en is 1 and CLKS is high, the transistors MN10 and MN11 are turned on to charge the voltage across the capacitor C1 to the power supply VDD; when vboost_en is 0 and CLKS is high, the transistors MN10 and MN11 are turned off, and the capacitor C1 is connected across the gate and the source of the MOS transistor MN4 in the analog switch.
In some embodiments, as shown in fig. 3, the analog switch further includes a MOS transistor MN3, a gate of the MOS transistor MN3 is connected to a gate of the sampling MOS transistor MN4, a drain of the MOS transistor MN3 is connected to an analog signal input end and a source of the sampling MOS transistor MN4, a source of the MOS transistor MN3 is connected to one end of the bootstrap voltage, and the gate of the MOS transistor MN3 and the gate of the sampling MOS transistor MN4 are controlled by the channel selection signal and then connected to the other end of the bootstrap voltage generator. Better switching action can be achieved through the MOS tube MN 3.
In some embodiments, as shown in fig. 3, the circuit further includes a transistor MP0, a transistor MN0, a transistor MP1, a transistor MN5, a transistor MP2, a transistor MN2, and an inverter INV0, the channel selection signal input terminal is connected to the gate of the transistor MP0, the gate of the transistor MN0, and the input terminal of the inverter INV0, the source of the transistor MP0 is connected to the source of the transistor MP1 and the other end of the bootstrap voltage, the drain of the transistor MP0 is connected to the gate of the transistor MP1, the drain of the transistor MN0, and the drain of the transistor MN1 are connected to the gate of the transistor MN1 and the drain of the transistor MN5, the gate of the MOS transistor MN3, the gate of the sampling MOS transistor MN4, the source of the transistor MN1 is connected to the source of the MOS transistor MN3 and one end of the bootstrap voltage, the source of the transistor MN5 is connected to the drain of the transistor MP2 and the drain of the transistor MN2, the gate of the transistor MP2 and the drain of the inverter MN2 are connected to the source of the transistor MN0 and the source of the transistor MN 2. The level shift circuit in fig. 3 may be omitted as long as the gate of the transistor MP0 and the gate driving of the transistor MN0 can be realized.
In some embodiments, a sampling control signal terminal CLKS is included, where the sampling control signal terminal may also be used to control the conduction of the sampling MOS transistor MN 4. As shown in fig. 3 to 5, the sampling control signal terminal CLKS can co-act with one channel CHSEL < N > in the channel selection signal input terminal CHSEL < M:0> through the logic gate AND0, so as to output a signal to the sampling MOS transistor in the analog switch, thereby realizing the control of the switch thereof.
The analog switch operation is shown in fig. 4 and 5, with fig. 4 being a non-sampling state and fig. 5 being a non-sampling state, wherein transistor crossing indicates that the transistor is non-conductive and arrow indicates that the transistor is conductive. As shown in fig. 4, when CLKS is low, CLK0 is low, and the level shift circuit outputs low so that MP0 is turned on, MP1 is turned off, and MN2 is turned on at the same time so that MN5 is turned on, so that the gate voltages of MN3 and MN4 are pulled down to GND off, when no sampling is required. As shown in FIG. 5, when the CHSEL is sampled<N>When CLKs is high, CLK0 is high, MP2 is turned on, MN5 is turned off, and the output voltage of the level shifter circuit is V BOOSTP MP0 is turned off, MN0 is turned on, the gate voltage of MP1 is pulled down to GND (i.e. ground), MP1 is turned on, which makes the gate voltages of MN3, MN4 equal to V BOOSTP And MN3 is turned on to make the source voltage of MN4 be V BOOSTN Therefore, the gate-source voltage vgs=vboostp-vboostn=vdd of the sampling MOS transistor MN4, in other words, when clks=1, the gate-source voltage VGS of the main sampling switch can be approximately kept constant, and as can be known from the characteristic of the on-resistance of the MOS transistor operating in the deep linear region, the on-resistance of the sampling switch MN4 is approximately independent of the input voltage, so that the analog switch has high linearity in sampling the input voltage.
In some embodiments, the present invention further includes a channel selection logic unit, as shown in FIG. 1, for converting a channel selection input signal CHSEL < M:0> to a channel selection signal CHSEL < N:0>; for example, CHSEL < M:0> of any protocol (such as SPI protocol) can be converted into channel selection signals CHSEL < N:0> of a plurality of single lines, so that the conversion and control of the protocol can be realized, and the external pins can be simplified.
The invention also provides an electronic device comprising a plurality of signal inputs, a selection output and an analog multiplexer as described in any one of the examples, the plurality of signal inputs being connected to a plurality of analog signal inputs of the analog multiplexer, respectively, the selection output being connected to a signal output of the analog multiplexer. That is, the analog multiplexer of the present invention can be used as a part of an electronic device to realize the control of the conduction from multiple paths to one path. When the electronic equipment samples an input signal, the gate-source voltage of the sampling MOS tube of the analog switch is kept unchanged through the bootstrap voltage, so that the on-resistance of the analog switch is irrelevant to the input signal, and the electronic equipment has high sampling linearity and is particularly suitable for being used as an analog multiplexer of an analog-digital converter. And the control of the multipath analog switch can be realized by using one path of bootstrap voltage generator circuit, so that the cost of the circuit scale is greatly reduced compared with the traditional bootstrap switch circuit.
It should be noted that, the transistor may be a MOS transistor, so long as the switching of the circuit can be achieved, and the control end, the input end, and the output end of the transistor may respectively correspond to the gate, the source, and the drain of the P-type MOS transistor or the gate, the drain, and the source of the N-type MOS transistor.
It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solution, directly or indirectly, to other relevant technical fields, all of which are included in the scope of the invention.

Claims (10)

1. An analog multiplexer, comprising:
a plurality of analog signal input terminals for receiving input analog signals;
a channel selection signal input terminal for receiving an input channel selection signal;
the bootstrap voltage generator is used for generating bootstrap voltage after receiving the voltage signal;
the signal output end is used for outputting the sampled signal;
the multi-path analog switch comprises sampling MOS tubes MN4 inside, wherein the source electrode of each sampling MOS tube MN4 in each path of analog switch is connected to an analog signal input end, the drain electrode of each sampling MOS tube MN4 in each path of analog switch is connected to a signal output end, the grid electrode and the source electrode of each sampling MOS tube MN4 in each path of analog switch are respectively controlled by the channel selection signals and then are connected with two ends of bootstrap voltage of the bootstrap voltage generator, the sampling MOS tube MN4 of one path of analog switch is selected by the channel selection signals to be conducted, the conducted sampling MOS tube MN4 samples the analog signal input end connected with the sampling MOS tube MN4, and the sampling signals are output at the signal output end.
2. The analog multiplexer of claim 1, wherein: the bootstrap voltage generator comprises a bootstrap circuit enabling end, a first voltage output end and a second voltage output end, wherein the bootstrap circuit enabling end is used for receiving an enabling signal or a disabling signal, the bootstrap circuit enabling end charges after receiving the enabling signal so that voltage is arranged between the first voltage output end and the second voltage output end, and the bootstrap circuit enabling end removes charging after receiving the disabling signal so as to keep the voltage difference between the first voltage output end and the second voltage output end.
3. The analog multiplexer of claim 2, wherein: the bootstrap voltage generator further comprises a capacitor C1, a transistor MN10 and a transistor MN11, wherein two ends of the capacitor C1 are respectively connected with the first voltage output end and the second voltage output end, the bootstrap circuit enabling end is connected with control ends of the transistor MN10 and the transistor MN11, one end of the capacitor C1 is connected with a power supply through the transistor MN10, the other end of the capacitor C1 is grounded through the transistor MN11, the transistor MN10 and the transistor MN11 are conducted after the bootstrap circuit enabling end receives an enabling signal so that the capacitor C1 is charged, and the transistor MN10 and the transistor MN11 are turned off after the bootstrap circuit enabling end receives a disabling signal so that the capacitor C1 keeps a charged state and a voltage difference is generated between the first voltage output end and the second voltage output end.
4. An analog multiplexer according to claim 2 or 3, wherein: the bootstrap circuit further comprises a sampling control signal end and a logic gate unit, wherein the sampling control signal end and the bootstrap circuit enabling end are respectively connected to one input end of the logic gate unit, and the output end of the logic gate unit outputs the enabling signal or the disabling signal.
5. The analog multiplexer of claim 4, wherein: the logic gate unit is a NAND gate unit.
6. An analog multiplexer according to claim 3, wherein: the bootstrap voltage generator further comprises a transistor MP10, a transistor MP11, a capacitor C2 and a capacitor C3, the enabling end of the bootstrap circuit is connected to one end of the capacitor C2 and one end of the capacitor C3, the input end of the transistor MP10 and the input end of the transistor MP11 are connected to a power supply, the control end of the transistor MP10 is connected with the output end of the transistor MP11, the other end of the capacitor C3 and the control end of the transistor MN10, and the control end of the transistor MP11 is connected with the output end of the transistor MP10 and the other end of the capacitor C2.
7. The analog multiplexer of claim 1, wherein the analog switch further comprises a MOS transistor MN3, a gate of the MOS transistor MN3 is connected to a gate of the sampling MOS transistor MN4, a drain of the MOS transistor MN3 is connected to an analog signal input terminal and a source of the sampling MOS transistor MN4, a source of the MOS transistor MN3 is connected to one end of the bootstrap voltage, and the gate of the MOS transistor MN3 and the gate of the sampling MOS transistor MN4 are connected to the other end of the bootstrap voltage generator after being controlled by the channel selection signal.
8. The analog multiplexer of claim 7, wherein: the transistor MP0, the transistor MN0, the transistor MP1, the transistor MN5, the transistor MP2, the transistor MN2 and the inverter INV0 are further included, a channel selection signal input end is connected to a gate of the transistor MP0, a gate of the transistor MN0 and an input end of the inverter INV0, a source of the transistor MP0 is connected with a source of the transistor MP1 and the other end of the bootstrap voltage, a drain of the transistor MP0 is connected with a gate of the transistor MP1, a drain of the transistor MN0 and a drain of the transistor MN1, a drain of the transistor MP1 is connected with a gate of the transistor MN1 and a drain of the transistor MN5, a gate of the MOS transistor MN3 and a gate of the sampling MOS transistor MN4 are connected, a source of the transistor MN1 is connected with a drain of the transistor MP2 and a drain of the transistor MN2, a gate of the transistor MP2 is connected with an output end of the inverter 0, and a source of the transistor MP 5 is connected with a source of the transistor MN2 and a source of the transistor MN2 is connected with the ground.
9. An analog multiplexer according to claim 1, further comprising channel selection logic for converting the channel selection input signal to a channel selection signal.
10. An electronic device, characterized in that: comprising a plurality of signal inputs connected to respective ones of the analog signal inputs of the analog multiplexer, a selection output connected to a signal output of the analog multiplexer, and an analog multiplexer as claimed in any one of claims 1 to 9.
CN202311848851.7A 2023-12-29 2023-12-29 Analog multiplexer and electronic equipment Pending CN117595856A (en)

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CN202311848851.7A CN117595856A (en) 2023-12-29 2023-12-29 Analog multiplexer and electronic equipment

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CN202311848851.7A CN117595856A (en) 2023-12-29 2023-12-29 Analog multiplexer and electronic equipment

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CN117595856A true CN117595856A (en) 2024-02-23

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