CN117595855A - Capacitive digital isolator without standby power consumption - Google Patents

Capacitive digital isolator without standby power consumption Download PDF

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Publication number
CN117595855A
CN117595855A CN202311404915.4A CN202311404915A CN117595855A CN 117595855 A CN117595855 A CN 117595855A CN 202311404915 A CN202311404915 A CN 202311404915A CN 117595855 A CN117595855 A CN 117595855A
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China
Prior art keywords
input
output
link
pin
resistor
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CN202311404915.4A
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Chinese (zh)
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岳鹏阁
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Rongpai Semiconductor Shanghai Co ltd
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Rongpai Semiconductor Shanghai Co ltd
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Priority to CN202311404915.4A priority Critical patent/CN117595855A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention provides a capacitor type digital isolator without standby power consumption, which relates to the technical field of signal isolation and comprises the following components: the isolation layer is connected with the positive electrode pin of the input end of the capacitive digital isolator through an input link, the isolation layer is connected with the positive electrode pin of the output end of the capacitive digital isolator through an output link, the negative electrode pin of the input end of the capacitive digital isolator is connected with the controller, and the positive electrode pin of the input end is connected with an external power supply; the negative electrode pin of the input end of the capacitive digital isolator is connected with the negative electrode pin of the output end of the capacitive digital isolator through the isolating layer; the controller turns on the input link when outputting digital signals, the current of the external power supply is input from the positive electrode pin of the input end, is coupled through the isolation layer after being boosted by the input link, is output through the positive electrode pin of the output end after being boosted by the output link, and the input link and the output link are turned off when the controller does not output digital signals. The power supply circuit has the beneficial effects that no extra secondary side power supply is needed in the output link, and no standby power consumption is realized.

Description

Capacitive digital isolator without standby power consumption
Technical Field
The invention relates to the technical field of signal isolation, in particular to a capacitive digital isolator without standby power consumption.
Background
The digital isolator is a circuit device capable of realizing an isolation function and is mainly used for protecting and isolating the mutual influence among various circuits. In an electronic system, when a digital signal and an analog signal are transmitted, a digital isolator has a very high resistance isolation characteristic so as to realize isolation between the electronic system and a user. The basic principle is that photoelectric isolation technology or magnetic isolation technology is adopted, and light or magnetic field is used for replacing traditional current signals to transmit and process digital signals.
The main functions of the digital isolator include reducing noise of the ground loop, galvanic isolation ensuring that data transmission is not through an electrical connection or leakage path, thereby avoiding safety risks. Furthermore, the digital isolator is also capable of providing a reliable data transmission path between different voltage domains and does not require consideration for initialization at start-up.
However, isolation brings about restrictions in terms of delay, power consumption, cost, and size, and thus the design of digital isolators needs to meet safety requirements while minimizing adverse effects.
The traditional digital isolator is used for improving the signal transmission rate, and the power supplies at two sides are required to be independently supplied with power; as the threshold of the Energy-Star authentication standard is higher and higher, the requirement of low standby power consumption and even no standby power consumption is more and more urgent.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a capacitor type digital isolator without standby power consumption, which comprises the following components:
the isolation layer is connected with an input end positive electrode pin of the capacitive digital isolator through an input link, the isolation layer is connected with an output end positive electrode pin of the capacitive digital isolator through an output link, an input end negative electrode pin of the capacitive digital isolator is connected with the controller, and the input end positive electrode pin is connected with an external power supply;
the negative electrode pin of the input end of the capacitive digital isolator is connected with the negative electrode pin of the output end of the capacitive digital isolator through the isolating layer;
the controller is connected with the input link when outputting digital signals, the current of the external power supply is input from the positive electrode pin of the input end, is coupled through the isolation layer after being boosted through the input link, is then output through the positive electrode pin of the output end after being boosted through the output link, and the input link and the output link are disconnected when the controller does not output digital signals.
Preferably, the input link includes:
an input control circuit comprising:
the electrostatic protection tube, one end of the electrostatic protection tube is used as the positive pin of the input end, and the other end of the electrostatic protection tube is connected with the negative pin of the input end;
one end of the first resistor is connected with the positive electrode pin of the input end, the other end of the first resistor is connected with one end of the second resistor and the in-phase input end of the first operational amplifier, and the other end of the second resistor is connected with the negative electrode pin of the input end and the reverse input end of the first operational amplifier;
the grid electrode of the field effect transistor is connected with the output end of the first operational amplifier, the drain electrode of the field effect transistor is connected with the positive electrode pin of the input end, and the source electrode of the field effect transistor is connected with the negative electrode pin of the input end;
an input boost circuit comprising:
the anode of the first diode is connected with the positive pin of the input end, the cathode of the second diode is connected with the anode of the second diode, and the cathode of the second diode is connected with the isolating layer.
Preferably, the output link includes:
an output boost circuit comprising:
the anode of the third diode is connected with the isolation layer, and the cathode of the third diode is connected with the anode of the fourth diode;
a level clamp circuit comprising:
the cathode of the first zener diode is connected with the cathode of the fourth diode, and the anode of the first zener diode is connected with the negative pin of the output end;
an adjustment feedback circuit comprising:
one end of the third resistor is connected with the cathode of the first zener diode, the other end of the third resistor is connected with the positive input end of the second operational amplifier and the cathode of the second zener diode, and the anode of the second zener diode is connected with the anode of the first zener diode;
and the base electrode of the triode is connected with the output end of the second operational amplifier, the collector electrode of the triode is used as the positive electrode pin of the output end, and the emitter electrode of the triode is connected with one end of the third resistor.
Preferably, a first adjustable resistor and a second adjustable resistor which are connected in series are connected between the positive electrode pin of the output end and the negative electrode pin of the output end, and the reverse input end of the second operational amplifier is connected between the first adjustable resistor and the second adjustable resistor.
Preferably, the positive electrode pin of the input end is connected with one end of a fourth resistor, and the other end of the fourth resistor is connected with the external power supply;
the negative electrode pin of the input end is connected with one end of a fifth resistor, the other end of the fifth resistor is connected with the drain electrode of a second field effect transistor, the source electrode of the second field effect transistor is grounded, and the grid electrode of the second field effect transistor is connected with the controller;
the controller outputs a digital signal to turn on the second field effect transistor to turn on the input link.
Preferably, the isolation layer comprises an isolation medium, and the isolation medium is respectively connected with one ends of the first isolation capacitor, the second isolation capacitor, the third isolation capacitor and the fourth isolation capacitor;
the other end of the first isolation capacitor is connected with the input link, the other end of the second isolation capacitor is connected with the output link, the other end of the third isolation capacitor is connected with the negative electrode pin of the input end, and the other end of the fourth isolation capacitor is connected with the negative electrode pin of the output end.
Preferably, the input end of the output link and the negative electrode pin of the output end are further connected with:
and one end of the first capacitor is connected with the input end of the output link, the other end of the first capacitor is connected with one end of the second capacitor and grounded, and the other end of the second capacitor is connected with the negative pin of the output end.
Preferably, the positive input end of the input control circuit is connected with a band gap reference circuit.
Preferably, the input end of the output boost circuit is connected with a band gap reference circuit.
The technical scheme has the following advantages or beneficial effects: when an external controller inputs a digital signal, an input link is conducted, and the current transmitted by an output link through the input link is used as a working power supply to work along with the input link; when the controller does not control the input of the digital signal, the output link and the input link do not work, and no additional secondary side power supply is needed in the output link, so that no standby power consumption is realized.
Drawings
FIG. 1 is a schematic diagram of a capacitive digital isolator without standby power consumption according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram showing waveforms during transmission of high and low level digital signals according to a preferred embodiment of the present invention;
FIG. 3 is a circuit diagram of an input link in a preferred embodiment of the present invention;
FIG. 4 is a circuit diagram of an output link in accordance with a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram showing the connection of the clock and bandgap reference circuits in a preferred embodiment of the invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.
In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, there is now provided a capacitive digital isolator without standby power consumption, as shown in fig. 1, comprising:
the isolation layer 1 is connected with an input end positive electrode pin VIN+ of the capacitive digital isolator through an input link 2, the isolation layer 1 is connected with an output end positive electrode pin VOUT+ of the capacitive digital isolator through an output link 3, an input end negative electrode pin VIN-of the capacitive digital isolator is connected with the controller 4, and the input end positive electrode pin VIN+ is connected with an external power supply VCC;
the input end cathode pin VIN of the capacitive digital isolator is connected with the output end cathode pin VOUT+ of the capacitive digital isolator through the isolation layer 1;
the controller 4 is connected to the input link 2 when outputting a digital signal, the current of the external power supply VCC is input from the positive terminal pin vin+ of the input terminal, is coupled via the isolation layer 1 after being boosted by the input link 2, is then output from the positive terminal pin vout+ of the output terminal after being boosted by the output link 3, and the input link 2 and the output link 3 are disconnected when the controller 4 does not output a digital signal.
Specifically, in this embodiment, in order to increase the signal transmission rate of the conventional digital isolator, two independent external power supplies are required to supply power to the isolator on both sides of the isolation gate, the power supply is maintained in a normally open state, and after the input port is filled with high-low level digital signals, the signals are coupled by an electric field and cross-SiO 2 The isolation medium is transmitted to the output port, and the output side signal link part restores the high-low level signal state of the output input port to the coupled signal, so that the isolation transmission of the signal is realized.
The capacitive digital isolator takes standby power consumption as a primary consideration, and the input end of the input link is the positive electrode pin VIN+ of the input end of the digital isolator and is also used as a power supply of the input link 2;
the output link 3 receives the electric field signal coupled by the isolation layer 1, namely the electric field signal is used as a signal source output by the positive electrode pin VOUT+ of the output end of the isolator and is also used as a power supply source of the output link, an external power supply is not required to be additionally arranged on one side of the output end, and the output link 3 only works when the input link 2 has current input, so that the standby without power consumption is realized.
The capacitance type digital isolator is based on SiO2 isolation medium and isolation capacitance of a CMOS process as an isolation layer 1, and achieves relevant isolation voltage-withstanding functions.
When the controller 4 has a digital signal, the input link 2 is controlled to be conducted, the current of the external power supply VCC is input from the positive terminal pin VIN+ of the input end, is coupled through the isolation layer 1 after being boosted through the input link 2, and is output through the positive terminal pin VOUT+ of the output end after being boosted through the output link 2.
When the input link 2 is turned on, the current input by the external power supply VCC is represented as a high-low level digital signal, the current is input from the positive terminal pin vin+ of the input end (point a), the level voltage is lifted by the input link 2, the current reaches the point B, the high-low level digital signal at the point B reaches the point C through the isolation medium and the isolation capacitive coupling in the isolation layer 1, the level of the high-low level digital signal at the point C is lower due to capacitive voltage division, the level voltage is lifted by the output link 3, and the voltage is stabilized by the level clamping circuit in the output link 3, and finally the input high-low level digital signal is restored and output through the positive terminal pin vout+ of the output end, and the waveform change of the high-low level digital signal is shown in fig. 2.
In a preferred embodiment of the present invention, the input link 2 includes:
the input control circuit 21 includes:
an electrostatic protection tube ESD, wherein one end of the electrostatic protection tube ESD is used as an anode pin VIN+ of the input end, and the other end of the electrostatic protection tube ESD is connected with a cathode pin VIN-of the input end;
one end of the first resistor R1 is connected with the positive electrode pin VIN+ of the input end, the other end of the first resistor R1 is connected with one end of the second resistor R2 and the non-inverting input end of the first operational amplifier OP1, and the other end of the second resistor R2 is connected with the negative electrode pin VIN-of the input end and the inverting input end of the first operational amplifier OP 1;
a gate of the field effect transistor MOS is connected with the output end of the first operational amplifier OP1, a drain of the field effect transistor MOS is connected with the positive electrode pin VIN+ of the input end, and a source of the field effect transistor MOS is connected with the negative electrode pin VIN-of the input end;
the input boost circuit 22 includes:
the anode of the first diode D1 is connected with the anode pin VIN+ of the input end, the cathode of the second diode D2 is connected with the anode of the second diode D2, and the cathode of the second diode D2 is connected with the isolation layer 1.
In a preferred embodiment of the present invention, the positive terminal pin vin+ of the input terminal is connected to one end of a fourth resistor R4, and the other end of the fourth resistor R4 is connected to the external power VCC;
the negative electrode pin VIN of the input end is connected with one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected with the drain electrode of a second field effect transistor MOS2, the source electrode of the second field effect transistor MOS2 is grounded, and the grid electrode of the second field effect transistor MOS2 is connected with the controller 4;
the controller 4 outputs a digital signal to turn on the second field effect transistor MOS2 to turn on the input link 2.
Specifically, in this embodiment, as shown in fig. 3, the fourth resistor R4 and the fifth resistor R5 are current limiting resistors, the second field effect transistor MOS2 is used as a switching tube, and the external power VCC is connected to the positive terminal pin vin+ of the input terminal through a series current limiting resistor; the input end cathode pin VIN is connected with the drain electrode of an external switching tube through a series current limiting resistor; an input signal from an external controller 4 controls a switch of a switching tube to conduct an input control circuit 21 so as to charge and discharge a SiO2 isolation medium capacitor in the isolation layer 1 through an input link 2.
Considering that after the voltage drop of the high-low level digital signal across the SiO2 isolation medium is too low, the output link 3 cannot be started due to the too low level potential, so that the input boost circuit 22 is introduced to boost the output voltage of the a node (input control circuit 22), the a node voltage-D1-D2 of node B voltage=2 times, and D1 and D2 are the resistances of the first diode D1 and the second diode D2.
In a preferred embodiment of the present invention, the output link 3 includes:
the output booster circuit 31 includes:
a third diode D3, wherein an anode of the third diode D3 is connected to the isolation layer 1, and a cathode of the third diode D3 is connected to an anode of a fourth diode D4;
the level clamp circuit 32 includes:
the cathode of the first zener diode DS1 is connected with the cathode of the fourth diode D4, and the anode of the first zener diode DS1 is connected with the cathode pin VOUT-of the output end;
the regulation feedback circuit 33 includes:
one end of the third resistor R3 is connected with the cathode of the first zener diode DS1, the other end of the third resistor R3 is connected with the positive input end of the second operational amplifier OP2 and the cathode of the second zener diode DS2, and the anode of the second zener diode DS2 is connected with the anode of the first zener diode DS 1;
and a base electrode of the triode BJT is connected with the output end of the second operational amplifier OP2, a collector electrode of the triode BJT is used as an anode pin VOUT+ of the output end, and an emitter electrode of the triode BJT is connected with one end of the third resistor R3.
In a preferred embodiment of the present invention, a first adjustable resistor RH1 and a second adjustable resistor RH2 are connected in series between the positive terminal pin vout+ and the negative terminal pin VOUT-, and the inverting input terminal of the second operational amplifier is connected between the first adjustable resistor and the second adjustable resistor.
In a preferred embodiment of the present invention, the isolation layer 1 includes an isolation medium SiO2, where the isolation medium SiO2 is connected to one ends of the first isolation capacitor CA1, the second isolation capacitor CA2, the third isolation capacitor CA3 and the fourth isolation capacitor CA4, respectively;
the other end of the first isolation capacitor CA1 is connected with the input link 2, the other end of the second isolation capacitor CA2 is connected with the output link 3, the other end of the third isolation capacitor CA3 is connected with the negative electrode pin VIN-of the input end, and the other end of the fourth isolation capacitor CA4 is connected with the negative electrode pin VOUT-of the output end.
As shown in fig. 5, the cathode of the first diode D1 is sequentially connected to one end of the electrostatic protection tube ESD through a third capacitor C3 and a clock, the cathode of the second diode D2 is further connected to one end of the electrostatic protection tube ESD through a fourth capacitor C4, the cathode of the third diode D3 is sequentially connected to one end of the first capacitor C1 through a fifth capacitor C5 and the clock, and the cathode of the fourth diode D4 is connected to one end of the first capacitor C1 through a sixth capacitor C6.
Specifically, in this embodiment, as shown in fig. 3, the signal at the node C is a signal that the node B is coupled to through three capacitors of the isolation layers SiO2, CA1, CA2, and C1, and the amplitude of the signal after capacitive coupling has a certain attenuation; the level of the C node signal is simply equivalent to (1/C1)/(1/C1 +1/CA1+1/CA 2) the node-B voltage.
In addition, the level voltage amplitude of the C node coupling needs to ensure that a circuit in an output link can effectively work, and the output link is ensured to stably realize input-output conversion; c1 end energy = c1 x C point voltage/2.
And the CD node is the voltage of the C node, and the voltage after the bootstrap voltage of the output boost circuit and the voltage clamped by the level clamping line is used for the reference power supply voltage of the series feedback voltage stabilizing circuit.
According to the principle of virtual short and virtual break of an operational amplifier in the regulation feedback circuit, under the negative feedback of the depth of an output loop, VF=VREF, and VF/D node voltage=RH 1/(RH 1+RH 2); the D node voltage=vref (1+rh1/RH 2) can be calculated.
In the design, the output level of the digital isolator without standby power consumption can be adjusted through the external adjustment by adjusting the RH1/RH2 external adjustable resistor, so that the level conversion of input and output signals is realized; the output level amplitude is flexibly configurable by the user.
In a preferred embodiment of the present invention, a connection between the input end of the output link 2 and the negative terminal VOUT of the output end is further:
and one end of the first capacitor C1 is connected with the input end of the output link 2, the other end of the first capacitor C1 is connected with one end of the second capacitor C2 and grounded, and the other end of the second capacitor C2 is connected with the negative electrode pin VOUT-of the output end.
In a preferred embodiment of the present invention, the positive input terminal of the input control circuit 22 is connected to a bandgap reference circuit.
In a preferred embodiment of the present invention, the input end of the output boost circuit 31 is connected to a bandgap reference circuit.
Specifically, in this embodiment, as shown in fig. 5, a bandgap reference circuit is connected to the positive input end of the input control circuit 22 and the input end of the output boost circuit 31, and it can be determined by the bandgap reference circuit whether the voltage at the positive input end of the input control circuit 22 and the voltage at the input end of the output boost circuit 31 reach predetermined references, so as to determine whether the capacitive digital isolator works normally.
The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and drawings, and are intended to be included within the scope of the present invention.

Claims (9)

1. A capacitive digital isolator without standby power consumption, comprising:
the isolation layer is connected with an input end positive electrode pin of the capacitive digital isolator through an input link, the isolation layer is connected with an output end positive electrode pin of the capacitive digital isolator through an output link, an input end negative electrode pin of the capacitive digital isolator is connected with the controller, and the input end positive electrode pin is connected with an external power supply;
the negative electrode pin of the input end of the capacitive digital isolator is connected with the negative electrode pin of the output end of the capacitive digital isolator through the isolating layer;
the controller is connected with the input link when outputting digital signals, the current of the external power supply is input from the positive electrode pin of the input end, is coupled through the isolation layer after being boosted through the input link, is then output through the positive electrode pin of the output end after being boosted through the output link, and the input link and the output link are disconnected when the controller does not output digital signals.
2. The capacitive digital isolator of claim 1, wherein the input link comprises:
an input control circuit comprising:
the electrostatic protection tube, one end of the electrostatic protection tube is used as the positive pin of the input end, and the other end of the electrostatic protection tube is connected with the negative pin of the input end;
one end of the first resistor is connected with the positive electrode pin of the input end, the other end of the first resistor is connected with one end of the second resistor and the in-phase input end of the first operational amplifier, and the other end of the second resistor is connected with the negative electrode pin of the input end and the reverse input end of the first operational amplifier;
the grid electrode of the field effect transistor is connected with the output end of the first operational amplifier, the drain electrode of the field effect transistor is connected with the positive electrode pin of the input end, and the source electrode of the field effect transistor is connected with the negative electrode pin of the input end;
an input boost circuit comprising:
the anode of the first diode is connected with the positive pin of the input end, the cathode of the second diode is connected with the anode of the second diode, and the cathode of the second diode is connected with the isolating layer.
3. The capacitive digital isolator of claim 1, wherein the output link comprises:
an output boost circuit comprising:
the anode of the third diode is connected with the isolation layer, and the cathode of the third diode is connected with the anode of the fourth diode;
a level clamp circuit comprising:
the cathode of the first zener diode is connected with the cathode of the fourth diode, and the anode of the first zener diode is connected with the negative pin of the output end;
an adjustment feedback circuit comprising:
one end of the third resistor is connected with the cathode of the first zener diode, the other end of the third resistor is connected with the positive input end of the second operational amplifier and the cathode of the second zener diode, and the anode of the second zener diode is connected with the anode of the first zener diode;
and the base electrode of the triode is connected with the output end of the second operational amplifier, the collector electrode of the triode is used as the positive electrode pin of the output end, and the emitter electrode of the triode is connected with one end of the third resistor.
4. A capacitive digital isolator as claimed in claim 3, wherein a first adjustable resistor and a second adjustable resistor are connected in series between the positive output terminal pin and the negative output terminal pin, and the inverting input terminal of the second operational amplifier is connected between the first adjustable resistor and the second adjustable resistor.
5. The capacitive digital isolator of claim 1, wherein the input terminal positive pin is connected to one end of a fourth resistor, and the other end of the fourth resistor is connected to the external power source;
the negative electrode pin of the input end is connected with one end of a fifth resistor, the other end of the fifth resistor is connected with the drain electrode of a second field effect transistor, the source electrode of the second field effect transistor is grounded, and the grid electrode of the second field effect transistor is connected with the controller;
the controller outputs a digital signal to turn on the second field effect transistor to turn on the input link.
6. The capacitive digital isolator of claim 1, wherein the isolation layer comprises an isolation medium connected to one end of the first, second, third, and fourth isolation capacitors, respectively;
the other end of the first isolation capacitor is connected with the input link, the other end of the second isolation capacitor is connected with the output link, the other end of the third isolation capacitor is connected with the negative electrode pin of the input end, and the other end of the fourth isolation capacitor is connected with the negative electrode pin of the output end.
7. The capacitive digital isolator of claim 1, wherein the input of the output link and the output negative pin are further connected with:
and one end of the first capacitor is connected with the input end of the output link, the other end of the first capacitor is connected with one end of the second capacitor and grounded, and the other end of the second capacitor is connected with the negative pin of the output end.
8. The capacitive digital isolator of claim 2, wherein the positive input of the input control circuit is connected to a bandgap reference circuit.
9. A capacitive digital isolator as claimed in claim 3, wherein the input of the output boost circuit is connected to a bandgap reference circuit.
CN202311404915.4A 2023-10-27 2023-10-27 Capacitive digital isolator without standby power consumption Pending CN117595855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311404915.4A CN117595855A (en) 2023-10-27 2023-10-27 Capacitive digital isolator without standby power consumption

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311404915.4A CN117595855A (en) 2023-10-27 2023-10-27 Capacitive digital isolator without standby power consumption

Publications (1)

Publication Number Publication Date
CN117595855A true CN117595855A (en) 2024-02-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
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