CN117594653A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117594653A
CN117594653A CN202310967603.8A CN202310967603A CN117594653A CN 117594653 A CN117594653 A CN 117594653A CN 202310967603 A CN202310967603 A CN 202310967603A CN 117594653 A CN117594653 A CN 117594653A
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layers
nitride crystal
semiconductor device
crystal insulating
layer
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中村浩
塩井伸一
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Sanyan Japan Technology Co ltd
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Sanyan Japan Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Embodiments of the present invention provide a semiconductor device with high channel mobility and a method of manufacturing the semiconductor device. The semiconductor device includes: a first impurity region formed of silicon carbide of a first conductivity type; a drift layer formed of silicon carbide of a first conductivity type; a plurality of body regions formed of silicon carbide of a second conductivity type; a plurality of second impurity regions each formed of silicon carbide of the first conductivity type; a plurality of body contact regions each formed of silicon carbide of the second conductivity type; a plurality of gate electrodes formed inside the plurality of trenches, respectively; a plurality of first electrode layers on each of the plurality of body regions to be in contact with the second impurity regions; a second electrode layer formed on the first impurity region; and a plurality of nitride crystal insulating layers formed between the inside of each of the plurality of trenches and the gate electrode, including aluminum and nitrogen.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
Background
Patent document 1 discloses a semiconductor device. According to this semiconductor device, the impurity layer and the electrode layer can be prevented from being lowered in connectivity.
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open No. 2022-102450
Disclosure of Invention
However, in the semiconductor device described in patent document 1, in the structure of the gate insulating film of the related art and the method of forming the gate insulating film of the related art, a high-density interface level is introduced as defects at the interface between the base layer (or body region) and the gate insulating film. Therefore, the inherent high channel mobility of silicon carbide is suppressed. Resulting in insufficient reduction of channel resistance.
The present invention has been made to solve the above-described problems. The invention aims to provide a semiconductor device with high channel mobility and a manufacturing method of the semiconductor device.
A semiconductor device according to the present invention includes: a first impurity region formed of silicon carbide of a first conductivity type; a drift layer provided on a first surface of the first impurity region, the drift layer being formed of silicon carbide of a first conductivity type; a plurality of body regions disposed in the drift layer, the plurality of body regions being formed of silicon carbide of a second conductivity type, respectively; a plurality of second impurity regions provided in each of the plurality of body regions, the plurality of second impurity regions being formed of silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer, respectively; a plurality of body contact regions surrounded by the second impurity region in each of the plurality of body regions, the plurality of body contact regions being formed of silicon carbide of the second conductivity type having a higher impurity concentration than the body regions, respectively; a plurality of gate electrodes formed inside a plurality of trenches penetrating the body region and the second impurity region between adjacent body regions to the drift layer; a plurality of first electrode layers disposed on each of the plurality of body regions and respectively contacting the second impurity regions; a second electrode layer formed on a second surface of the first impurity region; and a plurality of nitride crystal insulating layers formed between the inner surfaces of the plurality of trenches and the gate electrode, the plurality of nitride crystal insulating layers including aluminum and nitrogen.
As one embodiment of the present invention, the plurality of nitride crystal insulating layers are formed on bottom surfaces and side surfaces of the plurality of trenches, respectively.
As one embodiment of the present invention, the plurality of nitride crystal insulating layers are formed of aluminum and nitrogen.
As one embodiment of the present invention, the plurality of nitride crystal insulating layers include boron.
As one embodiment of the present invention, the plurality of nitride crystal insulating layers include at least one of gallium, indium, and scandium.
As one aspect of the present invention, the semiconductor device further includes: and a plurality of oxide layers disposed inside each of the plurality of trenches and formed between the nitride crystal insulating layer and the gate electrode.
As one embodiment of the present invention, the plurality of oxide layers are silicon dioxide layers.
As one embodiment of the present invention, the plurality of oxide layers are aluminum oxide layers.
As one embodiment of the present invention, the plurality of nitride crystal insulating layers are thicker than the plurality of oxide layers.
As one aspect of the present invention, the side surfaces of the plurality of grooves are nonpolar surfaces.
The method for manufacturing a semiconductor device according to the present invention includes: a drift layer forming step of forming a drift layer from silicon carbide of a first conductivity type on a first surface of a first impurity region formed from silicon carbide of the first conductivity type; a body region forming step of forming a plurality of body regions from silicon carbide of the second conductivity type in the drift layer; a second impurity region forming step of forming a plurality of second impurity regions from silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer in each of the plurality of body regions; a body contact region forming step of forming a plurality of body contact regions from silicon carbide of the second conductivity type having an impurity concentration higher than that of the body regions, respectively, in such a manner that each of the plurality of body regions is surrounded by the second impurity region; a trench forming step of forming a plurality of trenches between adjacent body regions so as to penetrate the body region and the second impurity region and reach the drift layer; a gate electrode forming step of forming a plurality of gate electrodes in each of the plurality of trenches; a first electrode layer forming step of forming a plurality of first electrode layers on each of the plurality of body regions, the plurality of first electrode layers being in contact with the second impurity regions, respectively; a second electrode layer forming step of forming a second electrode layer on a second surface of the first impurity region; and a nitride crystal insulating layer forming step of forming a plurality of nitride crystal insulating layers containing aluminum and nitrogen, respectively, on the inner surface of each of the plurality of trenches after the trench forming step and before the gate electrode forming step.
As one embodiment of the present invention, the nitride crystal insulating layer forming step includes a step of heteroepitaxially growing the plurality of nitride crystal insulating layers.
As one embodiment of the present invention, the method for manufacturing a semiconductor device further includes: and an annealing step of smoothing the junction between the bottom surfaces and the side surfaces of the plurality of trenches after the trench forming step.
As one embodiment of the present invention, the nitride crystal insulating layer forming step includes a step of supplying hydrogen as a carrier gas.
As one embodiment of the present invention, the nitride crystal insulating layer forming step includes a step of forming the plurality of nitride crystal insulating layers by an MOCVD method or an ALD method.
As one aspect of the present invention, the method for manufacturing a semiconductor device further includes: an oxide layer forming step of forming a plurality of oxide layers on the plurality of nitride crystal insulating layers, respectively, in the interior of each of the plurality of trenches, the gate electrode forming step including a step of forming the plurality of gate electrodes on the plurality of oxide layers, respectively, in the interior of each of the plurality of trenches.
In one aspect of the present invention, the trench forming step includes a step of forming the plurality of trenches such that side surfaces of the plurality of trenches are nonpolar surfaces.
According to the present invention, a semiconductor device having high channel mobility and a method for manufacturing the semiconductor device can be provided.
Drawings
Fig. 1 is a longitudinal sectional view of a main part of a semiconductor device in embodiment 1.
Fig. 2 is a diagram for explaining a method for selecting a nitride crystal insulating layer of the semiconductor device according to embodiment 1.
Fig. 3 is a flowchart for explaining a method of manufacturing the semiconductor device in embodiment 1.
Description of the reference numerals
1, a semiconductor device; 2 a drain layer (first impurity region); 3, a drift layer (epitaxial layer); 4, a main body region; 5 a source layer (second impurity region); a body contact region; 7, an oxide layer; 8, a gate electrode; 9, an interlayer insulating layer; 10 a source electrode layer (first electrode layer); 11, wiring electrode layer; a drain electrode layer (second electrode layer); and 13, nitride crystal insulating layer.
Detailed Description
Embodiments are described with reference to the accompanying drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals. Repeated description of this portion is appropriately simplified or omitted.
Embodiment 1.
Fig. 1 is a longitudinal sectional view of a main part of a semiconductor device in embodiment 1.
In fig. 1, a semiconductor device 1 is a MISFET (Metal Insulator Semiconductor Field Effect Transistor, metal-insulator-semiconductor field effect transistor) of silicon carbide. The semiconductor device 1 is of a trench type. The semiconductor device 1 includes a drain layer 2, a drift layer 3 (which may also be referred to as an epitaxial layer), a plurality of body regions 4, a plurality of source layers 5, a plurality of body contact regions 6, a plurality of oxide layers 7, a plurality of gate electrodes 8, a plurality of interlayer insulating layers 9, a plurality of source electrode layers 10, a wiring electrode layer 11, a drain electrode layer 12, and a plurality of nitride crystal insulating layers 13.
In fig. 1, only one of the plurality of oxide layers 7, the plurality of gate electrodes 8, the plurality of interlayer insulating layers 9, and the plurality of nitride crystal insulating layers 13 is illustrated.
The drain layer 2 is formed of silicon carbide of the first conductivity type as a first impurity region. For example, the drain layer 2 is formed of n + Type 4H-SiC. For example, the drain layer 2 is formed using nitrogen as an impurity. The drift layer 3 is formed on a first surface (upper surface in fig. 1) of the drain layer 2. The drift layer 3 is formed of silicon carbide of the first conductivity type having a lower impurity concentration than the drain layer 2. For example, the drift layer 3 is n － A layer of the type. The drift layer 3 is formed on the drain layer 2 by epitaxial growth, for example.
A plurality of body regions 4 are formed in the drift layer 3. The plurality of body regions 4 are formed of silicon carbide of the second conductivity type. For example, the plurality of body regions 4 are p － A layer of the type. For example, the plurality of body regions 4 are formed by ion implantation using aluminum as an impurity. A plurality of source layers 5 are formed as second impurity regions in each of the body regions 4 of the plurality of body regions 4. The plurality of source layers 5 are formed of silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer 3. For example, the plurality of source layers 5 is n + A layer of the type. For example, the plurality of source layers 5 are formed by ion implantation using nitrogen as an impurity. A plurality of body contact regions 6 are formed on each body region 4 of the plurality of body regions 4. In each body region 4 of the plurality of body regions 4, a body contact region 6 is surrounded by the source layer 5. The plurality of body contact regions 6 are formed of silicon carbide of the second conductivity type having a higher impurity concentration than the plurality of body regions 4. For example, the plurality of body contact regions 6 are p + A layer of the type. For example, the plurality of body contact regions 6 are formed by ion implantation using aluminum as an impurity.
A plurality of oxide layers 7 are formed inside the plurality of trenches T, respectively. Each trench T passes through the body region 4 and the source layer 5 between adjacent body regions 4 to the drift layer 3, for example, the plurality of oxide layers 7 are silicon dioxide layers. For example, the plurality of oxide layers 7 are aluminum oxide layers. For example, the plurality of oxide layers 7 are formed by thermal oxidation. For example, the plurality of oxide layers 7 are formed by a CVD (Chemical Vapor Deposition ) method or an ALD (Atomic layer deposition, atomic layer deposition) method. A plurality of gate electrodes 8 are formed on the plurality of oxide layers 7 inside each of the plurality of trenches T, respectively. The plurality of gate electrode layers 8 are formed of polysilicon by CVD, for example.
The plurality of interlayer insulating layers 9 are formed so as to cover the plurality of gate electrodes 8, respectively, that is, the plurality of interlayer insulating layers 9 are provided in one-to-one correspondence with the plurality of gate electrodes 8. For example, the plurality of interlayer insulating layers 9 are formed by CVD. A plurality of source electrode layers 10 are formed corresponding to each body region 4 of the plurality of body regions 4. The source electrode layer 10 is formed as a first electrode layer so as to be in contact with the source layer 5. The source electrode layer 10 may be formed so as to cross the body contact 6. For example, the plurality of source electrode layers 10 are formed by forming a film of Ni (nickel) or the like by sputtering and performing a heat treatment. For example, the plurality of source electrode layers 10 are formed by forming Ti (titanium) films by sputtering. The wiring electrode layer 11 is formed so as to cover the plurality of source electrode layers 10. For example, the wiring electrode layer 11 is formed of an aluminum alloy by a sputtering method.
The drain electrode layer 12 is formed as a second electrode layer on the second surface (lower surface in fig. 1) of the drain layer 2. For example, the drain electrode layer 12 is formed by forming a film of Ni or the like by sputtering and performing a heat treatment.
In the present embodiment, a plurality of nitride crystal insulating layers 13 are added. A plurality of nitride crystal insulating layers 13 are formed between the inner surface of each of the plurality of trenches T and the oxide layer 7. Specifically, a plurality of nitride crystal insulating layers 13 are formed on the bottom surfaces and the side surfaces of the plurality of trenches T, respectively. Wherein the total thickness of the plurality of nitride crystal insulating layers 13 ranges from 2nm to 200nm. The total thickness of the plurality of oxide layers 7 ranges from 2nm to 200nm. The thicknesses of the plurality of nitride crystal insulating layers 13 and the plurality of oxides 7 may be arbitrarily combined within the above-described range. For example, the plurality of nitride crystal insulating layers 13 are thicker than the plurality of oxide layers 7. Specifically, for example, the total thickness of the plurality of nitride crystal insulating layers 13 is 80nm, and the total thickness of the plurality of oxide layers 7 is 3nm. Or the total thickness of the plurality of nitride crystal insulating layers 13 is 40nm and the total thickness of the plurality of oxide layers 7 is 20nm. For example, the plurality of nitride crystal insulating layers 13 are thinner than the plurality of oxide layers 7.
The plurality of nitride crystal insulating layers 13 contain aluminum and nitrogen. For example, the plurality of nitride crystal insulating layers 13 are formed of only aluminum and nitrogen. For example, the plurality of nitride crystal insulating layers 13 contain boron. For example, the plurality of nitride crystal insulating layers 13 contain gallium. For example, the plurality of nitride crystal insulating layers 13 contain indium or scandium.
The bottom surface of the groove T is a polar surface. Specifically, the bottom surface of the trench T is a (0001) Si surface or a (000-1) C surface. The sides of the trench T are nonpolar surfaces. Specifically, the side of the trench T is the (11-20) A face or the (1-100) M face or the (03-38) face.
For example, the nitride crystal insulating layer 13 is formed by heteroepitaxial growth using the bottom surface (crystal plane) and the side surface (crystal plane) of the trench T as growth surfaces, in an environment at a lower temperature than the homoepitaxial growth temperature of silicon carbide. For example, the nitride crystal insulating layer 13 is formed by an MOCVD (Metal-organic Chemical Vapor Deposition, metal organic chemical vapor deposition) method or an ALD method with the bottom surface and the side surface of the trench T as growth surfaces. For example, the nitride crystal insulating layer 13 is formed in an environment in which hydrogen is supplied as a carrier gas.
Next, a method of selecting the nitride crystal insulating layer 13 will be described with reference to fig. 2.
Fig. 2 is a diagram for explaining a method for selecting a nitride crystal insulating layer of the semiconductor device according to embodiment 1.
In fig. 2, regarding silicon carbide (4H-SiC) and nitride crystal insulating layer 13, the band gap, electron affinity, lattice constant a, lattice constant c, the number of molecular layers in the c-axis direction, and the length of the monolayer are shown.
The composition of the nitride crystal insulating layer 13 is selected in consideration of the band gap, electron affinity, lattice constant a, monolayer length, self band gap, electron affinity, lattice constant a, and monolayer length of silicon carbide (4H-SiC).
In the case of the trench semiconductor device 1, it is preferable that the difference between the lattice constant a of the nitride crystal insulating layer 13 and the lattice constant a of silicon carbide (4H-SiC) is small for the bottom surface of the trench T, for example, the percentage of difference between the lattice constant a of the nitride crystal insulating layer 13 and the lattice constant a of silicon carbide (4H-SiC) is-5% to +5%. The difference percentage of the two lattice constants a in this embodiment refers to the ratio of the difference of the two lattice constants a to the lattice constant a of silicon carbide, i.e., the difference percentage of the two lattice constants a= (the lattice constant a of the nitride crystal insulating layer 13-the lattice constant a of silicon carbide)/the lattice constant a of silicon carbide. On the other hand, it is preferable that the difference between the monolayer length of the nitride crystal insulating layer 13 and the monolayer length of silicon carbide (4H-SiC) is small on the side surface of the trench T, and for example, the percentage difference between the monolayer length of the nitride crystal insulating layer 13 and the monolayer length of silicon carbide (4H-SiC) is in the range of-5% to +5%. In this embodiment, the difference percentage of the lengths of both monolayers, i.e., the ratio of the difference in the lengths of both monolayers to the length of the monolayer of silicon carbide, i.e., the difference percentage of the lengths of both monolayers = (the length of the monolayer of nitride crystal insulating layer 13-the length of the monolayer of silicon carbide)/the length of the monolayer of silicon carbide.
As shown in fig. 2, the difference between the lattice constant a of aluminum nitride (AlN) and the lattice constant a of silicon carbide (4H-SiC) is small. The percentage difference of the lattice constant a of aluminum nitride to that of silicon carbide shown in fig. 2 is (0.311-0.307)/0.307=1.3%. The difference between the monolayer length of aluminum nitride (AlN) and the monolayer length of silicon carbide (4H-SiC) is small. The percentage difference in monolayer length of aluminum nitride to that of silicon carbide as shown in fig. 2 is (0.249-0.251)/0.251= -0.79%. Thus, in the first example, aluminum nitride (AlN) is selected as the nitride crystal insulating layer 13.
The composition of the nitride crystal insulating layer 13 may be selected so that the lattice constant a and the monolayer length of the nitride crystal insulating layer 13 are closer to those of silicon carbide (4H-SiC), respectively. By changing the composition of the nitride crystal insulating layer 13, the band gap, electron affinity, lattice constant a, and monolayer length are changed, and sometimes the composition of the nitride crystal insulating layer 13 is also selected in such a manner as to approach the lattice constant a and monolayer length of silicon carbide (4H-SiC).
For example, a composition in which boron (B) is added to the nitride crystal insulating layer 13 of the first example by several percent is selected as the nitride crystal insulating layer 13 of the second example. The doping concentration of boron in the second example is, for example, 0.1% to 50%. For example, a composition in which gallium (Ga) is added to the nitride crystal insulating layer 13 of the first example or the nitride crystal insulating layer 13 of the second example by several percent is selected as the nitride crystal insulating layer 13 of the third example. In a third example, the doping concentration of gallium is, for example, 0.1% to 50%. For example, a composition In which indium (In) is added by several percent to any one of the nitride crystal insulating layers 13 of the first example to the nitride crystal insulating layer 13 of the third example is selected as the nitride crystal insulating layer 13 of the fourth example. In the fourth example, the doping concentration of indium is, for example, 0.1% to 50%. For example, a composition in which scandium (Sc) is added by several percent to any one of the nitride crystal insulating layers 13 of the first example to the nitride crystal insulating layer 13 of the fourth example is selected as the nitride crystal insulating layer 13 of the fifth example. In a fifth example, the doping concentration of scandium is, for example, 0.1% to 50%. That is, the nitride crystal insulating layer 13 may be composed of undoped AlN alone, or any one or more of B, ga, in, and Sc may be selected as a dopant to be doped into aluminum nitride (AlN) to form the nitride crystal insulating layer 13.
The nitride crystal insulating layer 13 may be a combination of a plurality of material sublayers, that is, the nitride crystal insulating layer is a stack of a plurality of sublayers, and the materials of adjacent sublayers may be the same or different. For example, when aluminum nitride of the first example is used as the nitride crystal insulating layer 13, the nitride crystal insulating layer 13 may be a stack of a plurality of sublayers of undoped AlN. For example, when doped aluminum nitride doped with a dopant In any one of the second to fifth examples is used as the nitride crystal insulating layer 13, the nitride crystal insulating layer 13 may be a stack of a plurality of sub-layers made of a material doped with AlN, wherein the dopant In the sub-layers doped with AlN is one or more of B, ga, in, and Sc. The materials of the adjacent sublayers in which the material is doped AlN may be the same or different. The nitride crystal insulating layer 13 may also be formed by combining sub-layers of any one of the materials of the first and second examples to the fifth example, for example, i.e., the plurality of sub-layers may include a plurality of sub-layers of which material is undoped AlN and a plurality of sub-layers of which material is doped AlN, wherein dopants In the sub-layers of doped AlN are one or more of B, ga, in, and Sc. For example, multiple sublayers may form a superlattice structure.
For example, a layer of a superlattice structure may be formed as the nitride crystal insulating layer 13 of the sixth example by combining the nitride crystal insulating layer 13 of the first example having a thin thickness and the nitride crystal insulating layer of other composition having a thin thickness. Wherein in a sixth example the thickness of the monolayer in the layer of the superlattice structure is for example 1nm to 10nm.
For example, the plurality of sub-layers may include a plurality of sub-layers of undoped AlN and a plurality of sub-layers of boron nitride. For example, a layer of a superlattice structure may be formed by combining the nitride crystal insulating layer 13 of the first example, which is thin, and a layer of Boron Nitride (BN), which is thin, as the nitride crystal insulating layer 13 of the seventh example. In a seventh example, the thickness of the monolayer in the layer of the superlattice structure is, for example, 1nm to 10nm.
Next, a method for manufacturing the semiconductor device 1 will be described with reference to fig. 3.
Fig. 3 is a flowchart for explaining a method of manufacturing the semiconductor device in embodiment 1.
As shown in fig. 3, the semiconductor device 1 is manufactured by a first impurity region forming process, a drift layer forming process, a body region forming process, a second impurity region forming process, a body contact region forming process, a high temperature annealing process, a trench forming process, an annealing process, a nitride crystal insulating layer forming process, an oxide layer forming process, a gate electrode forming process, an interlayer insulating layer forming process, a first electrode layer forming process, a wiring electrode layer forming process, and a second electrode layer forming process.
In step S1, a first impurity region forming step is performed. In the first impurity region forming step, the substrate is formed as the drain layer 2. Then, in step S2, a drift layer forming process is performed. In the drift layer forming step, an epitaxial layer is formed as the drift layer 3.
Thereafter, in step S3, a body region forming process is performed. In the body region forming step, a plurality of body regions 4 are formed by an ion implantation method. Thereafter, in step S4, a second impurity region forming step is performed. In the second impurity region forming step, a plurality of source layers 5 are formed as second impurity regions by an ion implantation method. Thereafter, in step S5, a body contact region forming process is performed. In the body contact region forming step, a plurality of body contact regions 6 are formed by an ion implantation method. Thereafter, in step S6, a high temperature annealing process is performed. In the high-temperature annealing step, annealing is performed in a high-temperature environment in order to activate the ion-implanted impurity element (dopant).
Thereafter, in step S7, a trench forming process is performed. In the trench forming step, a plurality of trenches T are formed by etching. At this time, the nonpolar surfaces of the side surfaces are exposed by etching, thereby forming a plurality of trenches T. Thereafter, in step S8, an annealing process is performed. In the annealing step, the flatness of the bottom surface and the side surface is improved and the junction between the bottom surface and the side surface is smoothed in the plurality of trenches T. For example, the annealing step is performed in a silicon gas atmosphere.
Thereafter, in step S9, a nitride crystal insulating layer forming process is performed. In the nitride crystal insulating layer forming process, a plurality of nitride crystal insulating layers 13, for example, a stack of a plurality of sub-layers is formed by heteroepitaxial growth by the MOCVD method, as an example. Alternatively, the plurality of nitride crystal insulating layers 13 having crystallinity are formed by an ALD method. Thereafter, in step S10, an oxide layer forming process is performed. In the oxide layer forming step, a plurality of oxide layers 7 are formed by CVD. Thereafter, in step S11, a gate electrode forming process is performed. In the gate electrode forming step, a plurality of gate electrodes 8 are formed.
Thereafter, in step S12, an interlayer insulating layer forming process is performed. In the interlayer insulating layer forming step, an interlayer insulating layer 9 is formed. Thereafter, in step S13, a first electrode layer forming process is performed. In the first electrode layer forming step, a plurality of source electrode layers 10 are formed as first electrode layers. Thereafter, in step S14, a wiring electrode layer forming process is performed. In the wiring electrode layer forming step, the wiring electrode layer 11 is formed.
Thereafter, in step S15, a second electrode layer forming process is performed. In the second electrode layer forming step, the drain electrode layer 12 is formed as a second electrode layer.
According to embodiment 1 described above, inside each of the plurality of trenches T, the nitride crystal insulating layer 13 is formed between the inner surface of the trench T and the gate electrode 8. The nitride crystal insulating layer 13 contains aluminum and nitrogen. Therefore, the interface defect density between the inner surface of the trench T and the nitride crystal insulating layer 13 can be reduced. As a result, channel mobility can be improved.
In addition, a nitride crystal insulating layer 13 is formed on the bottom and side surfaces of the trench T. Therefore, the channel mobility can be more reliably improved.
In addition, the nitride crystal insulating layer 13 is formed of aluminum and nitrogen. Therefore, the nitride crystal insulating layer 13 can be easily formed.
In addition, the nitride crystal insulating layer 13 contains boron. Therefore, the channel mobility can be more reliably improved.
In addition, the nitride crystal insulating layer 13 contains at least one of gallium, indium, and scandium. Therefore, the channel mobility can be more reliably improved.
In addition, inside each of the plurality of trenches T, an oxide layer 7 is formed between the nitride crystal insulating layer 13 and the gate electrode 8. Therefore, leakage current of the gate can be suppressed.
In addition, the oxide layer 7 is silicon dioxide. Thus, the oxide layer 7 can be easily formed.
The oxide layer 7 is alumina. Thus, the oxide layer 7 can be easily formed.
In addition, the nitride crystal insulating layer 13 is thicker than the oxide layer 7. Therefore, the reliability of the semiconductor device 1 can be improved.
When misfit dislocation is introduced into the nitride crystal insulating layer 13 due to lattice mismatch, the nitride crystal insulating layer 13 may be thinned to a thickness at which misfit dislocation is not introduced, and the oxide layer 7 may be additionally deposited. In this case, the leakage current of the gate can be suppressed more reliably. As a result, the reliability of the semiconductor device 1 can be improved.
In addition, the side surfaces of the groove T are nonpolar surfaces. In this case, in the nitride crystal insulating layer 13 heteroepitaxially grown on the side surface of the trench T, the generation of the piezoelectric field can be suppressed. Therefore, the unevenness caused by the piezoelectric field can be suppressed. A high-quality semiconductor device 1 with suppressed variation in performance can be obtained.
In addition, the nitride crystal insulating layer 13 is formed by heteroepitaxial growth. The heteroepitaxial growth temperature of nitride is lower than that of silicon carbide (4H-SiC). Furthermore, oxygen is excluded from the heteroepitaxial growth furnace. Therefore, oxidation of silicon carbide can be suppressed, and at the same time, the high-quality nitride crystal insulating layer 13 can be formed.
Further, in the trench T, the flatness of the bottom surface and the side surface is improved by the annealing step, and the junction between the bottom surface and the side surface of the trench T is smoothed. In this case, the area where the electric field is locally increased at the boundary between the bottom surface and the side surface of the trench T can be reduced. Therefore, the electric field distribution at the boundary between the bottom surface and the side surface of the trench T can be improved. The occurrence of dielectric breakdown can be suppressed.
In addition, the nitride crystal insulating layer 13 is formed in an atmosphere in which hydrogen is supplied as a carrier gas. Therefore, the nitride crystal insulating layer 13 of high quality can be formed.
The nitride crystal insulating layer 13 is formed by the MOCVD method or the ALD method. Therefore, the nitride crystal insulating layer 13 of high quality can be formed.
Note that the gate insulating layer may be formed only from the nitride crystal insulating layer 13, and the oxide layer 7 may not be formed. In this case, the step S10 in fig. 3 may not be required.
The first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the channel mobility can also be improved.
The semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor ). In this case, will be the firstA drain layer 2 of an impurity region is set as P + The collector layer of the type is just required. The source layer 5 serving as the second impurity region may be an emitter layer. The source electrode layer 10 as the first electrode layer may be used as the emitter electrode layer. The drain electrode layer 12 serving as the second electrode layer may be a collector layer.
While aspects of at least one embodiment have been described, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Related alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the scope of the invention.
It is to be understood that the embodiments of the methods and apparatus described herein are not limited in their application to the details of construction and the arrangement of components set forth in the above description or illustrated in the drawings. The methods and apparatus are capable of other embodiments and of being practiced or of being carried out in various ways.
The particular embodiments are presented for purposes of illustration only and are not intended to be limiting.
The expressions and terms used herein are for the purpose of illustration and are not to be construed as limiting. The use of "including," "comprising," "having," "containing," and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
Any term in reference to "or" may be interpreted such that the use of "or" indicates one, more than one, and all of the stated terms.
About front, back, left and right, top and bottom, up and down, transverse and longitudinal the exterior and interior are for convenience of explanation. This related is not intended to limit the position or spatial orientation of any of the components of the present invention. Accordingly, the foregoing description and drawings are by way of example only.

Claims (28)

1. A semiconductor device, comprising:
a first impurity region formed of silicon carbide of a first conductivity type;
a drift layer provided on a first surface of the first impurity region, the drift layer being formed of silicon carbide of a first conductivity type;
a plurality of body regions disposed in the drift layer, the plurality of body regions being formed of silicon carbide of a second conductivity type, respectively;
a plurality of second impurity regions provided in each of the plurality of body regions, the plurality of second impurity regions being formed of silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer, respectively;
a plurality of body contact regions surrounded by the second impurity region in each of the plurality of body regions, the plurality of body contact regions being formed of silicon carbide of the second conductivity type having a higher impurity concentration than the body regions, respectively;
a plurality of gate electrodes formed inside a plurality of trenches penetrating the body region and the second impurity region between adjacent body regions to the drift layer;
a plurality of first electrode layers disposed on each of the plurality of body regions and respectively contacting the second impurity regions;
a second electrode layer formed on a second surface of the first impurity region; and
a plurality of nitride crystal insulating layers formed between the inner surfaces of the plurality of trenches and the gate electrode, the plurality of nitride crystal insulating layers including aluminum and nitrogen.
2. The semiconductor device according to claim 1, wherein,
the plurality of nitride crystal insulating layers are respectively formed on bottom surfaces and side surfaces of the plurality of grooves.
3. The semiconductor device according to claim 1, wherein,
the plurality of nitride crystal insulating layers are formed of aluminum and nitrogen.
4. The semiconductor device according to claim 1, wherein,
the plurality of nitride crystal insulating layers include boron.
5. The semiconductor device according to claim 1, wherein,
the plurality of nitride crystal insulating layers contain at least one of gallium, indium, and scandium.
6. The semiconductor device according to any one of claims 1 to 5, wherein,
further comprises: and a plurality of oxide layers disposed inside each of the plurality of trenches and formed between the nitride crystal insulating layer and the gate electrode.
7. The semiconductor device according to claim 6, wherein,
the plurality of oxide layers are silicon dioxide layers.
8. The semiconductor device according to claim 6, wherein,
the plurality of oxide layers are aluminum oxide layers.
9. The semiconductor device according to claim 6, wherein,
the plurality of nitride crystal insulating layers are thicker than the plurality of oxide layers.
10. The semiconductor device according to any one of claims 1 to 4, wherein,
the sides of the plurality of grooves are nonpolar surfaces.
11. A method for manufacturing a semiconductor device, comprising:
a drift layer forming step of forming a drift layer from silicon carbide of the first conductivity type on the first surface of the first impurity region; the first impurity region is formed of silicon carbide of a first conductivity type;
a body region forming step of forming a plurality of body regions from silicon carbide of the second conductivity type in the drift layer;
a second impurity region forming step of forming a plurality of second impurity regions from silicon carbide of the first conductivity type having an impurity concentration higher than that of the drift layer in each of the plurality of body regions;
a body contact region forming step of forming a plurality of body contact regions from silicon carbide of the second conductivity type having an impurity concentration higher than that of the body regions, respectively, in such a manner that each of the plurality of body regions is surrounded by the second impurity region;
a trench forming step of forming a plurality of trenches between adjacent body regions so as to penetrate the body region and the second impurity region and reach the drift layer;
a gate electrode forming step of forming a plurality of gate electrodes in each of the plurality of trenches;
a first electrode layer forming step of forming a plurality of first electrode layers on each of the plurality of body regions, the plurality of first electrode layers being in contact with the second impurity regions, respectively;
a second electrode layer forming step of forming a second electrode layer on a second surface of the first impurity region; and
and a nitride crystal insulating layer forming step of forming a plurality of nitride crystal insulating layers containing aluminum and nitrogen on the inner surface of each of the plurality of trenches, respectively, after the trench forming step and before the gate electrode forming step.
12. The method for manufacturing a semiconductor device according to claim 11, wherein,
the nitride crystal insulating layer forming process includes a process of growing the plurality of nitride crystal insulating layers using a process of heteroepitaxial growth.
13. The method for manufacturing a semiconductor device according to claim 11, wherein,
further comprises: and an annealing step of smoothing the junction between the bottom surfaces and the side surfaces of the plurality of trenches after the trench forming step.
14. The method for manufacturing a semiconductor device according to claim 11, wherein,
the nitride crystal insulating layer forming step includes a step of supplying hydrogen as a carrier gas.
15. The method for manufacturing a semiconductor device according to claim 11, wherein,
the nitride crystal insulating layer forming step includes a step of forming the plurality of nitride crystal insulating layers by an MOCVD method or an ALD method.
16. The method for manufacturing a semiconductor device according to claim 11, wherein,
further comprises: an oxide layer forming step of forming a plurality of oxide layers on the plurality of nitride crystal insulating layers, respectively, in the interior of each of the plurality of trenches;
the gate electrode forming step includes a step of forming the plurality of gate electrodes on the plurality of oxide layers, respectively, inside each of the plurality of trenches.
17. The method for manufacturing a semiconductor device according to any one of claims 11 to 16, wherein,
the groove forming step includes a step of forming the plurality of grooves such that side surfaces of the plurality of grooves are nonpolar surfaces.
18. A semiconductor device, comprising:
a first impurity region which is silicon carbide of a first conductivity type;
a drift layer provided on the first surface of the first impurity region, the drift layer being silicon carbide of a first conductivity type;
a plurality of body regions disposed in the drift layer, the plurality of body regions being silicon carbide of a second conductivity type,
and a second impurity region and a body contact region provided in the body region;
a trench disposed between adjacent body regions and having a bottom surface extending to the drift layer, wherein a gate electrode and a nitride crystal insulating layer are disposed in the trench, the gate electrode is disposed in the trench, the nitride crystal insulating layer is disposed on the bottom surface and the side surface of the trench, the gate electrode is insulated from the body regions and the drift layer, and the nitride crystal insulating layer contains elements Al and N;
a first electrode layer disposed on the surface of the body region and in contact with the second impurity region;
and a second electrode layer provided on a second surface of the first impurity region, the first surface being opposite to the second surface.
19. The semiconductor device according to claim 18, wherein the nitride crystal insulating layer is a stack of a plurality of sublayers of material undoped AlN.
20. The semiconductor device of claim 18, wherein the nitride crystal insulating layer is a stack of a plurality of sub-layers of material doped AlN, wherein dopants In the sub-layers doped AlN are one or more of B, ga, in, and Sc.
21. The semiconductor device of claim 18, wherein the plurality of nitride crystal insulating layers are stacks of a plurality of sub-layers including a plurality of sub-layers of undoped AlN and a plurality of sub-layers of doped AlN, wherein dopants In the sub-layers of doped AlN are one or more of B, ga, in, and Sc.
22. The semiconductor device according to claim 18, wherein the plurality of nitride crystal insulating layers are stacked layers composed of a plurality of sub-layers of undoped AlN and a plurality of sub-layers of BN.
23. The semiconductor device according to claim 18, wherein the plurality of nitride crystal insulating layers are stacked layers composed of a plurality of sub-layers of a material doped with AlN and a plurality of sub-layers of a material doped with BN, wherein a dopant In the sub-layers doped with AlN is one or more of B, ga, in, and Sc.
24. The semiconductor device according to any one of claims 20 to 23, wherein the nitride crystal insulating layer is a superlattice structure.
25. The semiconductor device according to claim 18, wherein an oxide layer is further provided in the trench, the oxide layer being provided between the nitride crystal insulating layer and the gate electrode.
26. The semiconductor device according to claim 25, wherein a material of the oxide layer is silicon oxide or aluminum oxide.
27. The semiconductor device according to claim 18, wherein a side surface of the trench is a nonpolar surface.
28. The semiconductor device according to claim 18, wherein,
the plurality of nitride crystal insulating layers contain at least one of gallium, indium, and scandium.
CN202310967603.8A 2022-08-10 2023-08-02 Semiconductor device and method for manufacturing the same Pending CN117594653A (en)

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