CN117594489A - Uniform temperature plate assembly, semiconductor wafer baking equipment and wafer baking heat radiation compensation method - Google Patents
Uniform temperature plate assembly, semiconductor wafer baking equipment and wafer baking heat radiation compensation method Download PDFInfo
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- 230000005855 radiation Effects 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
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- 230000008878 coupling Effects 0.000 claims abstract description 7
- 238000010168 coupling process Methods 0.000 claims abstract description 7
- 238000005859 coupling reaction Methods 0.000 claims abstract description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 6
- 238000005485 electric heating Methods 0.000 claims description 38
- 239000000919 ceramic Substances 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
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- 230000000903 blocking effect Effects 0.000 claims description 8
- 238000004891 communication Methods 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
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- 238000007751 thermal spraying Methods 0.000 claims description 3
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- 230000000694 effects Effects 0.000 abstract description 15
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- 230000000875 corresponding effect Effects 0.000 description 6
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- 229910000838 Al alloy Inorganic materials 0.000 description 4
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- 238000002310 reflectometry Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
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- 238000000265 homogenisation Methods 0.000 description 1
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- 230000003647 oxidation Effects 0.000 description 1
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Abstract
The invention relates to the technical field of semiconductor processing, and discloses a temperature equalizing plate assembly, semiconductor wafer baking equipment and a wafer baking heat radiation compensation method. Wherein, the samming dish subassembly includes: the temperature equalizing disc comprises a first area and a second area; a heat source thermally coupled to the temperature uniformity plate; and the thermal radiation compensation component maintains the uniformity of thermal radiation applied to the wafer by the first area in the wafer covering state. Preferably, the graphene layer with uniform thickness is covered on the heat conduction coupling surface of the temperature equalizing disc. Through the technical scheme, the heating of the second area can be improved, the heat dissipation can be reduced, or the temperature of the edge part of the wafer is lower than the temperature of the central zone of the wafer, and the problems that the wafer is heated insufficiently uniformly due to the heat shield effect and the uniform temperature index and the level of wafer baking are affected are solved.
Description
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a temperature equalizing plate assembly, semiconductor wafer baking equipment and a wafer baking heat radiation compensation method.
Background
The semiconductor uniform temperature heating equipment is an important and key equipment in the field of semiconductor processing, and the maximum deviation of the temperature of each part of the surface of a wafer during heating and baking is required to be not lower than a certain limit so as to ensure the consistency of the physical characteristics of the baked wafer and further ensure the yield of the wafer processing. Therefore, the uniformity of baking temperature is of great importance.
A common heating mode of the current semiconductor soaking heating device is to install a heating plate in an upper and lower cylindrical cavity, and install a heat source at the bottom of the heating plate to provide heat for the heating plate. The processed wafer is placed above the heating plate for baking, and a top cover with a ventilation opening is arranged above the wafer. During baking, the wafer surface and the uniform temperature surface are not in direct contact, and a certain gap is formed between the wafer surface and the uniform temperature surface, and the gap is about 0.1mm. The diameter of the soaking plate is generally about 15% larger than the wafer.
When baking the wafer, the area of the temperature equalizing plate not covered by the wafer is an annular buffer zone. The annular buffer belt has the functions of providing heating buffer for the temperature equalizing disc and facilitating the installation of the limit column. The purpose of providing a heating buffer is to: because the temperature of the edge of the temperature equalizing disc is seriously reduced, the diameter of the temperature equalizing disc is increased, so that the low-temperature edge can be far away from the wafer. In this way, the temperature of the temperature equalizing plate area projected below the wafer can be substantially uniform.
At present, the average temperature technicians want to perform homogenization design in terms of materials, structures and the like, but the actual effect is poor, and the uniformity under the wafer baking condition is difficult to improve.
Disclosure of Invention
The inventors found that: the temperature of the isopipe is already very uniform without covering the wafer. However, once the wafer is covered on the hotplate, the otherwise uniform thermal field on the hotplate is broken. This phenomenon is the heat shield effect brought about by the wafer cover.
The heat shield effect was first proposed by the inventors, which means: the wafer itself plays the shielding effect to the upward radiation of samming dish for the radiation in the wafer coverage is sheltered from, and the radiation outside the wafer scope is direct to pass through, thereby forms relatively strong heat dissipation area. The temperature of the shielded part of the temperature equalizing disc is increased, and the temperature of the part of the radiation passing through the buffer zone of the disc body is relatively lower, so that the temperature of the disc body near the buffer zone is lowered, and the temperature of the edge part of the wafer is lower than that of the central zone of the wafer.
Based on the above, the invention provides a temperature equalizing plate assembly, a semiconductor wafer baking device and a wafer baking heat radiation compensation method, so as to solve the problem that the wafer is heated insufficiently uniformly due to the heat shield effect, and the temperature equalizing index and the level of wafer baking are affected.
In order to achieve the above object, a first aspect of the present invention provides a temperature uniformity plate assembly, comprising:
the temperature equalizing disc comprises a first area and a second area;
a heat source thermally coupled to the temperature uniformity plate;
and the thermal radiation compensation component maintains the uniformity of thermal radiation applied to the wafer by the first area in the wafer covering state.
Preferably, the graphene layer with uniform thickness is covered on the heat conduction coupling surface of the temperature equalizing disc.
Further:
the first region comprises R with the center of the temperature equalizing disc as an origin 1 An area defined by a radius;
the second region is formed into a circular ring structure, and comprises R with the center of the temperature equalizing disk as an origin 1 Is of inner diameter, R 2 A region defined for the outer diameter;
preferably, the first region and the second region are both continuous and uninterrupted.
Further, the heat source includes an electric heating plate;
preferably, the electric heating plate is arranged at the bottom of the temperature equalizing plate and is parallel to the temperature equalizing plate;
the electric heating plate includes:
an electrical heating circuit thermally coupled to the first region and the second region, respectively;
or alternatively, the first and second heat exchangers may be,
an electrical heating circuit thermally coupled to the first region and the second region; the density of the electrothermal wires distributed in the second area is greater than that of the electrothermal wires distributed in the first area; preferably, the ratio of power density of the electrothermal wire distributed in the first area to the electrothermal wire distributed in the second area is 1:2 to 5;
or alternatively, the first and second heat exchangers may be,
the electric heating lines are respectively and thermally coupled to the first area and the second area, and the electric heating line density of the electric heating plate corresponding to the wafer edge area is set to be greater than that of the electric heating plate corresponding to the wafer center area;
or alternatively, the first and second heat exchangers may be,
the same electrothermal circuit is thermally coupled with the first area and the second area, the density of electrothermal circuits distributed in the second area is greater than that of electrothermal circuits distributed in the first area, and the density of electrothermal circuits of electrothermal plates corresponding to the wafer edge area is set to be greater than that of electrothermal circuits of electrothermal plates corresponding to the wafer center area; preferably, the ratio of power density of the electrothermal wire distributed in the first area to the electrothermal wire distributed in the second area is 1:2 to 5.
Further, the thermal radiation compensation assembly comprises a thermal block tank; the heat-resistant groove is arranged on one side end face of the temperature equalizing disc, which faces the heat source;
preferably, the heat-resistant groove is of an annular structure and is arranged concentrically with the temperature equalizing disc;
further preferably, the diameter of the heat-blocking groove is 0.65 to 1.0 times the diameter of the first region;
further preferably, the depth of the heat-resistant groove is two-fifths to four-fifths of the thickness of the temperature equalizing plate.
Further, the thermal radiation compensation assembly comprises a heat shielding ring covered on the second area and a limit post for fixing the heat shielding ring;
preferably, the peripheral edge of the heat shielding ring is aligned with the peripheral edge of the second region;
preferably, the outer diameter of the heat shielding ring is R 2 The inner diameter is slightly larger than R 1 ；
Further preferably, the heat shielding ring is made of the same material as the wafer to be processed;
preferably, the plurality of limit posts are rotationally symmetrical with the axis of the temperature equalizing disc as the center.
Further, the thermal radiation compensation assembly further comprises a ceramic pad for the overhead wafer;
the ceramic gasket is positioned on or above the upper end surface of the heat shielding ring and partially stretches into the ceramic gasket in the first area;
or alternatively, the first and second heat exchangers may be,
the ceramic gasket is positioned at or below the lower end surface of the heat shielding ring and partially extends into the first area;
preferably, the distance between the lower surface of the heat shielding ring and the upper surface of the temperature equalizing plate is H 1 The method comprises the steps of carrying out a first treatment on the surface of the The distance between the upper surface of the ceramic gasket and the upper surface of the temperature equalizing disc is H 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein H is 1 ＝H 2 ；
Further preferably, the ceramic spacer has a thickness of 0.1mm.
Further:
oxide layers with different thicknesses are formed on the surfaces of the first area and the second area; preferably, the thickness of the oxide layer of the first area is 18-40 μm, and the thickness of the oxide layer of the surface of the second area is 2 μm;
or alternatively, the first and second heat exchangers may be,
the second region is provided with a higher finish than the first region; preferably, the second region has a finish of 0.1 to 0.8 and the first region has a finish of 0.8 to 1.6.
A second aspect of the present invention provides a semiconductor wafer baking apparatus comprising:
the temperature equalizing disc assembly is arranged on the upper surface of the base;
or alternatively, the first and second heat exchangers may be,
the device comprises a temperature equalizing disc, a heat source and a top cover, wherein the temperature equalizing disc comprises a first area and a second area; the heat source is thermally coupled to the temperature uniformity plate; a top cover radiation baffle ring is arranged on the end face of the top cover facing the temperature equalizing disc; the area defined by the top cover radiation baffle ring covers the upper part of the first area; preferably, the top cover radiation baffle ring is aligned with the boundary line of the first area and the second area;
or alternatively, the first and second heat exchangers may be,
the top cover and the temperature equalizing disc assembly; a top cover radiation baffle ring is arranged on the end face of the top cover facing the temperature equalizing disc; the area defined by the top cover radiation baffle ring covers the upper part of the first area; preferably, the top cover radiation baffle ring is aligned with the boundary line of the first area and the second area.
A third aspect of the present invention provides a wafer baking thermal radiation compensation method, comprising: blocking heat radiation communication between the first region and the second region.
The fourth aspect of the present invention provides a wafer baking thermal radiation compensation method, which comprises the steps of processing the temperature equalizing plate in any one of the following processing modes:
(a) Oxidizing the first region and the second region to form a radiation rate epsilon 1 And epsilon 2 Wherein ε is 2 ＞ε 1 ；
(b) Performing thermal spraying treatment on the first region and the second region to respectively form a radiation rate epsilon 3 And epsilon 4 Wherein ε is a coating of 4 ＞ε 3 ；
(c) PVD processing is carried out on the first area and the second area to respectively form the radiation rate epsilon 5 And epsilon 6 Wherein ε is a coating of 6 ＞ε 5 ；
(d) Electroplating the first region and the second region to form a radiation rate epsilon 7 And epsilon 8 Wherein ε is a coating of 8 ＞ε 7 ；
(e) And polishing the first area and the second area so that the smoothness of the second area is higher than that of the first area.
Through the technical scheme, the heating of the second area can be improved, the heat dissipation can be reduced, or the temperature of the edge part of the wafer is lower than the temperature of the central zone of the wafer, and the problems that the wafer is heated insufficiently uniformly due to the heat shield effect and the uniform temperature index and the level of wafer baking are affected are solved.
Drawings
In order to describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings used in the embodiments or the background of the present application.
FIG. 1 is a schematic diagram of one embodiment of a temperature uniformity plate assembly of the present invention;
FIG. 2 is a top view of the removed wafer of FIG. 1;
FIG. 3 is a perspective view of FIG. 1;
FIG. 4 is a schematic diagram of the distribution of the electric heating wires in the electric heating plate;
FIG. 5 is a schematic diagram of a third embodiment;
FIG. 6 is a cross-sectional view of A-A of FIG. 5;
FIG. 7 is a schematic diagram of a fifth embodiment;
FIG. 8 is a schematic diagram of one embodiment of a semiconductor wafer baking apparatus of the present invention;
FIG. 9 is a schematic illustration of the heat shield effect;
fig. 10 is a schematic diagram of a third embodiment.
In the figure: 10, a temperature equalizing disc; 11 a first region; a second region 12; 20 heat sources; 31 a heat-resistant tank; 32 a heat shielding ring; 33 limit posts; a ceramic spacer 34; a 40 top cover; 41 top cover radiation baffle ring; wafer 100.
Detailed Description
Embodiments of the present application are described below with reference to the accompanying drawings in the embodiments of the present application.
In the description of the embodiments of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and for example, "connected" may be either detachably connected or non-detachably connected; may be directly connected or indirectly connected through an intermediate medium. References to directional terms in the embodiments of the present application, such as "upper", "lower", "left", "right", "inner", "outer", etc., are merely with reference to the directions of the drawings, and thus, the directional terms are used in order to better and more clearly describe and understand the embodiments of the present application, rather than to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the present application. "plurality" means at least two.
In the embodiment of the present application, "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
The inventors found that: the temperature of the hotplate 10 is already very uniform without covering the wafer. However, once the wafer is covered on the hotplate 10, the otherwise uniform thermal field on the hotplate 10 is broken (as shown in fig. 9). This phenomenon is the heat shield effect brought about by the wafer cover.
The heat shield effect was first proposed by the inventors, which means that: the wafer itself plays the shielding effect to the upward radiation of samming dish for the radiation in the wafer coverage is shielded, and the radiation outside the wafer scope is direct to pass through. The temperature of the shielded part of the temperature equalizing disc is increased, and the temperature of the part of the radiation passing through the buffer zone of the disc body (the temperature equalizing disc) is relatively lowered, so that the temperature of the disc body nearby the buffer zone is lowered, the temperature of the edge part of the wafer is lower than the temperature of the central zone of the wafer, and the temperature equalizing index and the level of wafer baking are affected.
Based on the finding of the problem, the invention provides a temperature equalizing disc assembly, semiconductor wafer baking equipment and a wafer baking heat radiation compensation method, so as to solve the problem that the wafer is heated unevenly due to the heat shield effect, and the temperature equalizing index and the level of wafer baking are affected.
In order to solve the technical problem, a first aspect of the present invention provides a temperature equalizing disc assembly. As shown in fig. 1, the temperature uniformity plate assembly includes a temperature uniformity plate 10, a heat source 20, and a heat radiation compensation assembly.
As shown in fig. 2, the temperature uniformity plate 10 is divided into a first region 11 and a second region 12. There is no objective demarcation between the first region 11 and the second region 12, and the dashed lines shown in fig. 2 are added for ease of understanding and description. The extent of the first region 11 and the second region 12 is determined by other factors, which will be described later.
As shown in fig. 2, the first region 11 includes a center of the temperature uniformity plate 10 as an origin, R 1 Is the area defined by the radius. The second region 12 is formed in a circular ring structure, and includes an origin point, R, which is the center of the temperature uniformity plate 10 1 Is of inner diameter, R 2 Is the area defined by the outer diameter. In a preferred embodiment, the first region 11 and the second region 12 are each provided continuously and uninterruptedly.
It should be noted that "the first region 11 and the second region 12 are both continuous and uninterrupted" means that the first region 11 is continuous throughout, and the second region 12 is continuous throughout, instead of being formed by splicing a plurality of fan-shaped or other shaped structures.
As shown in fig. 1-3, the heat source 20 is thermally coupled to the temperature uniformity plate 10 to provide heat to the temperature uniformity plate 10. The thermal radiation compensation assembly is configured to maintain uniformity of thermal radiation applied to the wafer 100 by the first region 11 in the wafer covered state.
In a preferred embodiment, the thermally conductive coupling surface of the temperature equalizing plate 10 is covered with a graphene layer with a uniform thickness. Based on the characteristics of graphene on heat conduction, when the graphene layer is covered on the heat conduction coupling surface of the temperature equalizing disc 10, heat conduction in the radial direction of the temperature equalizing disc 10 is faster than that in the axial direction. This allows the entire thermally conductive coupling surface of the temperature uniformity plate 10 to reach a uniform temperature in a short time. After the whole heat conduction coupling surface of the temperature equalizing disc 10 reaches a uniform temperature, heat is more uniform when transferred along the axial direction of the temperature equalizing disc 10, so that heat radiation emitted outwards by the temperature equalizing disc 10 is more uniform. In actual baking of the wafer, the wafer 100 is placed in the center of the hotplate 10, and the extent of the first region 11 is determined by the size of the wafer, i.e., the size of the first region 11 is equal to the size of the wafer.
Further detailed description is provided below, how to solve the problem that the uniform temperature index and the level of wafer baking are affected due to insufficient uniform heating of the wafer caused by the heat shield effect.
The first embodiment is as follows:
the heat source 20 comprises an electric heating plate which is arranged at the bottom of the temperature equalizing plate 10 and is parallel to the temperature equalizing plate 10. The electric heating plate includes electric heating wires thermally coupled to the first region 11 and the second region 12, respectively.
It will be appreciated that the heat source 20 herein comprises two separate electric heating plates thermally coupled to the first region 11 and the second region 12, respectively. By providing two separate electric heating plates, the temperatures of the first region 11 and the second region 12 can be adjusted to be different. Further, the heat radiation emitted from the second region 12 to the outside can be increased to a level of the first region 11 even higher in the wafer covered state. This prevents the temperature of the wafer edge from being pulled down during wafer baking so that the temperature of the wafer edge portion is no longer lower than the temperature of the wafer center zone.
The second embodiment is as follows:
the heat source 20 comprises an electric heating plate which is arranged at the bottom of the temperature equalizing plate 10 and is parallel to the temperature equalizing plate 10. The hotplate comprises the same electrothermal wire thermally coupled to said first region 11 and said second region 12. As shown in fig. 4, the density of the electric heating wires distributed in the second area 11 is greater than the density of the electric heating wires distributed in the first area 11. Preferably, the ratio of power density of the electrothermal wire distributed in the first region 11 to the electrothermal wire distributed in the second region 12 is 1:2 to 5.
It will be appreciated that, unlike the present embodiment, the heat source 20 includes only one electric heating plate thermally coupled to both the first and second regions 11 and 12, and the electric heating lines are distributed at different densities between the first and second regions 11 and 12. The purpose of this arrangement is that: it is ensured that the temperature of the second region 12 is equal to or even higher than the temperature of the first region 11 when the wafer is baked. The condition that the temperature of the edge part of the wafer is lower than the temperature of the central zone of the wafer and finally the quality of the wafer is influenced because the temperature of the second area 12 is lower than the temperature of the first area 11 and the heat radiation communication exists between the second area 12 and the first area 11 is prevented.
And a third specific embodiment:
as shown in fig. 5 and 6, the heat radiation compensation assembly includes a heat blocking groove 31. The heat-blocking groove 31 is provided on an end surface of the temperature equalizing plate 10 on a side facing the heat source 20. Preferably, the heat-blocking groove 31 is provided in a ring structure and is concentric with the temperature equalizing plate 10. The depth of the heat-resistant groove 31 is two-fifths to four-fifths of the thickness of the temperature equalization plate 10.
When the distribution density of the electric heating wires in the first region 11 and the second region 12 is uniform and identical, due to the low steric barrier of the heat blocking grooves 31, heat radiation of the first region 11 and the second region 12 does not exchange in an ideal state because heat is transferred upward along the axis of the temperature uniformity plate 10 in both the first region 11 and the second region 12. The temperature at the edge of the wafer will not be pulled down.
However, in actual operation, although the heat radiation communication between the first region 11 and the second region 12 is negligible. It is undeniable that some heat radiation communication between the two areas does occur. In order to solve this problem, the technical solution of the first embodiment or the second embodiment may be referred to, as shown in fig. 10, on the basis of providing the heat-blocking groove 31, the densities of the electric heating wires thermally coupled to the first region 11 and the second region 12 are set to be different, or two independent heat-conducting plates are provided and thermally coupled to the first region 11 and the second region 12, respectively.
The specific embodiment IV is as follows:
on the basis of the first embodiment or the second embodiment, the density of the electric heating wires in the first area 11 is further defined: and setting the electric heating circuit density of the electric heating plate corresponding to the wafer edge area to be smaller than the electric heating circuit density of the electric heating plate corresponding to the wafer center area.
On the basis of this, the diameter of the heat-blocking groove 31 is set to 0.65 to 1.0 times the diameter of the first region 11. I.e. such that the thermal barrier 31 is located further inward than the wafer edge test points. In this way, heat exchange between the edge region of the wafer and the center region of the wafer can be reduced or prevented, thereby improving the uniformity of the wafer baking temperature.
Fifth embodiment:
as described above, the heat shield effect is due to the fact that the wafer does not completely cover the temperature uniformity plate 10, and the buffer zone (the area not covered by the wafer, i.e. the second area 12) is exposed, so that the buffer zone area is less shielded, resulting in more heat dissipation and lower temperature. Therefore, shielding the buffer tape (second region 12) as well can reduce the problem of excessive heat dissipation of the buffer tape (second region 12). In this embodiment, an annular heat shielding structure (for example, an annular wafer or an aluminum alloy) with a proper size and thickness is installed at the buffer zone position of the temperature equalizing plate 10 to cover the exposed buffer zone (the second zone 12) according to the wafer baking condition at the edge of the temperature equalizing plate 10. The inventors named this annular heat shielding structure as a "heat shielding ring". In the embodiment of the present invention, the heat shielding ring 32 is formed by cutting a wafer made of the same material as the wafer to be baked.
As shown in fig. 7, the heat shielding ring 32 may be mounted on the temperature uniformity plate 10 through a limit post 33. Preferably, the peripheral outer edge of the heat shielding ring 32 is aligned with the peripheral outer edge of the second region 12. The outer diameter of the heat shielding ring 32 is set to R 2 The inner diameter is set to be slightly larger than R 1 The purpose is to maintain a certain gap between the heat shield ring 32 and the wafer. Preferably, a plurality of limit posts 33 are provided, and the plurality of limit posts 33 are rotationally symmetrical about the axis of the temperature uniformity plate 10. The present embodiment also provides a ceramic spacer 34. The ceramic spacer 34 is disposed on the upper end surface or above the heat shielding ring 32, or may be disposed on the lower end surface or below the heat shielding ring 32, and the ceramic spacer 34 needs to partially extend into the first area 11 to overhead the wafer.
In order to ensure the same heat conduction link, as shown in the enlarged portion of fig. 7, it is preferable to provide a ceramic spacer 34 on the lower end face of the heat shielding ring 32, that is, the ceramic spacer 34 is located between the heat shielding ring 32 and the temperature uniformity plate 10. Further, willThe distance between the lower surface of the heat shielding ring 32 and the upper surface of the temperature equalizing plate 10 is set to be H 1 The distance between the upper surface of the ceramic spacer 34 and the upper surface of the temperature uniformity plate 10 is set to be H 2 ，H 1 ＝H 2 . In this way, the heat shield ring 32 has the same overhead height relative to the hotplate 10 as the wafer 100 being baked, ensuring the same thermal link. Further preferably, the thickness of the ceramic spacer 34 is set to 0.1mm.
Before baking, the mechanical arm conveys the wafer to the position above the temperature equalizing disc 10, the lifting device puts down the wafer, the wafer falls into a vacancy in the middle of the heat shielding ring 32 under the constraint of the limiting column 33, and then baking of the wafer is started.
Specific embodiment six:
for aluminum alloys, the emissivity of the surface oxide layer is directly related to and proportional to the film thickness. The thicker the film layer, the higher the emissivity and the lower the reflectivity. The data show that the emissivity of the aluminum alloy oxide film layer increases substantially linearly from 20% to 55% of the thickness of 2 μm. In the processing process, different surface oxidation thickness parameters are respectively set for the middle wafer baking area (the first area 11) and the buffer zone (the second area 12) of the temperature equalizing disc 10, so that the thickness of the film layer on the temperature equalizing disc 10 is thin at the middle thick edge. Specifically, an oxide layer having a thickness of 18 μm to 40 μm is provided in the first region 11, and an oxide layer having a thickness of 2 μm is provided in the second region 12.
In this way, when the wafer is baked, the temperature of the second region 12 can be increased to be equal to or even higher than the temperature of the first region 11, temperature compensation can be achieved, thermal radiation communication between the first region 11 and the second region 12 can be prevented, and the temperature of the edge portion of the wafer can be prevented from being lower than the temperature of the central zone of the wafer.
Seventh embodiment:
kirchhoff's law is one of the bases of thermal radiation theory. Kirchhoff's law states that: a good absorber must be a good emitter. Emissivity = absorptivity = 1-reflectivity of the object.
The ability of an object to radiate and absorb infrared radiation is highly correlated with the smoothness of its surface. The surface smoothness is high, the absorption force/radiation force is weak, and the reflection force is strong; the surface finish is low, and the absorption force/radiation force is strong and the reflection force is weak. The reason why the surface pits increase the absorption/emissivity is that the light is finally absorbed and converted into heat energy after being reflected and refracted many times on the rough surface, just like a blackbody darkroom absorbs photons.
The reflectivity of the metal surface and the surface finish are in positive correlation, taking aluminum alloy as an example, and the relationship between the surface finish and the emissivity is shown in table 1:
TABLE 1 Metal surface finish and emissivity relationship
Based on this, in the present embodiment, the finish of the second region 12 is set higher than that of the first region 11. Preferably, the finish of the first region 11 is set to 0.8 to 1.6, and the finish of the second region 12 is set to 0.1 to 0.8. It is further preferred that the intermediate wafer bake zone (first zone 11) be taken to have a slightly rough finish of 0.8, while the edge buffer zone (second zone 12) is taken to have a finish of 0.1 or even higher in the mirror level. In this way, the radiation heat dissipation of the buffer zone (second zone 12) is significantly reduced, and temperature compensation is achieved. During the wafer baking operation, the temperature of the second region 12 can be increased, so that the heat of the first region 11 is prevented from flowing to the second region 12, and the temperature of the edge region of the first region 11 is reduced, thereby affecting the uniformity of the temperature of the wafer.
It should be noted that, the first embodiment and the sixth embodiment may be selectively combined as required, so as to achieve the purpose of the present application, and solve the technical problem to be solved by the present application.
Eighth embodiment:
the embodiment provides a semiconductor wafer baking apparatus, as shown in fig. 8, which includes the temperature equalizing plate assembly.
Detailed description nine:
the present embodiment provides a semiconductor wafer baking apparatus, as shown in fig. 8, which includes a temperature uniformity plate 10, a heat source 20, and a top cover 40. The temperature equalizing disc 10 comprises a first area 11 and a second area 12; the heat source 20 is thermally coupled to the temperature uniformity plate 10; a top cover radiation baffle ring 41 is arranged on the end face of the top cover 40 facing the temperature equalizing disc; the area defined by the top cover radiation baffle ring 41 covers the upper part of the first area 11; preferably, the top cover radiation blocking ring 41 is aligned with the boundary between the first region 11 and the second region 12.
Detailed description ten:
the present embodiment provides a semiconductor wafer baking apparatus, as shown in fig. 8, which includes a top cover 40 and the above-described temperature uniformity plate assembly. The end face of the top cover 40 facing the temperature equalizing disc 10 is provided with a top cover radiation baffle ring 41. The area defined by the top cover radiation shield 41 covers the first area 11. Preferably, the top cover radiation blocking ring 41 is aligned with the boundary between the first region 11 and the second region 12.
The principle of providing the top cover radiation blocking ring 41 is similar to that of providing the heat shielding ring 32 in the fifth embodiment, and the heat radiation communication between the first area 11 and the second area 12 is blocked by a physical blocking manner.
In a third aspect of the present invention, a method for compensating heat radiation during baking a wafer is provided, wherein a barrier is disposed between a first region 11 and a second region 12 to block heat radiation communication between the first region 11 and the second region 12, so as to ensure uniformity of temperature of the wafer around the wafer during baking. Solves the problems that the wafer is heated insufficiently uniformly due to the heat shield effect, and the uniform temperature index and the level of wafer baking are affected. Details of the specific processing modes are described in the first embodiment, the fifth embodiment and the eighth embodiment.
The invention also provides other wafer baking heat radiation compensation methods, in particular to any one of the following treatment modes for the temperature equalizing plate 10:
(a) For the first region11 and said second region 12 are subjected to an oxidation treatment, respectively forming a emissivity epsilon 1 And epsilon 2 Wherein ε is 2 ＞ε 1 ；
(b) Performing thermal spraying treatment on the first region 11 and the second region 12 to respectively form a radiation rate epsilon 3 And epsilon 4 Wherein ε is a coating of 4 ＞ε 3 ；
(c) PVD processing is performed on the first region 11 and the second region 12 to form a respective emissivity ε 5 And epsilon 6 Wherein ε is a coating of 6 ＞ε 5 ；
(d) Electroplating the first region 11 and the second region 12 to form a film having emissivity epsilon 7 And epsilon 8 Wherein ε is a coating of 8 ＞ε 7 ；
(e) The first region 11 and the second region 12 are subjected to polishing treatment such that the second region 12 has a finish higher than that of the first region 11.
The processing modes (a) - (d) are similar to the working principle of the fifth embodiment, and film layers with different radiant rates are formed on the first area 11 and the second area 12, so that the radiant rates of the first area 11 and the second area 12 are caused to be different, the radiation heat dissipation capacity of the buffer zone (the second area 12) is reduced, and temperature compensation is realized. The working principle and purpose of the processing mode (e) are the same as those of the specific embodiment six, and are not repeated.
It should be noted that, under the condition of no conflict, the embodiments and features in the embodiments may be combined with each other, and any combination of features in different embodiments is also within the protection scope of the present application, that is, the above-described embodiments may also be combined arbitrarily according to actual needs. All of the above figures are exemplary illustrations of the present application and do not represent actual product sizes, nor are dimensional relationships between components in the figures as limiting the actual product of the present application.
The above is only a part of examples and embodiments of the present application, and the scope of the present application is not limited thereto, and any person skilled in the art who is familiar with the technical scope of the present application can easily think about the changes or substitutions, and all the changes or substitutions are covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A temperature uniformity plate assembly, characterized in that the temperature uniformity plate assembly comprises:
a temperature equalizing plate (10) comprising a first region (11) and a second region (12);
a heat source (20) thermally coupled to the temperature uniformity plate (10);
a thermal radiation compensation means for maintaining uniformity of thermal radiation applied to the wafer by the first region (11) in the wafer covered state;
preferably, the heat conduction coupling surface of the temperature equalizing disc (10) is covered with a graphene layer with uniform thickness.
2. The temperature uniformity plate assembly according to claim 1, wherein:
the first region (11) includes a center of the temperature equalizing plate (10) as an origin, R 1 An area defined by a radius;
the second region (12) is formed into a circular ring structure, and comprises an origin R which is the center of the temperature equalizing disk (10) 1 Is of inner diameter, R 2 A region defined for the outer diameter;
preferably, the first region (11) and the second region (12) are both continuous and uninterrupted.
3. The temperature uniformity plate assembly according to claim 1, wherein said heat source (20) comprises an electric hot plate;
preferably, the electric heating plate is arranged at the bottom of the temperature equalizing disc (10) and is parallel to the temperature equalizing disc (10);
the electric heating plate includes:
an electric heating circuit thermally coupled to the first region (11) and the second region (12), respectively;
or alternatively, the first and second heat exchangers may be,
-an electric heating circuit thermally coupled to said first region (11) and to said second region (12); the density of the electrothermal wires distributed in the second area (12) is greater than that of the electrothermal wires distributed in the first area (11); preferably, the ratio of power density of the electric heating wires distributed in the first area (11) to the electric heating wires distributed in the second area (12) is 1:2 to 5;
or alternatively, the first and second heat exchangers may be,
the electric heating circuits are respectively and thermally coupled to the first region (11) and the second region (12), and the electric heating circuit density of the electric heating plate corresponding to the wafer edge region is set to be larger than that of the electric heating plate corresponding to the wafer center region;
or alternatively, the first and second heat exchangers may be,
the same electrothermal circuit thermally coupled to the first region (11) and the second region (12), the density of electrothermal circuits distributed in the second region (12) is greater than that of electrothermal circuits distributed in the first region (11), and the density of electrothermal circuits of electrothermal plates corresponding to the wafer edge region is set to be greater than that of electrothermal circuits of electrothermal plates corresponding to the wafer center region; preferably, the ratio of power density of the electric heating wires distributed in the first area (11) to the electric heating wires distributed in the second area (12) is 1:2 to 5.
4. A temperature equalizing plate assembly according to claim 1 or 3, characterized in that said thermal radiation compensation assembly comprises a thermal block tank (31); the heat-resistant groove (31) is arranged on one side end surface of the temperature equalizing disc (10) facing the heat source (20);
preferably, the heat-resistant groove (31) is of an annular structure and is arranged concentrically with the temperature equalizing disc (10);
further preferably, the diameter of the heat-resistant groove (31) is 0.65 to 1.0 times the diameter of the first region (11);
further preferably, the depth of the heat-resistant groove (31) is two-fifths to four-fifths of the thickness of the temperature equalization plate (10).
5. The temperature uniformity plate assembly according to claim 1, characterized in that the thermal radiation compensation assembly comprises a heat shielding ring (32) covering the second area (12) and a limit post (33) for fixing the heat shielding ring (32);
preferably, the peripheral edge of the heat shielding ring (32) is aligned with the peripheral edge of the second region (12);
preferably, the heat shielding ring (32) has an outer diameter R 2 The inner diameter is slightly larger than R 1 ；
Further preferably, the heat shielding ring (32) is made of the same material as the wafer to be processed;
preferably, the plurality of limit posts (33) are rotationally symmetrical with respect to the axis of the temperature equalizing plate (10).
6. The isopipe disk assembly of claim 5, wherein the thermal radiation compensation assembly further comprises a ceramic gasket (34) for an overhead wafer;
the ceramic gasket (34) is positioned on or above the upper end surface of the heat shielding ring (32) and partially extends into the ceramic gasket (34) of the first area (11);
or alternatively, the first and second heat exchangers may be,
the ceramic gasket (34) is positioned at or below the lower end surface of the heat shielding ring (32) and partially extends into the first area (11);
preferably, the distance between the lower surface of the heat shielding ring (32) and the upper surface of the temperature equalizing disc (10) is H 1 The method comprises the steps of carrying out a first treatment on the surface of the The distance between the upper surface of the ceramic gasket (34) and the upper surface of the temperature equalizing disc (10) is H 2 The method comprises the steps of carrying out a first treatment on the surface of the Wherein H is 1 ＝H 2 ；
Further preferably, the ceramic spacer (34) has a thickness of 0.1mm.
7. The temperature equalizing disk according to claim 1, wherein:
an oxide layer with different thickness is formed on the surfaces of the first area (11) and the second area (12); preferably, the thickness of the oxide layer of the first region (11) is 18-40 μm, and the thickness of the oxide layer of the surface of the second region (12) is 2 μm;
or alternatively, the first and second heat exchangers may be,
-the second area (12) is provided with a higher finish than the first area (11); preferably, the second region (12) has a finish of 0.1 to 0.8 and the first region (11) has a finish of 0.8 to 1.6.
8. A semiconductor wafer baking apparatus, characterized by comprising:
a temperature uniformity plate assembly according to any one of claims 1-7;
or alternatively, the first and second heat exchangers may be,
the device comprises a temperature equalizing disc (10), a heat source (20) and a top cover (40), wherein the temperature equalizing disc (10) comprises a first area (11) and a second area (12); the heat source (20) is thermally coupled to the temperature uniformity plate (10); a top cover radiation baffle ring (41) is arranged on the end face of the top cover (40) facing the temperature equalizing disc; -the area defined by the top cover radiation baffle ring (41) covers over the first area (11); preferably, the top cover radiation baffle ring (41) is aligned with the boundary line of the first region (11) and the second region (12);
or alternatively, the first and second heat exchangers may be,
a top cover (40) and a temperature uniformity plate assembly according to any one of claims 1-7; a top cover radiation baffle ring (41) is arranged on the end face of the top cover (40) facing the temperature equalizing disc; -the area defined by the top cover radiation baffle ring (41) covers over the first area (11); preferably, the top cover radiation baffle ring (41) is aligned with the boundary line of the first region (11) and the second region (12).
9. The wafer baking thermal radiation compensation method is characterized by comprising the following steps of: blocking heat radiation communication between the first region (11) and the second region (12).
10. A wafer baking thermal radiation compensation method, characterized in that, the temperature equalizing plate (10) in the temperature equalizing plate assembly according to claim 1 is processed by any one of the following processing modes:
(a) Oxidizing the first region (11) and the second region (12) to form a radiation rate epsilon 1 And epsilon 2 Is oxidized by (a)A layer, wherein ε 2 ＞ε 1 ；
(b) Performing thermal spraying treatment on the first region (11) and the second region (12) to respectively form the radiation rate epsilon 3 And epsilon 4 Wherein ε is a coating of 4 ＞ε 3 ；
(c) PVD-treating the first region (11) and the second region (12) to form a respective emissivity ε 5 And epsilon 6 Wherein ε is a coating of 6 ＞ε 5 ；
(d) Electroplating the first region (11) and the second region (12) to form a film having emissivity epsilon 7 And epsilon 8 Wherein ε is a coating of 8 ＞ε 7 ；
(e) -subjecting the first region (11) and the second region (12) to a polishing treatment such that the second region (12) has a finish higher than the finish of the first region (11).
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311556881.0A CN117594489A (en) | 2023-11-21 | 2023-11-21 | Uniform temperature plate assembly, semiconductor wafer baking equipment and wafer baking heat radiation compensation method |
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| CN202311556881.0A CN117594489A (en) | 2023-11-21 | 2023-11-21 | Uniform temperature plate assembly, semiconductor wafer baking equipment and wafer baking heat radiation compensation method |
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| JPH06163444A (en) * | 1992-11-27 | 1994-06-10 | Oki Electric Ind Co Ltd | Wafer thermal treatment method and guard ring structure used therefor |
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