CN117591462A - Peripheral connection method based on PCIE protocol in digital processor - Google Patents
Peripheral connection method based on PCIE protocol in digital processor Download PDFInfo
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- CN117591462A CN117591462A CN202410082641.XA CN202410082641A CN117591462A CN 117591462 A CN117591462 A CN 117591462A CN 202410082641 A CN202410082641 A CN 202410082641A CN 117591462 A CN117591462 A CN 117591462A
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- 230000002093 peripheral effect Effects 0.000 title claims abstract description 98
- 238000000034 method Methods 0.000 title claims abstract description 78
- 238000004088 simulation Methods 0.000 claims abstract description 35
- 230000003993 interaction Effects 0.000 claims abstract description 14
- 238000012544 monitoring process Methods 0.000 claims abstract description 4
- 230000004044 response Effects 0.000 claims description 38
- 238000004891 communication Methods 0.000 claims description 35
- 238000005516 engineering process Methods 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a peripheral connection method based on PCIE protocol in a digital processor, which comprises the following steps: s1: defining a device hardware information protocol and a message type; s2: when the digital host is started, monitoring unix socket paths corresponding to the digital equipment, after the peripheral simulation process is started, connecting PCIE according to the equipment hardware information protocol and the message type defined in S1, and sending self hardware information to the PCIE by the peripheral simulation process through a network, after the digital host receives the hardware information of the digital equipment, distributing an address for the peripheral simulation process according to the corresponding hardware information protocol, loading a drive, and finishing peripheral loading; s3: creating a memory pool; s4: and the peripheral equipment and the digital host machine realize data interaction through the memory pool. According to the method and the device, the PCIE protocol is abstracted, so that the connection process between the digital processor and the peripheral equipment is simplified, and the connection efficiency and stability are improved.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a peripheral connection method based on PCIE protocol in a digital processor.
Background
In digital processors, the connection of peripheral devices has been an important issue.
The traditional peripheral connection mode has the problems of low connection speed, high connection complexity, high realization difficulty, poor compatibility and high coupling performance of different digital hosts, and the like, so that the application of the digital processor is greatly limited, the hardware digitization of the peripheral is realized, the connection interaction with PCIE is realized, and the realization cost is high. Therefore, a new peripheral connection is needed to solve these problems.
Disclosure of Invention
In order to solve the problems in the background art, the invention provides a peripheral connection method based on PCIE protocol in a digital processor, which aims at solving the problems of low peripheral connection speed, high connection complexity, high realization difficulty, poor compatibility for different digital hosts and high coupling property in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a peripheral connection method based on PCIE protocol in digital processor includes the following steps:
s1: defining a device hardware information protocol and a message type;
s2: loading the peripheral equipment; when the digital host is started, monitoring unix socket paths corresponding to the digital equipment, after the peripheral simulation process is started, connecting PCIE according to the equipment hardware information protocol and the message type defined in S1, and sending self hardware information to the PCIE by the peripheral simulation process through a network, after the digital host receives the hardware information of the digital equipment, distributing an address for the peripheral simulation process according to the corresponding hardware information protocol, loading a drive, and finishing peripheral loading;
s3: creating a memory pool; creating a memory pool when the digital host is started, obtaining a file descriptor when a file is opened, associating the file descriptor into the memory pool which is just created, sharing the file descriptor to the peripheral after the peripheral is loaded successfully, and communicating by taking the file descriptor to the peripheral;
s4: the peripheral device interacts with the data of the digital host; and the communication interaction process of sending a communication request by the peripheral simulation process, receiving the communication request by the digital host, sending a response message by the digital host and receiving the response message by the peripheral simulation process is realized through the memory pool.
Preferably, the device hardware information protocol in S1 includes: base address register array, vendor information, device unique identification information, PCI category identification, PCI sub-category identification, PCI version information, PCI programmable interface information, PCI interrupt vector MSI number, PCI interrupt vector MSI-X table base address register number and PCI interrupt vector MSI-X table offset address.
Preferably, the message types in S1 include: device-to-host read requests, device-to-host write requests, device-to-host interrupt requests, device-to-host read completions, device-to-host write completions, host-to-device read requests, host-to-device write requests, host-to-device interrupt requests, host-to-device read completions, and host-to-device write completions.
Preferably, when the digital host is started in S3, a memory pool is created by utilizing a Linux mmap technology, and file descriptors are shared to the peripheral by utilizing a Linux sendmsg mode.
Preferably, in S4, the method for implementing data interaction between the peripheral device and the digital host device includes:
s4.1, the peripheral simulation process sends a communication request: when the peripheral simulation process needs to communicate with the digital host, a communication request is sent to the digital host, and is written into a memory pool, wherein the communication request comprises a data sending request, a data receiving request, a state query request and an interrupt request;
s4.2, the digital host receives a communication request: after receiving a communication request of the peripheral simulation process from the memory pool, the digital host analyzes and processes the communication request, selects a corresponding processing method according to the type and the content of the communication request, and returns a processing result to the peripheral simulation process;
s4.3, the digital host sends a response message: after the digital host computer processes the communication request of the peripheral simulation process, a response message is sent to the peripheral simulation process, wherein the response message comprises a data sending response, a data receiving response and a state query response;
s4.4, the peripheral simulation process receives a response message: after receiving the response message of the digital host, the peripheral simulation process analyzes and processes the response message, and the peripheral simulation process processes the response message according to the type and the content of the response message to complete the communication interaction process.
Compared with the prior art, the invention has the beneficial effects that:
according to the method and the device, the PCIE protocol is abstracted, so that the connection process between the digital processor and the peripheral equipment is simplified, and the connection efficiency and stability are improved. The digital processor can be quickly accessed only by realizing corresponding content according to the protocol, so that the communication with the digital host is realized, the complexity and complexity of the traditional connection mode are avoided, the time cost of connection is saved, and the stability and reliability of connection are improved.
Drawings
Fig. 1 is a schematic diagram of a shared memory pool creation flow in the present application.
Fig. 2 is a schematic diagram of a peripheral device and PCIE data interaction flow in the present application.
Detailed Description
The present invention will be further described in detail below with reference to the accompanying drawings and specific examples in order to facilitate understanding of the technical content of the present invention by those skilled in the art. It should be understood that the specific examples described herein are intended to illustrate the invention and are not intended to limit the invention.
Example 1:
a peripheral connection method based on PCIE protocol in digital processor includes the following steps:
s1: the equipment hardware information protocol definition comprises a base address register array, manufacturer information, equipment unique identification information, PCI type identification, PCI sub-type identification, PCI version information, PCI programmable interface information, PCI interrupt vector MSI number, PCI interrupt vector MSI-X table base address register number and PCI interrupt vector MSI-X table offset address.
A message type definition comprising the following: device-to-host read requests, device-to-host write requests, device-to-host interrupt requests, device-to-host read completions, device-to-host write completions, host-to-device read requests, host-to-device write requests, host-to-device interrupt requests, host-to-device read completions, host-to-device write completions.
S2: and (5) a peripheral loading process.
When the digital host is started, monitoring unix socket paths corresponding to the digital equipment, and after the peripheral simulation process is started, connecting PCIEs by using the unix socket paths according to set PCIE information, so as to establish network connection. After the peripheral device process is connected, the peripheral device process sends the hardware information to the PCIE through the network, and after the digital host receives the hardware information of the equipment, the digital host distributes addresses to the peripheral device according to the corresponding hardware information, loads the drive, and completes the loading of the peripheral device.
S3: and a data interaction mode.
As shown in fig. 1, the peripheral device and PCIE data interaction is performed based on a shared memory manner. The method comprises the specific process that when the digital host is started, a memory pool is created by utilizing a Linux mmap technology, a file descriptor is created, and after the internal initialization of the memory pool, the digital host associates the file descriptor to the memory pool which is just created. After the peripheral is successfully connected with the digital host, the digital host shares the file descriptor to the peripheral in a Linux sendsg mode, the peripheral can communicate with the digital host through a memory pool after the file descriptor is taken by the peripheral, and the mode can realize cross-process data interaction in the memory, so that the data communication delay between the peripheral and the digital host is greatly reduced.
S4: and a data interaction process between the peripheral equipment and the host.
As shown in fig. 2, the peripheral sends a communication request through the peripheral emulation process: when the peripheral needs to communicate with the digital host, the peripheral sends a communication request to the PCIE through the peripheral simulation process, the communication request is written into the memory pool, and the memory pool updates the memory content. The communication request may include a data transmission request, a data reception request, a status query request, an interrupt request, and the like.
The digital host receives the communication request: and after the digital host reads the data of the communication request of the peripheral simulation process from the shared memory pool through PCIE, analyzing and processing the data.
The digital host sends a response message: the digital host computer selects a corresponding processing method to generate a response according to the type and the content of the data of the communication request, and writes the generated response into the memory pool through PCIE, and at the moment, the memory pool updates the memory content, wherein the content of the response can comprise a data sending response, a data receiving response, a state query response and the like.
The peripheral emulation process receives a response message: after the peripheral reads the response message of the digital host from the memory pool through the peripheral simulation process, the peripheral receives the returned response data, analyzes the type and the content of the response message and then processes the response message so as to complete the communication interaction process.
In this embodiment, the present application reduces the limitation of peripheral access of the digital processor, makes the peripheral access PCIE have the same digital protocol standard, solves the problem of the speed and the simplicity of connection of peripheral devices in the digital processor, and provides a peripheral connection method based on the PCIE protocol, so that the connection of the digital peripheral devices is faster and easier, and the connection process between the digital processor and the peripheral devices is simplified by abstracting the PCIE protocol, thereby improving the connection efficiency and stability. The digital processor can be quickly accessed only by realizing corresponding content according to the protocol, so that the communication with the digital host is realized, the complexity and complexity of the traditional connection mode are avoided, the time cost of connection is saved, and the stability and reliability of connection are improved.
Claims (5)
1. A peripheral connection method based on PCIE protocol in digital processor is characterized by comprising the following steps:
s1: defining a device hardware information protocol and a message type;
s2: loading the peripheral equipment; when the digital host is started, monitoring unix socket paths corresponding to the digital equipment, after the peripheral simulation process is started, connecting PCIE according to the equipment hardware information protocol and the message type defined in S1, and sending self hardware information to the PCIE by the peripheral simulation process through a network, after the digital host receives the hardware information of the digital equipment, distributing an address for the peripheral simulation process according to the corresponding hardware information protocol, loading a drive, and finishing peripheral loading;
s3: creating a memory pool; creating a memory pool when the digital host is started, obtaining a file descriptor when a file is opened, associating the file descriptor into the memory pool which is just created, sharing the file descriptor to the peripheral after the peripheral is loaded successfully, and communicating by taking the file descriptor to the peripheral;
s4: the peripheral device interacts with the data of the digital host; and the communication interaction process of sending a communication request by the peripheral simulation process, receiving the communication request by the digital host, sending a response message by the digital host and receiving the response message by the peripheral simulation process is realized through the memory pool.
2. The peripheral connection method based on PCIE protocol in a digital processor as set forth in claim 1 wherein the device hardware information protocol in S1 comprises: base address register array, vendor information, device unique identification information, PCI category identification, PCI sub-category identification, PCI version information, PCI programmable interface information, PCI interrupt vector MSI number, PCI interrupt vector MSI-X table base address register number and PCI interrupt vector MSI-X table offset address.
3. The peripheral connection method based on PCIE protocol in a digital processor according to claim 1, wherein the message types in S1 include: device-to-host read requests, device-to-host write requests, device-to-host interrupt requests, device-to-host read completions, device-to-host write completions, host-to-device read requests, host-to-device write requests, host-to-device interrupt requests, host-to-device read completions, and host-to-device write completions.
4. The peripheral connection method based on PCIE protocol in digital processor as claimed in claim 1 wherein S3 the digital host creates a memory pool by Linux mmap technology when started, and file descriptors are shared to the peripheral by Linux sendsg.
5. The peripheral connection method based on PCIE protocol in a digital processor as claimed in claim 4, wherein in S4, the method for implementing data interaction between peripheral and digital host is:
s4.1, the peripheral simulation process sends a communication request: when the peripheral simulation process needs to communicate with the digital host, a communication request is sent to the digital host, and is written into a memory pool, wherein the communication request comprises a data sending request, a data receiving request, a state query request and an interrupt request;
s4.2, the digital host receives a communication request: after receiving a communication request of the peripheral simulation process from the memory pool, the digital host analyzes and processes the communication request, selects a corresponding processing method according to the type and the content of the communication request, and returns a processing result to the peripheral simulation process;
s4.3, the digital host sends a response message: after the digital host computer processes the communication request of the peripheral simulation process, a response message is sent to the peripheral simulation process, wherein the response message comprises a data sending response, a data receiving response and a state query response;
s4.4, the peripheral simulation process receives a response message: after receiving the response message of the digital host, the peripheral simulation process analyzes and processes the response message, and the peripheral simulation process processes the response message according to the type and the content of the response message to complete the communication interaction process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410082641.XA CN117591462A (en) | 2024-01-19 | 2024-01-19 | Peripheral connection method based on PCIE protocol in digital processor |
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| CN116069453A (en) * | 2023-04-04 | 2023-05-05 | 苏州浪潮智能科技有限公司 | Simulation system |
| CN116401984A (en) * | 2022-12-09 | 2023-07-07 | 平头哥(上海)半导体技术有限公司 | System-on-chip simulation method and system based on virtual machine |
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- 2024-01-19 CN CN202410082641.XA patent/CN117591462A/en active Pending
Patent Citations (7)
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| CN103312720A (en) * | 2013-07-01 | 2013-09-18 | 华为技术有限公司 | Data transmission method, equipment and system |
| CN105592492A (en) * | 2015-12-18 | 2016-05-18 | 重庆邮电大学 | Platform and method for testing high-layer protocol stack consistency |
| CN113064846A (en) * | 2021-04-14 | 2021-07-02 | 中南大学 | Zero-copy data transmission method based on Rsockets protocol |
| CN113986513A (en) * | 2021-11-10 | 2022-01-28 | 眸芯科技（上海）有限公司 | Master-slave core communication method and system of master-slave architecture chip |
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