CN114584526A - ARP protocol processing method, system, storage medium and electronic equipment - Google Patents
ARP protocol processing method, system, storage medium and electronic equipment Download PDFInfo
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Abstract
The invention discloses an ARP protocol processing method, a system, a storage medium and electronic equipment, wherein the FPGA and a CPU are in work division cooperation, and the FPGA undertakes the processes of MAC address retrieval, aging control, communication interface processing and the like; the CPU undertakes ARP request, ARP response and FPGA configuration, the invention adopts the idea of software and hardware cooperation to realize ARP protocol processing, on one hand, FPGA hardware undertakes the operation of massive MAC address inquiry in the process of IP data processing, reduces the occupation of system CPU time, releases partial CPU resources in the process of ARP processing, improves the response speed, and is beneficial to reducing IP data sending delay; on the other hand, the MAC address mapping table is not in the system memory and is not easy to be tampered by other software, and the safety of the network system is improved.
Description
Technical Field
The invention relates to an ARP protocol processing method, an ARP protocol processing system, a storage medium and electronic equipment, and belongs to the technical field of computer network communication.
Background
An FPGA (field Programmable Gate array) field Programmable Gate array is a product developed further on the basis of Programmable devices such as PAL (Programmable array logic), GAL (general array logic) and the like, and appears as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), thereby not only solving the defects of the custom circuit, but also overcoming the defect of limited Gate circuits of the original Programmable devices. A central processing unit (cpu) is a final execution unit for information processing and program operation, and serves as an operation and control core of a computer system.
The ARP (address Resolution protocol) protocol is a basic network protocol, the operation of which is generally transparent to an application program or a system, and is usually implemented in a network protocol stack of an operating system, and a CPU executes a specific software module to implement ARP protocol processing, and puts a Resolution result into a device memory for caching.
At present, network equipment needs to occupy system resources when processing an ARP message, and meanwhile, because of requirements on system memory access and MAC table lookup efficiency, security and lookup efficiency of caching an MAC address table in a memory during the operation of a network system are very critical.
Disclosure of Invention
Therefore, the invention provides an ARP protocol processing method, a system, a storage medium and electronic equipment, which realize the ARP protocol processing by the division and cooperation of FPGA and CPU and by adopting a software and hardware cooperative mode and solve the safety and efficiency problems of the traditional pure software mode for ARP processing.
In order to achieve the above purpose, the invention provides the following technical scheme: in a first aspect, an ARP protocol processing method is provided, which includes an FPGA processing stage, where the FPGA processing stage includes the following steps:
s001: resetting and initializing FPGA module operating parameters;
s002: receiving a network data packet through an initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing; if the network data packet is a data packet from an external network interface ARP request and an ARP response, then the process goes to S201; if the network data packet is the data packet of the ARP request and the ARP response from the CPU module, the S301 is switched to;
s101: judging that the network data packet is a normal data communication IP packet, and turning to S102;
s102: searching a destination MAC address entry of the network data packet in the MAC address mapping table, and turning to S103;
s103: and judging the search result of S102: if the destination MAC address entry exists, go to S104; otherwise go to S105;
s104: delivering the target MAC address entry and the network data packet to a subsequent forwarding module;
s105: forwarding the IP packet header information to the CPU module through a configuration management interface, and turning to S106;
s106: sending an alarm message through a configuration management interface to inform a CPU module to carry out ARP analysis processing;
s201: receiving a data packet from an external network interface ARP request and an ARP response, and turning to S202;
s202: the data packet contents from the ARP request and the ARP response of the external network interface are forwarded to the CPU module through the configuration management interface to be subjected to protocol processing;
s301: receiving the ARP request and ARP response data packet from the CPU module, and going to S302;
s302: and forwarding the data packet contents of the ARP request and the ARP response from the CPU module to a specified host through a network communication port.
As a preferred scheme of the ARP protocol processing method, the ARP protocol processing method further comprises a CPU processing stage, wherein the CPU processing stage comprises the following steps:
s401: initializing the operation of an FPGA module and configuring parameters;
s402: receiving the network data packet forwarded by the FPGA module, and identifying and classifying the protocol: if the network data packet forwarded by the FPGA module is an ARP alarm packet, the step goes to S411 for processing; if the network data packet forwarded by the FPGA module is an ARP response packet, turning to S421 for processing; if the network data packet forwarded by the FPGA module is the ARP request packet, the step goes to S431 for processing;
s411: analyzing the received network data packet as an ARP alarm packet, and turning to S412;
s412: searching a destination MAC address entry of the network data packet in the MAC address mapping table, and turning to S413;
s413: judging the search result: if the destination MAC address entry exists, go to S423; otherwise go to S414;
s414: generating a corresponding ARP request packet, and turning to S415;
s415: the ARP request packet generated in the S414 is sent to the FPGA module, and the FPGA module forwards the ARP request packet to perform port broadcasting and send the ARP request;
s421: analyzing the received network data packet as an ARP response packet, and turning to S422;
s422: analyzing the ARP response packet data to extract address information, and turning to S423;
s423: refreshing the MAC address mapping table and writing the newly added entries into the table entries;
s431: analyzes the received network data packet as an ARP request packet, and goes to S432
S432: judging whether the request is a request for resolving the IP address of the local machine: if the local IP is analyzed, go to S434; otherwise go to S433;
s433: directly ending the treatment;
s434: generating a corresponding ARP response packet, filling the MAC of the local analyzer into a data packet, and turning to S435;
s435: and sending the ARP response packet of the S434 to the FPGA module through the configuration management interface, and sending the ARP response packet from the designated port by the FPGA module.
The second aspect provides an ARP protocol processing system, and the ARP protocol processing method based on the first aspect comprises an FPGA module, a dual-port RAM module and a CPU module; the FPGA module and the double-port RAM module are communicated through address and data buses, and the CPU module and the double-port RAM module are communicated through the address and data buses;
the FPGA module accesses an MAC address mapping table and executes MAC address query operation through the double-port RAM module; if the FPGA module does not inquire the MAC address, the FPGA module sends an MAC address analysis request to the CPU module; the FPGA module forwards the received network ARP message to the CPU module;
the CPU module is used for receiving the MAC address resolution request sent by the FPGA module, and is also used for sending an ARP request message and processing an ARP response message;
and the CPU module writes the analyzed MAC address into the double-port RAM module for the FPGA module to inquire.
As a preferred scheme of the ARP protocol processing system, the FPGA module communicates with the CPU module through a configuration management interface, and forwards the MAC address resolution request and the network ARP message to the CPU module through the configuration management interface.
As a preferred scheme of the ARP protocol processing system, the FPGA module ages the MAC address entries in the dual-port RAM module, and deletes the unused MAC address entries in a preset time at regular time.
As a preferred scheme of the ARP protocol processing system, the system further includes a PHY module, where the PHY module is used for physical link layer network communication, and the FPGA module implements network communication connection and performs IP network data transceiving through the PHY module.
The DDR module is electrically connected with the CPU module and is used as a memory part for the operation of the CPU module.
The preferred scheme of the ARP protocol processing system also comprises a FLASH module, wherein the FLASH module is electrically connected with the CPU module, and the FLASH module is used as a permanent storage part for the running of the CPU module.
In a third aspect, there is provided a non-transitory computer-readable storage medium having stored therein program code of an ARP protocol processing method, the program code comprising instructions for performing the ARP protocol processing method of the first aspect or any possible implementation thereof.
In a fourth aspect, an electronic device is provided, comprising: a memory and a processor; the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions to perform the ARP protocol processing method of the first aspect or any possible implementation thereof.
The invention has the following advantages: the FPGA hardware bears the operation of inquiring a large number of MAC addresses in the process of processing IP data, so that the occupation of the CPU time of the system is reduced, partial CPU resources are released in the process of processing the ARP, the response speed is improved, and the delay of sending the IP data is favorably reduced; on the other hand, the MAC address mapping table is not in the system memory and is not easy to be tampered by other software, and the safety of the network system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so that those skilled in the art can understand and read the present invention, and do not limit the conditions for implementing the present invention, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the functions and purposes of the present invention, should still fall within the scope of the present invention.
Fig. 1 is a schematic diagram of logic of an FPGA processing stage in an ARP protocol processing method according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a CPU processing stage logic in the ARP protocol processing method provided in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of an ARP protocol processing system provided in embodiment 2 of the present invention.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1, an embodiment 1 of the present invention provides an ARP protocol processing method, including an FPGA processing stage, where the FPGA processing stage includes the following steps:
s001: resetting and initializing FPGA module operating parameters; specifically, after the FPGA module is powered on, resetting is completed, the management unit is started to receive the configuration management instruction, the network interface of the FPGA module, the number of cache entries and other operation parameters are initialized, and then the process goes to S002;
s002: receiving a network data packet through an initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing; if the network data packet is a data packet from an external network interface ARP request and an ARP response, then the process goes to S201; if the network data packet is the data packet of the ARP request and the ARP response from the CPU module, the step is switched to S301 for processing;
specifically, the number of the MAC interfaces is consistent with the number of the network ports, the MAC interfaces perform network communication through the PHY physical link layer, and different network data packets are transferred to different processing flows by identifying and classifying the types of the network data packets.
S101: judging that the network data packet is a normal data communication IP packet, and turning to S102;
s102: searching a destination MAC address entry of the network data packet in the MAC address mapping table, and turning to S103;
s103: and judging the search result of S102: if the destination MAC address entry exists, go to S104; otherwise go to S105;
s104: delivering the target MAC address entry and the network data packet to a subsequent forwarding module;
s105: forwarding the IP packet header information to the CPU module through a configuration management interface, and turning to S106;
s106: sending an alarm message through a configuration management interface to inform a CPU module to carry out ARP analysis processing;
s201: receiving a data packet from an external network interface ARP request and an ARP response, and turning to S202;
s202: the data packet contents from the ARP request and ARP response of the external network interface are forwarded to the CPU module through the configuration management interface for protocol processing;
s301: receiving the ARP request and ARP response data packet from the CPU module, and going to S302;
s302: and forwarding the ARP request and the ARP response data packet contents from the CPU module to the appointed host through the network communication port.
Specifically, in the FPGA processing stage, the FPGA module is reset after being powered on, a management unit is started to receive a configuration management instruction, and operating parameters such as network interfaces, the number of cache entries and the like of the FPGA module are initialized; receiving a network data packet through an initialized MAC interface, identifying the type of the network data packet, if the network data packet is a normal data communication IP packet, searching a target MAC address entry of the network data packet in an MAC address mapping table, and judging a searching result: if the target MAC address entry exists, the target MAC address entry and the network data packet are delivered to a subsequent forwarding module, otherwise, the IP packet header information is forwarded to the CPU module through the configuration management interface, and an alarm message is sent through the configuration management interface to inform the CPU module to carry out ARP analysis processing; if the network data packet is a data packet from an external network interface ARP request and an ARP response, forwarding the data packet contents from the external network interface ARP request and the ARP response to a CPU module through a configuration management interface for protocol processing; if the network data packet is the data packet of the ARP request and the ARP response from the CPU module, the content of the data packet of the ARP request and the ARP response from the CPU module is forwarded to the appointed host through the network communication port for processing.
Referring to fig. 2, in this embodiment, the method further includes a CPU processing stage, where the CPU processing stage includes the following steps:
s401: initializing the operation of an FPGA module and configuring parameters;
specifically, after the CPU module is powered on, the CPU module completes reset, the start management unit initializes and configures parameters of the FPGA module through the configuration management interface, initializes the network interface of the FPGA module, the number of cache entries, and other operation parameters, and then goes to S402;
s402: receiving the network data packet forwarded by the FPGA module, and identifying and classifying the protocol: if the network data packet forwarded by the FPGA module is an ARP alarm packet, the step goes to S411 for processing; if the network data packet forwarded by the FPGA module is an ARP response packet, turning to S421 for processing; if the network data packet forwarded by the FPGA module is the ARP request packet, the step goes to S431 for processing;
specifically, the CPU module receives the network data packet forwarded by the FPGA module, performs protocol identification and classification on the forwarded network data packet, and if the network data packet is an ARP alarm packet, goes to S411 for processing; if the packet is the ARP response packet, go to S421 to process; if it is the ARP request packet, the process goes to S431.
S411: analyzing the received network data packet as an ARP alarm packet, and turning to S412;
s412: searching a destination MAC address entry of the network data packet in the MAC address mapping table, and turning to S413;
s413: judging the search result: if the destination MAC address entry exists, go to S423; otherwise go to S414;
s414: generating a corresponding ARP request packet, and turning to S415;
s415: the ARP request packet generated in the S414 is sent to the FPGA module, and the FPGA module forwards the ARP request packet to perform port broadcasting and send the ARP request;
s421: analyzing the received network data packet as an ARP response packet, and turning to S422;
s422: analyzing the ARP response packet data to extract address information, and turning to S423;
s423: refreshing the MAC address mapping table and writing the newly added entries into the table entries;
s431: analyzes the received network data packet as an ARP request packet, and goes to S432
S432: judging whether the request is a request for resolving the IP address of the local machine: if the local IP is analyzed, go to S434; otherwise go to S433;
s433: directly ending the treatment;
s434: generating a corresponding ARP response packet, filling the MAC of the local analyzer into a data packet, and turning to S435;
s435: and sending the ARP response packet of the S434 to the FPGA module through the configuration management interface, and sending the ARP response packet from the designated port by the FPGA module.
Specifically, in the CPU processing stage, the CPU module completes reset after being powered on, and the start management unit initializes and configures parameters of the FPGA module through the configuration management interface, and initializes the network interface of the FPGA module, the number of cache entries, and other operation parameters; receiving the network data packet forwarded by the FPGA module, and identifying and classifying the protocol: if the network data packet forwarded by the FPGA module is an ARP alarm packet, searching a destination MAC address entry of the network data packet in an MAC address mapping table, and judging a searching result: if the target MAC address entry exists, refreshing the MAC address mapping table, and writing the newly added entry into the table entry; otherwise, generating a corresponding ARP request packet, sending the generated ARP request packet to the FPGA module, and forwarding the ARP request packet through the FPGA module to perform port broadcasting so as to send the ARP request. If the network data packet forwarded by the FPGA module is an ARP response packet, analyzing the ARP response packet data to extract address information, refreshing an MAC address mapping table, and writing the newly added entry into the table entry. If the network data packet forwarded by the FPGA module is an ARP request packet, judging whether the network data packet is a request for analyzing the IP address of the local machine: if the IP of the local computer is analyzed, generating a corresponding ARP response packet, filling the MAC of the local computer into a data packet, sending the ARP response packet to the FPGA module through the configuration management interface, and sending the ARP response packet from the designated port by the FPGA module; otherwise, the process is directly ended.
In summary, in the FPGA processing stage, the operation parameters of the FPGA module are reset and initialized; receiving a network data packet through an initialized MAC interface, identifying the type of the network data packet, if the network data packet is a normal data communication IP packet, searching a target MAC address entry of the network data packet in an MAC address mapping table, and judging a searching result: if the target MAC address entry exists, the target MAC address entry and the network data packet are delivered to a subsequent forwarding module, otherwise, the IP packet header information is forwarded to the CPU module through the configuration management interface, and an alarm message is sent through the configuration management interface to inform the CPU module to carry out ARP analysis processing; if the network data packet is a data packet from an external network interface ARP request and an ARP response, forwarding the data packet contents from the external network interface ARP request and the ARP response to a CPU module through a configuration management interface for protocol processing; if the network data packet is the data packet of the ARP request and the ARP response from the CPU module, the content of the data packet of the ARP request and the ARP response from the CPU module is forwarded to the appointed host through the network communication port for processing. The CPU processing stage is used for initializing the operation of the FPGA module and configuring parameters; receiving the network data packet forwarded by the FPGA module, and identifying and classifying the protocol: if the network data packet forwarded by the FPGA module is an ARP alarm packet, searching a destination MAC address entry of the network data packet in an MAC address mapping table, and judging a searching result: if the target MAC address entry exists, refreshing the MAC address mapping table, and writing the newly added entry into the table entry; otherwise, generating a corresponding ARP request packet, sending the generated ARP request packet to the FPGA module, and forwarding the ARP request packet through the FPGA module to perform port broadcasting so as to send the ARP request. If the network data packet forwarded by the FPGA module is an ARP response packet, analyzing the ARP response packet data to extract address information, refreshing an MAC address mapping table, and writing the newly added entry into the table entry. If the network data packet forwarded by the FPGA module is an ARP request packet, judging whether the network data packet is a request for analyzing the IP address of the local machine: if the IP of the local computer is analyzed, generating a corresponding ARP response packet, filling the MAC of the local computer into a data packet, sending the ARP response packet to the FPGA module through the configuration management interface, and sending the ARP response packet from the designated port by the FPGA module; otherwise, the process is directly ended. According to the invention, the FPGA and the CPU are in work division and cooperation, and the ARP protocol processing is realized by adopting the idea of software and hardware cooperation, on one hand, the FPGA hardware bears the operation of inquiring a large number of MAC addresses in the IP data processing process, so that the occupation of the CPU time of the system is reduced, part of CPU resources are released in the ARP processing process, the response speed is improved, and the IP data sending delay is favorably reduced; on the other hand, the MAC address mapping table is not in the system memory and is not easy to be tampered by other software, and the safety of the network system is improved.
Example 2
Referring to fig. 3, embodiment 2 of the present invention further provides an ARP protocol processing system, which includes an FPGA module a001, a dual-port RAM module a002, and a CPU module a003, based on the ARP protocol processing method of embodiment 1 or any possible implementation manner thereof; the FPGA module A001 and the double-port RAM module A002 communicate through address and data buses, and the CPU module A003 and the double-port RAM module A002 communicate through address and data buses;
the FPGA module A001 accesses the MAC address mapping table and executes MAC address query operation through the double-port RAM module A002; if the FPGA module A001 does not inquire the MAC address, the FPGA module A001 sends an MAC address resolution request to the CPU module A003; the FPGA module A001 forwards the received network ARP message to the CPU module A003;
the CPU module a003 is configured to receive an MAC address resolution request sent by the FPGA module a001, and the CPU module a003 is further configured to send an ARP request message and process an ARP response message;
the CPU module a003 writes the resolved MAC address into the dual-port RAM module a002 for the FPGA module a001 to query.
In this embodiment, the FPGA module a001 communicates with the CPU module a003 through a configuration management interface, and the FPGA module a001 forwards the MAC address resolution request and the network ARP message to the CPU module a003 through the configuration management interface.
In this embodiment, the FPGA module a001 ages the MAC address entry in the dual-port RAM module a002, and deletes the unused MAC address entry in a preset time at regular time.
In this embodiment, the system further includes a PHY module a004, where the PHY module a004 is configured to implement network communication in a physical link layer network, and the FPGA module a001 implements network communication connection through the PHY module a004 and performs IP network data transceiving.
In this embodiment, the device further includes a DDR module a005, the DDR module a005 and the CPU module a003 are electrically connected, the DDR module a005 is used as a memory portion for the CPU module a003 to run, and the DDR module a005 implements a memory for system software and an application program when running.
In this embodiment, the FLASH memory further includes a FLASH module a006, the FLASH module a006 is electrically connected to the CPU module a003, and the FLASH module a006 is used as a persistent storage portion for the operation of the CPU module a 003. The FLASH module a006 is used as a memory permanently maintained by system software, a file system and an application program, and data is guided and read from the FLASH module a006 after the system is powered on.
It should be noted that, for the contents of information interaction, execution process, and the like between the modules/units of the system, since the contents are based on the same concept as the method embodiment in embodiment 1 of the present application, the technical effect brought by the contents is the same as the method embodiment of the present application, and specific contents may refer to the description in the foregoing method embodiment of the present application, and are not described again here.
Example 3
Embodiment 3 of the present invention provides a non-transitory computer-readable storage medium having stored therein a program code of an ARP protocol processing method, the program code including instructions for executing the ARP protocol processing method of embodiment 1 or any possible implementation thereof.
The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
Example 4
An embodiment 4 of the present invention provides an electronic device, including: a memory and a processor;
the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, the processor invoking the program instructions capable of performing the ARP protocol processing method of embodiment 1 or any possible implementation thereof.
Specifically, the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like; when implemented in software, the processor may be a general-purpose processor implemented by reading software code stored in a memory, which may be integrated in the processor, located external to the processor, or stand-alone.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (10)
1. An ARP protocol processing method is characterized by comprising an FPGA processing stage, wherein the FPGA processing stage comprises the following steps:
s001: resetting and initializing FPGA module operating parameters;
s002: receiving a network data packet through an initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing; if the network data packet is a data packet from an external network interface ARP request and an ARP response, then the process goes to S201; if the network data packet is the data packet of the ARP request and the ARP response from the CPU module, the S301 is switched to;
s101: judging that the network data packet is a normal data communication IP packet, and turning to S102;
s102: searching a destination MAC address entry of the network data packet in the MAC address mapping table, and turning to S103;
s103: and judging the search result of S102: if the destination MAC address entry exists, go to S104; otherwise go to S105;
s104: delivering the target MAC address entry and the network data packet to a subsequent forwarding module;
s105: forwarding the IP packet header information to the CPU module through a configuration management interface, and turning to S106;
s106: sending an alarm message through a configuration management interface to inform a CPU module to carry out ARP analysis processing;
s201: receiving a data packet from an external network interface ARP request and an ARP response, and turning to S202;
s202: the data packet contents from the ARP request and the ARP response of the external network interface are forwarded to the CPU module through the configuration management interface to be subjected to protocol processing;
s301: receiving the ARP request and ARP response data packet from the CPU module, and going to S302;
s302: and forwarding the ARP request and the ARP response data packet contents from the CPU module to the appointed host through the network communication port.
2. The ARP protocol processing method according to claim 1, further comprising a CPU processing stage, wherein the CPU processing stage comprises the steps of:
s401: initializing the operation of an FPGA module and configuring parameters;
s402: receiving the network data packet forwarded by the FPGA module, and identifying and classifying the protocol: if the network data packet forwarded by the FPGA module is an ARP alarm packet, the step goes to S411 for processing; if the network data packet forwarded by the FPGA module is an ARP response packet, turning to S421 for processing; if the network data packet forwarded by the FPGA module is the ARP request packet, the step goes to S431 for processing;
s411: analyzing the received network data packet as an ARP alarm packet, and turning to S412;
s412: searching a destination MAC address entry of the network data packet in the MAC address mapping table, and turning to S413;
s413: judging the search result: if the destination MAC address entry exists, go to S423; otherwise go to S414;
s414: generating a corresponding ARP request packet, and turning to S415;
s415: the ARP request packet generated in the S414 is sent to the FPGA module, and the FPGA module forwards the ARP request packet to perform port broadcasting and send the ARP request;
s421: analyzing the received network data packet as an ARP response packet, and turning to S422;
s422: analyzing the ARP response packet data to extract address information, and turning to S423;
s423: refreshing the MAC address mapping table and writing the newly added entries into the table entries;
s431: analyzes the received network data packet as an ARP request packet, and goes to S432
S432: judging whether the request is a request for resolving the IP address of the local machine: if the local IP is analyzed, go to S434; otherwise go to S433;
s433: directly ending the treatment;
s434: generating a corresponding ARP response packet, filling the MAC of the local analyzer into a data packet, and turning to S435;
s435: and sending the ARP response packet of the S434 to the FPGA module through the configuration management interface, and sending the ARP response packet from the specified port by the FPGA module.
3. An ARP protocol processing system based on the ARP protocol processing method of any one of claims 1 to 2, characterized by comprising an FPGA module, a dual-port RAM module and a CPU module; the FPGA module and the dual-port RAM module are communicated through address and data buses, and the CPU module and the dual-port RAM module are communicated through the address and data buses;
the FPGA module accesses an MAC address mapping table and executes MAC address query operation through the double-port RAM module; if the FPGA module does not inquire the MAC address, the FPGA module sends an MAC address analysis request to the CPU module; the FPGA module forwards the received network ARP message to the CPU module;
the CPU module is used for receiving the MAC address resolution request sent by the FPGA module, and is also used for sending an ARP request message and processing an ARP response message;
and the CPU module writes the analyzed MAC address into the double-port RAM module for the FPGA module to inquire.
4. The ARP protocol processing system of claim 3, wherein said FPGA module communicates with said CPU module via a configuration management interface, and said FPGA module forwards MAC address resolution requests, network ARP messages to said CPU module via said configuration management interface.
5. The ARP protocol processing system of claim 3, wherein the FPGA module ages MAC address entries in the dual-port RAM module and periodically deletes unused MAC address entries within a predetermined time.
6. The ARP protocol processing system of claim 5, further comprising a PHY module, wherein the PHY module is configured to perform physical link layer network communication, and the FPGA module implements network communication connection and performs IP network data transceiving through the PHY module.
7. The ARP protocol processing system of claim 6, further comprising a DDR module, said DDR module being electrically connected to said CPU module, said DDR module being configured to operate as a memory portion of said CPU module.
8. The ARP processing system of claim 7, characterized in that it further comprises a FLASH module, said FLASH module is electrically connected to said CPU module, said FLASH module is used as a persistent storage for said CPU module.
9. A non-transitory computer-readable storage medium having stored therein a program code of the ARP protocol processing method, characterized in that the program code comprises instructions for executing the ARP protocol processing method of claim 1 or 2.
10. An electronic device, comprising: a memory and a processor; the processor and the memory are communicated with each other through a bus; the memory stores program instructions executable by the processor, wherein the processor invokes the program instructions to perform the ARP protocol processing method of claim 1 or 2.
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