CN117591359A - Testing device and testing method for solid state disk - Google Patents
Testing device and testing method for solid state disk Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 221
- 239000007787 solid Substances 0.000 title claims abstract description 215
- 238000011056 performance test Methods 0.000 claims abstract description 38
- 238000010998 test method Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 13
- 238000004590 computer program Methods 0.000 description 11
- 238000013403 standard screening design Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 6
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a testing device and a testing method for a solid state disk. The testing device of the solid state disk comprises a target chip, a power module and a testing host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module and connected with the test host; the target chip is used for establishing connection with a second preset number of solid state disks to be tested through a second preset number of solid state disk interfaces; the test host is used for performing performance test on the solid state disk to be tested accessed to the solid state disk interface and generating a solid state disk performance test result; and the power supply module is used for providing power supply for the target chip. Therefore, the target chip is provided with the first preset number of solid state disk interfaces, and can simultaneously perform performance test on a plurality of solid state disks to be tested, so that the test efficiency can be improved, manual connection for a plurality of times is avoided, and the operability is improved. And the manufacturing cost of the target chip is low, so that the testing cost can be saved.
Description
Technical Field
The present disclosure relates to testing technology, and in particular, to a testing device and a testing method for a solid state disk.
Background
Solid State Disk (Solid State Disk or Solid State Drive, SSD for short), also called Solid State drive, is a hard Disk made of Solid State electronic memory chip array. There are various classifications, but solid state disks have no rotating media compared to mechanical disks, and therefore have excellent shock resistance. Because the solid state disk has the advantages of high read-write speed, difficult damage, low power consumption, small volume and the like, the solid state disk is widely applied to various fields at present.
To ensure proper operation and reliability of SSDs, their performance is often tested. In the related art, taking the example of testing Nvme m.2ssd, performance test is usually performed on the Nvme m.2ssd by using the m.2 interface of the computer motherboard, but the number of m.2 interfaces of the computer motherboard is small, and there may be only one m.2 interface. If the Nvme m.2ssd is required to be mass-produced, performance test is required to be performed on the Nvme m.2ssd, so that the test efficiency of the Nvme m.2ssd is easily affected. And the M.2 interface of the computer motherboard has service life, is easy to wear after being used for many times, increases the replacement cost of the interface, and easily causes the increase of the test cost.
Therefore, how to improve the testing efficiency of the SSD and reduce the testing cost is a problem to be solved.
Disclosure of Invention
In view of this, the embodiment of the application provides a testing device and testing cost for a solid state disk, which aims to improve the testing efficiency of an SSD and reduce the testing cost of the SSD.
In a first aspect, an embodiment of the present application provides a testing device for a solid state disk, where the testing device includes a target chip, a power module, and a testing host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module, and the target chip is connected with the test host;
the target chip is used for establishing connection with a second preset number of solid state disks to be tested through a second preset number of solid state disk interfaces; the second preset number is less than or equal to the first preset number;
the test host is used for performing performance test on the solid state disk to be tested connected to the solid state disk interface to generate a solid state disk performance test result;
the power module is used for providing power for the target chip.
Optionally, the target chip is further provided with an indicating device;
and the indicating device is used for indicating the testing state of the solid state disk to be tested, which is accessed to the solid state disk interface.
Optionally, the target chip is further configured to establish connection with a solid state disk redundant array with a third preset number of solid state disks to be tested through a third preset number of solid state disk interfaces; the third preset number is less than or equal to the first preset number.
Optionally, the target chip is provided with a power interface, and the target chip is connected with the power module through the power interface; the testing device also comprises a singlechip control module; the singlechip control module is connected with the test host, and is connected with a power interface of the target chip;
the test host is also used for sending a power supply control instruction to the singlechip control module;
the singlechip control module is used for receiving a power control instruction sent by the test host and controlling the power interface to be turned on or turned off based on the power control instruction.
Optionally, the testing device further comprises a temperature sensor, and the temperature sensor is connected with the singlechip control module;
the temperature sensor is used for collecting temperature data of a test environment where the test device of the solid state disk is located and sending the temperature data to the singlechip control module;
the singlechip control module is also used for sending the temperature data to the test host;
the test host is further configured to compare the temperature data with a preset temperature threshold to obtain a first comparison result, and determine a state of the test environment based on the first comparison result.
Optionally, the testing device further comprises a humidity sensor, and the humidity sensor is connected with the singlechip control module;
the humidity sensor is used for collecting humidity data of a test environment where the testing device of the solid state disk is located and sending the humidity data to the singlechip control module;
the singlechip control module is also used for sending the humidity data to the test host;
the test host is further configured to compare the humidity data with a preset humidity threshold to obtain a second comparison result, and determine a state of the test environment based on the second comparison result.
Optionally, the test host has a display screen;
the test host is also used for identifying the basic information of the solid state disk to be tested which is accessed to the solid state disk interface and generating a test report based on the basic information and the solid state disk performance test result;
and the display screen is used for displaying the test report of the solid state disk to be tested, which is accessed to the solid state disk interface, to a user.
Optionally, the target chip is a PCIE bridge chip having 8 solid state disk interfaces.
In a second aspect, an embodiment of the present application provides a method for testing a solid state disk, which is applied to a device for testing a solid state disk, where the device for testing a solid state disk includes a target chip, a power module, and a test host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module, and the target chip is connected with the test host; the target chip is used for establishing connection with a second preset number of solid state disks to be tested through the second preset number of solid state disk interfaces; the second preset number is less than or equal to the first preset number; the test method comprises the following steps:
and the test host performs performance test on the solid state disk to be tested which is accessed to the solid state disk interface, and generates a solid state disk performance test result.
Optionally, the test method further comprises:
and the test host identifies the basic information of the solid state disk to be tested which is accessed to the solid state disk interface, and generates a test report based on the basic information and the solid state disk performance test result.
In a third aspect, an embodiment of the present application provides a testing device for a solid state disk, where the device includes a memory and a processor:
the memory is used for storing a computer program and transmitting the computer program to the processor;
the processor is configured to execute the computer program, so that the device executes the method for testing a solid state disk according to the second aspect.
In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, where a computer program is stored, and when the computer program is executed, a device running the computer program implements the method for testing a solid state hard disk according to the second aspect.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
the embodiment of the application provides a testing device and a testing method for a solid state disk. The testing device of the solid state disk comprises a target chip, a power module and a testing host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module and connected with the test host; the target chip is used for establishing connection with a second preset number of solid state disks to be tested through a second preset number of solid state disk interfaces; the second preset number is smaller than or equal to the first preset number; the test host is used for performing performance test on the solid state disk to be tested accessed to the solid state disk interface and generating a solid state disk performance test result; and the power supply module is used for providing power supply for the target chip. Therefore, the target chip is provided with the first preset number of solid state disk interfaces, and can simultaneously perform performance test on a plurality of solid state disks to be tested, so that the test efficiency can be improved, manual connection for a plurality of times is avoided, and the operability is improved. And the cost of the target chip is low, so that the testing cost of the solid state disk to be tested can be saved.
Drawings
In order to more clearly illustrate the present embodiments or the technical solutions in the prior art, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a testing device for a solid state disk according to an embodiment of the present application;
fig. 2 is a schematic size diagram of an Nvme m.2ssd according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of a specific solid state disk testing device according to an embodiment of the present application;
fig. 4 is a flowchart of a method for testing a solid state disk according to an embodiment of the present application.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Several terms which may be referred to in the embodiments below in this application are explained first.
PCIE: is a high-speed serial computer expansion bus standard, which is known as PeripheralComponent Interconnect Express.
PCIE Switch: an extension or aggregation capability is provided for extending PCIE interfaces, which may act as packet routers, identifying which path a given packet needs to travel based on address or other routing information. Hereinafter, the embodiment is referred to as PCIE bridge chip.
M.2 interface: a solid state disk interface, also called Next Generation FormFactor, may be referred to simply as NGFF. The speed is faster, the volume is smaller, and the hard disk interface is adopted in most notebook computers at present.
Nvme: refers to the Non-volatile memory host controller interface specification (Non-Volatile MemoryExpress), which is a storage standard interface protocol formulated for PCIE.
SSD: solid State Disk (Solid State Disk or Solid State Drive, SSD), also known as a Solid State drive, is a hard Disk made from an array of Solid State electronic memory chips.
RAID: the redundant array of independent disks (Redundant Array of Independent Disks) is a redundant array formed by a plurality of hard disks.
ATX: is a computer architecture standard (Advanced Technologye Xtended), ATX is the default dimensional specification for newer computer systems.
ATX power: a common standard size power supply for an ATX power supply is mainly 150 x 140 x 86mm (W x D x H), where 150 x 86 is the size of the chassis related to the ATX, D is the size of the power supply and the rear abutment of the chassis, and 140mm is the length of the power supply compartment inside the chassis.
At present, the existing testing method of the solid state disk is generally as follows: the performance test is carried out on the solid state disk to be tested through the solid state disk interfaces of the computer main board, but the number of the hard disk interfaces is usually small. Taking nvmem.2ssd as an example of a solid state disk to be tested, a computer motherboard generally includes 1-2 m.2 interfaces. If multiple Nvme m.2ssds are required to be generated in batch, performance test is required to be performed on the multiple Nvme m.2ssds, and the m.2 interfaces of the computer motherboard are fewer, so that the test efficiency of the Nvme m.2ssds is easily affected. And solid state disk interfaces such as an M.2 interface of a computer main board have service lives, are easy to wear after being used for many times, and are easy to increase the replacement cost of the interfaces, so that the test cost is increased.
Based on this, in order to solve the above problems, the embodiments of the present application provide a testing device and a testing method for a solid state disk. The method aims to improve the test efficiency of the SSD and reduce the test cost of the SSD. The testing device of the solid state disk comprises a target chip, a power module and a testing host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module and connected with the test host; the target chip is used for establishing connection with a second preset number of solid state disks to be tested through a second preset number of solid state disk interfaces; the second preset number is smaller than or equal to the first preset number; the test host is used for performing performance test on the solid state disk to be tested accessed to the solid state disk interface and generating a solid state disk performance test result; and the power supply module is used for providing power supply for the target chip. Therefore, the target chip is provided with the first preset number of solid state disk interfaces, and can simultaneously perform performance test on a plurality of solid state disks to be tested, so that the test efficiency can be improved, manual connection for a plurality of times is avoided, and the operability is improved. And the cost of the target chip is low, so that the testing cost of the solid state disk to be tested can be saved.
The specific implementation manner of the testing device and the testing method of the solid state disk in the embodiment of the application are described in detail through embodiments with reference to the accompanying drawings.
Referring to fig. 1, the schematic structural diagram of a testing device for a solid state disk provided in an embodiment of the present application, and referring to fig. 1, the testing device for a solid state disk may include a target chip, a power module, and a testing host.
The target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power module and the test host. The solid state disk interface is used for being connected with a solid state disk to be tested, and the solid state disk to be tested is a solid state disk to be subjected to performance test.
As an example, the solid state disk to be tested may be Nvme m.2ssd to be tested, which is not limited in this application. It should be noted that, the size of the solid state disk to be tested is not limited in the application. Illustratively, the Nvme m.2ssd may be sized as Type 2230, type 2242, type 2260, type 2280, type 22110, and the like. The size of Nvme m.2ssd may be expressed as Typexxyy, xx denotes width, yy denotes length, and the unit is millimeter. Such as Type 2242 mentioned above, represents a width of 22mm and a length of 42mm. Type 2230 indicates a width of 22nm and a length of 30nm. See in particular the size schematic of the Nvme m.2ssd as shown in fig. 2. The width is 22mm, and the lengths are different.
In one possible implementation of the present application, the target chip may be a PCIE bridge chip having 48-channel 12 ports providing multi-host PCI Express switching functionality enabling users to connect multiple hosts to respective endpoints through scalable, high bandwidth, non-blocking interconnects to connect various applications including servers, storage, communication, and graphics platforms. The PCIE bridge chip has 8 ports (such ports may also be referred to as slots) that may be connected to the solid state disk to be tested.
It should be noted that the foregoing is only an example, the target chip may also have 3 solid state disk interfaces and 5 solid state disk interfaces, and the first preset number is not limited, and the first preset number may be greater than or equal to 2.
Taking the solid state disk to be tested as an NVMe M.2SSD as an example, the uplink of the PCIE bridging chip can be in butt joint with the test host through an X16 LAN. And the NVMe m.2ssd is a PCIE 3.0X 4 interface, so the PCIE bridge chip may use X4 LAN connection for downstream.
The target chip is used for establishing connection with the second preset number of solid state disks to be tested through the second preset number of solid state disk interfaces.
It can be understood that the solid state disk interfaces on the target chip are of a first preset number, which can perform performance test on the first preset number of solid state disks to be tested, and also can perform performance test on the solid state disks to be tested smaller than the first preset number, so that the second preset number can be smaller than or equal to the first preset number.
For example, take the solid state disk as NVMe m.2ssd and the target chip as a PCIE bridge chip. The PCIE bridge chip has 8 solid state hard disk interfaces, and may be used to establish connection with any number of NVMe m.2ssds in 1-8, that is, at most, 8 NVMe m.2ssds may be tested simultaneously.
In addition, in one possible implementation manner of the present application, the target chip is further configured to establish connection with a solid state disk redundant array having a third preset number of solid state disks to be tested through a third preset number of solid state disk interfaces. The third preset number is less than or equal to the first preset number.
The solid state disk redundant array consists of a plurality of solid state disks to be tested. Illustratively, the solid state disk redundant arrays may be Raid0, raid1, raid5, raid6, and Raid10. The present application is not limited in this regard.
The test host is used for performing performance test on the solid state disk to be tested accessed to the solid state disk interface and generating a solid state disk performance test result.
As an example, the performance test may include a read-write speed test, a random access speed test, a response time test, and the like for the solid state disk to be tested, which is not limited in this application.
The test host may be a data processing device such as a terminal device or a server, which has data processing capability. The terminal equipment can be electronic equipment such as a smart phone, a computer, a tablet personal computer and the like. The server may be a stand-alone server, a cluster server, a cloud server, or the like. The terminal device or the server mentioned above is not particularly limited in this application. The test host may be a terminal device or a server connected by communication, and the connection mode is not limited in this application, and may be wireless communication connection or wired communication connection.
In one possible implementation of the present application, the test host may have a display screen.
The test host is also used for identifying the basic information of the solid state disk to be tested which is accessed to the solid state disk interface and generating a test report based on the basic information and the solid state disk performance test result.
And the display screen is used for displaying a test report of the solid state disk to be tested, which is accessed to the solid state disk interface, to a user.
Illustratively, the basic information of the solid state disk to be tested may include, but is not limited to, manufacturer information, storage capacity, serial number of the hardware board, software version and firmware information, etc.
The test report is used for recording performance test results of the solid state disk to be tested.
And the power supply module is used for providing power supply for the target chip.
The power module may be an ATX power supply for converting a 220V ac power supply into a 3.3V, 5V or 12V dc power supply for the solid state disk to be tested.
In a possible embodiment of the present application, the target chip further has an indication device.
The indicating device is used for indicating the testing state of the solid state disk to be tested which is accessed to the solid state disk interface.
The test state of the solid state disk to be tested refers to whether the solid state disk to be tested is being tested or not.
Taking a target chip as an example of a PCIE bridge chip, a status indicator lamp is arranged beside a solid state disk interface and used for indicating the testing status of the solid state disk to be tested, which is connected with the solid state disk interface. As an example, if the solid state disk 1 to be tested is connected to the solid state disk interface 1 of the PCIE bridge chip, the status indicator light 1 of the solid state disk interface 1 is still in an off state, indicating that the connection is wrong, and the solid state disk interface 1 does not detect the solid state disk 1 to be tested; if the status indicator lamp 1 is on, the interface 1 of the solid state disk is indicated to detect the solid state disk 1 to be detected; and if the test host performs performance test on the solid state disk 1 to be tested, the status indicator lamp 1 turns into flash, so that the solid state disk 1 to be tested is indicated to be tested.
In one possible implementation manner of the application, the target chip is provided with a power interface, and the target chip is connected with the power module through the power interface; the testing device also comprises a singlechip control module; the singlechip control module is connected with the test host, and the singlechip control module is connected with a power interface of the target chip.
The test host is also used for sending a power supply control instruction to the singlechip control module;
the singlechip control module is used for receiving a power control instruction sent by the test host and controlling the on or off of the power interface based on the power control instruction. Namely, the test host can control whether the target chip is connected with a power supply or not through the singlechip control module.
It can be understood that the testing environment of the solid state disk to be tested is also particularly important, and if the testing environment is problematic, the accuracy of the performance testing result of the solid state disk is also affected.
Therefore, in one possible implementation manner of the application, the testing device of the solid state disk may further include a temperature sensor, where the temperature sensor is connected with the single-chip microcomputer control module.
The temperature sensor is used for collecting temperature data of a testing environment where the testing device of the solid state disk is located and sending the temperature data to the singlechip control module.
And the singlechip control module is also used for sending the temperature data to the test host. Namely, the singlechip control module is used for acquiring temperature data.
The test host is also used for comparing the temperature data with a preset temperature threshold value to obtain a first comparison result and determining the state of the test environment based on the first comparison result.
In addition, in a possible implementation manner of the application, the temperature sensor is further used for testing the temperature of the solid state disk to be tested and sending the temperature to the test host through the singlechip control module, the basic information identified by the test host comprises the temperature information of the solid state disk to be tested, the test host can compare the values of the temperature information and the temperature information of the solid state disk to be tested, when the temperature of the solid state disk to be tested exceeds the value in the temperature information of the solid state disk to be tested, the fact that the power consumption of the solid state disk to be tested is overlarge is indicated, and an alarm prompt can be sent.
As an example, the preset temperature threshold may include a preset maximum temperature threshold, as well as a preset minimum temperature threshold of the device. The lowest temperature threshold is smaller than the highest temperature threshold, after the test host receives the temperature data sent by the singlechip control module, the temperature data can be compared with the highest temperature threshold and the lowest temperature threshold, and if the first comparison result is that the value of the temperature data is equal to or smaller than the lowest temperature threshold and is smaller than or equal to the highest temperature threshold, the state of the test environment is determined to be normal. If the first comparison result is that the value of the temperature data is smaller than the lowest temperature threshold value or larger than the highest temperature threshold value, the state of the test environment is determined to be abnormal, and an alarm prompt can be sent to a tester and the like. It should be noted that, the value of the preset temperature threshold is not limited in this application. Illustratively, the minimum temperature threshold may be-40 ℃, and the maximum temperature threshold may be 80 ℃.
In a possible implementation manner of the application, the testing device of the solid state disk may further include a humidity sensor, and the humidity sensor is connected with the single chip microcomputer control module.
The humidity sensor is used for collecting humidity data of a test environment where the testing device of the solid state disk is located and sending the humidity data to the singlechip control module.
And the singlechip control module is also used for sending the humidity data to the test host.
The test host is also used for comparing the humidity data with a preset humidity threshold value to obtain a second comparison result, and determining the state of the test environment based on the second comparison result.
As an example, the preset humidity threshold may include a preset maximum humidity threshold, and a preset minimum humidity threshold of the device. The lowest humidity threshold is smaller than the highest humidity threshold, after the test host receives the humidity data sent by the singlechip control module, the humidity data can be compared with the highest humidity threshold and the lowest humidity threshold, and if the second comparison result is that the value of the humidity data is equal to or smaller than the lowest humidity threshold and smaller than or equal to the highest humidity threshold, the state of the test environment is determined to be normal. If the second comparison result is that the value of the humidity data is smaller than the lowest humidity threshold or larger than the highest humidity threshold, the state of the test environment is determined to be abnormal, and an alarm prompt can be sent to a tester and the like.
In addition, in a possible implementation manner of the application, the testing device of the solid state disk may further include a current detection sensor, and the current detection sensor is connected with the single chip microcomputer control module.
The current detection sensor is used for collecting current data when the power supply module outputs power to the target chip and sending the current data to the singlechip control module.
Illustratively, taking the power module as an ATX power module as an example, the current data may be used to detect the power condition of the ATX power output power.
The singlechip control module is also used for sending the current data to the test host.
The test host is also used for comparing the current data with a preset current threshold value to obtain a third comparison result and determining the power supply state of the power supply module based on the third comparison result.
As an example, if the current data exceeds the preset current threshold, it indicates that the power supply of the power supply module is abnormal, and the test host may send an alarm prompt. For example, the preset current threshold may be 15A, and if the current data received by the test host exceeds 15A, an alarm may be sent.
In one possible implementation manner of the application, the testing device of the solid state disk may further comprise a testing tooling plate, which supports the installation of target chips with various sizes, and installs a singlechip control module, a temperature sensor, a power interface and the like. The target chip is respectively connected with the test host and the power module through the test tool board. Illustratively, the test workboard may be a process control block circuit board (Processing ControlBlock, PCB), which is not limited in this application.
Referring to fig. 3, an example is shown, which is a schematic structural diagram of a testing device for a specific solid state disk according to an embodiment of the present application. As shown in fig. 3, the target chip on the test tooling board is a PCIE bridge chip, which has 8 solid state disk interfaces, that is, 8 slots, that is, slots 1-8 in the figure, and a status indicator light is provided beside each slot. Slots 1-8 are connected to Nvme m.2ssd1-Nvme m.2ssd8, respectively. The test tooling plate is connected with the test host through the PCIE X16 adapter plate and is in communication connection with the external ATX power module through the ATX power interface. The test host computer controls the power supply to be turned on or off by a power generation source on-off control signal under the singlechip control module, and also can collect temperature data of the temperature sensor through the singlechip control module. The temperature sensor can be used for measuring the temperature of the test tooling plate and measuring temperature data of the test environment where the test tooling plate is located. The humidity sensor may be used to measure humidity data of a test environment in which the tooling plate is located. The current detection sensor is used for collecting current data when the external ATX power module outputs power to the target chip.
The embodiments of the present application provide some specific implementation manners of the testing device for a solid state disk, and based on this, the present application further provides a corresponding method. The method for testing the solid state disk provided by the embodiment of the application will be described.
Referring to fig. 4, the flowchart of a method for testing a solid state disk according to an embodiment of the present application is applied to a device for testing a solid state disk, where the device for testing a solid state disk includes a target chip, a power module, and a test host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module and connected with the test host; the target chip is used for establishing connection with a second preset number of solid state disks to be tested through a second preset number of solid state disk interfaces; the second preset number is less than or equal to the first preset number.
The testing method of the solid state disk can comprise the following steps:
s401: the test host identifies the basic information of the solid state disk to be tested which is accessed to the solid state disk interface.
S402: and the test host performs performance test on the solid state disk to be tested accessed to the solid state disk interface.
S403: and the test host generates a solid state disk performance test result.
As an example, the test host receives response time, read-write speed, temperature data, humidity data and the like of the solid state disk to be tested, which are sent by the singlechip control module, and generates a solid state disk performance test result.
S404: and the test host generates a test report based on the basic information and the solid state disk performance test result.
S405: the test host displays the test report to the user.
As an example, it may be that the test report is directly displayed after being generated; the test report may also be displayed to the user in response to a user's viewing operation of the test report, which is not limited in this application. Therefore, a user can conveniently conduct further analysis on the solid state disk to be tested.
S406: the test host stores the test report.
As an example, the test host may include a database in which test reports are stored by the test host for easy viewing by the user at any time.
The embodiment of the application also provides corresponding equipment and a computer readable storage medium, which are used for realizing the scheme provided by the embodiment of the application.
The device comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor is used for executing the computer program so that the device can execute the testing method of the solid state disk.
The computer readable storage medium stores a computer program, and when the computer program is executed, a device executing the computer program realizes the method for testing the solid state disk according to any embodiment of the application.
The "first" and "second" in the names of "first", "second" (where present) and the like in the embodiments of the present application are used for name identification only, and do not represent the first and second in sequence.
From the above description of embodiments, it will be apparent to those skilled in the art that all or part of the steps of the above described example methods may be implemented in software plus general hardware platforms. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which may be stored in a readable storage medium, such as a read-only memory (ROM)/RAM, a magnetic disk, an optical disk, or the like, including several instructions for causing a computer device (which may be a personal computer, a server, or a network communication device such as a router) to perform the methods described in the embodiments or some parts of the embodiments of the present application.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points. The apparatus embodiments described above are merely illustrative, wherein elements illustrated as separate elements may or may not be physically separate, and elements illustrated as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing is merely one specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The testing device of the solid state disk is characterized by comprising a target chip, a power supply module and a testing host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module, and the target chip is connected with the test host;
the target chip is used for establishing connection with a second preset number of solid state disks to be tested through a second preset number of solid state disk interfaces; the second preset number is less than or equal to the first preset number;
the test host is used for performing performance test on the solid state disk to be tested connected to the solid state disk interface to generate a solid state disk performance test result;
the power module is used for providing power for the target chip.
2. The test device of claim 1, wherein the target chip further has an indication device;
and the indicating device is used for indicating the testing state of the solid state disk to be tested, which is accessed to the solid state disk interface.
3. The test device of claim 1, wherein the target chip is further configured to establish a connection with a solid state disk redundant array having a third preset number of solid state disks under test through a third preset number of solid state disk interfaces; the third preset number is less than or equal to the first preset number.
4. The test device of claim 1, wherein the target chip has a power interface through which the target chip is connected to the power module; the testing device also comprises a singlechip control module; the singlechip control module is connected with the test host, and is connected with a power interface of the target chip;
the test host is also used for sending a power supply control instruction to the singlechip control module;
the singlechip control module is used for receiving a power control instruction sent by the test host and controlling the power interface to be turned on or turned off based on the power control instruction.
5. The test device of claim 4, further comprising a temperature sensor, the temperature sensor being coupled to the single-chip microcomputer control module;
the temperature sensor is used for collecting temperature data of a test environment where the test device of the solid state disk is located and sending the temperature data to the singlechip control module;
the singlechip control module is also used for sending the temperature data to the test host;
the test host is further configured to compare the temperature data with a preset temperature threshold to obtain a first comparison result, and determine a state of the test environment based on the first comparison result.
6. The test device of claim 4, further comprising a humidity sensor, wherein the humidity sensor is coupled to the single-chip microcomputer control module;
the humidity sensor is used for collecting humidity data of a test environment where the testing device of the solid state disk is located and sending the humidity data to the singlechip control module;
the singlechip control module is also used for sending the humidity data to the test host;
the test host is further configured to compare the humidity data with a preset humidity threshold to obtain a second comparison result, and determine a state of the test environment based on the second comparison result.
7. The test device of claim 1, wherein the test host has a display screen;
the test host is also used for identifying the basic information of the solid state disk to be tested which is accessed to the solid state disk interface and generating a test report based on the basic information and the solid state disk performance test result;
and the display screen is used for displaying the test report of the solid state disk to be tested, which is accessed to the solid state disk interface, to a user.
8. The test device of any one of claims 1-7, wherein the target chip is a PCIE bridge chip having 8 solid state disk interfaces.
9. The testing method of the solid state disk is characterized by being applied to a testing device of the solid state disk, wherein the testing device comprises a target chip, a power module and a testing host; the target chip is provided with a first preset number of solid state disk interfaces; the target chip is connected with the power supply module, and the target chip is connected with the test host; the target chip is used for establishing connection with a second preset number of solid state disks to be tested through the second preset number of solid state disk interfaces; the second preset number is less than or equal to the first preset number; the test method comprises the following steps:
and the test host performs performance test on the solid state disk to be tested which is accessed to the solid state disk interface, and generates a solid state disk performance test result.
10. The method of testing of claim 9, further comprising:
and the test host identifies the basic information of the solid state disk to be tested which is accessed to the solid state disk interface, and generates a test report based on the basic information and the solid state disk performance test result.
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| CN202311559543.2A CN117591359A (en) | 2023-11-21 | 2023-11-21 | Testing device and testing method for solid state disk |
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| CN202311559543.2A CN117591359A (en) | 2023-11-21 | 2023-11-21 | Testing device and testing method for solid state disk |
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