CN117581378A

CN117581378A - Semiconductor device, packaging structure and electronic equipment

Info

Publication number: CN117581378A
Application number: CN202180099748.XA
Authority: CN
Inventors: 简中祥; 徐向明
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2024-02-20
Also published as: WO2022266987A1

Abstract

The application discloses a semiconductor device, a packaging structure and electronic equipment, which are used for reducing the insertion loss of the semiconductor device and improving the linearity of the semiconductor device. The semiconductor device comprises a semiconductor substrate, a first well region doped with first type impurities is arranged above the semiconductor substrate, a source diffusion region and a drain diffusion region doped with second type impurities are arranged in the first well region, a first insulating layer positioned between the source diffusion region and the drain diffusion region is arranged above the first well region, and a grid electrode is arranged above the first insulating layer; still include first isolation groove, first isolation groove sets up in first well region, and first isolation groove is provided with the relief structure that is used for alleviating stress.

Description

Semiconductor device, packaging structure and electronic equipment

Technical Field

The application relates to the technical field of electronic equipment, in particular to a semiconductor device, a packaging structure and electronic equipment.

Background

The integration of a plurality of functional modules of the chip plays an increasingly important role in photoelectric and microwave high-frequency technical applications along with the evolution of moore's law and the advancement of standards of communication technologies.

In view of the low cost and high integration requirements of the chip, it is generally required to integrate a plurality of functional modules such as a low noise amplifier (low noise amplifier, LNA), a Power Amplifier (PA) and a switching circuit into the same chip, so how to obtain the chip functions of the index of low insertion loss and high linearity becomes a key problem to be solved currently.

Disclosure of Invention

The application provides a semiconductor device, a packaging structure and electronic equipment, so as to improve the yield and the use reliability of the semiconductor device.

In a first aspect, the present application provides a semiconductor device that may include a semiconductor substrate having a first well region disposed thereon, the first well region being doped with a first type impurity. The first well region is provided with a source diffusion region and a drain diffusion region which are spaced apart from each other, and the source diffusion region and the drain diffusion region can be doped with second type impurities respectively. A first insulating layer is arranged above the first well region, the first insulating layer is positioned between the source electrode diffusion region and the drain electrode diffusion region, a grid electrode is arranged above the first insulating layer, and the grid electrode can be used for controlling the on-off state between the source electrode and the drain electrode. The semiconductor device may further include a first isolation trench disposed within the first well region to reduce electrical interference between the semiconductor device and surrounding devices. In addition, the first isolation groove may be further provided with a relief structure for relieving stress.

According to the semiconductor device in the scheme, when the first isolation groove is formed, the stress of the first isolation groove in the technical processing process can be relieved through the release structure, the risk of failure of the first isolation groove is reduced, and then the yield and the use reliability of the semiconductor device can be improved.

In some possible embodiments, a first sidewall may be further disposed on a peripheral side of the gate, and the first sidewall may isolate the gate from the source diffusion region and the drain diffusion region, thereby preventing leakage between the electrodes.

When the first isolation trench is specifically provided, the first isolation trench may have a ring structure, and the source diffusion region and the drain diffusion region are located in a ring region defined by the first isolation trench. Thus, the first isolation groove can form a continuous isolation structure on the periphery of the first well region, thereby being beneficial to improving the isolation effect of the semiconductor device.

In order to improve the isolation effect between the adjacent semiconductor devices, the number of the first isolation trenches may be plural, and the plural first isolation trenches may be sequentially spaced apart in a direction away from the gate electrode. In a specific arrangement, the number of the first isolation grooves may be 3 to 6.

In some possible embodiments, the first isolation groove may be a rectangular ring structure, and the relief structure may be a chamfer structure provided at each corner of the first isolation groove. Compared with a right-angle structure, the chamfer structure can realize gentle transition at the corner of the first isolation groove, so that the stress of the corner of the first isolation groove in the process can be relieved.

In some possible embodiments, the first isolation groove may be a rectangular ring structure, and the relief structure may be a rounded corner structure provided at each corner of the first isolation groove. The round corner structure can connect adjacent edges of the first isolation groove through circular arcs, so that gentle transition is realized at the corner of the first isolation groove, and stress of the corner of the first isolation groove in technological processing is relieved.

In some possible embodiments, the relief structure may be a partition, so that when the first isolation groove is formed, the stress of the first isolation groove during the processing process may be relieved by interrupting at the position of the partition, and the risk of failure of the first isolation groove is reduced.

When specifically setting up, first isolation groove can be rectangular ring structure, and first isolation groove can include first bight, second bight, third bight and fourth bight, and wherein, first bight is diagonal setting with third bight, and second bight is diagonal setting with fourth bight. Since the stress concentration points of the first isolation groove are mainly concentrated at the four corners, the above-mentioned partition portion may be provided at one or more corners of the first isolation groove in particular in order to relieve the stress at the corners.

In a specific embodiment, when the number of the first isolation grooves is plural, the partition portion of one first isolation groove may be disposed at the first corner portion, and the partition portion of the other first isolation groove may be disposed at least one corner portion of the second corner portion, the third corner portion, and the fourth corner portion. By adopting the design, the partition parts of two adjacent first isolation grooves can be staggered, so that the isolation structure formed by a plurality of first isolation grooves can be effectively isolated at any circumferential position, and further, the stress of the first isolation grooves in the technical processing process is relieved on the premise of not influencing the isolation effect of the first isolation grooves, and the yield and the use reliability of the semiconductor device are improved.

In another specific embodiment, when the number of the first isolation grooves is plural, each first isolation groove may be provided with two partition portions, respectively, and two partition portions of one first isolation groove may be provided at the first corner portion and the third corner portion thereof, respectively, and two partition portions of the other first isolation groove may be provided at the second corner portion and the fourth corner portion thereof, respectively, in the adjacent two first isolation grooves. The arrangement mode can also enable the partition parts of two adjacent first isolation grooves to be staggered, so that the isolation structure formed by a plurality of first isolation grooves can be effectively isolated at any circumferential position.

In some possible embodiments, the depth of the first isolation trench may be greater than the depth of the first well region, such that the bottom of the first isolation trench may extend into the semiconductor substrate, thereby facilitating maintaining high resistance characteristics of the semiconductor substrate, which may reduce substrate loss of the semiconductor device, and improve linearity of the semiconductor device. In a specific arrangement, the depth of the first isolation groove may be 4-6 um.

In some possible embodiments, the semiconductor device may further include an epitaxial layer, the epitaxial layer may be disposed over the semiconductor substrate, and the first well region may be disposed over the epitaxial layer. By arranging the epitaxial layer, the semiconductor device can obtain a more excellent and controllable crystal structure, and the performance of the semiconductor device can be improved.

In some possible embodiments, the semiconductor device may further include a second isolation trench, where the second isolation trench is disposed in the first well region, and a depth of the second isolation trench is greater than a thickness of the epitaxial layer, so that a low-resistance leakage channel formed by an epitaxial layer material existing below the second isolation trench may be avoided, thereby effectively maintaining advantages of the high-resistance semiconductor substrate and reducing substrate loss of the semiconductor device.

When the second isolation groove is specifically provided, the second isolation groove can also be in a ring structure, and the source diffusion region and the drain diffusion region are also located in the ring-shaped region defined by the second isolation groove. Thus, a continuous isolation structure can be formed on the periphery of the first well region in the second isolation groove, so that the isolation effect of the semiconductor device is improved.

In some possible embodiments, the second isolation trench may coincide with an end of the first isolation trench facing away from the semiconductor substrate.

In some possible embodiments, when the number of the first isolation trenches is plural, under the second isolation trench, the adjacent two first isolation trenches may have the same intrinsic characteristics as the semiconductor substrate, that is, the silicon material between the adjacent two first isolation trenches maintains the same doping condition as the semiconductor substrate, thereby being beneficial to maintain the high-resistance characteristics of the semiconductor substrate, and further, the substrate loss of the semiconductor device may be reduced.

In some possible embodiments, the edge of the first well region may be provided with a guard ring, and the first isolation trench and the second isolation trench may be located between the active region and the guard ring. The protection ring may be doped with a first type of impurity and the first protection ring may be grounded or set up to a power source. The guard ring can reduce parasitic resistance of the semiconductor substrate and enhance isolation effect on the MOS transistor.

In some possible embodiments, the first isolation trench may be filled with silicon dioxide and polysilicon in sequence, and the second isolation trench may be filled with silicon dioxide. The polysilicon in the first isolation groove can be used for maintaining the potential of the first isolation groove, so that parasitic leakage phenomenon caused by unstable potential of the first isolation groove is prevented.

In some possible embodiments, the first isolation trench may be a Deep Trench Isolation (DTI) structure, and the second isolation trench may be a Shallow Trench Isolation (STI) structure.

In some possible embodiments, the semiconductor device may be specifically a BiCMOS device. A SiGe base region of the SiGe HBT can be arranged above the epitaxial layer in a region avoiding the MOS transistor, a collector region doped with second type impurities is arranged in the epitaxial layer, and the collector regions are positioned at two sides of the SiGe base region; an emitter and a base are arranged above the SiGe base region, the base is arranged on two sides of the emitter, and a second insulating layer can be arranged between the emitter and the base. Illustratively, the emitter and the base may be made of polysilicon, and the second insulating layer may be made of silicon dioxide.

In addition, the second side wall can be arranged on the periphery of the emitter, the third side wall can be arranged on the periphery of the base, the second side wall can isolate the emitter from the base and the collector, and the third side wall can isolate the base from the collector, so that electric leakage between the electrodes is prevented.

In some possible embodiments, a buried layer may be further disposed below the epitaxial layer, N-type impurities may be doped in the buried layer, and the collector regions on both sides may be electrically connected to the buried layer, respectively, to reduce the series resistance of the collector regions and provide a current low-resistance channel for the collector regions.

In some possible embodiments, the edge of the SiGe HBT may be further provided with a third isolation trench in the shape of a ring, which may be specifically disposed at the periphery of the collector region, and the third isolation trench may be sequentially filled with silicon dioxide and polysilicon. The third isolation groove can reduce the electrical interference between the HBT and surrounding devices and improve the working reliability of the HBT.

In some possible embodiments, the first type of impurity may be a P-type impurity, in which case the second type of impurity may be an N-type impurity; alternatively, the first type impurity may be an N type impurity, and the second type impurity is a P type impurity.

In a second aspect, the present application provides a semiconductor device that may include a semiconductor substrate having a first well region disposed thereon, the first well region being doped with a first type impurity. The first well region is provided with a source diffusion region and a drain diffusion region which are spaced apart from each other, and the source diffusion region and the drain diffusion region can be doped with second type impurities respectively. A first insulating layer is arranged above the first well region, the first insulating layer is positioned between the source electrode diffusion region and the drain electrode diffusion region, a grid electrode is arranged above the first insulating layer, and the grid electrode can be used for controlling the on-off state between the source electrode and the drain electrode. The semiconductor device may further include a first isolation trench disposed within the first well region to reduce electrical interference between the semiconductor device and surrounding devices. When the semiconductor device is specifically arranged, the depth of the first isolation groove can be larger than that of the first well region, so that the bottom of the first isolation groove can extend into the semiconductor substrate, the high resistance of the semiconductor substrate is kept, the substrate loss of the semiconductor device can be reduced, and the linearity of the semiconductor device is improved.

In a third aspect, the present application further provides a package structure, where the package structure includes a substrate, a lead, and a semiconductor device in any one of the foregoing possible embodiments, where the semiconductor device is disposed on a surface of the substrate, the lead is disposed on a surface of the substrate on a same side as the semiconductor device, and the lead is disposed around the semiconductor device, and one end of the lead is electrically connected to the semiconductor device. The semiconductor substrate of the semiconductor device can maintain high resistance characteristics, so that substrate loss of the semiconductor device can be reduced and linearity of the semiconductor device can be improved. In addition, the structure of the first isolation groove of the semiconductor device is improved, so that the stress of the first isolation groove in the technical processing process is effectively relieved, the yield and the use reliability of the semiconductor device can be improved, and the reliability of the packaging structure can be improved.

In a fourth aspect, the present application further provides an electronic device, where the electronic device may include a circuit board and a package structure in the foregoing embodiment, where the package structure may be fixed on the circuit board by means of soldering or the like, and a signal pin may be further disposed in a region of the circuit board that avoids the package structure, and the signal pin may be connected to the other end of the lead, so that the package structure may be connected to other devices through a trace on the circuit board, and further connection between the semiconductor device and an external circuit is achieved. The semiconductor device has the advantages of low loss, high linearity and the like, and the yield and the use reliability of the semiconductor device are high, so that the performance stability of the electronic equipment is improved.

Drawings

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application;

FIG. 3 is a schematic cross-sectional structure of the semiconductor device shown in FIG. 2 at A-A;

FIG. 4 is another cross-sectional schematic view of the semiconductor device shown in FIG. 2 at A-A;

FIG. 5 is another cross-sectional schematic view of the semiconductor device shown in FIG. 2 at A-A;

fig. 6 is another cross-sectional structure schematic view of the semiconductor device shown in fig. 2 at A-A;

fig. 7 is a flowchart of a method of fabricating the semiconductor device shown in fig. 2;

fig. 8 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a package structure according to an embodiment of the present application.

Reference numerals:

a 100-semiconductor device; 10-a semiconductor substrate; 20-an epitaxial layer; 21-a first well region; 31-an active region;

32-source diffusion regions; 33-drain diffusion regions; 34-a first insulating layer; 35-grid; 36-a first side wall; 40-protecting ring;

50-a first isolation groove; 60-a second isolation groove; 51-a partition; 501-a first corner; 502-a second corner;

503-third corner; 504-fourth corners; 52-chamfering structure; 53-rounded corner structure; 71-collector; a 72-base region;

73-emitter; a 74-base; 75-a second insulating layer; 76-a second side wall; 77-a third side wall; 78-buried layer;

80-a third isolation groove; 200-a substrate; 300-lead wire.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings.

The transistors of metal-oxide-semiconductor (MOS) structure are referred to as MOS transistors, which are divided into P-type MOS transistors and N-type MOS transistors, i.e., PMOS transistors and NMOS transistors. The integrated circuit formed by the MOS tube is called MOS integrated circuit, and the complementary MOS integrated circuit formed by the PMOS tube and the NMOS tube is CMOS-IC (complementary MOS integrated circuit). The MOS transistor is a unipolar semiconductor device with the electric field effect controlling the current, basically does not take current or has extremely small current at the input end, has the characteristics of high input impedance, low noise, good thermal stability, simple manufacturing process and the like, and is often applied to large-scale and ultra-large-scale integrated circuits.

Bipolar transistors (bipolar junction transistor, BJTs), commonly known as transistors, are electronic devices with three terminals made of three differently doped semiconductors, and the charge flow in the transistor is mainly due to the diffusion and drift motion of carriers at the PN (PN junction) junction. Such a transistor may in operation involve the flow of both electron and hole carriers and is therefore also referred to as a bipolar transistor. BJTs are capable of amplifying signals and have good power control, high speed operation, and endurance, and are often used to construct amplifier circuits, drive speakers, or motors, among other devices.

The BiCMOS technology is a process technology of integrating the BJT and the CMOS on the same chip, and the BiCMOS integrates the advantages of the BJT and the CMOS, thereby opening up a brand-new way for developing very large scale integrated circuits for various communication, information processing and digital communication with high speed and high performance. With the growing popularity of the fifth generation mobile communication technology (5th generation mobile communication technology,5G), the silicon germanium alloy (SiGe) BiCMOS process plays an increasingly important role in photovoltaic and microwave high frequency applications. The SiGe heterojunction bipolar transistor (heterojunction bipolar transistor, HBT) is a core key of a SiGe BiCMOS (bipolar complementary metal oxide semiconductor) manufacturing process technology, the SiGe HBT is formed by adding a small amount of germanium component into a base region of a silicon-based BJT, and the base region is made of SiGe materials, so that the performance of the device can be remarkably improved, the SiGe HBT has excellent characteristics of low noise, high gain, high linearity, high breakdown voltage and the like, and the SiGe HBT is suitable for the design of a low-noise amplifier and a power amplifier.

In the field of wireless communication technology (WIFI) radio frequency front ends, a WIFI chip has high requirements on cost, product integration level and the like, and a low-noise amplifier, a power amplifier, a switching circuit and the like are always integrated on the same chip in design, so that insertion loss is inevitably generated; in addition, siGe BiCMOS is formed on bulk silicon (bulk Si) with no dielectric layer between the device and the substrate as isolation, which inevitably results in substrate loss during operation, as compared to silicon-on-insulator (SOI) technology on an insulating substrate. Therefore, how to obtain a radio frequency switching device with low insertion loss and high linearity becomes a critical problem to be solved in the radio frequency field.

Fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application. Referring to fig. 1, a semiconductor device 100 provided in an embodiment of the present application may be a MOS transistor, where the semiconductor device 100 may include a semiconductor substrate 10, and the semiconductor substrate 10 may be a silicon substrate, and a first type impurity may be doped in the semiconductor substrate 10. The first type impurity may be an N-type impurity or a P-type impurity, and it is understood that if the first type impurity is an N-type impurity, the formed semiconductor substrate 10 is an N-type semiconductor substrate; if the first type impurity is a P-type impurity, the semiconductor substrate 10 formed is a P-type semiconductor substrate.

The first WELL region 21 may be formed on the semiconductor substrate 10 by an ion implantation process, and the ions implanted in the first WELL region 21 may be specifically a first type impurity, and it may be understood that if the first type impurity is a P-type impurity, the first WELL region formed is a P-WELL (P-WELL), and if the first type impurity is an N-type impurity, the first WELL region 21 formed is an N-WELL (N-WELL).

An active region 31 of a MOS transistor is disposed in the first well region 21, a source diffusion region 32 and a drain diffusion region 33 are disposed in the active region 31, the source diffusion region 32 and the drain diffusion region 33 are disposed at a distance, and the source diffusion region 32 and the drain diffusion region 33 are doped with a second type impurity, respectively. A first insulating layer 34 is further disposed over the active region 31, the first insulating layer 34 being located between the source diffusion region 32 and the drain diffusion region 33, and a gate electrode 35 is disposed over the first insulating layer 34. In addition, a first sidewall 36 may be disposed on a peripheral side of the gate electrode 35, and the first sidewall 36 may isolate the gate electrode 35 from the source diffusion region 32 and the drain diffusion region 33. For example, in the embodiment of the present application, the material of the gate 35 may be polysilicon, the material of the first insulating layer 34 may be silicon dioxide, the material of the first sidewall 36 may be silicon dioxide, or the lower portion of the first sidewall 36 may be silicon dioxide, and the upper portion may be silicon nitride.

When the first well region 21 is a P-well, the source diffusion region 32 and the drain diffusion region 33 are N diffusion regions, respectively, and when the MOS transistor is turned on, an N-type conductive channel is formed between the source diffusion region 32 and the drain diffusion region 33, and the MOS transistor thus formed is an NMOS. When the first well region 21 is an N-well, the source diffusion region 32 and the drain diffusion region 33 are P diffusion regions, respectively, and when the MOS transistor is turned on, a P-type conductive channel is formed between the source diffusion region 32 and the drain diffusion region 33, and the MOS transistor thus formed is a PMOS.

It should be noted that the number of the first well regions 21 may be plural, and the first well regions 21 may include P-wells or N-wells, so that plural NMOS and plural PMOS are formed on the semiconductor substrate 10, and the NMOS and PMOS may be connected in a specific manner to form various CMOS circuits. Since the CMOS circuit is a circuit structure commonly known and well known in the art, a specific arrangement form thereof will not be described in detail.

In addition, the edge of the first well region 21 may be further provided with a guard ring 40, and the first type impurity may be doped in the guard ring 40. When the first well region 21 is a P-well, the guard ring 40 can be electrically connected to the first well region 21 and grounded through the first well region 21. When the first well region 21 is an N-well, the guard ring 40 can be connected to a power Voltage (VDD) through the first well region 21. The guard ring 40 can reduce parasitic resistance of the semiconductor substrate 10, enhance isolation effect on the MOS transistor, and thereby reduce the risk of latch-up.

It will be appreciated that in some embodiments, the semiconductor device may further comprise an epitaxial layer 20 disposed between the semiconductor substrate 10 and the first well region 21. That is, the epitaxial layer 20 may be disposed above the semiconductor substrate 10, the first well region 21 is disposed in the epitaxial layer 20, and the depth of the first well region 21 may be greater than the thickness of the epitaxial layer 20. The doping type of the impurities in the epitaxial layer 20 and the semiconductor substrate 10 may be the same, i.e., the first type of impurities may also be doped in the epitaxial layer 20. In particular, the doping concentration of the first type of impurity in epitaxial layer 20 may be different from the doping concentration of the first type of impurity in semiconductor substrate 10, e.g., the doping concentration of the first type of impurity in epitaxial layer 20 may be less than the doping concentration of the first type of impurity in semiconductor substrate 10.

In other embodiments, the epitaxial layer 20 and the semiconductor substrate 10 may also be doped with different types of impurities, such as the epitaxial layer 20 may be doped with a second type of impurity. It should be understood that the second type of impurity may also be an N-type impurity or a P-type impurity, and when the first type of impurity is an N-type impurity, the second type of impurity is a P-type impurity; when the first type impurity is a P-type impurity, the second type impurity is an N-type impurity. The doping concentration of the second type impurity in the epitaxial layer 20 may be designed with reference to the aforementioned scheme of doping the first type impurity, and will not be described herein.

With continued reference to fig. 1, in an embodiment of the present application, in order to reduce electrical interference between adjacent MOS transistors, the periphery of the active region 31 may further be provided with a first isolation trench 50, and the first isolation trench 50 may be specifically located between the active region 31 and the guard ring 40, so as to isolate the active region 31 from the guard ring 40. When the device is specifically arranged, silicon dioxide and polysilicon are sequentially filled in the first isolation groove 50 from the bottom of the first isolation groove 50 to the direction of the notch, namely, silicon dioxide is filled at one end, close to the bottom, of the first isolation groove 50, and polysilicon is filled at one end, close to the notch. The polysilicon filled in the first isolation trench 50 can be used to maintain the potential in the first isolation trench 50, so as to prevent parasitic leakage caused by unstable potential of the first isolation trench 50.

In a specific design, the first isolation trench 50 may have a substantially annular structure, and the first isolation trench 50 is disposed at the periphery of the active region of the MOS transistor, that is, the active region 31 is located in the annular region defined by the first isolation trench 50, so that a continuous isolation structure can be formed on the periphery of the active region 31, which is beneficial to improving the isolation effect on the MOS transistor. The depth of the first isolation trench 50 may be greater than the depth of the first well region 21, and since the depth of the first well region 21 is greater than the thickness of the epitaxial layer 20, in the embodiment of the present application, the bottom of the first isolation trench 50 may extend into the semiconductor substrate 10, which is beneficial to maintain the high-resistance property of the semiconductor substrate 10, thereby reducing the substrate loss of the semiconductor device 100 and improving the linearity of the semiconductor device 100. In particular, the depth of the first isolation trench 50 may be between 4um and 6um, and for example, the depth of the first isolation trench may be 4um,5um, or 6um, etc.

It should be noted that, in the embodiment of the present application, the number of the first isolation trenches 50 may be plural to improve the isolation effect between the adjacent MOS transistors. In particular, the plurality of first isolation trenches 50 are sequentially spaced apart in a direction away from the active region 31. That is, at the periphery of the active region 31, a plurality of first isolation trenches 50 are arranged radially. The number of the first isolation grooves 50 may be 3 to 6, and the number of the first isolation grooves 50 may be 3, 4, 5, or 6, for example, without being particularly limited thereto.

Fig. 2 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application. As shown in fig. 2, in order to further improve the isolation effect between adjacent MOS transistors, a second isolation trench 60 may be provided between the active region 31 and the guard ring 40 in addition to the first isolation trench 50. The second isolation trench 60 may have a ring structure, and the second isolation trench 60 may be filled with silicon dioxide. In the present embodiment, the depth of the second isolation trench 60 is smaller than the depth of the first isolation trench 50, and thus, the isolation formed by the first isolation trench 50 may also be referred to as deep trench isolation (Deep Trench Isolation, DTI), and the isolation formed by the second isolation trench 60 may also be referred to as shallow trench isolation (Shallow Trench Isolation, STI). In particular, the second isolation trench 60 may coincide with an end of the first isolation trench 50 facing away from the semiconductor substrate. In addition, the depth of the second isolation trench 60 may be greater than the thickness of the epitaxial layer 20, and this design may avoid the existence of the epitaxial layer 20 material under the second isolation trench 60, which is referred to as a low-resistance leakage path, compared to the scheme in which the depth of the second isolation trench 60 is less than the thickness of the epitaxial layer 20, so that the advantage of the high-resistance semiconductor substrate 10 may be more effectively maintained, the substrate loss of the semiconductor device 100 may be reduced, and the linearity of the semiconductor device 100 may be improved.

Fig. 3 is a schematic cross-sectional structure of the semiconductor device shown in fig. 2 at A-A. Referring to fig. 2 and 3 together, in some embodiments, the region between two adjacent first isolation trenches 50 may be avoided when the first well region 21 is ion implanted, so that under the second isolation trench 60, the two adjacent first isolation trenches 50 may have the same doping condition as the semiconductor substrate 10, that is, maintain the same intrinsic characteristic as the semiconductor substrate 10, which is also beneficial to maintaining the high-resistance characteristic of the semiconductor substrate 10, thereby reducing the substrate loss of the semiconductor device 100 and improving the linearity of the semiconductor device 100.

With continued reference to fig. 3, in this embodiment of the present application, the first isolation trench 50 may be provided with a relief structure, and the stress of the first isolation trench 50 during the processing process may be relieved by using the relief structure, so as to reduce the risk of failure of the first isolation trench 50, and further improve the yield and the reliability of use of the semiconductor device.

In a specific embodiment, the relief structure may be a partition 51, so that when the first isolation trench 50 is formed, the stress during the processing may be relieved by interrupting at the position of the partition 51, thereby reducing the risk of failure of the first isolation trench 50.

In a specific arrangement, the first isolation trench 50 may have a substantially rectangular ring structure, and the second isolation trench 60 may have a substantially rectangular ring structure, and the aspect ratio of the second isolation trench 60 is substantially equal to that of the first isolation trench 50, so that a relatively uniform isolation structure can be formed on four sides of the active region 31. It will be appreciated that, in the case of the rectangular annular first isolation groove 50, the stress concentration points of the first isolation groove 50 are mainly concentrated at four corners during the process, so that the above-mentioned partition portion 51 may be specifically disposed at the corners of the first isolation groove 50 in order to relieve the stress at the corners, and in this case, the partition portion 51 has a substantially L-shaped structure.

In a specific design, the four corners of the first isolation groove 50 may be a first corner 501, a second corner 502, a third corner 503 and a fourth corner 504, respectively, where the first corner 501 and the third corner 503 are diagonally disposed, and the second corner 502 and the fourth corner 504 are diagonally disposed. It should be noted that, in the plurality of first isolation trenches 50 according to the embodiment of the present application, the first corners 501 of each first isolation trench 50 are respectively aligned, or it is understood that the first corners 501 of each first isolation trench 50 are respectively corners pointing in the same direction, and the second corners 502, the third corners 503 and the fourth corners 504 are not described here again.

In a specific embodiment, at least one corner of the first isolation groove 50 may be provided with the above-described partition 51, for example, in the embodiment shown in fig. 3, the outermost first isolation groove 50 may be provided with the partition 51 at the first corner 501. At this time, the partition portion 51 of the first isolation groove 50 adjacent to the outermost first isolation groove 50 may be provided at a corner other than the first corner 501, for example, at one of the second corner 502, the third corner 503, and the fourth corner 504, or at two of the second corner 502, the third corner 503, and the fourth corner 504, or at the second corner 502, the third corner 503, and the fourth corner 504, respectively. That is, the two adjacent first isolation grooves 50 may be provided with the partition portions 51 at the corners of different orientations, so that the partition portions 51 of the two adjacent first isolation grooves 50 are offset, and thus, from the perspective of the whole isolation structure formed by the plurality of first isolation grooves 50, the offset design of the partition portions 51 of each first isolation groove 50 enables the whole isolation structure to be effectively isolated at any circumferential position, so that the stress of each first isolation groove 50 in the process can be relieved without affecting the isolation effect of the first isolation groove 50, and the yield and the reliability of the semiconductor device 100 can be improved.

Fig. 4 is a schematic view of another cross-sectional structure of the semiconductor device shown in fig. 2 at A-A. Referring to fig. 4, in this embodiment, the first isolation groove 50 may be provided with two partition portions 51, which may be provided at a pair of opposite corners of the first isolation groove 50, respectively, and in adjacent two first isolation grooves 50, two partition portions 51 of one first isolation groove 50 may be provided at a first corner 501 and a third corner 503, respectively, and two partition portions 51 of the other first isolation groove 50 may be provided at a second corner 502 and a fourth corner 504, respectively. The arrangement mode can also enable the partition parts of two adjacent first isolation grooves 50 to be staggered, so that the isolation structure formed by a plurality of first isolation grooves 50 can be effectively isolated at any circumferential position, and on the premise that the isolation effect of the first isolation grooves 50 is not affected, the stress of each first isolation groove 50 in the process is relieved, and the yield and the use reliability of the semiconductor device 100 can be improved.

Fig. 5 is a schematic view of another cross-sectional structure of the semiconductor device shown in fig. 2 at A-A. Referring to fig. 5, in this embodiment, the relief structure may be a chamfer structure 52 disposed at a corner of the first isolation groove 50, so that two adjacent sides of the first isolation groove 50 may be connected by a bevel edge, and the angle between the bevel edge and the two adjacent sides is an obtuse angle, and compared with a right angle structure, the chamfer structure 52 may implement a gentle transition at the corner of the first isolation groove 50, so as to relieve stress of the corner of the first isolation groove 50 in the process. Illustratively, the four corners of the first isolation trench 50 may each be designed as a chamfer structure 52, which may further relieve the stress of the first isolation trench 50 during processing, reducing the risk of failure of the first isolation trench 50.

Fig. 6 is a schematic view of another cross-sectional structure of the semiconductor device shown in fig. 2 at A-A. Referring to fig. 6, in this embodiment, the relief structure may be a rounded structure 53 disposed at a corner of the first isolation groove 50, and the design may enable two adjacent sides of the first isolation groove 50 to be connected by an arc, so that a smooth transition may be implemented at the corner of the first isolation groove 50, and stress of the corner of the first isolation groove 50 in the process may be relieved. Similarly, the four corners of the first isolation trench 50 may each be designed with rounded structures 53, thereby further relieving the stress of the first isolation trench 50 during processing and reducing the risk of failure of the first isolation trench 50.

Fig. 7 is a flowchart of a method of fabricating the semiconductor device shown in fig. 2. Referring to fig. 2 and 7 together, the method for manufacturing the semiconductor device 100 according to the embodiment of the present application includes the following steps:

step 101, a semiconductor substrate 10 is formed. The semiconductor substrate 10 may be a silicon substrate in particular, and the semiconductor substrate 10 may be doped with a first type impurity.

Step 102, an epitaxial layer 20 is formed over a semiconductor substrate 10. The epitaxial layer 20 may be doped with a first type of impurity or a second type of impurity, which is not limited in this application.

Step 103, etching the side of the epitaxial layer 20 facing away from the semiconductor substrate 10 by a mask patterning process to form a ring-shaped first isolation trench 50, and sequentially filling silicon dioxide and polysilicon in the first isolation trench 50. The depth of the first isolation trench 50 may be greater than the thickness of the epitaxial layer 20. In addition, the number of the first isolation grooves 50 may be plural, and the plurality of first isolation grooves 50 may be arranged in a radial shape.

Step 104, etching the side of the epitaxial layer 20 facing away from the semiconductor substrate 10 by a mask patterning process to form a ring-shaped second isolation trench 60, and filling silicon dioxide into the second isolation trench 60. The inner side of the first isolation trench 50 is the active region 31 of the semiconductor device 100. In a specific arrangement, the depth of the second isolation trench 60 is smaller than the depth of the first isolation trench 50, and the second isolation trench 60 may coincide with an end of the first isolation trench 50 facing away from the semiconductor substrate 10. In addition, the depth of the first isolation trench 50 may be greater than the thickness of the epitaxial layer 20, so that formation of a low-resistance leakage path due to the presence of the epitaxial layer 20 material under the second isolation trench 50 may be avoided, thereby more effectively maintaining the advantages of the high-resistance semiconductor substrate 10, reducing the substrate loss of the semiconductor device 100, and improving the linearity of the semiconductor device 100.

In step 105, ion implantation is performed on the side of the epitaxial layer 20 facing away from the semiconductor substrate 10 by a mask patterning process to form a first well region 21 doped with a first type impurity. It should be noted that, when the ion implantation is performed, the regions where the first isolation trenches 50 and the second isolation trenches 60 are located may be avoided, so that under the second isolation trenches 60, two adjacent first isolation trenches 50 may have the same doping condition as the semiconductor substrate 10, that is, the same intrinsic characteristics as the semiconductor substrate 10 are maintained, and this design is also beneficial to maintain the high-resistance characteristics of the semiconductor substrate 10. In addition, the depth of the first well region 21 may be greater than the thickness of the epitaxial layer 20 and less than the depth of the first isolation trench 50, so that the bottom of the first isolation trench 50 may extend into the semiconductor substrate 10, which is advantageous in maintaining the high-resistance characteristics of the semiconductor substrate 10, thereby reducing the substrate loss of the semiconductor device 100, and improving the linearity of the semiconductor device 100.

Step 106, forming a first insulating layer 34 through a mask patterning process over the active region 31, and forming a gate electrode 35 through a mask patterning process over the first insulating layer 34. The material of the first insulating layer 34 may be silicon dioxide, and the material of the gate 35 may be polysilicon.

Step 107, forming a first sidewall 36 on the periphery of the gate 35. The first side wall 36 may be made of silicon dioxide, or may have a lower portion made of silicon dioxide and an upper portion made of silicon nitride.

Step 108, performing ion implantation in the active region 31 through a mask patterning process to form a source diffusion region 32 and a drain diffusion region 33 doped with a second type impurity, wherein the source diffusion region 32 and the drain diffusion region 33 are respectively located at two sides of the first insulating layer.

Fig. 8 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application. Referring to fig. 8, the semiconductor device provided in this embodiment may be a SiGe BiCMOS device, and the semiconductor device may also include a semiconductor substrate 10 and an epitaxial layer 20 disposed on the semiconductor substrate 10. On the epitaxial layer 20, one or more SiGe HBTs may be formed in addition to MOS transistors. The specific structures of the semiconductor substrate 10, the epitaxial layer 20 and the MOS transistor may refer to the arrangement manner of the foregoing embodiments, and will not be described herein again.

In the region avoiding the MOS transistor, the collector 71 of the SiGe HBT may be formed in the epitaxial layer 20 by an ion implantation process, and the second type impurity may be doped in the collector 71, and the formed collector 71 is an N type collector, taking the second type impurity as an example. In this embodiment, the epitaxial layer 20 can reduce the resistance of the collector 71, thereby improving the dc characteristics and the rf characteristics of the HBT device.

A SiGe base region 72 is provided above the epitaxial layer 20, the SiGe base region 72 being located between the two collectors 71. An emitter 73 and a base 74 are arranged above the SiGe base 72, the emitter 73 is arranged between the two bases 74, the left and right sides of the emitter 73 can extend to above the two bases 74, and a second insulating layer 75 is arranged between the emitter 73 and the bases 74. In addition, a second sidewall 76 may be disposed on the periphery of the emitter 73, and the second sidewall 76 may isolate the emitter 73 from the base 74 and the collector 71; similarly, a third sidewall 77 may be disposed on the peripheral side of the base 74, and the third sidewall 77 may isolate the base 74 from the collector 71. For example, in the embodiment of the present application, the emitter 73 and the base 74 may be made of polysilicon, the second insulating layer 75 may be made of silicon dioxide, the second side wall 76 and the third side wall 77 may be made of silicon dioxide, or the second side wall 76 and the third side wall 77 may be made of silicon dioxide at the lower portion and silicon nitride at the upper portion.

It should be noted that, an N-type buried layer 78 may be further disposed below the epitaxial layer 20, and the collectors 71 on both sides may be electrically connected to the N-type buried layer respectively, so as to reduce the series resistance of the collectors 71 and provide a low-resistance current path for the collectors 71.

In addition, in the embodiment of the present application, the periphery of the collector 71 may further be provided with an annular third isolation groove 80, and when specifically arranged, from the bottom of the third isolation groove 80 to the direction of the notch, silicon dioxide and polysilicon may be sequentially filled in the third isolation groove 80, that is, one end, close to the bottom, of the third isolation groove 80 is filled with silicon dioxide, and one end, close to the notch, is filled with polysilicon. The third isolation trench 80 can reduce electrical interference between the HBT and surrounding devices and improve the operational reliability of the HBT.

In the embodiment, the MOS transistor and the HBT are integrated on the same chip, and the advantage of the high-resistance semiconductor substrate 10 is effectively maintained, the substrate loss of the semiconductor device 100 is reduced, and the linearity of the semiconductor device 100 is improved by controlling the depths of the first isolation trench 50 and the second isolation trench 60 at the periphery of the MOS transistor. In addition, by isolating or optimizing the corner of the first isolation trench 50, the stress of each first isolation trench 50 in the process of processing can be effectively relieved on the premise of not affecting the isolation effect of the first isolation trench 50, and thus the yield and the use reliability of the semiconductor device 100 can be improved.

Referring to fig. 9, the embodiment of the present application further provides a package structure, which may include a substrate 200, a lead 300, and the semiconductor device 100 in any of the foregoing possible embodiments, where the semiconductor device 100 may be disposed on one surface of the substrate 200, the lead 300 is disposed on the surface of the substrate 200 on the same side as the semiconductor device 100, and the lead 300 is disposed around the semiconductor device 100, and one end of the lead 300 is electrically connected to the semiconductor device 100. In some embodiments, the semiconductor device 100 may be a MOS transistor or a SiGe BiCMOS device in particular. The semiconductor substrate of the semiconductor device can maintain high resistance characteristics, so that substrate loss of the semiconductor device can be reduced and linearity of the semiconductor device can be improved. In addition, the structure of the first isolation groove of the semiconductor device is improved, so that the stress of the first isolation groove in the technical processing process is effectively relieved, the yield and the use reliability of the semiconductor device can be improved, and the reliability of the packaging structure can be improved.

The embodiment of the application also provides electronic equipment which can be communication equipment, a server, a super computer or equipment such as a router, a switch and the like in the prior art. The electronic device may include a circuit board and the package structure in the foregoing embodiment, where the package structure may be fixed on the circuit board by means of soldering or the like, and a signal pin may be disposed on a region of the circuit board that avoids the package structure, and the signal pin may be electrically connected to the other end of the lead, so that the package structure may be connected to other devices through a trace on the circuit board, and further, connection between the semiconductor device and an external circuit is achieved. The semiconductor device has the advantages of low loss, high linearity and the like, and the yield and the use reliability of the semiconductor device are high, so that the performance stability of the electronic equipment is improved.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

The semiconductor device is characterized by comprising a semiconductor substrate, wherein a first well region doped with first-type impurities is arranged above the semiconductor substrate, a source diffusion region and a drain diffusion region doped with second-type impurities are arranged in the first well region, a first insulating layer positioned between the source diffusion region and the drain diffusion region is arranged above the first well region, and a grid is arranged above the first insulating layer;

the semiconductor device further comprises a first isolation groove, wherein the first isolation groove is arranged in the first well region, and a relieving structure for relieving stress is arranged on the first isolation groove.
The semiconductor device of claim 1, wherein the first isolation trench is a ring-shaped structure, the source diffusion region and the drain diffusion region being located within a ring-shaped region defined by the first isolation trench.
The semiconductor device according to claim 2, wherein the number of the first isolation grooves is plural, and the plural first isolation grooves are sequentially spaced apart in a direction away from the gate electrode.
The semiconductor device according to claim 2 or 3, wherein the first isolation trench is a rectangular ring structure, and the relief structure is a chamfer structure provided at each corner of the first isolation trench.
The semiconductor device according to claim 2 or 3, wherein the first isolation trench is a rectangular ring structure, and the relief structure is a rounded corner structure provided at each corner of the first isolation trench.
The semiconductor device according to claim 2 or 3, wherein the relief structure is a partition.
The semiconductor device according to claim 6, wherein the first isolation trench has a rectangular ring structure, and the plurality of first isolation trenches respectively include a first corner portion, a second corner portion, a third corner portion, and a fourth corner portion, the first corner portion being disposed diagonally to the third corner portion, and the second corner portion being disposed diagonally to the fourth corner portion;

at least one corner of the first isolation groove is provided with the partition portion.
The semiconductor device according to claim 7, wherein when the number of the first isolation grooves is plural, the partition portion is provided in a first corner portion of one of the adjacent two first isolation grooves, and the partition portion is provided in at least one corner portion of a second corner portion, a third corner portion, and a fourth corner portion of the other one of the first isolation grooves.
The semiconductor device according to claim 7, wherein when the number of the first isolation grooves is plural, the first corner portion and the third corner portion of one of the adjacent two first isolation grooves are provided with the partition portion, respectively, and the second corner portion and the fourth corner portion of the other one of the first isolation grooves are provided with the partition portion, respectively.
The semiconductor device according to any one of claims 1 to 9, wherein a depth of the first isolation trench is greater than a depth of the first well region.
The semiconductor device according to claim 10, wherein a depth of the first isolation trench is 4 to 6um.
The semiconductor device according to any one of claims 1 to 11, wherein the number of the first isolation grooves is 3 to 6.
The semiconductor device according to any one of claims 1 to 12, further comprising an epitaxial layer disposed over the semiconductor substrate, the first well region being disposed over the epitaxial layer.
The semiconductor device of claim 13, further comprising a second isolation trench disposed in the first well region, the second isolation trench having a depth greater than a thickness of the epitaxial layer.
The semiconductor device of claim 14, wherein the second isolation trench is a ring-shaped structure, the source diffusion region and the drain diffusion region being located within a ring-shaped region defined by the second isolation trench.
The semiconductor device according to claim 14 or 15, wherein the second isolation trench coincides with an end of the first isolation trench facing away from the semiconductor substrate.
The semiconductor device according to any one of claims 14 to 16, wherein when the number of the first isolation grooves is plural, a material between two adjacent first isolation grooves has the same intrinsic characteristics as the semiconductor substrate at a side where a bottom of the second isolation groove faces the semiconductor substrate.
The semiconductor device according to any one of claims 14 to 17, wherein an edge of the first well region is provided with a guard ring, the guard ring is internally doped with the first type impurity, and the guard ring is grounded or set to a power supply;

the first isolation groove and the second isolation groove are positioned on the inner side of the protection ring.
The semiconductor device according to any one of claims 14 to 18, wherein the first isolation trench is filled with silicon dioxide and polysilicon, and the second isolation trench is filled with silicon dioxide.
The semiconductor device of any of claims 14-19, wherein the first isolation trench is a Deep Trench Isolation (DTI) structure and the second isolation trench is a Shallow Trench Isolation (STI) structure.
The semiconductor device according to any one of claims 13 to 20, wherein a base region of a silicon germanium alloy heterojunction bipolar transistor (SiGe HBT) is provided above the epitaxial layer, and collector electrodes doped with the second type impurity are provided in the epitaxial layer, and the collector electrodes are respectively provided on both sides of the base region;

an emitter and a base are arranged above the base region, the base is arranged on two sides of the emitter, and a second insulating layer is arranged between the base and the emitter.
The semiconductor device according to claim 21, wherein an annular third isolation trench is provided at a periphery of the collector, and the third isolation trench is filled with silicon dioxide and polysilicon.
The semiconductor device according to any one of claims 1 to 22, wherein the first type impurity is a P-type impurity, and the second type impurity is an N-type impurity;

alternatively, the first type impurity is an N type impurity, and the second type impurity is a P type impurity.
A package structure comprising a substrate and the semiconductor device according to any one of claims 1 to 23, wherein:

the semiconductor device is disposed on the substrate.
An electronic device comprising a circuit board and the package structure of claim 24, wherein the package structure is disposed on the circuit board.