CN117579187A - On-chip high-speed low-loss multichannel signal wiring and shielding mode - Google Patents

On-chip high-speed low-loss multichannel signal wiring and shielding mode Download PDF

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Publication number
CN117579187A
CN117579187A CN202311432415.1A CN202311432415A CN117579187A CN 117579187 A CN117579187 A CN 117579187A CN 202311432415 A CN202311432415 A CN 202311432415A CN 117579187 A CN117579187 A CN 117579187A
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shaped
signal
metal
loss
signal wiring
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闫娜
许灏
田野辰
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Fudan University
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Fudan University
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention belongs to the technical field of microelectronics, and particularly relates to a high-speed low-loss multichannel signal wiring and shielding mode on a chip. The signal wiring and shielding mode comprises a secondary top metal Y-shaped signal wiring and a low-level metal shielding layer; the Y-shaped tree-shaped signal wiring is used for realizing broadband low-loss radio frequency signal transmission and ensuring signal symmetry among multiple channels; the low-layer metal shielding layers are symmetrically arranged at two sides of the Y-shaped tree-shaped signal wiring so as to shield crosstalk of other on-chip radio frequency signals; the Y-shaped tree-shaped signal wiring is of a differential structure, the secondary top metal is used as a main body wiring, the top metal is used as a jumper wire, and the minimum parasitic resistance and capacitance are ensured; an obtuse angle mode with a Y-shaped structure is adopted every two times so as to ensure that the characteristic impedance of each transmission line is unchanged; the invention can improve the symmetry of signal transmission between channels, reduce the signal transmission loss and effectively shield noise and ripple coupling introduced by other circuit modules.

Description

On-chip high-speed low-loss multichannel signal wiring and shielding mode
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a high-speed low-loss multichannel signal wiring and shielding mode on a chip.
Background
The rapid development of 5G technology has led human beings to enter the 'everything interconnection' era, and the high-speed and low-delay data transmission network greatly facilitates the life of people and improves the working efficiency, and simultaneously promotes the rapid development of the wired communication fields such as 5G base stations, data centers and the like. In the development of the wired communication field, the fastest technology module is the Serdes system.
Serdes is an English abbreviation for Serializer (Serializer) and Deserializer (Deserializer), and is used in the field of optical fiber communication at the earliest, and is now mostly used for a physical layer interface for serial data communication. The Serdes system utilizes low-voltage differential signals to transmit, can support high-broadband long-distance transmission, has the characteristics of point-to-point communication and time multiplexing, and has become a mainstream high-speed serial transmission technology in the field of wired communication. The Serdes system, which enables faster sample rates and transfer rates and higher energy efficiency ratios, is a popular research direction worldwide in the field of integrated circuit design.
The solid state technology association (Solid State Technology Association, JEDEC) has specified a range of high speed serial interface protocols by means of the Serdes technology. A complete Serdes system comprises a reference clock, a PLL, an upper layer protocol, a coder/decoder, a Transmitter (TX), a channel, a Receiver (RX) and the like. The core technology of the receiving end (RX) generally adopts a multi-channel Time-Interleaved analog-to-digital converter (Time-Interleaved ADC) architecture or a multi-channel decision feedback equalizer (Decision Feedback Equalizer, DFE) architecture, and the common point of both architectures is that an ultra-wideband, symmetrical, low-loss multi-channel front-end circuit is required. Any mismatch between channels can lead to errors in data transmission, and high loss on-chip traces can directly affect the energy efficiency ratio of the chip.
The data transmission rate of the most advanced Serdes transceiver system in the world reaches 224Gb/s, and is proposed by Intel corporation in 2022 International solid-state conference (IEEE International Solid-State Circuits Conference, ISSCC) conference, and foreign head IP suppliers IBM, candence, xilinx and the like also propose Serdes interfaces with data transmission rates greater than 128Gb/s and supporting multiple transmission protocols. The Serdes technology with data transmission rates up to 64Gb/s was also proposed by national Huai corporation as early as 2019. It follows that the trend in the future of wired data transmission must be toward faster transmission rates, higher bandwidths and better energy efficiency.
The conventional multi-channel on-chip routing generally adopts a binary tree mode as shown in fig. 1 or an H-type tree mode as shown in fig. 2, and both modes can ensure that the routing distances input to each output end of the multi-channel are the same, and simultaneously reduce crosstalk among the channels. The wiring scheme of fig. 1 lacks an effective shielding scheme and ripple from other on-chip modules, such as power supplies, switches, etc., is easily coupled to the signal lines. The right angle routing in fig. 2 results in a change in the characteristic impedance of the transmission line due to an increase in the line width of the transmission line at the corners, and the signal loss is not negligible when the on-chip routing distance is long because of the large number of channels.
Aiming at the problems, the invention provides a high-speed low-loss multichannel signal wiring and shielding mode on a chip. The invention uses Y-shaped tree wire to ensure the consistency of characteristic impedance of transmission line and symmetry among multiple channels, and uses low-layer metal as shielding layer at two sides of differential wire to shield noise coupling from other circuit modules. Through verification, the broadband low-loss multichannel radio frequency signal transmission can be well realized.
Disclosure of Invention
The invention aims to provide a signal wiring and shielding mode of a high-speed low-loss multichannel on a chip, so as to solve the problem that errors such as error codes occur in high-speed data transmission caused by mismatch among the multichannel and influence of crosstalk of other radio frequency signals on the transmission of the radio frequency signals during the transmission of broadband radio frequency signals in the chip.
The invention provides an on-chip high-speed low-loss multichannel signal wiring and shielding mode, which comprises a Y-shaped tree-shaped signal wiring 100 and a low-layer metal shielding layer 110; wherein:
the Y-tree signal trace 100 is used for implementing broadband low-loss radio frequency signal transmission, and guaranteeing signal symmetry among multiple channels; the lower metal shielding layers 110 are symmetrically disposed on both sides of the Y-tree signal trace 100 to shield crosstalk of other on-chip rf signals.
The Y-tree signal trace 100 is of a differential structure, adopts a secondary top metal as a main trace, and adopts a top metal as a jumper wire, so that the minimum parasitic resistance and capacitance are ensured; the Y-shaped structure obtuse angle mode is adopted every time in two times, so that the characteristic impedance of each transmission line is unchanged, the differential wiring is symmetrical, the number of through holes is kept consistent, and the same loss caused by metal wires between channels is ensured.
Furthermore, the Y-shaped tree-shaped signal wiring (100) selects a specific secondary top metal to realize the transmission of high-frequency signals in a Y-shaped binary mode, and the combination of the selected wire width, wire spacing and wire length ensures that the characteristic impedance of the transmission line is kept unchanged under different frequencies and realizes the optimization of broadband signal transmission loss.
The lower metal shielding layer 110 is a metal lower than the metal of the Y-tree signal trace 100, and multiple layers of lower metals are connected by vias, and metal shielding layers are formed on two layers of the signal trace, so that coupling of ripple waves, radio frequency signals and clock signals from a power supply, a switch and the ground can be shielded.
Further, the Y-tree signal trace 100 and the low-level metal shielding layer 110 are shown as signal link traces applied to on-chip differential-to-4 channels, and similar methods can be extended to differential-to-8, 16 or more channels, and the trace mode is unchanged.
Further, the Y-tree signal trace 100 and the low-level metal shielding layer 110 may be fabricated in a CMOS process, a BiCMOS process, a GeSi process, or a GaAs process, including but not limited to the listed processes, as well as other processes. The metal layer is ensured to be the metal given by a process manufacturer under the process node. In addition, the method is not only applied to the chip, but also is applicable to board-level signal wiring of various materials, and wiring and shielding modes are unchanged.
The invention ensures the consistency of characteristic impedance of the transmission line and the symmetry among multiple channels by utilizing the Y-shaped sub-top metal tree-shaped wiring, and simultaneously uses low-layer metal connected by the through holes at two sides of the differential wiring as a signal shielding layer so as to shield the coupling of signals from other circuit modules and ripple waves, thereby realizing the broadband low-loss multi-channel radio frequency signal transmission.
Compared with the prior art, the invention has the remarkable advantages that:
if the routing scheme lacks an effective shielding scheme, ripple from other modules on the chip, such as power supplies, switches, etc., can easily be coupled to the signal lines to affect the quality of the signal transmission. Meanwhile, the characteristic impedance of the long-distance transmission line on the chip is changed due to the excessive right-angle wiring mode, so that loss of the transmission signal and unbalance among channels are deteriorated. The high-speed low-loss multichannel signal wiring mode on the chip can ensure low loss and symmetry of multichannel signals, and the low-layer metal shielding layer can effectively shield noise and ripple coupling introduced by other circuit modules.
Drawings
FIG. 1 shows an on-chip H-tree metal routing scheme.
FIG. 2 is an on-chip binary tree metal routing scheme.
Fig. 3 is a top view of the high-speed low-loss multi-channel signal trace and shielding on a chip.
Fig. 4 is a 3D diagram of on-chip high-speed low-loss multi-channel signal routing and shielding. Wherein, the double lines represent the top metal, the thick ink lines represent the sub-top metal, and the three lines represent the low metal.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a high-speed low-loss multichannel signal wiring and shielding mode on a chip. The invention uses Y-shaped tree wire to ensure the consistency of characteristic impedance of transmission line and symmetry among multiple channels, and uses low-layer metal as shielding layer at two sides of differential wire to shield noise coupling from other circuit modules.
As shown in fig. 3, the signal routing and shielding method of the on-chip high-speed low-loss multi-channel of the present invention includes a Y-type tree-shaped signal routing 100 and a low-layer metal shielding layer 110, and the differential Y-type tree-shaped signal routing 100 is used for implementing wideband low-loss radio frequency signal transmission, while guaranteeing signal symmetry between the multi-channels. The lower metal shielding layers 110 are symmetrically placed on both sides of the Y-shaped tree-shaped signal trace 100 to shield cross-talk of other on-chip radio frequency signals.
Therefore, the characteristic impedance of each transmission line is unchanged by a novel Y-shaped tree-shaped signal wiring mode, the differential wiring is symmetrical, and the number of the through holes is consistent so as to ensure that the loss among channels due to the metal wires is the same. Meanwhile, the proper combination of the width, the spacing and the length of the metal wires is selected, and the loss and the symmetry of the transmission signals are optimized on the basis of not increasing the layout area of the wiring layout.
Fig. 4 shows an example of a specific implementation of the signal routing and shielding method based on the on-chip high-speed low-loss multi-channel of the present invention, which is a front-end routing of a high-speed analog-to-digital converter applied in a high-speed wired data transmission Serdes system. The front-end trace is a Y-tree signal trace 100. The core module is mainly realized by two layers of metal of a top layer metal and a secondary top layer metal and a via hole, wherein the metal square resistivity of the secondary top layer metal is 0.0051 omega/mu m 2 The metal sheet resistivity of the top layer metal was 0.011 Ω/μm 2 . The width of the differential metal traces was 5 μm and the inter-trace spacing was 10 μm, with a distance from the input to any of the output ports of approximately 518 μm. The overall transmission line wiring height and the length of the signal line are determined by the position of the subsequent stage circuit. Since the transmission line back end can be regarded as an open circuit high impedance, its characteristic impedance does not need to be specially matched to 50Ω. The wiring length and the number of the through holes of each passage are kept consistent so as to realizeSymmetry between the channels is now present.
Wherein the metal shielding layer is a low-level metal shielding layer 110. The metal shielding layer adopts the same metal width (5 μm) and pitch (10 μm) as the signal wiring, and uses the method of overlapping and punching via holes by using low-layer metal, wherein the square resistivity of the low-layer metal is 0.45 Ω/μm 2 . The metal layers are overlapped and connected layer by layer so as to realize the function of a shielding layer. In addition to the outer sides of the Y-tree signal traces 100, the traces of the rear output section are also added with metal shielding according to the trace profile.
The working flow of the signal wiring and shielding mode circuit of the whole on-chip high-speed low-loss multichannel is as follows:
as shown in fig. 4, the rf signal enters the differential input terminal, passes through the Y-tree signal trace 100, and is transmitted to the output terminal. There is an inherent loss on the transmission path due to the parasitics of the transmission lines, but the attenuation loss of each channel signal is almost uniform, so that the aim of inputting differential signals into multiple channels symmetrically at the same time is fulfilled. In the process of signal input, most of a series of non-ideal signals such as noise generated by ripple waves occurring on a power supply, ripple waves occurring on the ground of a chip, continuous opening and closing of a clock circuit switch are shielded or absorbed by the low-layer metal shielding layer 110, and finally released to the ground of the chip, and cannot be coupled into an input signal wire, so that the quality of the input signal is ensured, and the fluctuation and error rate of radio frequency signals are reduced.
In summary, the signal routing and shielding mode based on the on-chip high-speed low-loss multichannel provided by the invention solves the problems of poor symmetry, poor signal transmission quality and high signal transmission loss of multichannel signals caused by the unstable characteristic impedance of the transmission line and more on-chip crosstalk signals in the traditional chip radio frequency front-end wiring, and realizes the signal routing method applied to multichannel of broadband high-speed low-loss on a single chip. The invention can change the overall height and length according to the layout size of the post-stage analog-to-digital converter, and realizes the multichannel signal transmission with high symmetry and low loss and the effective shielding of on-chip crosstalk signals on the basis of not increasing the chip area. The multi-channel wiring requirement on the wired data transmission high-speed interface chip is met.
Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.

Claims (3)

1. An on-chip high-speed low-loss multi-channel signal trace and shield mode, comprising: a Y-shaped tree-shaped signal wiring (100) and a lower metal shielding layer (110); wherein:
the Y-shaped tree-shaped signal wiring (100) is used for realizing broadband low-loss radio frequency signal transmission and ensuring signal symmetry among multiple channels; the low-layer metal shielding layers (110) are symmetrically arranged at two sides of the Y-shaped tree-shaped signal wiring (100) so as to shield crosstalk of other on-chip radio frequency signals;
the Y-shaped tree-shaped signal wiring (100) is of a differential structure, adopts secondary top metal as a main body wiring, and adopts top metal as a jumper wire, so that the minimum parasitic resistance and capacitance are ensured; an obtuse angle mode of a Y-shaped structure is adopted every two times so as to ensure that the characteristic impedance of each transmission line is unchanged, and the differential wiring ensures symmetry and the number of the through holes is kept consistent so as to ensure that the losses among channels due to the metal wires are the same;
the lower metal shielding layer (110) is a metal lower than the metal of the Y-shaped tree-shaped signal wiring (100), multiple layers of lower metals are connected by a via, and metal shielding layers are formed on two layers of the signal wiring to shield the coupling of ripples, radio frequency signals and clock signals from a power supply, a switch and the ground.
2. The on-chip high-speed low-loss multi-channel-oriented signal routing and shielding mode according to claim 1, wherein the Y-shaped tree-shaped signal routing (100) selects a specific sub-top metal to realize the transmission of high-frequency signals in a Y-shaped binary manner, and the combination of the selected wire width, wire spacing and wire length ensures that the characteristic impedance of the transmission line is kept unchanged at different frequencies and optimizes the broadband signal transmission loss.
3. The on-chip high-speed low-loss multi-channel-oriented signal trace and shielding mode of claim 1, wherein said Y-tree signal trace (100) and low-level metal shielding layer (110) are both implemented on-chip.
CN202311432415.1A 2023-10-31 2023-10-31 On-chip high-speed low-loss multichannel signal wiring and shielding mode Pending CN117579187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311432415.1A CN117579187A (en) 2023-10-31 2023-10-31 On-chip high-speed low-loss multichannel signal wiring and shielding mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311432415.1A CN117579187A (en) 2023-10-31 2023-10-31 On-chip high-speed low-loss multichannel signal wiring and shielding mode

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CN117579187A true CN117579187A (en) 2024-02-20

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