CN117578358A - Intelligent power module of dual-drive IC - Google Patents
Intelligent power module of dual-drive IC Download PDFInfo
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- CN117578358A CN117578358A CN202311557998.0A CN202311557998A CN117578358A CN 117578358 A CN117578358 A CN 117578358A CN 202311557998 A CN202311557998 A CN 202311557998A CN 117578358 A CN117578358 A CN 117578358A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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Abstract
The invention relates to the technical field of semiconductor power devices, in particular to an intelligent power module with double drive ICs, wherein a first drive IC comprises a first fault judging module and a second drive IC comprises a second fault judging module; the fault enabling end of the first fault judging module is electrically connected with the fault enabling end of the second fault judging module; when the protection signal of the fault judging module received by the second fault judging module is in a low level, the generated enabling signal is in a low level, and a turn-off signal is output, so that the output signal of the lower bridge front side processing module stops transmitting to the lower bridge rear side processing module; when the enabling signal received by the first fault judging module is at a low level or when the bootstrap voltage of the upper bridge rear side processing module is lower than a preset voltage, the output signal of the upper bridge front side processing module stops transmitting to the upper bridge rear side processing module; therefore, the first driving IC and the second driving IC synchronously realize linkage protection, and the reliability and the safety of the intelligent power module are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to an intelligent power module with double drive ICs.
Background
The smart power module, IPM (Intelligent Power Module), is a power driven product that combines power electronics and integrated circuit technology. The intelligent power module integrates the power switch device and the high-voltage driving circuit and is internally provided with fault detection circuits such as overvoltage, overcurrent, overheat and the like. The intelligent power module receives the control signal of the MCU on one hand, drives the subsequent circuit to work, and sends the state detection signal of the system back to the MCU on the other hand. Compared with the traditional discrete scheme, the intelligent power module gains larger and larger markets by virtue of the advantages of high integration level, high reliability and the like, is particularly suitable for a frequency converter of a driving motor and various inverter power supplies, and is an ideal power electronic device for frequency conversion speed regulation, metallurgical machinery, electric traction, servo driving and frequency conversion household appliances.
In the current intelligent power module adopting the double drive ICs, the three-phase lower bridge drive ICs are generally provided with overcurrent protection, undervoltage power protection and overtemperature protection, while the three-phase upper bridge drive ICs are not provided with overcurrent protection, undervoltage power protection and overtemperature protection; therefore, when the intelligent power module triggers over-current protection, under-voltage protection and over-temperature protection, the intelligent power module can only ensure that the driving signals of the three-phase lower bridge driving ICs are turned off and output fault signals, and after the external control system receives the fault signals, the external control system turns off the driving signals of the three-phase upper bridge driving ICs, so that the intelligent power module is protected from being damaged.
However, the three-phase upper bridge driving IC is protected in an untimely manner, and the three-phase upper bridge driving IC is connected with a higher power supply voltage and outputs a stronger driving signal, so that when overcurrent, undervoltage power supply and overtemperature faults occur, the three-phase upper bridge driving IC is easier and faster to burn out than the three-phase lower bridge driving IC, and the untimely protection condition can lead the intelligent power module to burn out from the three-phase upper bridge driving IC and then spread to the whole intelligent power module to burn out, so that all protection measures of the three-phase lower bridge driving IC are not significant.
Disclosure of Invention
Aiming at the defects, the invention aims to provide an intelligent power module with double drive ICs, wherein the first drive IC and the second drive IC synchronously realize linkage protection, so that the reliability and the safety of the intelligent power module are further improved.
To achieve the purpose, the invention adopts the following technical scheme:
an intelligent power module with double drive ICs comprises a first drive IC and a second drive IC; the first driving IC comprises an upper bridge front side processing module and an upper bridge rear side processing module, and the second driving IC comprises a lower bridge front side processing module, a lower bridge rear side processing module and a fault protection module; the fault enabling end of the first driving IC is electrically connected with the fault enabling end of the second driving IC;
the first driving IC further comprises a first fault judging module, a fault enabling end of the first fault judging module is used as a fault enabling end of the first driving IC, a first input end, a second input end and a third input end of the first fault judging module are respectively and electrically connected with an output end of the upper bridge front side processing module of the U, V, W phase, a first output end, a second output end and a third output end of the first fault judging module are respectively and electrically connected with an input end of the upper bridge rear side processing module of the U, V, W phase, and a first detection end, a second detection end and a third detection end of the first fault judging module are respectively and electrically connected with a bootstrap output end of the upper bridge rear side processing module of the U, V, W phase;
the second driving IC further includes a second fault judging module, a fault enabling end of the second fault judging module is used as a fault enabling end of the first driving IC, a protecting end of the second fault judging module is used as a VFO end of the first driving IC, a first input end, a second input end and a third input end of the second fault judging module are respectively and electrically connected with an output end of the lower bridge front side processing module of U, V, W phase, a first output end, a second output end and a third output end of the second fault judging module are respectively and electrically connected with an input end of the lower bridge rear side processing module of U, V, W phase, and a plurality of detecting ends of the second fault judging module are respectively and electrically connected with output ends of the fault protecting modules;
the fault judging module is used for generating a protection signal;
the second fault judging module is used for receiving the protection signal to generate an enabling signal and a switching-off signal; when the protection signal is at a low level, the enable signal is at a low level and the turn-off signal is output;
the second fault judging module is further configured to receive an output signal of the lower bridge front side processing module and transmit the output signal to the lower bridge rear side processing module, and stop transmitting when the enable signal is at a low level;
the upper bridge rear side processing module is used for generating bootstrap voltage;
the first fault judging module is used for receiving an output signal of the upper bridge front side processing module and transmitting the output signal to the upper bridge rear side processing module; and stopping transmitting the output signal of the upper bridge front side processing module when the enabling signal received by the first fault judging module is in a low level or when the bootstrap voltage is lower than a preset voltage which is internally set.
Further, the first fault judging module comprises an enabling signal processing unit, a first fault judging unit, an upper bridge single-phase control unit and an under-voltage protection unit; the input end of the enabling signal processing unit is used as a fault enabling end of the first fault judging module, the input end of the upper bridge single-phase control unit is used as a first, second or third input end of the first fault judging module, the output end of the upper bridge single-phase control unit is used as a first, second or third output end of the first fault judging module, and the input end of the under-voltage protection unit is used as a first, second or third detection end of the first fault judging module;
the output end of the enabling signal processing unit is electrically connected with the first input end of the first fault judging unit, the output end of the under-voltage protection unit is electrically connected with the second, third or fourth input end of the first fault judging unit, and the control end of the upper bridge single-phase control unit is electrically connected with the output end of the first fault judging unit;
the under-voltage protection unit is used for receiving the bootstrap voltage and generating an under-voltage protection signal; when the bootstrap voltage is lower than the preset voltage, the undervoltage protection signal is at a low level;
the first fault judging unit is used for receiving the enabling signal subjected to noise removal and filtering by the enabling signal processing unit and the undervoltage protection signal, and generating an action signal; when the enabling signal or the undervoltage protection signal is at a low level, the action signal is at a low level;
the upper bridge single-phase control unit is used for receiving the output signal of the upper bridge front side processing module and transmitting the output signal to the upper bridge rear side processing module; and when the action signal received by the upper bridge single-phase control unit is at a low level, stopping transmitting the output signal of the upper bridge front side processing module.
Further, the second fault judging module comprises a second fault judging unit, a lower bridge single-phase control unit and a MOS tube Q1; the output end of the second fault judging unit is used as a fault enabling end of the second fault judging module, the input end of the second fault judging unit is used as a detection end of the second fault judging module, the drain electrode of the MOS tube Q1 is used as a protection end of the second fault judging module, the input end of the lower bridge single-phase control unit is used as a first, second or third input end of the second fault judging module, and the output end of the lower bridge single-phase control unit is used as a first, second or third output end of the second fault judging module;
the control end of the lower bridge single-phase control unit is electrically connected with the output end of the second fault judging unit, and the grid electrode of the MOS tube Q1 is electrically connected with the turn-off end of the second fault judging unit;
the second fault judging unit is used for receiving the protection signal, generating the enabling signal and the turning-off signal, and controlling the on or off of the MOS tube Q1; when the protection signal is at a low level, the enabling signal is at a low level, and the MOS tube Q1 is controlled to be conducted;
the lower bridge single-phase control unit is used for receiving an output signal of the lower bridge front side processing module and transmitting the output signal to the lower bridge rear side processing module, and stopping transmitting when the enabling signal is in a low level;
when the MOS transistor Q1 is turned on, the turn-off signal is output.
Further, the first fault judging unit includes an and gate U1, an and gate U2 and an and gate U3; the first input end of the and gate U1 is used as the first input end of the first fault judging unit, the second input end of the and gate U1 is used as the second input end of the first fault judging unit, the second input end of the and gate U2 is used as the third input end of the first fault judging unit, the second input end of the and gate U3 is used as the fourth input end of the first fault judging unit, and the output end of the and gate U3 is used as the output end of the first fault judging unit;
the output end of the and gate U1 is electrically connected to the first input end of the and gate U2, and the output end of the and gate U2 is electrically connected to the first input end of the and gate U3.
Further, the second fault judging unit comprises an and gate U4 and an not gate U5; the output end of the NOT gate U5 is used as the turn-off end of the second fault judging unit;
the number of the AND gates U4 is one less than the number of the fault protection modules; the first input end and the second input end of the foremost AND gate U4 are used as the input ends of the second fault judging unit, and the output end of the rearmost AND gate U4 is used as the output end of the second fault judging unit;
the output end of the former and gate U4 is electrically connected to the first input end of the latter and gate U4, the second input end of the latter and gate U4 is used as the input end of the second fault judging unit, and the output end of the last and gate U4 is electrically connected to the input end of the not gate U5.
Further, the under-voltage protection unit comprises a comparator CMP, a MOS tube Q2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a logic circuit; one end of the resistor R1 is used as an input end of the undervoltage protection unit, and the output end of the logic circuit is used as an output end of the undervoltage protection unit;
the other end of the resistor R1 and one end of the resistor R2 are electrically connected with the positive input end of the comparator CMP, one end of the resistor R3 is connected with a reference voltage, the other end of the resistor R3 and one end of the resistor R4 are electrically connected with the negative input end of the comparator CMP, the output end of the comparator CMP is electrically connected with the input end of the logic circuit, the other end of the resistor R4 and one end of the resistor R5 are electrically connected with the drain electrode of the MOS tube Q2, the source electrode of the MOS tube Q2, the other end of the resistor R5 and the other end of the resistor R2 are grounded, and the grid electrode of the MOS tube Q2 is electrically connected with the feedback end of the logic circuit;
the logic circuit is configured to output an output signal of the comparator CMP, and drive the MOS transistor Q2 to be turned off when the output signal of the comparator CMP is at a low level, and drive the MOS transistor Q2 to be turned on when the output signal of the comparator CMP is at a high level.
Further, the upper bridge single-phase control unit comprises an AND gate U6; the first input end of the and gate U6 is used as an input end of the upper bridge single-phase control unit, the second input end of the and gate U6 is used as a control end of the upper bridge single-phase control unit, and the output end of the and gate U6 is used as an output end of the upper bridge single-phase control unit.
Further, the lower bridge single-phase control unit comprises an AND gate U7; the first input end of the and gate U7 is used as an input end of the lower bridge single-phase control unit, the second input end of the and gate U7 is used as a control end of the lower bridge single-phase control unit, and the output end of the and gate U7 is used as an output end of the lower bridge single-phase control unit.
The technical scheme provided by the invention can comprise the following beneficial effects: the second drive IC (lower bridge) receives the protection signals generated by all the fault judging modules through the second fault judging modules to comprehensively judge the internal condition of the second drive IC, when the protection signal of any one fault judging module is low level, namely, the fault occurs in a certain part in the second drive IC, the work of the second drive IC is stopped immediately, the damage of fault diffusion and an external circuit is avoided, therefore, the signal transmission between the lower bridge front side processing module and the lower bridge rear side processing module is stopped when the enable signal is low level to realize the self turn-off of the second drive IC, the low-level enable signal is fed back to the first drive IC by the fault enabling end of the second fault judging module to inform the fault condition, and the turn-off signal is output to stop the work of all the external circuits of the intelligent power module, so that the purpose that the internal circuit and the external circuit stop working is achieved.
The first drive IC (upper bridge) determines whether the first drive IC outputs a drive signal through signal transmission between the upper bridge front side processing module and the upper bridge rear side processing module by the first fault judging module, so that the control of the first drive IC is realized, therefore, the first fault judging module receives an enable signal from the second drive IC through a fault enabling end of the first drive IC to judge whether the second drive IC has a fault, and the first detection end, the second detection end and the third detection end detect whether the bootstrap voltage generated by the upper bridge rear side processing module has an undervoltage condition, when any one of the above items has a fault, the low level is used as a judging basis, so that the second drive IC and the first drive IC synchronously realize linkage protection measures, and simultaneously the first drive IC and the second drive IC are turned off to achieve the simultaneous upper bridge and lower bridge, thereby avoiding the other bridge from being burnt down and spreading to the whole intelligent power module due to the single bridge turn-off, and further improving the reliability and safety of the intelligent power module.
Drawings
Fig. 1 is a circuit schematic of a dual-driver IC smart power module according to one embodiment of the present invention.
Fig. 2 is a circuit schematic of the first driving IC shown in fig. 1.
Fig. 3 is a circuit schematic of the second driving IC shown in fig. 1.
Fig. 4 is a circuit diagram of the first failure determination unit shown in fig. 2.
Fig. 5 is a circuit diagram of the second failure determination unit shown in fig. 3.
Fig. 6 is a circuit diagram of the under-voltage protection unit shown in fig. 2.
Fig. 7 is a circuit diagram of the upper bridge single phase control unit shown in fig. 2; or a circuit diagram of a lower bridge single phase control unit as shown in fig. 3.
Wherein: the first driving IC1, the second driving IC2, the upper bridge front side processing module 11, the upper bridge rear side processing module 12, the lower bridge front side processing module 21, the lower bridge rear side processing module 22, the second failure judgment module 23, the failure protection module 24, the enable signal processing unit 131, the first failure judgment unit 132, the upper bridge single-phase control unit 133, the under-voltage protection unit 134, the second failure judgment unit 231, the lower bridge single-phase control unit 232, the MOS transistor Q1, the and gate U2, the and gate U3, the and gate U4, the not gate U5, the comparator CMP, the MOS transistor Q2, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the logic circuit 1341, the and gate U6, and the and gate U7.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of embodiments of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In describing embodiments of the present invention, it should be noted that the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be either fixedly coupled, detachably coupled, or integrally coupled, for example, unless otherwise indicated and clearly defined; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific circumstances.
Next, an intelligent power module with dual driving ICs according to an embodiment of the present invention will be described with reference to fig. 1 to 7.
An intelligent power module with double drive ICs comprises a first drive IC1 and a second drive IC2; the first driving IC1 includes an upper bridge front side processing module 11 and an upper bridge rear side processing module 12, and the second driving IC2 includes a lower bridge front side processing module 21, a lower bridge rear side processing module 22, and a fail-safe module 24; the fail-enabling terminal of the first driving IC1 and the fail-enabling terminal of the second driving IC2 are electrically connected;
the first driving IC1 further includes a first failure determination module 13, the failure enabling terminal of the first failure determination module 13 is used as the failure enabling terminal of the first driving IC1, the first, second and third input terminals of the first failure determination module 13 are respectively electrically connected with the output terminal of the upper bridge front side processing module 11 of the U, V, W phase, the first, second and third output terminals of the first failure determination module 13 are respectively electrically connected with the input terminal of the upper bridge rear side processing module 12 of the U, V, W phase, and the first, second and third detection terminals of the first failure determination module 13 are respectively electrically connected with the bootstrap output terminal of the upper bridge rear side processing module 12 of the U, V, W phase;
the second driving IC2 further includes a second fault determining module 23, the fault enabling terminal of the second fault determining module 23 is used as the fault enabling terminal of the first driving IC1, the protecting terminal of the second fault determining module 23 is used as the VFO terminal of the first driving IC1, the first, second and third input terminals of the second fault determining module 23 are respectively electrically connected with the output terminal of the lower bridge front side processing module 21 of the U, V, W phase, the first, second and third output terminals of the second fault determining module 23 are respectively electrically connected with the input terminal of the lower bridge rear side processing module 22 of the U, V, W phase, and the plurality of detecting terminals of the second fault determining module 24 are respectively electrically connected with the output terminals of the plurality of fault protecting modules 24;
the fault judging module 24 is used for generating a protection signal;
the second fault judging module 23 is configured to receive the protection signal generation enable signal and the shutdown signal; when the protection signal is at a low level, the enable signal is at a low level and outputs a shutdown signal;
the second fault judging module 23 is further configured to receive the output signal of the lower bridge front side processing module 21 and transmit the output signal to the lower bridge rear side processing module 22, and stop transmitting when the enable signal is at a low level;
the upper bridge back side processing module 12 is used for generating bootstrap voltage;
the first fault judging module 13 is configured to receive an output signal of the upper bridge front side processing module 11 and transmit the output signal to the upper bridge rear side processing module 12; when the enable signal received by the first failure determination module 13 is at a low level, or when the bootstrap voltage is lower than the preset voltage set in, the transmission of the output signal of the upper bridge front side processing module 11 is stopped.
In the preferred embodiment of the intelligent power module with dual driving ICs according to the present invention, as shown in fig. 1 to 3, the second driving IC2 (lower bridge) receives the protection signals generated by all the fault determining modules 24 through the second fault determining module 23 to comprehensively determine the internal condition of the second driving IC2, when the protection signal of any one of the fault determining modules 24 is at a low level, that is, a fault occurs in a certain portion of the second driving IC2, the operation of the second driving IC2 should be stopped immediately, so as to avoid the fault diffusion and the damage of the external circuit, so that the enable signal is at a low level to stop the signal transmission between the lower bridge front side processing module 21 and the lower bridge rear side processing module 22 to realize the self-turn-off of the second driving IC2, and the enable signal at a low level is fed back to the first driving IC1 from the fault enabling end (enableL end in fig. 3) of the second fault determining module 23 to inform the fault condition, and output the turn-off signal to stop the operation of all the external circuits of the intelligent power module, so as to achieve the purpose that the internal and external circuits stop the operation.
The first driving IC1 (upper bridge) determines whether the first driving IC1 outputs a driving signal by controlling signal transmission between the upper bridge front side processing module 11 and the upper bridge rear side processing module 12 by the first failure judging module 13, so as to realize control of the first driving IC1, therefore, the first failure judging module 13 receives an enabling signal from the second driving IC2 by a failure enabling end (enable h end in fig. 2) of the first driving IC1 to judge whether the second driving IC2 has a failure, the first, second and third detecting ends detect whether the bootstrap voltage generated by the upper bridge rear side processing module 12 has an under-voltage condition, when any one of the above failures occurs, a low-level effective basis is adopted, so that the second driving IC2 and the first driving IC1 synchronously realize linkage protection measures, and simultaneously, the first driving IC1 and the second driving IC2 are turned off simultaneously to turn off the upper bridge and the lower bridge, thereby avoiding that the single bridge is turned off to cause the other bridge to burn and spread to the whole intelligent power module, and further improving the reliability and safety of the intelligent power module.
It should be noted that, since the fault detection and protection of the over-temperature, the over-current, and the like of the intelligent power module are all completed by the second driving IC2, the first driving module IC1 needs to know the fault condition of the second driving IC2 to know the operation condition of the whole intelligent power module; the first driving IC1 needs to set a bootstrap voltage to improve the working reliability, so that the bootstrap voltage can be automatically turned off to cut off the fault and cannot spread to the second driving IC2 when the bootstrap voltage is under-voltage, and the fault condition of the first driving IC1 does not need to be fed back to the second driving IC2.
Further, the first fault determining module 13 includes an enable signal processing unit 131, a first fault determining unit 132, an upper bridge single-phase control unit 133, and an under-voltage protection unit 134; the input end of the enable signal processing unit 131 is used as the fault enabling end of the first fault judging module 13, the input end of the upper bridge single-phase control unit 133 is used as the first, second or third input end of the first fault judging module 13, the output end of the upper bridge single-phase control unit 133 is used as the first, second or third output end of the first fault judging module 13, and the input end of the under-voltage protection unit 134 is used as the first, second or third detection end of the first fault judging module 13;
the output end of the enable signal processing unit 131 is electrically connected with the first input end of the first fault judging unit 132, the output end of the under-voltage protection unit 134 is electrically connected with the second, third or fourth input end of the first fault judging unit 132, and the control end of the upper bridge single-phase control unit 133 is electrically connected with the output end of the first fault judging unit 132;
the under-voltage protection unit 134 is configured to receive the bootstrap voltage and generate an under-voltage protection signal; when the bootstrap voltage is lower than the preset voltage, the undervoltage protection signal is at a low level;
the first fault determining unit 132 is configured to receive the enable signal after noise removal and filtering by the enable signal processing unit 131 and the under-voltage protection signal, and generate an action signal; when the enabling signal or the undervoltage protection signal is at a low level, the action signal is at a low level;
the upper bridge single-phase control unit 133 is configured to receive an output signal of the upper bridge front side processing module 11 and transmit the output signal to the upper bridge rear side processing module 12; when the action signal received by the upper bridge single-phase control unit 133 is at a low level, the transmission of the output signal of the upper bridge front side processing module 11 is stopped.
In this embodiment, as shown in fig. 2, the first fault determining module 13 obtains a stable enabling signal through the enabling signal processing unit 131, so as to avoid misjudgment; then the bootstrap voltage condition of the first driving IC1 is obtained through the undervoltage protection unit 134; then, the first fault judging unit 132 respectively carries out identification judgment on the enabling signal and the bootstrap voltage condition; finally, the upper bridge single-phase control unit 133 controls the signal transmission between the upper bridge front side processing module 11 and the upper bridge rear side processing module 12 to realize the fault protection of the first driving IC1.
Further, the second fault determining module 23 includes a second fault determining unit 231, a single-phase control unit 232 for getting off the bridge, and a MOS transistor Q1; the output end of the second fault determining unit 231 is used as the fault enabling end of the second fault determining module 23, the input end of the second fault determining unit 231 is used as the detecting end of the second fault determining module 23, the drain electrode of the MOS transistor Q1 is used as the protecting end of the second fault determining module 23, the input end of the lower bridge single-phase control unit 232 is used as the first, second or third input end of the second fault determining module 23, and the output end of the lower bridge single-phase control unit 232 is used as the first, second or third output end of the second fault determining module 23;
the control end of the lower bridge single-phase control unit 232 is electrically connected with the output end of the second fault judging unit 231, and the grid electrode of the MOS tube Q1 is electrically connected with the turn-off end of the second fault judging unit 231;
the second fault determining unit 231 is configured to receive the protection signal, generate an enable signal and a turn-off signal, and control on or off of the MOS transistor Q1; when the protection signal is at a low level, the enabling signal is at a low level, and the MOS transistor Q1 is controlled to be conducted;
the lower bridge single-phase control unit 232 is configured to receive an output signal from the lower bridge front side processing module 21 and transmit the output signal to the lower bridge rear side processing module 22, and stop transmitting when the enable signal is at a low level;
when the MOS transistor Q1 is turned on, an off signal is output.
In this embodiment, as shown in fig. 3, the second fault determining module 23 first performs comprehensive determination on the protection signals of the multiple fault determining modules 24 through the second fault determining unit 231, and then implements fault protection of the second driving IC2 through the lower bridge single-phase control unit 232 and fault protection of the external circuit of the intelligent power module through the MOS transistor Q1 respectively; therefore, the driving lower bridge single-phase control unit 232 stops the signal transmission between the lower bridge front side processing module 21 and the lower bridge rear side processing module 22 to represent the fault condition of the second driving IC2, so that the enabling signal can be fed back to the first driving IC1.
Further, the first fault determining unit 132 includes an and gate U1, an and gate U2, and an and gate U3; the first input terminal of the and gate U1 is used as the first input terminal of the first failure determination unit 132, the second input terminal of the and gate U1 is used as the second input terminal of the first failure determination unit 132, the second input terminal of the and gate U2 is used as the third input terminal of the first failure determination unit 132, the second input terminal of the and gate U3 is used as the fourth input terminal of the first failure determination unit 132, and the output terminal of the and gate U3 is used as the output terminal of the first failure determination unit 132;
the output of the and gate U1 is electrically connected to the first input of the and gate U2, and the output of the and gate U2 is electrically connected to the first input of the and gate U3.
In this embodiment, as shown in fig. 4, since the judging logic of the first fault judging module 13 is that the first driving IC1 needs to be turned off whenever any one of the fault of the second driving IC2 and the under-voltage of the single-phase bootstrap voltage occurs, the first fault judging unit 132 as the logic circuit of the first fault judging module 13 is interlocked through the output ends of the three and gates, so as to achieve the purpose that the output ends output the low level as long as the input end of any and gate inputs the low level, thereby meeting the logic judging requirement.
Further, the second fault determining unit 231 includes an and gate U4 and an not gate U5; the output terminal of the not gate U5 serves as the off terminal of the second failure determination unit 231;
the number of and gates U4 is one less than the number of fault protection modules 24; the first and second input ends of the foremost and gate U4 are used as input ends of the second fault judging unit 231, and the output end of the rearmost and gate U4 is used as an output end of the second fault judging unit 231;
the output terminal of the former and gate U4 is electrically connected to the first input terminal of the latter and gate U4, the second input terminal of the latter and gate U4 is used as the input terminal of the second failure determination unit 231, and the output terminal of the last and gate U4 is electrically connected to the input terminal of the not gate U5.
In this embodiment, as shown in fig. 5 (taking 3 fault protection modules 24 as an example), since the judgment logic of the second fault judgment module 23 is that the protection signal output by any one of the fault judgment modules 24 is at a low level (representing that the fault judgment module 24 is responsible for detecting the occurrence of a fault), the second driving IC2 needs to be turned off, so that the second fault judgment unit 231 also interlocks with the output ends of the and gates U4, so as to achieve the purpose of outputting a low level as long as the input end of any and gate U4 inputs a low level, and the logic judgment requirement is satisfied. More importantly, when there are multiple fault judging modules 24 to be comprehensively judged, one input end of the and gate U4 is interlocked with the previous and gate U4, so that except for the two input ends of the first and gate U4, each and gate U4 is added to receive the protection signals of the fault judging modules 24, only one more protection signal of the fault judging module 24 can be judged, and therefore the number of the and gates U4 is one less than that of the fault protecting modules 24, and fault judgment on all the fault protecting modules 24 is just realized. It should be noted that, if the second fault determining unit 231 determines that there is a fault, the output enable signal is valid at low level, and the on-off signal of the MOS transistor Q2 may output the required high level, so that the inverter of the enable signal is implemented by the not gate U5, and the MOS transistor Q1 is turned on.
Further, the under-voltage protection unit 134 includes a comparator CMP, a MOS transistor Q2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, and a logic circuit 1341; one end of the resistor R1 is used as an input end of the under-voltage protection unit 134, and an output end of the logic circuit 1341 is used as an output end of the under-voltage protection unit 134;
the other end of the resistor R1 and one end of the resistor R2 are electrically connected with the positive input end of the comparator CMP, one end of the resistor R3 is connected with a reference voltage, the other end of the resistor R3 and one end of the resistor R4 are electrically connected with the negative input end of the comparator CMP, the output end of the comparator CMP is electrically connected with the input end of the logic circuit 1341, the other end of the resistor R4 and one end of the resistor R5 are electrically connected with the drain electrode of the MOS tube Q2, the source electrode of the MOS tube Q2, the other end of the resistor R5 and the other end of the resistor R2 are grounded, and the grid electrode of the MOS tube Q2 is electrically connected with the feedback end of the logic circuit 1341;
the logic circuit 1341 is configured to output an output signal of the comparator CMP, and when the output signal of the comparator CMP is at a low level, the driving MOS transistor Q2 is turned off, and when the output signal of the comparator CMP is at a high level, the driving MOS transistor Q2 is turned on.
In this embodiment, because the bootstrap voltage circuit of the first driving IC1 is composed of the current-limiting resistor R1 and the diode D1, one end of the current-limiting resistor R1 is connected to the power supply VCCH, the other end is electrically connected to the anode of the diode D1, the cathode of the diode D1 is connected to the power supply VB, the bootstrap capacitor externally connected to the intelligent power module is charged through the current-limiting resistor R1 and the diode D1, and VBs floating voltage is generated at two ends of the bootstrap capacitor, so as to support the switching of OUH relative VS. With the upper bridge IGBT switch, the D1 of the diode is in reverse bias when the VS is high voltage, the VBS and the power supply VCCH are isolated, and finally the intelligent power module enters a stable working state.
Therefore, in order to ensure the voltage stability of the power supply VB, the voltage of the power supply VB should be slightly higher than the voltage required by the operation of the first driving IC1, as shown in fig. 6, taking 13V as an example, when the VB voltage (bootstrap voltage) is lower than 13V (preset voltage), the first driving IC1 stops working, the undervoltage protection signal is kept at a low level, when the VB starts rising from a low point and is higher than 13.7V, the undervoltage protection signal is kept at a high level, wherein the voltage difference of 0.7V is the conducting voltage of the MOS transistor Q2, so as to form a hysteresis effect, and when the MOS transistor Q2 is ensured to be conducted, the voltage slightly higher than the voltage required by the operation can be provided, so that the operation stability of the first driving IC1 is improved.
It should be noted that, the voltage of the point a and the voltage of the point B are obtained by means of a voltage divider circuit formed by resistors from both the VB voltage (bootstrap voltage) and the reference power supply (preset voltage), the point a voltage and the point B voltage are compared by using the comparator CMP, when the output signal of the comparator CMP is at a low level, that is, the bootstrap voltage is smaller than the preset voltage, and when the output signal of the comparator CMP is at a high level, that is, the bootstrap voltage is greater than the preset voltage, the logic circuit 1341 directly outputs the output signal of the comparator CMP to the first fault judging unit 132 for judgment, and the logic circuit 1341 processes the output signal of the comparator CMP to generate a signal capable of feeding back to drive the MOS transistor Q2 to be turned on or off; further, the method for realizing the function of the logic circuit 1341 is not limited thereto.
Further, the upper bridge single-phase control unit 133 includes an and gate U6; the first input of the and gate U6 serves as an input of the upper bridge single-phase control unit 133, the second input of the and gate U6 serves as a control of the upper bridge single-phase control unit 133, and the output of the and gate U6 serves as an output of the upper bridge single-phase control unit 133.
In this embodiment, as shown in fig. 7, in order to simply and quickly implement the signal transmission function of the upper bridge single-phase control unit 133 and be controlled by the first fault determination unit 132, the and gate U6 is used as the upper bridge single-phase control unit 133, and the circuit structure is simpler while satisfying the determination logic.
Further, the lower bridge single-phase control unit 232 includes an and gate U7; the first input of the and gate U7 is used as an input of the lower bridge single-phase control unit 232, the second input of the and gate U7 is used as a control of the lower bridge single-phase control unit 232, and the output of the and gate U7 is used as an output of the lower bridge single-phase control unit 232.
In this embodiment, the lower bridge single-phase control unit 232 and the upper bridge single-phase control unit 133 have the same principle, and as shown in fig. 7, an and gate U7 is used as the lower bridge single-phase control unit 232, so that the circuit structure is simpler while the judgment logic is satisfied.
Other constitution, etc. and operation of a dual driving IC intelligent power module according to an embodiment of the present invention are known to those skilled in the art, and will not be described in detail herein.
In the description herein, reference to the term "embodiment," "example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (8)
1. An intelligent power module with double drive ICs comprises a first drive IC and a second drive IC; the first driving IC comprises an upper bridge front side processing module and an upper bridge rear side processing module, and the second driving IC comprises a lower bridge front side processing module, a lower bridge rear side processing module and a fault protection module; the method is characterized in that: the fault enabling end of the first driving IC is electrically connected with the fault enabling end of the second driving IC;
the first driving IC further comprises a first fault judging module, a fault enabling end of the first fault judging module is used as a fault enabling end of the first driving IC, a first input end, a second input end and a third input end of the first fault judging module are respectively and electrically connected with an output end of the upper bridge front side processing module of the U, V, W phase, a first output end, a second output end and a third output end of the first fault judging module are respectively and electrically connected with an input end of the upper bridge rear side processing module of the U, V, W phase, and a first detection end, a second detection end and a third detection end of the first fault judging module are respectively and electrically connected with a bootstrap output end of the upper bridge rear side processing module of the U, V, W phase;
the second driving IC further includes a second fault judging module, a fault enabling end of the second fault judging module is used as a fault enabling end of the first driving IC, a protecting end of the second fault judging module is used as a VFO end of the first driving IC, a first input end, a second input end and a third input end of the second fault judging module are respectively and electrically connected with an output end of the lower bridge front side processing module of U, V, W phase, a first output end, a second output end and a third output end of the second fault judging module are respectively and electrically connected with an input end of the lower bridge rear side processing module of U, V, W phase, and a plurality of detecting ends of the second fault judging module are respectively and electrically connected with output ends of the fault protecting modules;
the fault judging module is used for generating a protection signal;
the second fault judging module is used for receiving the protection signal to generate an enabling signal and a switching-off signal; when the protection signal is at a low level, the enable signal is at a low level and the turn-off signal is output;
the second fault judging module is further configured to receive an output signal of the lower bridge front side processing module and transmit the output signal to the lower bridge rear side processing module, and stop transmitting when the enable signal is at a low level;
the upper bridge rear side processing module is used for generating bootstrap voltage;
the first fault judging module is used for receiving an output signal of the upper bridge front side processing module and transmitting the output signal to the upper bridge rear side processing module; and stopping transmitting the output signal of the upper bridge front side processing module when the enabling signal received by the first fault judging module is in a low level or when the bootstrap voltage is lower than a preset voltage which is internally set.
2. The dual drive IC intelligent power module of claim 1, wherein: the first fault judging module comprises an enabling signal processing unit, a first fault judging unit, an upper bridge single-phase control unit and an under-voltage protection unit; the input end of the enabling signal processing unit is used as a fault enabling end of the first fault judging module, the input end of the upper bridge single-phase control unit is used as a first, second or third input end of the first fault judging module, the output end of the upper bridge single-phase control unit is used as a first, second or third output end of the first fault judging module, and the input end of the under-voltage protection unit is used as a first, second or third detection end of the first fault judging module;
the output end of the enabling signal processing unit is electrically connected with the first input end of the first fault judging unit, the output end of the under-voltage protection unit is electrically connected with the second, third or fourth input end of the first fault judging unit, and the control end of the upper bridge single-phase control unit is electrically connected with the output end of the first fault judging unit;
the under-voltage protection unit is used for receiving the bootstrap voltage and generating an under-voltage protection signal; when the bootstrap voltage is lower than the preset voltage, the undervoltage protection signal is at a low level;
the first fault judging unit is used for receiving the enabling signal subjected to noise removal and filtering by the enabling signal processing unit and the undervoltage protection signal, and generating an action signal; when the enabling signal or the undervoltage protection signal is at a low level, the action signal is at a low level;
the upper bridge single-phase control unit is used for receiving the output signal of the upper bridge front side processing module and transmitting the output signal to the upper bridge rear side processing module; and when the action signal received by the upper bridge single-phase control unit is at a low level, stopping transmitting the output signal of the upper bridge front side processing module.
3. The dual drive IC intelligent power module of claim 1, wherein: the second fault judging module comprises a second fault judging unit, a lower bridge single-phase control unit and a MOS tube Q1; the output end of the second fault judging unit is used as a fault enabling end of the second fault judging module, the input end of the second fault judging unit is used as a detection end of the second fault judging module, the drain electrode of the MOS tube Q1 is used as a protection end of the second fault judging module, the input end of the lower bridge single-phase control unit is used as a first, second or third input end of the second fault judging module, and the output end of the lower bridge single-phase control unit is used as a first, second or third output end of the second fault judging module;
the control end of the lower bridge single-phase control unit is electrically connected with the output end of the second fault judging unit, and the grid electrode of the MOS tube Q1 is electrically connected with the turn-off end of the second fault judging unit;
the second fault judging unit is used for receiving the protection signal, generating the enabling signal and the turning-off signal, and controlling the on or off of the MOS tube Q1; when the protection signal is at a low level, the enabling signal is at a low level, and the MOS tube Q1 is controlled to be conducted;
the lower bridge single-phase control unit is used for receiving an output signal of the lower bridge front side processing module and transmitting the output signal to the lower bridge rear side processing module, and stopping transmitting when the enabling signal is in a low level;
when the MOS transistor Q1 is turned on, the turn-off signal is output.
4. The dual drive IC intelligent power module of claim 2, wherein: the first fault judging unit comprises an AND gate U1, an AND gate U2 and an AND gate U3; the first input end of the and gate U1 is used as the first input end of the first fault judging unit, the second input end of the and gate U1 is used as the second input end of the first fault judging unit, the second input end of the and gate U2 is used as the third input end of the first fault judging unit, the second input end of the and gate U3 is used as the fourth input end of the first fault judging unit, and the output end of the and gate U3 is used as the output end of the first fault judging unit;
the output end of the and gate U1 is electrically connected to the first input end of the and gate U2, and the output end of the and gate U2 is electrically connected to the first input end of the and gate U3.
5. A dual driver IC intelligent power module according to claim 3, wherein: the second fault judging unit comprises an AND gate U4 and an NOT gate U5; the output end of the NOT gate U5 is used as the turn-off end of the second fault judging unit;
the number of the AND gates U4 is one less than the number of the fault protection modules; the first input end and the second input end of the foremost AND gate U4 are used as the input ends of the second fault judging unit, and the output end of the rearmost AND gate U4 is used as the output end of the second fault judging unit;
the output end of the former and gate U4 is electrically connected to the first input end of the latter and gate U4, the second input end of the latter and gate U4 is used as the input end of the second fault judging unit, and the output end of the last and gate U4 is electrically connected to the input end of the not gate U5.
6. The dual drive IC intelligent power module of claim 2, wherein: the undervoltage protection unit comprises a comparator CMP, a MOS tube Q2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a logic circuit; one end of the resistor R1 is used as an input end of the undervoltage protection unit, and the output end of the logic circuit is used as an output end of the undervoltage protection unit;
the other end of the resistor R1 and one end of the resistor R2 are electrically connected with the positive input end of the comparator CMP, one end of the resistor R3 is connected with a reference voltage, the other end of the resistor R3 and one end of the resistor R4 are electrically connected with the negative input end of the comparator CMP, the output end of the comparator CMP is electrically connected with the input end of the logic circuit, the other end of the resistor R4 and one end of the resistor R5 are electrically connected with the drain electrode of the MOS tube Q2, the source electrode of the MOS tube Q2, the other end of the resistor R5 and the other end of the resistor R2 are grounded, and the grid electrode of the MOS tube Q2 is electrically connected with the feedback end of the logic circuit;
the logic circuit is configured to output an output signal of the comparator CMP, and drive the MOS transistor Q2 to be turned off when the output signal of the comparator CMP is at a low level, and drive the MOS transistor Q2 to be turned on when the output signal of the comparator CMP is at a high level.
7. The dual drive IC intelligent power module of claim 2, wherein: the upper bridge single-phase control unit comprises an AND gate U6; the first input end of the and gate U6 is used as an input end of the upper bridge single-phase control unit, the second input end of the and gate U6 is used as a control end of the upper bridge single-phase control unit, and the output end of the and gate U6 is used as an output end of the upper bridge single-phase control unit.
8. A dual driver IC intelligent power module according to claim 3, wherein: the lower bridge single-phase control unit comprises an AND gate U7; the first input end of the and gate U7 is used as an input end of the lower bridge single-phase control unit, the second input end of the and gate U7 is used as a control end of the lower bridge single-phase control unit, and the output end of the and gate U7 is used as an output end of the lower bridge single-phase control unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311557998.0A CN117578358A (en) | 2023-11-21 | 2023-11-21 | Intelligent power module of dual-drive IC |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311557998.0A CN117578358A (en) | 2023-11-21 | 2023-11-21 | Intelligent power module of dual-drive IC |
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