CN117577730A - InAs waveguide detection system based on SOI platform and preparation method thereof - Google Patents
InAs waveguide detection system based on SOI platform and preparation method thereof Download PDFInfo
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- 229910000673 Indium arsenide Inorganic materials 0.000 title claims abstract description 183
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 title claims abstract description 183
- 238000001514 detection method Methods 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
- H01L31/1852—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound
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- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
- H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L31/03044—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds comprising a nitride compounds, e.g. GaN
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
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- H01L31/1856—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising nitride compounds, e.g. GaN
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Abstract
The invention provides an InAs waveguide detection system based on an SOI platform and a preparation method thereof, wherein the preparation method comprises the following steps: firstly, respectively carrying out patterning treatment on the silicon surface in an SOI platform, sequentially forming a grating, an optical connection assembly and a bottom Si material layer, wherein the grating is connected with the bottom Si material layer through the optical connection assembly, secondly, epitaxially growing a Ge buffer layer on the bottom Si material layer by adopting MOCVD equipment, thirdly, sequentially growing a GaAs buffer layer and an InAs active layer on the Ge buffer layer by adopting solid molecular beam epitaxy equipment, forming an interface mismatch array between the InAs active layer and the GaAs buffer layer, and finally, forming an electrode assembly on the InAs active layer; according to the preparation method, the solid molecular beam epitaxy equipment is adopted to form the interface mismatch array between the InAs active layer and the GaAs buffer layer, so that screw dislocation formed by merging island structures of the InAs material in the early growth stage is reduced through the dislocation layer technology, the growth quality of the InAs material is improved, and the detection performance of the InAs waveguide detection system is further improved.
Description
Technical Field
The invention relates to the field of mid-infrared light communication receivers, in particular to an InAs waveguide detection system based on an SOI platform and a preparation method thereof.
Background
InAs is a group III-V compound semiconductor material with a high electron mobility to mobility ratio, low magnetoresistance effect and small temperature coefficient of resistance. The InAs forbidden band width corresponds to the wavelength of 3.34 mu m, and can be used for an optical communication receiver with the wave band of 2-3 mu m.
The mid-infrared communication technology is widely applied to optical communication receivers, and provides new insight for the development of future secure free space links. The method breaks through the constraint of limited optical fibers, increases bit transmission rate, and improves availability, performance and coverage of optical communication technology. The mid-infrared communication system comprises a radiation source which emits after intensity modulation and an optical communication receiver, and the transmission rate of the mid-infrared communication system can reach 40Gbit/s currently. In addition, the development of the technology is expected to play a pushing role in the development of the fields of on-chip chemical biosensing, medical detection, environmental monitoring, industrial safety and the like.
The silicon waveguide integrated optical communication receiver is one of important devices of the mid-infrared silicon-based photoelectron technology and comprises a plurality of integration modes; among other things, heteroepitaxial growth techniques are advantageous for achieving large-scale and low-cost integration of silicon waveguide integrated optical communication receivers. However, the integration of optical communication receivers on silicon platforms using heteroepitaxial growth techniques requires consideration of the unavoidable formation of dislocations at the interface to release strain energy in high lattice mismatched heteroepitaxial systems, and how to reduce dislocations and increase the level of growth technology is a major challenge for mid-infrared silicon-based optoelectronic devices.
Disclosure of Invention
The invention aims to provide an InAs waveguide detection system based on an SOI platform and a preparation method thereof, which are used for solving the technical problem that the detection performance of the InAs waveguide detection system is poor due to too many interface dislocation of an active layer and a buffer layer in the existing InAs waveguide detection system prepared by adopting a heteroepitaxial growth technology.
In order to solve the technical problems, the invention firstly provides a preparation method of an InAs waveguide detection system based on an SOI platform, which comprises the following steps:
s10, respectively carrying out patterning treatment on the surface of monocrystalline top silicon in the SOI platform, sequentially forming a grating, an optical connection assembly and a bottom Si material layer, wherein the grating is connected with the bottom Si material layer through the optical connection assembly;
s20, epitaxially growing a Ge buffer layer on the bottom Si material layer by adopting MOCVD equipment;
s30, sequentially growing a GaAs buffer layer and an InAs active layer on the Ge buffer layer by adopting solid molecular beam epitaxy equipment, and forming an interface mismatch array between the InAs active layer and the GaAs buffer layer;
and S40, forming an electrode assembly on the InAs active layer.
Preferably, step S10 further comprises:
s101, depositing a passivation protection layer on the surface of the grating, wherein the passivation protection layer completely wraps the periphery of the grating, and the optical connection assembly penetrates through the passivation protection layer.
Preferably, the step S20 specifically includes:
s201, transferring the SOI platform to MOCVD equipment, introducing hydrogen and performing heating baking treatment;
s202, epitaxially growing a Si transition layer on a bottom Si material layer, wherein the bottom Si material layer and the Si transition layer form a Si buffer layer;
s203, epitaxially growing a Ge low-temperature growth layer on the Si buffer layer;
s204, epitaxially growing a Ge high-temperature growth layer on the Ge low-temperature growth layer;
and S205, performing thermal cycle annealing treatment on the Ge low-temperature growth layer and the Ge high-temperature growth layer respectively to form a Ge buffer layer.
Preferably, the step S30 specifically includes:
s301, transferring the SOI platform into solid molecular beam epitaxy equipment, and growing a GaAs buffer layer on the Ge buffer layer by adopting a migration-enhanced epitaxial growth process;
and S302, growing an InAs active layer on the GaAs buffer layer, wherein an interface mismatch array is formed between the InAs active layer and the GaAs buffer layer by adopting a high lattice mismatch growth strategy.
Preferably, the step S301 specifically includes:
s3011, transferring the SOI platform into solid molecular beam epitaxy equipment, and performing heating treatment on the Ge buffer layer in a vacuum environment to form a Ge double-atomic step structure on the surface of the Ge buffer layer;
s3012, cooling the reaction temperature of the solid-state molecular beam epitaxy equipment to a first temperature, and alternately introducing a Ga source and an As source into the solid-state molecular beam epitaxy equipment in a first time period to obtain a first GaAs sublayer;
s3013, heating the reaction temperature of the solid-state molecular beam epitaxy equipment to a second temperature, and alternately introducing a Ga source and an As source into the solid-state molecular beam epitaxy equipment in a second time period to obtain a second GaAs sublayer;
s3014, heating the reaction temperature of the solid-state molecular beam epitaxy equipment to a third temperature, and alternately introducing a Ga source and an As source into the solid-state molecular beam epitaxy equipment in a third time period to obtain a third GaAs sublayer.
Preferably, in the steps S3012 to S3014, the growth rate of the first GaAs sublayer and the second GaAs sublayer is 100 nm/hr, and the growth rate of the third GaAs sublayer is 1000 nm/hr; the V/III ratio of the first GaAs sub-layer, the second GaAs sub-layer and the third GaAs sub-layer is 4.
Preferably, the step S302 specifically includes:
s3021, reducing the reaction temperature of the solid-state molecular beam epitaxy equipment from the third temperature to a fourth temperature, and continuously introducing an As source into the solid-state molecular beam epitaxy equipment in a fourth time period to reconstruct a (100) crystal face of the GaAs buffer layer into a (2X 4) structural model;
s3022, maintaining the reaction temperature of the solid-state molecular beam epitaxy equipment unchanged, and alternately introducing an In source, an As source and an Si source into the solid-state molecular beam epitaxy equipment In a fifth time period to obtain an N-type doped InAs sub-layer, wherein an interface mismatch array is formed between the N-type doped InAs sub-layer and the GaAs buffer layer;
s3023, maintaining the reaction temperature of the solid-state molecular beam epitaxy equipment unchanged, and alternately introducing an In source and an As source into the solid-state molecular beam epitaxy equipment In a sixth time period to obtain an unintentionally doped InAs sub-layer;
s3024, maintaining the reaction temperature of the solid-state molecular beam epitaxy device unchanged, and alternately introducing an In source, an As source and a Be source into the solid-state molecular beam epitaxy device In a seventh time period to obtain the P-type doped InAs sub-layer.
Preferably, in steps S3022 to S3024, the growth rates of the N-type doped InAs sub-layer, the unintentionally doped InAs sub-layer, and the P-type doped InAs sub-layer are 650 nm/hr; the V/III ratio of the N-type doped InAs sub-layer, the unintentional doped InAs sub-layer and the P-type doped InAs sub-layer is 3.
Preferably, the step S40 specifically includes:
s401, patterning the InAs active layer to form a step-shaped structure between two ends of the InAs sub-layer which is not intentionally doped and the N-type InAs sub-layer, wherein the area of the InAs sub-layer which is not intentionally doped is smaller than that of the N-type InAs sub-layer;
s402, depositing a top electrode on the P-type doped InAs sub-layer and depositing a bottom electrode at the step-shaped structure of the N-type doped InAs sub-layer.
Correspondingly, the invention also provides an InAs waveguide detection system based on the SOI platform, which is prepared by adopting the preparation method of any InAs waveguide detection system based on the SOI platform.
The beneficial effects of the invention are as follows: different from the prior art, the invention provides an InAs waveguide detection system based on an SOI platform and a preparation method thereof, wherein the preparation method comprises the following steps: firstly, respectively carrying out patterning treatment on the surface of monocrystalline top silicon in an SOI platform, sequentially forming a grating, an optical connection assembly and a bottom Si material layer, wherein the grating is connected with the bottom Si material layer through the optical connection assembly, secondly, epitaxially growing a Ge buffer layer on the bottom Si material layer by adopting MOCVD equipment, thirdly, sequentially growing a GaAs buffer layer and an InAs active layer on the Ge buffer layer by adopting solid molecular beam epitaxy equipment, forming an interface mismatch array between the InAs active layer and the GaAs buffer layer, and finally, forming an electrode assembly on the InAs active layer; according to the preparation method, firstly, the grating, the optical connection assembly and the bottom Si material layer are formed on the same SOI platform, then the MOCVD equipment is adopted to grow the Ge buffer layer, so that the GaAs buffer layer can grow on the bottom Si material layer, then the solid-state molecular beam epitaxy equipment is adopted to form an interface mismatch array between the InAs active layer and the GaAs buffer layer, and therefore screw dislocation formed by merging island structures of the InAs material in the early growth stage is reduced through the dislocation layer technology, strain energy is released, material defects are restrained, the growth quality of the InAs material is improved, and the detection performance of the InAs waveguide detection system is improved.
Drawings
FIG. 1 is a process flow diagram of a method for preparing an InAs waveguide detection system based on an SOI platform according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of an InAs waveguide detection system based on an SOI platform according to an embodiment of the present invention;
FIG. 3 is an enlarged schematic view of FIG. 2 at A;
fig. 4 is a schematic diagram of a transmission electron microscope at an interface between an InAs active layer and a GaAs buffer layer in a method for manufacturing an InAs waveguide detection system based on an SOI platform according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an interface mismatch array formed between an InAs active layer and a GaAs buffer layer in an InAs waveguide detection system based on an SOI platform according to an embodiment of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
Referring to fig. 1 to 3, fig. 1 is a process flow chart of a method for preparing an InAs waveguide detection system 100 based on an SOI platform according to an embodiment of the present invention; fig. 2 is a schematic structural diagram of an InAs waveguide detection system 100 based on an SOI platform according to an embodiment of the present invention; FIG. 3 is an enlarged schematic view of FIG. 2 at A;
the preparation method specifically comprises the following steps:
and S10, respectively carrying out patterning treatment on the surface of the monocrystalline top silicon in the SOI platform, sequentially forming a grating, an optical connection assembly 30 and a bottom Si material layer, wherein the grating is connected with the bottom Si material layer through the optical connection assembly 30.
Specifically, S10 further includes:
first, an SOI (Silicon-On-Insulator) platform is provided, which consists of a single-crystal top Silicon, buried oxide layer 22 (SiO material 2 For isolating the bulk silicon 21) and the bulk silicon 21.
Specifically, the SOI platform achieves full dielectric isolation of the device from the bulk silicon 21 through the buried oxide layer 22, which can reduce parasitic capacitance of the device and increase the operating speed of the device.
Secondly, respectively carrying out patterning treatment on the surface of the monocrystalline top silicon by adopting a photoetching process:
coating photoresist on the surface of monocrystalline top silicon, transferring the pattern on the mask plate to the photoresist through an exposure step under a photoetching machine, and then carrying out development and solidification steps. And then, etching the wafer by adopting phosphoric acid and hydrogen peroxide mixed etching liquid, and sequentially forming a grating, an optical connection assembly 30 and a bottom Si material layer respectively, wherein the grating is connected with the bottom Si material layer through the optical connection assembly 30, as shown in fig. 2 and 3.
Specifically, the grating is a mid-infrared grating, which can disperse incident light into light with different wavelengths through the diffraction effect of light, and is beneficial to the detection of InAs detectors connected with the grating.
Specifically, the optical connection assembly 30 includes a connection waveguide 31 and a tapered coupler 32 integrally formed with the connection waveguide 31, one end of the connection waveguide 31 is connected with the grating, and one end of the tapered coupler 32 is connected with the underlying Si material layer; the connecting waveguide 31 is in a strip shape, and the connecting waveguide 31 is used for binding the light beam therein so as to reduce loss in the light transmission process; the tapered coupler 32 is tapered, and the tapered coupler 32 is used to couple light transmitted by the connection waveguide 31 into the underlying Si material layer.
Specifically, the step S10 further includes:
s101, depositing a passivation layer 50 on the surface of the grating, wherein the passivation layer 50 completely wraps the periphery of the grating, and the optical connection assembly 30 penetrates through the passivation layer 50. Passivation layer 50 prevents contamination of the surface of the grating by harmful impurities, passivation layer 50 is made of SOI 2 。
And S20, epitaxially growing a Ge buffer layer 42 on the bottom Si material layer by adopting MOCVD equipment.
Specifically, the S20 step is mainly performed in MOCVD (metal organic chemical vapor deposition) equipment of the model Veeco K465i, wherein high purity H is used 2 Or high purity N 2 Or high purity H 2 And high purity N 2 As a carrier gas, tetramethyl germanium (TMGe) as a germanium source.
Specifically, the step S20 further includes:
s201, transferring the SOI platform into MOCVD equipment, introducing hydrogen and performing heating baking treatment. Wherein the temperature of the heating and baking treatment is 1000-1300 ℃, the baking time is 30-600 min, and H 2 Partial pressure of 10 -8 torr。
Preferably, the temperature of the heating and baking treatment is 1050 ℃, and the baking time is 100min.
Further, the hydrogen is introduced and the heating and baking treatment is performed mainly to remove impurities attached to the SOI platform after the treatment in step S10.
S202, epitaxially growing a Si transition layer on the underlying Si material layer, wherein the underlying Si material layer and the Si transition layer form the Si buffer layer 41. Preferably, the thickness of the Si transition layer is 100nm.
S203, epitaxially growing a Ge low-temperature growth layer on the Si buffer layer 41; wherein, because of the large lattice mismatch of Si material and GaAs material, a thin Ge buffer layer 42 needs to be grown before the GaAs material is grown; further, the Ge low-temperature growth layer is used as a low-temperature nucleation layer, the thickness range of the Ge low-temperature growth layer is 1 nm-50 nm, and the growth temperature range of the Ge low-temperature growth layer is 400-500 ℃.
Preferably, the growth temperature of the Ge low-temperature growth layer is 450 ℃, and the thickness of the Ge low-temperature growth layer is 30nm.
S204, epitaxially growing a Ge high-temperature growth layer on the Ge low-temperature growth layer; the thickness of the Ge high-temperature growth layer ranges from 10nm to 500nm, and the growth temperature of the Ge high-temperature growth layer ranges from 550 ℃ to 700 ℃.
Preferably, the growth temperature of the Ge high-temperature growth layer is 650 ℃, and the thickness of the Ge high-temperature growth layer is 100nm.
Further, since the Ge low-temperature growth layer has poor crystallization quality, it is necessary to epitaxially grow a Ge high-temperature growth layer having good crystallization quality on the Ge low-temperature growth layer.
Further, the growth temperature of the Ge high-temperature growth layer is higher than that of the Ge low-temperature growth layer, and the high-temperature growth is beneficial to rapid transverse combination of the low-temperature nucleation layer so as to reduce dislocation density.
S205, the Ge low temperature growth layer and the Ge high temperature growth layer are respectively subjected to thermal cycle annealing treatment to form the Ge buffer layer 42, as shown in fig. 3.
In this embodiment, the thermal cycle annealing treatment specifically includes the steps of: in a hydrogen atmosphere (10) -8 torr), the sample temperature is raised to 850 ℃ at a rate of 10 ℃/min. After the sample reached 850℃it was incubated for 10 minutes and then cooled to 650℃at a rate of 10℃per minute. The above is one cycle. Finishing 5 cycles according to the same condition, namely, the whole thermal cycle annealing process, wherein H is in the annealing process 2 The partial pressure remains unchanged.
Further, the thermal cycle annealing process can further enhance the growth quality of the Ge buffer layer 42.
And S30, sequentially growing a GaAs buffer layer 43 and an InAs active layer 44 on the Ge buffer layer 42 by adopting a solid molecular beam epitaxy device, and forming an interface mismatch array between the InAs active layer 44 and the GaAs buffer layer 43.
Specifically, S30 further includes:
s301, transferring the SOI platform into a solid state molecular beam epitaxy apparatus and growing GaAs buffer layer 43 on Ge buffer layer 42 using a migration-enhanced epitaxial growth process.
Preferably, the step S301 specifically includes:
s3011, transferring the SOI platform into a solid molecular beam epitaxy equipment (MBE), and performing heating treatment on the Ge buffer layer 42 in a vacuum environment to form a Ge double-atomic step structure on the surface of the Ge buffer layer 42; the MBE molecular beam epitaxy technique is a technique of growing an epitaxial thin layer by spraying molecular (or atomic) beams of its components onto a substrate under ultra-high vacuum conditions. The proper growth temperature allows the adsorbed atoms to have enough energy to migrate to the proper equilibrium position for epitaxial growth. The temperature is too low, and polycrystal or amorphous may grow; too high a temperature will cause the adsorbed atoms to re-evaporate and desorb.
Specifically, the silicon-based Ge buffer layer 42 is first subjected to a vacuum environment (gas pressure less than 10 a -10 torr) is heated to 650 ℃ and maintained for 20 minutes to detach oxygen molecules attached to the surface (the SOI platform is in contact with air during the transfer process) and form a Ge diatomic step structure on the surface. The presence of the Ge diatomic step structure can avoid reverse grain boundary defects that occur when InAs materials are epitaxially grown on the Ge buffer layer 42.
S3012, cooling the reaction temperature of the solid-state molecular beam epitaxy equipment to a first temperature, and alternately introducing a Ga source (TMGa) and an As Source (TMAs) into the solid-state molecular beam epitaxy equipment in a first time period to obtain a first GaAs sub-layer;
wherein the first temperature is in the range of 200-300 ℃, preferably 250 ℃; the first GaAs sub-layer is obtained by sequentially opening or closing the shutter switch of the Ga source/As source of the solid-state molecular beam epitaxy device so As to realize the alternate growth of one layer of Ga and one layer of As atoms.
Preferably, the reaction temperature of the solid state molecular beam epitaxy apparatus is reduced from 650 ℃ to 250 ℃ at a rate of 15 ℃ per minute to grow a first GaAs sublayer 10nm thick.
S3013, heating the reaction temperature of the solid-state molecular beam epitaxy equipment to a second temperature, and alternately introducing a Ga source and an As source into the solid-state molecular beam epitaxy equipment in a second time period to obtain a second GaAs sublayer;
wherein the second temperature is in the range of 300-400 ℃, preferably 330 ℃; the alternate growth of one layer of Ga and one layer of As atoms is achieved by sequentially opening or closing the shutter switches of the Ga source/As source of the solid state molecular beam epitaxy apparatus to obtain a second GaAs sublayer, preferably 40nm thick.
Preferably, the reaction temperature of the solid state molecular beam epitaxy apparatus is raised from 250 ℃ to 330 ℃ at a rate of 15 ℃ per minute to grow a 40nm thick second GaAs sublayer.
S3014, heating the reaction temperature of the solid-state molecular beam epitaxy equipment to a third temperature, and alternately introducing a Ga source and an As source into the solid-state molecular beam epitaxy equipment in a third time period to obtain a third GaAs sublayer;
wherein the third temperature is in the range of 500-600deg.C, preferably 580 deg.C; the third GaAs sub-layer is obtained by sequentially opening or closing the shutter switch of the Ga source/As source of the solid-state molecular beam epitaxy device to realize the alternate growth of one layer of Ga and one layer of As atoms.
Preferably, the reaction temperature of the solid state molecular beam epitaxy apparatus is raised from 330 ℃ to 580 ℃ at a rate of 15 ℃ per minute, growing a third GaAs sublayer 150nm thick.
Preferably, in the steps S3012 to S3014, the growth rate of the first GaAs sublayer and the second GaAs sublayer is 100 nm/hr, and the growth rate of the third GaAs sublayer is 1000 nm/hr; the V/III ratio of the first GaAs sub-layer, the second GaAs sub-layer and the third GaAs sub-layer is 4.
Specifically, the V/III ratio refers to the molar ratio of a V group source to a III group source which is introduced into a reaction cavity of solid molecular beam epitaxy equipment in the epitaxial growth process, and the grown epitaxial layer can bring higher epitaxial lattice quality under the condition of high V/III ratio.
And S302, growing the InAs active layer 44 on the GaAs buffer layer 43, wherein an interface mismatch array is formed between the InAs active layer 44 and the GaAs buffer layer 43 by adopting a high lattice mismatch growth strategy.
Preferably, the step S302 specifically includes:
s3021, reducing the reaction temperature of the solid-state molecular beam epitaxy equipment from the third temperature to a fourth temperature, and continuously introducing an As source into the solid-state molecular beam epitaxy equipment in a fourth time period to reconstruct a (100) crystal face of the GaAs buffer layer 43 into a (2X 4) structural model;
wherein the fourth temperature is in the range of 300-400 ℃, preferably 310 ℃; at this temperature, the partial pressure range of the As source is adjusted to 2X10 by changing the switch proportion of the shutter of the As source -6 ~8X10 -6 Torr such that the (100) crystal plane of GaAs buffer layer 43 is reconstructed into a (2X 4) structural model, and the (2X 4) structural model of the (100) crystal plane of GaAs buffer layer 43 facilitates the formation of an interface mismatch array (Interfacial Misfit arrays, IMF) with InAs.
Specifically, the surface reconstruction can be confirmed by a reflective high-energy electron diffractometer attached to the molecular beam epitaxy apparatus.
Specifically, when the partial pressure of the As source is less than 2X10 -6 At Torr, the surface of the GaAs buffer layer 43 becomes rough due to the continuous high temperature; when the partial pressure of the As source is greater than 8X10 -6 In Torr, the (100) crystal plane of the GaAs buffer layer 43 is reconstructed into a (1X 3) structural model.
S3022, maintaining the reaction temperature of the solid-state molecular beam epitaxy device unchanged, and alternately introducing an In source (TMIn), an As source and an Si source into the solid-state molecular beam epitaxy device In a fifth time period to obtain an N-type doped InAs sub-layer, wherein an interface mismatch array is formed between the N-type doped InAs sub-layer and the GaAs buffer layer 43;
the method comprises the steps of keeping the reaction temperature unchanged, and sequentially opening or closing a shutter switch of an In source/As source of solid-state molecular beam epitaxy equipment to realize alternate growth of one layer of In and one layer of As atoms, and continuously introducing a Si source to obtain an N-type doped InAs sub-layer.
S3023, maintaining the reaction temperature of the solid-state molecular beam epitaxy equipment unchanged, and alternately introducing an In source and an As source into the solid-state molecular beam epitaxy equipment In a sixth time period to obtain an unintentionally doped InAs sub-layer;
the reaction temperature is kept unchanged, and the alternate growth of one layer of In and one layer of As atoms is realized by sequentially opening or closing a shutter switch of an In source/As source of the solid molecular beam epitaxy device, so that an unintentionally doped InAs sub-layer is obtained.
S3024, maintaining the reaction temperature of the solid-state molecular beam epitaxy device unchanged, and alternately introducing an In source, an As source and a Be source (di-tert-butylberyllium) into the solid-state molecular beam epitaxy device In a seventh time period to obtain the P-type doped InAs sub-layer.
The method comprises the steps of keeping the reaction temperature unchanged, and sequentially opening or closing a shutter switch of an In source/As source of solid-state molecular beam epitaxy equipment to realize alternate growth of one layer of In and one layer of As atoms, and continuously introducing a Be source to obtain a P-type doped InAs sub-layer; at this time, the N-type doped InAs sub-layer, the unintentionally doped InAs sub-layer, and the P-type doped InAs sub-layer form a PIN structure.
Preferably, in steps S3022 to S3024, the growth rates of the N-type doped InAs sub-layer, the unintentionally doped InAs sub-layer, and the P-type doped InAs sub-layer are 650 nm/hr; the V/III ratio of the N-type doped InAs sub-layer, the unintentional doped InAs sub-layer and the P-type doped InAs sub-layer is 3.
Preferably, the thickness of the N-type doped InAs sub-layer is 200nm, the thickness of the unintentional doped InAs sub-layer is 600nm, and the thickness of the P-type doped InAs sub-layer is 200nm.
And S40, forming an electrode assembly on the InAs active layer 44.
Specifically, the step S40 further includes:
s401, patterning is carried out on the InAs active layer 44, so that a step-shaped structure is formed between two ends of the unintentionally doped InAs sub-layer and the N-type doped InAs sub-layer, and the area of the unintentionally doped InAs sub-layer is smaller than that of the N-type doped InAs sub-layer.
Further, the specific steps of patterning the InAs active layer 44 include: firstly, coating photoresist on the surface of a wafer after growth, transferring the pattern on the mask plate to the photoresist through an exposure step under a photoetching machine, and then carrying out development and solidification steps. And etching the wafer by adopting phosphoric acid and hydrogen peroxide mixed etching liquid to form a step structure of the InAs waveguide detector 40, wherein the etching depth is controlled in real time through steps. After the etching is completed, the photoresist is washed away by an organic solvent.
S402, depositing a top electrode 45 on the P-type doped InAs sub-layer and depositing a bottom electrode 46 at the step-like structure of the N-type doped InAs sub-layer.
Further, photoresist is coated on the wafer surface after the step forming step, the pattern on the mask plate is transferred to the photoresist through the exposure step under a photoetching machine, and then the steps of developing and solidifying are carried out. Next, the wafer is placed into an electron beam evaporation apparatus, a top electrode 45 is deposited on the P-type doped InAs sub-layer under certain conditions, and a bottom electrode 46 is deposited at the step-like structure of the N-type doped InAs sub-layer, and finally the photoresist and the metal layer thereon are all removed by an organic solvent, thereby obtaining a desired metal pattern.
Preferably, the top electrode 45 and the bottom electrode 46 are Ti/Au alloys deposited in the order of 10nm Ti followed by 150nm Au.
Preferably, the InAs active layer 44 has a thickness of 1000-1400nm, wherein the preferred thickness of the unintentionally doped InAs sub-layer is 600nm; the thickness of the Si buffer layer 41 is 400-500nm, preferably 450nm; the thickness of the Ge buffer layer 42 is 100.+ -.50 nm, preferably 100nm; the thickness of the GaAs buffer layer 43 is 200.+ -.50 nm, preferably 200nm.
The present invention first employs a heavily doped crystal nucleation layer scheme to grow a Ge buffer layer 42 on an SOI platform, followed by a solid state molecular beam epitaxy system to grow a GaAs buffer layer 43 and InAs waveguide detector 40. An interface mismatch array is formed between the GaAs buffer layer 43 and the InAs active layer 44 by adopting a high lattice mismatch growth strategy, and threading dislocation formed by merging island structures in the early growth stage of the InAs active layer 44 is reduced by a dislocation layer technology, so that strain energy is released, material defects are suppressed, and growth quality is improved.
The present invention also employs standard photolithographic, electron beam evaporation and metal lift-off fabrication techniques to form Au/Ti metal plate electrodes on the surface of the InAs active layer 44. Sample growth and in-situ thermal annealing are performed in a molecular beam epitaxy system, a Ge buffer layer 42 is grown on an SOI platform, and during the annealing step, the heat treatment temperature exceeds the growth temperature of the Ge buffer layer 42.
Correspondingly, referring to fig. 2 and 3, the present invention further provides an InAs waveguide detection system 100 based on the SOI platform, which is prepared by adopting the preparation method of any InAs waveguide detection system 100 based on the SOI platform as described above.
Specifically, the InAs waveguide detection system 100 includes a grating, an optical connection assembly 30 and an InAs waveguide detector 40 simultaneously fabricated on an SOI platform, the optical connection assembly 30 including a connection waveguide 31 and a tapered coupler 32 integrally formed with the connection waveguide 31;
wherein the grating is connected to the connecting waveguide 31 and the tapered coupler 32 is connected to the InAs waveguide detector 40.
Specifically, the InAs waveguide detection system 100 further includes a passivation layer 50, the passivation layer 50 completely surrounds the grating, and the optical connection assembly 30 extends through the passivation layer 50.
Specifically, the InAs waveguide detector 40 includes a Si buffer layer 41, a Ge buffer layer 42, a GaAs buffer layer 43, an InAs active layer 44, and an electrode assembly formed in this order on the buried oxide layer 22;
the InAs active layer 44 includes an N-type doped InAs sub-layer, an unintentionally doped InAs sub-layer, and a P-type doped InAs sub-layer disposed from bottom to top, wherein a step structure is formed between both ends of the unintentionally doped InAs sub-layer and the N-type doped InAs sub-layer, and an area of the unintentionally doped InAs sub-layer is smaller than an area of the N-type doped InAs sub-layer.
Specifically, the electrode assembly includes a top electrode 45 deposited on the P-type doped InAs sub-layer, and a bottom electrode 46 deposited at the stepped structure of the N-type doped InAs sub-layer; the bottom electrode 46 is disposed around and not in contact with the unintentionally doped InAs sub-layer.
Referring to fig. 4, fig. 4 is a schematic diagram of a transmission electron microscope of an interface between an InAs active layer 44 and a GaAs buffer layer 43 in an InAs waveguide detection system 100 based on an SOI platform according to an embodiment of the present invention; among them, as can be seen from fig. 4, dislocation defects in the InAs waveguide detector 40 are mainly concentrated at the interface between the InAs active layer 44 and the GaAs buffer layer 43, rather than inside the InAs active layer 44 material, so that the InAs active layer 44 material has a good growth effect, which is advantageous for obtaining the InAs waveguide detector 40 with high absorption efficiency.
Referring to fig. 5, fig. 5 is a schematic diagram of an interface mismatch array formed between the InAs active layer 44 and the GaAs buffer layer 43 in the SOI platform based InAs waveguide detection system 100 according to an embodiment of the present invention. As can be seen from fig. 4, an interface mismatch array (within a white dashed box in the figure) is formed between the InAs active layer 44 and the GaAs buffer layer 43;
among them, the interface mismatch array is very remarkable in terms of stress relief and reduction of threading dislocation density. It effectively releases more than 98% of the stress on the interface layer of several molecular monolayers by forming a 90 ° pure-sided dislocation periodic array at the GaAs and InAs interface, thus reducing the probability of threading dislocation generation, resulting in the formation of an epitaxial layer of low threading dislocation density, thereby enabling the fabrication of high performance InAs waveguide detectors 40 on SOI platforms.
Accordingly, after epitaxial growth of the InAs waveguide detector 40, x-rays omega-2θ scan, omega scan, and Reciprocal Space Map (RSM) are obtained with an x-ray diffractometer with a beam collimator and analytical crystal to achieve sufficiently high resolution. The surface morphology was measured using AFM (Atomic Force Microscope ) and the interface microstructure was examined using transmission electron microscopy. The type and concentration of carriers were evaluated using the hall-van der waals method. Mid-infrared light responsiveness measurements were made using a tunable laser and a 700 ℃ blackbody radiation source, and the results indicated that:
AFM measurements showed that the roughness root mean square of the InAs active layer 44 was low;
the X-ray omega-2 theta diffraction scanning result shows that the strain relaxation of the InAs active layer 44 reaches 98.9%, and the surface has excellent growth effect and extremely high growth quality;
the mid-infrared light responsiveness measurement results show that: after an external optical fiber light source is transmitted to the InAs waveguide detector 40 through the grating and the connecting waveguide 31, the InAs waveguide detection system 100 based on the SOI platform has the absorption efficiency reaching more than 95%, and the responsivity exceeding 2.37A/W; the 3dB bandwidth of 40.5GHz is shown in the aspect of frequency response, which shows the potential application of the broadband antenna in the field of mid-infrared light communication.
The inventors of the present application have found in research that there is currently no report about mid-infrared waveguide type optical communication receivers on heteroepitaxially integrated SOI. The mid-infrared waveguide detection system has the characteristic of excellent high-frequency condition. The invention prepares the mid-infrared light communication receiver on the SOI substrate by a heteroepitaxial growth mode, and epitaxially grows the active layer material InAs by an interface dislocation layer technology so as to reduce the screw dislocation density.
In the process, the low threading dislocation density InAs is epitaxially grown on GaAs by a self-assembly periodic interface misfit dislocation technology, so that the interface of the multi-material graded buffer layer is smooth, the misfit dislocation angle is 90 degrees, and the strain relaxation is close to 100 percent, thereby solving the technical problem of material defects; in terms of manufacturing, the invention solves the problems of difficult large-scale manufacturing process and low integration level of the silicon-based mid-infrared light communication receiver; in terms of performance, the invention solves the problem that the bandwidth and the responsivity of the device cannot be simultaneously considered, and provides a search road for the monolithic integration of the mid-infrared light device on the SOI and the widening of the optical communication field, especially the free space optical communication.
Compared with the prior art, the invention has the following beneficial effects:
after an external optical fiber light source is transmitted to the InAs waveguide detector 40 through the grating and the connecting waveguide 31, the InAs waveguide detection system 100 based on the SOI platform has the absorption efficiency reaching more than 95%, and the responsivity exceeding 2.37A/W; the 3dB bandwidth of 40.5GHz is shown in the aspect of frequency response, which shows the potential application of the broadband antenna in the field of mid-infrared light communication.
The preparation method of the photoelectric detection system of the invention utilizes the self-assembled periodic interface misfit dislocation technology to grow a completely relaxed low threading dislocation density InAs active layer 44 on the GaAs buffer layer 43.
The invention realizes the preparation of the mid-infrared waveguide type optical communication receiver on the SOI platform in a heteroepitaxial growth mode, reduces dislocation through an interface dislocation layer technology, improves the growth quality of a semiconductor, and provides a promising approach for further improving the mid-infrared silicon photonics process level, developing mid-infrared silicon photonics and expanding free space optical communication.
In summary, unlike the prior art, the present invention provides an InAs waveguide detection system 100 based on an SOI platform and a method for manufacturing the same, which comprises: firstly, respectively patterning the surface of monocrystalline top silicon in an SOI platform to sequentially form a grating, an optical connection assembly 30 and a bottom Si material layer, wherein the grating is connected with the bottom Si material layer through the optical connection assembly 30, secondly, epitaxially growing a Ge buffer layer 42 on the bottom Si material layer by MOCVD equipment, thirdly, sequentially growing a GaAs buffer layer 43 and an InAs active layer 44 on the Ge buffer layer 42 by solid-state molecular beam epitaxy equipment, forming an interface mismatch array between the InAs active layer 44 and the GaAs buffer layer 43, and finally, forming an electrode assembly on the InAs active layer 44; according to the preparation method, firstly, the grating, the optical connection assembly 30 and the bottom Si material layer are formed on the same SOI platform, then the MOCVD equipment is adopted to grow the Ge buffer layer 42, so that the GaAs buffer layer 43 can grow on the bottom Si material layer, and then the solid-state molecular beam epitaxy equipment is adopted to form an interface mismatch array between the InAs active layer 44 and the GaAs buffer layer 43, so that screw dislocation formed by the combination of island structures of the InAs material in the early growth stage is reduced through the dislocation layer technology, strain energy is released, material defects are restrained, the growth quality of the InAs material is improved, and the detection performance of the InAs waveguide detection system 100 is improved.
The foregoing examples merely illustrate embodiments of the invention and are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. The preparation method of the InAs waveguide detection system based on the SOI platform is characterized by comprising the following steps of:
s10, patterning the silicon surface in the SOI platform to sequentially form a grating, an optical connection assembly and a bottom Si material layer, wherein the grating is connected with the bottom Si material layer through the optical connection assembly;
s20, epitaxially growing a Ge buffer layer on the bottom Si material layer by adopting MOCVD equipment;
s30, sequentially growing a GaAs buffer layer and an InAs active layer on the Ge buffer layer by adopting solid molecular beam epitaxy equipment, and forming an interface mismatch array between the InAs active layer and the GaAs buffer layer;
and S40, forming an electrode assembly on the InAs active layer.
2. The method for preparing an InAs waveguide detection system based on an SOI platform according to claim 1, wherein the step S10 further comprises:
s101, depositing a passivation protection layer on the surface of the grating, wherein the passivation protection layer completely wraps the periphery of the grating, and the optical connection assembly penetrates through the passivation protection layer.
3. The method for preparing an InAs waveguide detection system based on an SOI platform according to claim 1, wherein the step S20 specifically comprises:
s201, transferring the SOI platform to MOCVD equipment, introducing hydrogen and performing heating baking treatment;
s202, epitaxially growing a Si transition layer on the bottom Si material layer, wherein the bottom Si material layer and the Si transition layer form a Si buffer layer;
s203, epitaxially growing a Ge low-temperature growth layer on the Si buffer layer;
s204, epitaxially growing a Ge high-temperature growth layer on the Ge low-temperature growth layer;
and S205, respectively carrying out thermal cycle annealing treatment on the Ge low-temperature growth layer and the Ge high-temperature growth layer to form the Ge buffer layer.
4. The method for preparing the InAs waveguide detection system based on the SOI platform according to claim 1, wherein the step S30 specifically comprises:
s301, transferring the SOI platform into the solid molecular beam epitaxy equipment, and adopting a migration-enhanced epitaxial growth process to grow the GaAs buffer layer on the Ge buffer layer;
and S302, growing the InAs active layer on the GaAs buffer layer, wherein an interface mismatch array is formed between the InAs active layer and the GaAs buffer layer by adopting a high lattice mismatch growth strategy.
5. The method for preparing an InAs waveguide detection system based on an SOI platform according to claim 4, wherein the step S301 specifically comprises:
s3011, transferring the SOI platform into the solid molecular beam epitaxy equipment, and performing heating treatment on the Ge buffer layer in a vacuum environment to form a Ge double-atomic step structure on the surface of the Ge buffer layer;
s3012, cooling the reaction temperature of the solid-state molecular beam epitaxy equipment to a first temperature, and alternately introducing a Ga source and an As source into the solid-state molecular beam epitaxy equipment in a first time period to obtain a first GaAs sublayer;
s3013, heating the reaction temperature of the solid-state molecular beam epitaxy equipment to a second temperature, and alternately introducing the Ga source and the As source into the solid-state molecular beam epitaxy equipment in a second time period to obtain a second GaAs sub-layer;
s3014, heating the reaction temperature of the solid-state molecular beam epitaxy equipment to a third temperature, and alternately introducing the Ga source and the As source into the solid-state molecular beam epitaxy equipment in a third time period to obtain a third GaAs sublayer.
6. The method for preparing an InAs waveguide detection system based on an SOI platform according to claim 5, wherein in steps S3012 to S3014, the growth rate of the first GaAs sublayer and the second GaAs sublayer is 100 nm/hr, and the growth rate of the third GaAs sublayer is 1000 nm/hr; the V/III ratio of the first GaAs sub-layer, the second GaAs sub-layer and the third GaAs sub-layer is 4.
7. The method for preparing an InAs waveguide detection system based on an SOI platform as claimed in claim 6, wherein said step S302 specifically comprises:
s3021, reducing the reaction temperature of the solid-state molecular beam epitaxy equipment from the third temperature to a fourth temperature, and continuously introducing the As source into the solid-state molecular beam epitaxy equipment in a fourth time period so As to reconstruct a (100) crystal face of the GaAs buffer layer into a (2X 4) structural model;
s3022, maintaining the reaction temperature of the solid-state molecular beam epitaxy equipment unchanged, and alternately introducing an In source, the As source and an Si source into the solid-state molecular beam epitaxy equipment In a fifth time period to obtain an N-type doped InAs sub-layer, wherein the interface mismatch array is formed between the N-type doped InAs sub-layer and the GaAs buffer layer;
s3023, maintaining the reaction temperature of the solid-state molecular beam epitaxy equipment unchanged, and alternately introducing the In source and the As source into the solid-state molecular beam epitaxy equipment In a sixth time period to obtain an unintentionally doped InAs sub-layer;
and S3024, maintaining the reaction temperature of the solid-state molecular beam epitaxy equipment unchanged, and alternately introducing the In source, the As source and the organic beryllium source into the solid-state molecular beam epitaxy equipment In a seventh time period to obtain the P-type doped InAs sub-layer.
8. The method for preparing an InAs waveguide detection system based on an SOI platform according to claim 7, wherein in steps S3022 to S3024, the growth rates of the N-type doped InAs sub-layer, the unintentionally doped InAs sub-layer, and the P-type doped InAs sub-layer are 650 nm/hr; the V/III ratio of the N-type doped InAs sub-layer, the unintended doped InAs sub-layer and the P-type doped InAs sub-layer is 3.
9. The method for preparing an InAs waveguide detection system based on an SOI platform according to claim 7, wherein the step S40 specifically comprises:
s401, carrying out patterning treatment on the InAs active layer to enable a step-shaped structure to be formed between two ends of the unintentionally doped InAs sub-layer and the N-type doped InAs sub-layer, wherein the area of the unintentionally doped InAs sub-layer is smaller than that of the N-type doped InAs sub-layer;
s402, depositing a top electrode on the P-type doped InAs sub-layer and depositing a bottom electrode at the step-shaped structure of the N-type doped InAs sub-layer.
10. An InAs waveguide detection system based on an SOI platform, characterized in that the system is prepared by a preparation method of the InAs waveguide detection system based on an SOI platform as claimed in any one of claims 1 to 9.
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