CN117577614A - Chip packaging structure, method and electronic equipment - Google Patents

Chip packaging structure, method and electronic equipment Download PDF

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Publication number
CN117577614A
CN117577614A CN202311620205.5A CN202311620205A CN117577614A CN 117577614 A CN117577614 A CN 117577614A CN 202311620205 A CN202311620205 A CN 202311620205A CN 117577614 A CN117577614 A CN 117577614A
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CN
China
Prior art keywords
chip
solder ball
bump
conductive
memory
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CN202311620205.5A
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Chinese (zh)
Inventor
刘军
郝沁汾
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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Priority to CN202311620205.5A priority Critical patent/CN117577614A/en
Publication of CN117577614A publication Critical patent/CN117577614A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body

Abstract

The invention relates to a chip packaging structure, a chip packaging method and electronic equipment. Wherein the chip packaging structure includes: the memory chip comprises a plurality of first solder ball bumps and a plurality of first conductive through holes, wherein the arrangement density of the first solder ball bumps is greater than that of the first conductive through holes; the control chip is at least partially overlapped with the projection of the storage chip in the first direction, is electrically connected with the storage chip through the first solder ball bump and transmits a data signal, an address signal or a control signal to the storage chip; the first direction is a direction perpendicular to the memory chip; and the power management module is at least partially overlapped with the projection of the memory chip in the first direction, is electrically connected with the memory chip through the first conductive through hole and supplies power to the memory chip. The chip packaging structure, the method and the electronic equipment can reduce signal transmission loss and delay.

Description

Chip packaging structure, method and electronic equipment
Technical Field
The present invention relates to the field of chip packaging technologies, and in particular, to a chip packaging structure, a method and an electronic device.
Background
With the rapid development of the fields of AI (Artificial Intelligence ), HPC (High performance computing, high performance computing), and the like, the requirements of chips on storage bandwidth are becoming higher and higher, and storage packaging integrated applications based on HBM (High Bandwidth Memory ) particles are becoming more and more popular. The currently mainstream packaging technology for XPU and HBM integration is 2.5D silicon interposer technology. The HBM particles are led to one side of the particles in a highly integrated manner by TSVs (Through Silicon Via, through silicon vias), and then interconnected with an SOC (System on Chip) Chip by a 2.5D silicon interposer.
In the prior art, the HBM is usually interconnected with the SoC chip through a silicon adapter board (silicon bridge) to complete the transmission of signals such as data, address, clock and the like; the number of 1024DQ actual transmission lines exceeds 1700; the standard design adopts a line width line distance of 2/2um, and generally has 2 layers of signals; considering constraints such as equal length, the actual routing length exceeds 5mm; however, as the transmission speed increases, the line width/line spacing needs to be increased, and the RDL (Re-distributed layer, redistribution layer) thickness is increased, and DTC (Data Center) is integrated to meet the packaging requirements. With the future faster standard transmission speed (HBM 4 up to 12.8 Gbps), the existing packaging method will have difficulty meeting the requirements of signal integrity and bandwidth per unit length.
Disclosure of Invention
Accordingly, it is necessary to provide a chip package structure, a method and an electronic device capable of reducing signal transmission loss and delay and improving bandwidth per unit length, aiming at the problem of low bandwidth per unit length in the prior art.
In a first aspect, the present application provides a chip package structure, the package structure comprising:
a memory chip including a plurality of first solder ball bumps and a plurality of first conductive vias; wherein the arrangement density of the first solder ball bumps is greater than the arrangement density of the first conductive vias;
the control chip is at least partially overlapped with the projection of the storage chip in the first direction, is electrically connected with the storage chip through the first solder ball bump and transmits a data signal, an address signal or a control signal to the storage chip; the first direction is a direction perpendicular to the memory chip;
and the power management module is at least partially overlapped with the projection of the memory chip in the first direction, is electrically connected with the memory chip through the first conductive through hole and supplies power to the memory chip.
In some embodiments, the package structure further comprises:
the test module is used for testing the memory chip according to the input data;
The memory chip comprises a second conductive through hole, and the test module is electrically connected with the memory chip through the second conductive through hole and sends a test signal to the memory chip module.
In some embodiments, the package structure includes a plurality of memory chips; the plurality of memory chips constitute a memory stack chip;
the memory chip comprises a third conductive through hole, a first solder ball bump and a second solder ball bump are respectively formed at two ends of the third conductive through hole, wherein two adjacent memory chips are electrically connected through the first solder ball bump, the first conductive through hole and the second solder ball bump in sequence, and the control chip is electrically connected with the memory chip through the first solder ball bump, the first conductive through hole and the second solder ball bump and sends data signals, address signals or control signals to the memory chip.
In some embodiments, the control chip includes a control port physical layer electrically connected to the memory chip through the first metal wiring layer;
the package structure further includes:
a system chip including a system port physical layer; the system chip is electrically connected with the control port physical layer through the system port physical layer.
In some embodiments, the control chip includes a fourth conductive via, one end of the fourth conductive via is electrically connected to the first metal wiring layer, and a third solder ball bump is formed at the other end of the fourth conductive via, and the third solder ball bump is used for connecting to the memory chip; a fourth solder ball bump is formed above the control port physical layer, the fourth solder ball bump being for connecting to a system port physical layer of the system chip.
In some embodiments, a surface of the system chip opposite to the control chip includes a first area and a second area, wherein a fifth solder ball bump is disposed on the first area, a sixth solder ball bump is disposed on the second area, the fifth solder ball bump is used for connecting with a fourth solder ball bump, the sixth solder ball bump is used for connecting with a second metal wiring layer for signal transmission routing, and an arrangement density of the fifth solder ball bump is greater than an arrangement density of the sixth solder ball bump.
In some embodiments, when the arrangement density of the fifth solder ball bump is greater than or equal to twice the arrangement density of the sixth solder ball bump, the dimension of the fourth solder ball bump in the first direction is greater than the dimension of the fifth solder ball bump in the first direction;
in the case where the arrangement density of the fifth solder ball bumps is less than twice the arrangement density of the sixth solder ball bumps, the size of the sixth solder ball bumps in the first direction is equal to the size of the fifth solder ball bumps in the first direction.
In some embodiments, the package structure includes: a substrate;
the insulating layer is arranged on the surface of the substrate, a second metal wiring layer is formed in the insulating layer, and the second metal wiring layer is electrically connected with the system chip through a sixth solder ball bump.
In a second aspect, the present application provides a chip packaging method, for packaging a chip packaging structure according to the first aspect or any one of possible implementation manners of the first aspect, where the method includes:
providing a memory chip, forming a first conductive through hole, a second conductive through hole and a third conductive through hole on the memory chip, forming a first solder ball bump at the end part of the first conductive through hole, which is positioned on the upper surface of the memory chip, and forming a second solder ball bump at the end part, which is positioned on the lower surface of the memory chip; the arrangement density of the first solder ball bumps is greater than the arrangement density of the second conductive through holes and the arrangement density of the third conductive through holes;
sequentially connecting the first solder ball bumps and the second solder ball bumps of adjacent memory chips to form a memory chip module;
providing a control chip, forming a conductive through hole area on the control chip, forming a metal wiring layer electrically connected with the conductive through hole area on the upper surface of the control chip, forming a third solder ball bump electrically connected with the conductive through hole area on the lower surface of the control chip, and forming a fourth solder ball bump electrically connected with the physical layer of the control port on the upper surface of the control chip;
providing a system chip, and forming fifth solder ball bumps and sixth solder ball bumps on the surface of the system chip opposite to the control chip, wherein the arrangement density of the fifth solder ball bumps is greater than that of the sixth solder ball bumps;
The fifth solder ball bump is connected with the fourth solder ball bump, and the sixth solder ball bump is connected with the second metal wiring layer;
providing a power management module and a test module;
the power management module is connected with the second conductive through hole, and the test module is connected with the third conductive through hole.
In a third aspect, the present application provides an electronic device, including a chip package structure according to the first aspect or any one of the possible implementation manners of the first aspect.
According to the chip packaging structure, the control chip and the power management module are distributed, the control chip and the power management module can be electrically connected through different areas of the storage chip respectively, flexibility of the chip packaging structure is improved, complexity in a processing process can be reduced due to separation of different signal transmission areas, signal crosstalk is reduced, and integrity of signal transmission is improved; the arrangement density of the first solder ball bumps is larger than that of the first conductive through holes, so that the control chip and the memory chip can be partially overlapped in the direction perpendicular to the memory chip according to different signal transmission density requirements, and the electric connection can be realized through the first solder ball bumps in the overlapped area, so that a silicon adapter plate is not used for transferring, the data transmission distance is effectively shortened, and the transmission loss and delay of control signals can be reduced.
Drawings
FIG. 1 is a schematic diagram of a chip package structure 010 according to an embodiment;
FIG. 2 is a schematic diagram of a memory chip in one embodiment;
FIG. 3 is a schematic diagram of a power management module and a test module according to one embodiment;
FIG. 4 is a schematic diagram of a memory stack chip in one embodiment;
FIG. 5 is a schematic diagram of a storage stack module in one embodiment;
FIG. 6 is a schematic diagram of a control chip in one embodiment;
FIG. 7 is a schematic diagram of a system-on-chip structure in one embodiment;
FIG. 8 is a schematic diagram of a system-on-chip structure in one embodiment;
FIG. 9 is a schematic diagram of a second chip package structure 020 according to an embodiment;
FIG. 10 is a schematic diagram of the structure of a substrate and metal wiring layers in one embodiment;
FIG. 11 is a schematic diagram of a packaging step of a memory stack chip in one embodiment;
FIG. 12 is a schematic diagram of a temporary bonding step of a memory stack chip in one embodiment;
FIG. 13 is a schematic diagram of a packaging step of a control chip and a system chip in one embodiment.
FIG. 14 is a schematic diagram of a wafer dicing step in one embodiment.
The above and other objects, features, advantages and embodiments of the present invention will become more apparent by the following description of the attached symbols:
010: chip package structure one, 020: chip package structure two, 100: memory chip, 100_a: upper surface (functional surface) of memory chip, 100_b: lower surface (substrate surface) of memory chip, 101_a: power signal pad, 101_b: test signal pad, 101_c: control signal pad, 102_a: first solder ball bump, 102_b: second solder ball bump, 103_a: first conductive via, 103_b: second conductive via, 103_c: third conductive via, 106: memory chip without third conductive via, 107: glue layer, 108: protective layer, 110: storage stack chip, 111: management wafer, 112: power solder ball bumps, 113: transfer solder ball bumps, 114: testing solder ball bumps, 115, a power management module; 116, a test module; 120: storage stack module, 200: control chip, 201: conductive via area, 202: control port physical layer, 203: control chip insulating layer, 204: first metal wiring layer, 205: third solder ball bump, 206: support bump, 207: fourth solder ball bump, 300_a: system chip one, 300_b: system chip two, 301: system port physical layer, 302: sixth solder ball bump, 303: fifth solder ball bump, 310: metal seed layer, 400: memory module fan out structure wafer, 401: interconnect solder balls, 410: second metal wiring layer, 411: bump, 412: package pads, 420: insulating layer, 421: system chip corresponding pad, 422: control chip corresponds to pad, 430: underfill material, 431: epoxy layer, 432: a first wafer thinning layer; 500: second wafer thinned layer, 510: wafer dicing position, 600: substrate, 600_b: temporary bonding carrier plate, 601: temporary bonding material.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
It will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
With the high-speed development of the HBM technology, the HBM has been developed to HBM3 at present, the single data path (lane) rate reaches 6.4Gbps, the maximum support bit width of a single HBM is 1024 bits, and the bandwidth reaches 819GB/s. In order to cope with the signal integrity problem caused by the increase of bandwidth, the latest generation of HBM3 is designed with related compromises, the size of PHY (Physical, port Physical layer) is increased, the buffer interval is increased in a phase change manner, and the PHY position is changed to be closer to the XPU chip. Taking the latest HBM3 as an example, in the packaging structure, core die realizes multi-slice integration through TSV interconnection, and all data channels are integrated; in addition, the TSVs are connected with a bank power supply in series, and each core Die (DRAM) is isomorphic, so that large-scale production can be realized. Currently, the mainstream method is realized by adopting TCB-NCF (thermal compression bonding-non-conductive adhesive filling), and the manufacturing process can firstly test a chip to obtain KGD (Known Good Die) so as to improve the overall packaging yield; a more advanced approach is to achieve multi-chip stacking by wafer level hybrid-bond, which currently suffers from a relatively low yield. The whole module after stacking (4 Hi, 8Hi and 16 Hi) of the multi-chip DRAM can realize test screening, and the relative acquisition difficulty is lower. The Base die mainly comprises a related DRAM PHY, a power supply and a test signal; the DRAM stacked particles are interconnected by TSVs and DRAM PHYs. HBM particles are finally formed by wafer level packaging. The size of the base die is typically larger than that of the DRAM stack module, but is mainly designed to accommodate the packaging process, and most of the base die area is not functional.
When analyzing the prior art, it is found that the above technical problems mainly include 2 points, one of which is: the transmission distance of the DRAM slice to the SOC_PHY is long. This transmission channel comprises 1: DRAM slice TSV 2: base die RDL 3: hbm_phy:4: silicon interposer RDL 5: SOCHBM_PHY, its transmission length is generally more than 6mm, the main length sources are 2 and 4, the base die RDL length is limited by HBM size in the existing technology, the silicon adapter RDL length is limited by side-by-side packaging mode, can't reduce the length; and two,: the architecture of HBM limits its packaging form, and even though its bump pitch is small, there is a problem of crosstalk when transmitting on the transmission line, and it is still difficult to achieve high density and high bandwidth per unit length interconnection.
Based on the above problems, the invention mainly considers the optimization of the slice and base die interconnection and the SOCHBM_PHY interconnection of the DRAM (distributed RAM) to realize the signal integrity optimization of the system, and can adapt to the faster transmission rate standard in the future. The original HBM architecture is disassembled into a module mainly based on Dram slice and a small HBM_PHY chip. And the Dram slices are interconnected through TSVs, the requirement of bit width expansion is met, and finally, the data channel and the address channel are integrated on the functional surface of the module. And a chip for power management and testing is integrated below the stacked modules, and the whole module can be subjected to test screening through larger C4 (controllable collapse chip interconnection) to improve the overall assembly yield. The hbm_hpy chip will integrate TSV channels and corresponding HBM related IPs, where the TSVs are used for interconnection with the Dram module, and the HBM IPs are interconnected by micro bumps and SOC like chips. The chip can be interconnected with the SOC chip in a face-to-face interconnection mode, and the total length of a transmission path is reduced.
Fig. 1 is a schematic diagram of a chip package structure 010 according to an embodiment of the present invention, fig. 2 is a schematic diagram of a memory chip 100 according to an embodiment, and fig. 3 is a schematic diagram of a power management module and a test module according to an embodiment. As shown in fig. 1 to 3, the chip package structure one 010 includes:
a memory chip 100, the memory chip 100 including a plurality of first solder ball bumps 102_a and a plurality of first conductive vias 103_a; wherein, the arrangement density of the first solder ball bumps 102_a is greater than the arrangement density of the first conductive vias 103_a;
the control chip 200, the projection of the control chip 200 and the memory chip 100 in the first direction at least partially overlaps, the control chip 200 is electrically connected with the memory chip 100 through the first solder ball bump 102_a and transmits a data signal, an address signal or a control signal to the memory chip 100; wherein the first direction is a direction perpendicular to the memory chip 100;
and a power management module 115, wherein the power management module 115 at least partially overlaps with a projection of the memory chip 100 in the first direction, and the power management module 115 is electrically connected to the memory chip 100 through the first conductive via 103_a and supplies power to the memory chip 100.
In some embodiments, as shown in fig. 2, a plurality of signal pads are disposed on the functional surface 100_a of the memory chip 100, and the plurality of signal pads are divided into a power signal pad 101_a, a test signal pad 101_b, and a control signal pad 101_c for data storage/address/control according to functions, wherein the power signal pad 101_a and the test signal pad 101_b are located at ends of the first conductive via 103_a and the second conductive via 103_b near the functional surface 100_a of the memory chip 100, respectively. A first solder ball bump 102_a is formed over the control signal pad 101_c for connecting the control chip 200. On the substrate surface 100_b of the memory chip 100, second solder ball bumps 102_b are formed at the ends of the first conductive via 103_a and the second conductive via 103_b, corresponding to the positions of the first solder ball bumps 102_a. As shown in fig. 3, the power management module 115 and the test module 116 are integrated on the management wafer 111, the power management module 115 and the test module 116 respectively have a power solder ball bump 112 and a test solder ball bump 114 for connecting the memory chip 100, and the power management module 115 and the test module 116 are connected with the solder ball bump on the substrate surface of the management wafer 111 through conductive vias, so as to be able to connect to a metal wiring layer connected with the system chip, and acquire power or test signals. When the chip package structure includes a plurality of power management modules 115, a set of power signal pads 101_a and first conductive vias 103_a may be disposed corresponding to each power management module 115, for example, as shown in fig. 3 or fig. 4, the package structure includes two power management modules 115, and a set of power signal pads 101_a and first conductive vias 103_a are disposed on two sides of the memory chip 100.
The power management module 115, the second solder ball bump 102_b, the first conductive via 103_a, and the power pad are electrically connected in sequence, so as to form a data transmission channel for transmitting a power signal to the memory chip 100, and the control chip 200 is connected to the first solder ball bump 102_a, so as to form a data transmission channel for transmitting a control signal to the memory chip 100.
In the chip packaging structure, the control chip 200 and the power management module 115 can be electrically connected through different areas of the memory chip 100, so that the flexibility of the chip packaging structure is improved, the complexity of a processing process can be reduced due to separation of different signal transmission areas, signal crosstalk is reduced, and the integrity of signal transmission is improved; the arrangement density of the first solder ball bumps 102_a is greater than that of the first conductive through holes 103_a, so that different signal transmission densities can be adapted; the demand control chip 200 and the memory chip 100 are partially overlapped in a direction perpendicular to the memory chip 100, and can be electrically connected through the first solder ball bump 102_a in the overlapped region, so that the transfer can be performed without using a silicon transfer board, the data transmission distance is effectively shortened, and the transmission loss and delay of control signals can be reduced. The first, second, and third conductive vias 103_a, 103_b, 103_c may be vertical TSV channels.
In some embodiments, as shown in fig. 1 to 3, the package structure further includes:
a test module 116 for testing the memory chip 100 according to the input data;
the memory chip 100 includes a second conductive via 103_b, and the test module 116 is electrically connected to the memory chip 100 through the second conductive via 103_b and transmits a test signal to the memory chip 100 module.
The control chip 200, the second solder ball bump 102_b, the second conductive via 103_b, and the test signal pad 101_b are electrically connected in sequence, and form a data transmission channel for transmitting a test signal to the memory chip 100.
Fig. 4 is a schematic diagram of a structure of a memory stack chip 110 in one embodiment. As shown in fig. 4, in some embodiments, the package structure includes a plurality of memory chips 100; the plurality of memory chips 100 constitute a memory stack chip 110; the memory chip 100 includes a third conductive via 103_c, and a first solder ball bump 102_a and a second solder ball bump 102_b are formed at both ends of the third conductive via 103_c, respectively, wherein two adjacent memory chips 100 are electrically connected through the first solder ball bump 102_a, the first conductive via 103_a and the second solder ball bump 102_b in sequence, and the control chip 200 is electrically connected with the memory chip 100 through the first solder ball bump 102_a, the third conductive via 103_c and the second solder ball bump 102_b and transmits a data signal, an address signal or a control signal to the memory chip. The adjacent memory chips 100 are bonded and fixed by an adhesive layer 107, and the uppermost functional surface 100_a is protected by a protective layer 108.
As shown in fig. 4, in the memory stack chip 110 in which a plurality of memory chips 100 are stacked, the memory chip 100 located at the lowermost layer for directly electrically connecting with the power management module 115 and the test module 116 is not provided with the third conductive via 103_c, the first solder ball bump 102_a of the memory chip 100 is directly formed on the functional surface 100_a thereof, and the second solder ball bump 102_b is directly formed on the substrate surface 100_b. The other memory chips 100 are provided with third conductive vias 103_c, and two ends of the third conductive via 103_c are respectively connected to the first solder ball bump 102_a and the second solder ball bump 102_b. The lowermost memory chip 100 is electrically connected to the adjacent memory chips 100 through the first solder ball bump 102_a, and the remaining adjacent memory chips 100 are electrically connected to each other through the first solder ball bump 102_a, the third conductive via 103_c, and the second solder ball bump 102_b.
FIG. 5 is a schematic diagram of a storage stack module 120 in one embodiment. As shown in fig. 5 to 6, after the plurality of memory chips 100 form the memory stack chip 110, the second solder ball bump 102_b of the substrate layer of the lowest memory chip 100 is electrically connected to the power management module 115 and the test module 116, and the whole of the management wafer 111 is referred to as a memory stack module 120.
In some embodiments, the control chip 200 includes a control port physical layer 202, the control port physical layer 202 being electrically connected to the memory chip 100 through a first metal wiring layer 204; the package structure further includes: a system chip including a system port physical layer 301; the system chip 300 is electrically connected to the control port physical layer 202 through the system port physical layer 301.
In some embodiments, the control chip 200 includes a fourth conductive via having one end electrically connected to the first metal wiring layer 204 and the other end formed with a third solder ball bump 205, the third solder ball bump 205 being used to connect the memory chip 100; a fourth solder ball bump 207 is formed over the control port physical layer 202, the fourth solder ball bump 207 being for connecting to the system port physical layer of the system chip 300.
Fig. 6 is a schematic structural diagram of a control chip 200 in one embodiment. As shown in fig. 6, the control chip 200 includes a control port physical layer 202, a first metal wiring layer 204, and a conductive via region 201, one end of the conductive via region 201 is connected to the control port physical layer 202 through the first metal wiring layer 204, and the other end is formed with a third solder ball bump 205 for connecting the memory chip 100 or the memory stack module 120. A fourth solder ball bump 207 is formed over the control port physical layer 202 for connecting to the system chip. The substrate layer of the control chip 200 is also formed with support bumps 206 in areas other than the metal via areas, which serve as support during the packaging process.
Fig. 7 is a schematic structural diagram of a system chip in one embodiment, and fig. 8 is a schematic structural diagram of a system chip in another embodiment, where the system chips in fig. 7 and fig. 8 are referred to as a system chip one 010 and a system chip two 020, respectively, for convenience of description. As shown in fig. 7, the system chip one includes a system port physical layer 301, and a fifth solder bump 303 is formed on the system port physical layer 301, and since the system chip needs to have other functions in addition to providing the IP function for the control chip 200, a sixth solder bump 302 is formed on a functional surface of the system chip except for the area of the system port physical layer 301, and the density requirements for the solder bumps are different when different signals are transmitted, so that the arrangement density of the fifth solder bump 303 is the same as the arrangement density of the fourth solder bump 207 on the control chip 200, and the arrangement density of the sixth solder bump 302 can be set according to the actual transmission requirement.
As shown in fig. 7 or fig. 8, in some embodiments, the surface of the system chip 300 opposite to the control chip 200 includes a first area and a second area, where a fifth solder bump 303 is disposed on the first area, a sixth solder bump 302 is disposed on the second area, the fifth solder bump 303 is used to connect to the fourth solder bump 207, the sixth solder bump 302 is used to connect to the second metal wiring layer 410 used for signal transmission routing, and the arrangement density of the fifth solder bump 303 is greater than that of the sixth solder bump 302.
As shown in fig. 7, in some embodiments, when the arrangement density of the fifth solder ball bumps 303 is greater than or equal to twice the arrangement density of the sixth solder ball bumps 302, the size of the sixth solder ball bumps 302 in the first direction is greater than the size of the fifth solder ball bumps 303 in the first direction; as shown in fig. 8, in the case where the arrangement density of the fifth solder ball bumps 303 is less than twice the arrangement density of the sixth solder ball bumps 302, the size of the sixth solder ball bumps 302 in the first direction is equal to the size of the fifth solder ball bumps 303 in the first direction.
Fig. 9 is a schematic diagram of a chip package structure in another embodiment, and fig. 10 is a schematic diagram of a structure of a substrate and a metal wiring layer in one embodiment. As shown in fig. 8 to 10, the package structure includes: a substrate; an insulating layer 420 disposed on the substrate surface, wherein a second metal wiring layer 410 is formed in the insulating layer 420, and the second metal wiring layer 410 is electrically connected to the system chip 300 through the sixth solder bump 302.
As shown in fig. 9 to 10, a temporary bonding material layer is coated on the substrate, a second metal wiring layer 410 and an insulating material layer are formed on the temporary bonding material layer through a re-wiring process and the like, the package pad and the signal pad are electrically connected through the second metal wiring layer 410, a bump 411 is provided on the second metal wiring layer 410, the bump 411 is used for connecting a system chip, as shown in fig. 11, both ends of the bump 411 are respectively connected with the second metal wiring layer and a system chip corresponding pad 421 for connecting the system chip, and the height of the bump 411 is adapted to the size of the storage stack module 120, i.e., the height of the bump 411 is not less than the height of the storage stack module 120 so as to connect the system chip. As shown in fig. 10 to 11, after the second metal wiring layer 410 is processed, the storage stacking module 120 is mounted on the second metal wiring layer 410, and the solder ball bumps are protected by the underfill material 430, and then the storage stacking module 120 and the bumps are covered by the epoxy resin layer 431 to form a wafer-like structure, and the thickness of the first wafer thin layer 432 above the storage stacking module 120 is thinned by the wafer thinning method, so that the bumps on the surface of the storage stacking module 120 and the bumps connected with the second metal wiring layer are exposed, and the corresponding pads 422 of the control chip for connecting the control chip are formed by the re-wiring process.
Based on the same inventive concept, the embodiment of the application also provides a chip packaging method based on the chip packaging structure. The solution to the problem provided by this method is similar to the implementation described in the apparatus described above, so the specific limitations in one or more chip packaging method embodiments provided below may be found in the limitations of the chip stack module 120 above. The method comprises the following steps:
providing the memory chip 100 as shown in fig. 5, forming a first conductive via 103_a, a second conductive via 103_b and a third conductive via 103_c on the memory chip 100, forming a first solder ball bump 102_a at an end of the first conductive via 103_a on the upper surface of the memory chip 100, and forming a second solder ball bump 102_b at an end of the lower surface; wherein the arrangement density of the first solder ball bumps 102_a is greater than the arrangement density of the second conductive vias 103_b and the arrangement density of the third conductive vias 103_c;
sequentially connecting the first solder ball bump 102_a and the second solder ball bump 102_b of adjacent memory chips 100 to form a memory chip 100 module;
providing a control chip 200, forming a conductive through hole region 201 on the control chip 200, forming a metal wiring layer electrically connected to the conductive through hole region 201 on the upper surface of the control chip 200, forming a third solder ball bump 205 electrically connected to the conductive through hole region 201 on the lower surface of the control chip 200, and forming a fourth solder ball bump 207 electrically connected to the control port physical layer 202 on the upper surface of the control chip 200;
Providing a system chip, forming a fifth solder ball bump 303 and a sixth solder ball bump 302 on a surface of the system chip opposite to the control chip 200, wherein an arrangement density of the fifth solder ball bump 303 is greater than an arrangement density of the sixth solder ball bump 302;
the fourth solder ball bump 207 is connected through the fifth solder ball bump 303, and the second metal wiring layer 410 is connected through the sixth solder ball bump 302;
providing a power management module 115 and a test module 116;
the power management module 115 is connected through the second conductive via 103_b and the test module 116 is connected through the third conductive via 103_c.
In one exemplary embodiment, a method of chip packaging is provided, the method comprising the steps of:
step 102: and processing the memory chip.
The processing of TSVs and bumps is performed on the monolithic memory chip 100, so that signal routing and connection of the memory chip front side functional surface 100_a and the memory chip back side substrate surface 100_b can be realized. The specific chip functional surface 100_a has connection points available for subsequent processes, and can be divided into a power signal pad 101_a, a test signal pad 101_b, and a control signal pad 101_c for data storage/address/control signals according to functions. An interconnected TSV structure is formed beside the pads, and the vertical TSV channels 103_a for connecting the power signal pad 101_a, the vertical TSV channel 103_b for connecting the test signal pad 101_b, and the vertical TSV channel 103_c for connecting the control signal pad 101_c are respectively formed, and finally, the second solder ball bump 102_b for soldering is formed on the memory chip substrate surface 100_b, and the first solder ball bump 102_a corresponding to the control signal pad 101_c is reserved on the memory chip front surface 100_a for interconnection of subsequent chips and control chips.
Step 104: processing the memory stacked chips.
The stacking of layers (4 Hi, 8Hi, 16Hi, etc.) may be implemented according to the storage capacity requirements, as exemplified by the conventional TCB-NCF process. The memory chips 100 with the Hi-1 number are stacked and packaged by TCB-NCF, the interconnection between the chips 100 is realized by the first solder ball bump 102_a and the second solder ball bump 102_b, and the whole structure realizes the reliable packaging structure by forming the adhesive layer 107 by NCF (non-flowing underfill film) to realize the adhesion between the chips, and the protective layer 108 is added on the front surface of the stacked chips 110, so that the first solder ball bump 102_a is protected in the subsequent process. A piece of memory chip 106 without the vertical TSV channel 103_b of the connection 101_b is prepared again, so that the entire memory stack chip 110 is assembled, which mainly includes the memory chip 100 stacked with the Hi-1 layer, and the memory chip 106 without the vertical TSV channel 103_b. A management wafer 111 for integrated power management and signal testing is prepared, on which are formed power solder bumps 112 corresponding to the second solder bumps 102_b of the memory stack chip 110 for interconnection bonding, and the entire power, test portion is transferred to the transfer solder bumps 113 of the management wafer 111 through TSVs. Eventually forming a storage stack module 120.
Step 106: a processing control chip and an SOC chip.
The data signal of the storage stack module 120 cannot be directly given to the SOC, and must be implemented through corresponding HBM control, logic layer, and physical layer. The control chip 200 may implement this function. The control chip 200 is interconnected with the first solder ball bump 102_a of the memory stack module 120 through the third solder ball bump 205, and the interconnection of signals is achieved through the conductive via area 201. Interconnection of the signal and control port physical layer (phy_ip region) 202 is achieved through a first metal wiring layer 204 on the functional surface of the control chip 200, and the control chip insulating layer 203 is made of a material such as silicon nitride or silicon oxide to protect the metal wiring layer, and a fourth solder ball bump 207 corresponding to the system port physical layer (SOC phy_ip region) is formed above the control port physical layer (phy_ip region) 202. The SOC chip 300 has many other IP functions besides integrating the corresponding Dram IP, the bump density required for these IP functions is different, the difference between the bump pitch on the physical layer 301 of the system port and the bump pitch on the physical layer 301 of the system port will be divided into two cases, one is that the conventional sixth solder bump 302 pitch is greater than the fourth solder bump 207 pitch by more than 2 times, in which case it is difficult to make bumps with the same height, based on which the sixth solder bump 302 with different specifications from the fifth solder bump 303 is directly processed according to the conventional bump preparation method, so as to obtain the SOC chip 300_a. Alternatively, as shown in fig. 8, if the pitch ratio is 2 times or less, the bump heights of the two regions may be considered to be the same, but the bump diameters will be set to be different according to the chip size and other requirements, the fifth solder bump 303 with a relatively smaller size is used at the dram PHY IP-compliant connection, and the sixth solder bump 302 with a relatively larger size is used at the other region.
Step 108: and processing the embedded storage stacked chip fan-out structure.
A wafer level substrate 600 for temporarily carrying chips is prepared, and may be a silicon wafer or glass having a coefficient of expansion matching with a subsequent process according to different processes. The substrate 600 is coated with a temporary bonding material 601 having a uniform thickness, which can satisfy the subsequent processing without problems of delamination, tearing, deformation, etc., and can be removed by a specific process, and generally the material is matched with the substrate 600. A process such as re-wiring is performed on the temporary bonding material, and finally an insulating layer 420 using polyimide as a main material and a second metal wiring layer 410 for signal transmission routing are formed. The package pads 412 and the signal pads of the chip and the bumps 411 are interconnected by the wirings of the wiring layer.
Step 110: the memory stack chip is mounted to the buried memory stack chip fan-out structure.
And physically protecting the transfer solder ball bumps 113 of the storage stack module 120 by the underfill material 430; the storage stack module 120 and the bump 411 are then all covered and reconstructed into a wafer-like structure by the epoxy layer 431 by means of wafer-level plastic packaging. The thickness of the first wafer thinning layer 432 above the storage stacking module 120 is thinned by a wafer level thinning manner, the bumps and the bumps 411 on the front surface of the storage stacking module 120 are exposed and a rewiring process is performed, and the fan-out of the control chip corresponding pad 422 corresponding to the control chip 200 is performed through the insulating layer 420 and the system chip corresponding pad 421 corresponding to the SOC 300, so that the complete wafer 400 with the embedded storage stacking chip fan-out structure is finally formed.
Step 112: and (5) packaging and integrating.
The singulated control chip 200 is mounted on the wafer 400 with the embedded memory stack chip fan-out structure, the third solder ball bump 205 and the corresponding pad 422 of the system chip on the wafer form interconnection, and the supporting bump 206 plays a role in supporting. The SOC chip 300_a is mounted to the memory module fan-out structure wafer 400 with the sixth solder ball bump 302 and the system chip corresponding pad 421 forming an electrical interconnect thereon. After the mounting is completed, the bumps of the chips are protected by adopting an underfilling material 430; the wafer-level plastic packaging process is adopted to protect the whole wafer by utilizing the epoxy resin layer 431, the thickness of the second wafer thinning layer 500 is thinned by utilizing the wafer plastic packaging thinning process, the substrate silicon of the SOC chip is ground out, and finally, the metal seed layer 310 is sputtered on the back surface of the whole package in a metal sputtering mode for the interface IMC of the subsequent radiating fin, so that the packaged chip and the TIM heat conducting glue are reinforced.
The temporary bonding material 601 is coated on the sputtered surface, the fan-out structure and the temporary bonding carrier 600_b are temporarily bonded, the bonding material and the bonding carrier of the implant surface are removed, the related residues and seed layers are cleaned, and finally wafer ball implantation is performed on the package pads 412 to form the interconnection solder balls 401.
After the debonding, dicing and sorting are completed by wafer dicing, as shown in fig. 14, 510 is a wafer dicing position, and finally a single embedded memory particle packaging fan-out module, that is, a chip packaging structure 010 is obtained. If the SOC chip is the structure shown in fig. 8, the chip package structure 020 as shown in fig. 9 is formed after the package is completed.
In one embodiment, there is provided an electronic apparatus including the chip package structure in the above-described respective apparatus embodiments, or including the chip package structure obtained by the above-described respective method embodiments.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A chip package structure, the package structure comprising:
a memory chip including a plurality of first solder ball bumps and a plurality of first conductive vias; wherein the arrangement density of the first solder ball bumps is greater than the arrangement density of the first conductive vias;
the control chip is at least partially overlapped with the projection of the storage chip in the first direction, is electrically connected with the storage chip through the first solder ball bump and transmits a data signal, an address signal or a control signal to the storage chip; wherein the first direction is a direction perpendicular to the memory chip;
the power management module is at least partially overlapped with the projection of the memory chip in the first direction, and is electrically connected with the memory chip through the first conductive through hole and supplies power to the memory chip.
2. The package structure of claim 1, further comprising:
the test module is used for testing the memory chip according to the input data;
the memory chip comprises a second conductive through hole, and the test module is electrically connected with the memory chip through the second conductive through hole and sends a test signal to the memory chip module.
3. The package structure of claim 1, wherein the package structure comprises a plurality of memory chips; the plurality of memory chips constitute a memory stack chip;
the memory chip comprises a third conductive through hole, the two ends of the third conductive through hole are respectively provided with the first solder ball bump and the second solder ball bump, wherein two adjacent memory chips are electrically connected through the first solder ball bump, the first conductive through hole and the second solder ball bump in sequence, and the control chip is electrically connected with the memory chip through the first solder ball bump, the first conductive through hole and the second solder ball bump and transmits data signals, address signals or control signals to the memory chip.
4. The package structure of claim 1, wherein the control chip comprises a control port physical layer electrically connected to the memory chip through a first metal wiring layer;
the package structure further includes:
a system chip including a system port physical layer; the system chip is electrically connected with the control port physical layer through the system port physical layer.
5. The package structure according to claim 4, wherein the control chip includes a fourth conductive via having one end electrically connected to the first metal wiring layer and the other end formed with a third solder ball bump for connecting to the memory chip; and a fourth solder ball bump is formed above the control port physical layer and is used for connecting with the system port physical layer of the system chip.
6. The package structure according to claim 5, wherein a surface of the system chip opposite to the control chip includes a first area and a second area, wherein a fifth solder bump is disposed on the first area, a sixth solder bump is disposed on the second area, the fifth solder bump is used for connecting the fourth solder bump, the sixth solder bump is used for connecting a second metal wiring layer for signal transmission routing, and an arrangement density of the fifth solder bump is greater than an arrangement density of the sixth solder bump.
7. The package structure according to claim 6, wherein when an arrangement density of the fifth solder ball bumps is greater than or equal to twice an arrangement density of the sixth solder ball bumps, a dimension of the fourth solder ball bumps in the first direction is greater than a dimension of the fifth solder ball bumps in the first direction;
in the case where the arrangement density of the fifth solder ball bumps is less than twice the arrangement density of the sixth solder ball bumps, the dimension of the sixth solder ball bumps in the first direction is equal to the dimension of the fifth solder ball bumps in the first direction.
8. The package structure of claim 6, wherein the package structure comprises:
A substrate;
and the insulating layer is arranged on the surface of the substrate, a second metal wiring layer is formed in the insulating layer, and the second metal wiring layer is electrically connected with the system chip through a sixth solder ball bump.
9. A chip packaging method for the chip packaging structure of any one of claims 1 to 8, the method comprising:
providing a storage chip, forming a first conductive through hole, a second conductive through hole and a third conductive through hole on the storage chip, forming a first solder ball bump at the end part of the first conductive through hole, which is positioned on the upper surface of the storage chip, and forming a second solder ball bump at the end part, which is positioned on the lower surface of the storage chip; wherein the arrangement density of the first solder ball bumps is greater than the arrangement density of the second conductive vias and the arrangement density of the third conductive vias;
sequentially connecting the first solder ball bumps and the second solder ball bumps of adjacent memory chips to form a memory chip module;
providing a control chip, forming a conductive through hole area on the control chip, forming a metal wiring layer electrically connected with the conductive through hole area on the upper surface of the control chip, forming a third solder ball bump electrically connected with the conductive through hole area on the lower surface of the control chip, and forming a fourth solder ball bump electrically connected with the control port physical layer on the upper surface of the control chip;
Providing a system chip, and forming a fifth solder ball bump and a sixth solder ball bump on the surface of the system chip opposite to the control chip, wherein the arrangement density of the fifth solder ball bump is greater than that of the sixth solder ball bump;
the fourth solder ball bump is connected through the fifth solder ball bump, and the second metal wiring layer is connected through the sixth solder ball bump;
providing a power management module and a test module;
and the second conductive through hole is connected with the power management module, and the third conductive through hole is connected with the test module.
10. An electronic device comprising the chip package structure of any one of claims 1-8.
CN202311620205.5A 2023-11-29 2023-11-29 Chip packaging structure, method and electronic equipment Pending CN117577614A (en)

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