CN117577530A - Preparation method of gallium nitride power electronic device and device - Google Patents
Preparation method of gallium nitride power electronic device and device Download PDFInfo
- Publication number
- CN117577530A CN117577530A CN202311395016.2A CN202311395016A CN117577530A CN 117577530 A CN117577530 A CN 117577530A CN 202311395016 A CN202311395016 A CN 202311395016A CN 117577530 A CN117577530 A CN 117577530A
- Authority
- CN
- China
- Prior art keywords
- gallium nitride
- single crystal
- crystal substrate
- electronic device
- power electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 165
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 163
- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 239000013078 crystal Substances 0.000 claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 238000003780 insertion Methods 0.000 claims abstract description 38
- 230000037431 insertion Effects 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 37
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 22
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 239000002131 composite material Substances 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 9
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052723 transition metal Inorganic materials 0.000 claims description 8
- -1 transition metal chalcogenide Chemical class 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims description 4
- 229910000085 borane Inorganic materials 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000007781 pre-processing Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 16
- 230000004888 barrier function Effects 0.000 abstract description 13
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 16
- 239000012071 phase Substances 0.000 description 12
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000002207 thermal evaporation Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004506 ultrasonic cleaning Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000005428 wave function Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000007605 air drying Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009830 intercalation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H01L29/66462—
-
- H01L29/452—
-
- H01L29/778—
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a preparation method of a gallium nitride power electronic device and the device, wherein the preparation method comprises the following steps: providing a gallium nitride single crystal substrate; preparing an insertion layer on the bottom surface of the gallium nitride single crystal substrate; wherein the interposer comprises a two-dimensional material having metallic or semi-metallic properties; and preparing a bottom electrode on one side of the insertion layer far away from the gallium nitride single crystal substrate, and preparing a top electrode on the top surface of the gallium nitride single crystal substrate to obtain the gallium nitride power electronic device. Because the two-dimensional material with metal or semi-metal is used as the insertion layer of the metal-semiconductor contact interface, the influence caused by Fermi pinning at the interface can be reduced or eliminated, the Schottky barrier height is reduced, the contact resistance is smaller, and the ohmic contact performance of the nitrogen face of the gallium nitride device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device preparation, in particular to a preparation method of a gallium nitride power electronic device and the device.
Background
Gallium nitride is used as an excellent semiconductor material and has the characteristics of wide band gap, high saturation drift speed, higher heat conductivity and the like. The gallium nitride conductive substrate has wide application prospect and covers a plurality of fields such as high-frequency electronic devices, optoelectronic devices, photoelectric detectors, power electronic devices, solar cells and the like.
In the related art, the electrical contact resistance of the metal-semiconductor interface is a key and urgent problem to be solved in the semiconductor industry, and the quality of the electrical contact resistance has a great influence on the final performance of the gallium nitride electronic device. However, the gallium (Ga) and nitrogen (N) faces of gallium nitride epitaxial wafers have more complex surface states than the N faces due to their different surface properties, which results in higher schottky barrier heights (Schottky Barrier Height, SBH) while large schottky barrier heights (Schottky Barrier Height, SBH) severely hamper charge injection efficiency, thereby reducing the ohmic performance of the fabricated gallium nitride devices.
Disclosure of Invention
The invention aims to solve the technical problem of larger Schottky barrier height of a nitrogen surface of a gallium nitride epitaxial wafer in the related art.
In order to solve the technical problem, a first aspect of the present invention provides a method for preparing a gallium nitride power electronic device, including:
providing a gallium nitride single crystal substrate;
preparing an insertion layer on the bottom surface of the gallium nitride single crystal substrate; wherein the insertion layer comprises a two-dimensional material having metallic or semi-metallic properties;
and preparing a bottom electrode on one side of the insertion layer far away from the gallium nitride single crystal substrate, and preparing a top electrode on the top surface of the gallium nitride single crystal substrate to obtain the gallium nitride power electronic device.
Optionally, the step of preparing an insertion layer on the bottom surface of the gallium nitride single crystal substrate includes:
and transferring the two-dimensional material film to the bottom surface of the gallium nitride single crystal substrate by utilizing wet transfer to obtain an insertion layer.
Optionally, the transferring the two-dimensional material film to the bottom surface of the gallium nitride single crystal substrate by wet transfer to obtain an insertion layer includes:
epitaxially growing on the gallium nitride single crystal substrate to obtain a gallium nitride epitaxial wafer;
preprocessing the gallium nitride epitaxial wafer;
spin-coating PMMA on the surface of a metal matrix with a two-dimensional material film to obtain a PMMA film;
heating the metal matrix to solidify the PMMA film;
placing the cured metal matrix into an etching solution to etch and remove the metal layer, so as to obtain the PMMA-two-dimensional material composite film;
and drying the PMMA-two-dimensional material composite film, placing the dried PMMA-two-dimensional material composite film on the bottom surface of the gallium nitride epitaxial wafer, and removing the PMMA film to obtain the insert layer attached to the bottom surface of the gallium nitride epitaxial wafer.
Optionally, the two-dimensional material includes any one of a metallic transition metal chalcogenide, a semi-metallic transition metal chalcogenide, a borane, and a semi-metallic chloride.
Optionally, the thickness of the insertion layer ranges from 0.5nm to 10nm.
Optionally, the step of preparing a bottom electrode on a side of the insertion layer away from the gallium nitride single crystal substrate includes:
evaporating a metal film on one side of the insertion layer far away from the gallium nitride single crystal substrate;
and annealing the metal film to obtain the bottom electrode.
Optionally, before the step of preparing the insertion layer on the bottom surface of the gallium nitride single crystal substrate, the method further includes:
epitaxially growing an n-type gallium nitride drift layer on the top surface of the gallium nitride single crystal substrate;
and implanting ions into one side of the n-type gallium nitride drift layer, which is far away from the gallium nitride single crystal substrate, according to a first preset pattern to form a terminal protection ring with a box-shaped outline.
Optionally, the step of implanting ions according to a first preset pattern on the side of the n-type gallium nitride drift layer away from the gallium nitride single crystal substrate to form a terminal protection ring with a box-shaped profile includes:
preparing a first preset pattern on one side of the n-type gallium nitride drift layer far away from the gallium nitride single crystal substrate;
forming a mesa structure by plasma etching according to the first preset pattern;
preparing a second preset pattern on the mesa structure;
and implanting ions on the mesa structure according to the second preset pattern to form a terminal protection ring with a box-shaped outline.
Optionally, the step of preparing a top electrode on the top surface of the gallium nitride single crystal substrate includes:
and evaporating a metal film on one side of the terminal guard ring far away from the n-type gallium nitride drift layer to form a top electrode.
The second aspect of the present invention provides a gallium nitride power electronic device, which is manufactured by adopting the manufacturing method of the gallium nitride power electronic device, wherein the gallium nitride power electronic device comprises a gallium nitride single crystal substrate, an insertion layer, a bottom electrode, an n-type gallium nitride drift layer, a terminal protection ring and a top electrode, and the bottom electrode, the insertion layer, the gallium nitride single crystal substrate, the n-type gallium nitride drift layer, the terminal protection ring and the top electrode are stacked from bottom to top.
Compared with the related technology, the preparation method of the gallium nitride power electronic device and the device have the beneficial effects that: because the two-dimensional material with metal or semi-metal is used as the insertion layer of the metal-semiconductor contact interface, the influence caused by Fermi pinning at the interface can be reduced or eliminated, the Schottky barrier height is reduced, the contact resistance is smaller, and the ohmic contact performance of the nitrogen face of the gallium nitride device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a basic flowchart of a method for manufacturing a gallium nitride power electronic device according to an embodiment of the present invention;
fig. 2 is a detailed flowchart of a method for manufacturing a gallium nitride power electronic device according to an embodiment of the present invention;
fig. 3 is a block diagram of a method for manufacturing a gallium nitride power electronic device according to an embodiment of the present invention;
fig. 4 is a cross-sectional view of a gallium nitride power electronic device provided by an embodiment of the invention.
In the drawings, each reference numeral denotes: 1. a gallium nitride single crystal substrate; 2. an interposer layer; 3. a bottom electrode; 4. an n-type gallium nitride drift layer; 5. a terminal protection ring; 6. a top electrode.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below are exemplary and intended to illustrate the present invention and should not be construed as limiting the invention, and all other embodiments, based on the embodiments of the present invention, which may be obtained by persons of ordinary skill in the art without inventive effort, are within the scope of the present invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "circumferential", "radial", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplify the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Examples:
referring to fig. 1, an embodiment of the present invention provides a method for manufacturing a gallium nitride power electronic device, including the following steps:
step S10: a gallium nitride single crystal substrate is provided.
Specifically, the gallium nitride single crystal substrate may be doped with Si, and the thickness of the gallium nitride single crystal substrate is in the range of 200 μm to 800 μm, for example, 200 μm, 300 μm, 500 μm, 600 μm, 800 μm, etc., preferably 300 μm, and the top surface and the bottom surface of the gallium nitride single crystal substrate are polished.
Step S11: an insertion layer is prepared on the bottom surface of the gallium nitride single crystal substrate.
Specifically, the bottom surface of the gallium nitride single crystal substrate is a nitrogen surface, and the insertion layer is arranged on the nitrogen surface; the insertion layer comprises a two-dimensional material with metallic or semi-metallic properties, namely the insertion layer is a two-dimensional material layer, wherein the two-dimensional material can be directly provided with metallic or semi-metallic properties, or the two-dimensional material can be indirectly provided with metallic or semi-metallic properties after being modified in a doping mode or the like.
Step S12: and preparing a bottom electrode on one side of the insertion layer far away from the gallium nitride single crystal substrate, and preparing a top electrode on the top surface of the gallium nitride single crystal substrate to obtain the gallium nitride power electronic device.
Specifically, the bottom electrode is a cathode, and the metal material used for the bottom electrode can be Ti/Al/Ni/Au or Ti/Au; the top electrode is an anode, and the metal material used for the top electrode can be Ni/Au or Gr/Au. In a specific example, the bottom electrode is Ti (25 nm), or Al (100 nm), or Ni (20 nm), or Au (60 nm), and the top electrode is Ni (20 nm), or Au (100 nm).
In the embodiment of the invention, as the two-dimensional material with metal or semi-metal is used as the insertion layer of the metal-semiconductor contact interface, the influence caused by Fermi pinning at the interface can be reduced or eliminated, the Schottky barrier height is reduced, the contact resistance is smaller, and the ohmic contact performance of the nitrogen face of the gallium nitride device is improved.
It should be noted that, the formation of the schottky barrier mainly has two reasons: (I) The energy difference between the metal work function and the semiconductor electron affinity; (II) Metal Induced Gap State (MIGS), resulting in fermi pinning. MIGS is the fact that when a semiconductor is very close to a metal surface, the spread wave function from the metal disturbs the environment of the semiconductor, resulting in a remixing of the original wave function of the semiconductor, i.e. when the metal is in contact with the semiconductor, a new resonance state occurs. The density of MIGS is determined by the valence and conduction bands. The fermi level of the metal-semiconductor system is pinned near the branching point of these two components (known as gap state pinning) in an energy-favorable state in the absence of residual charge. Schottky barriers are unavoidable if the fermi level of the system is within the semiconductor bandgap.
The semi-metal is a metal having a carrier concentration of about 10 22 cm -3 -10 17 cm -3 ) A class of materials far below normal metals is collectively referred to as its Conduction band (Conduction band, CB) and Valence Band (VB) are closely spaced or in contact, and electron density near the fermi level is near zero, which can be characterized by both metallic and semiconductor properties. Thus, the semi-metal hardly induces MIGS, or MIGS can be greatly reduced or even zero when the fermi level of the semi-metal approaches the bottom of the conduction band of the semiconductor; at this point, the semiconductor in contact with the semi-metal will be in a degenerate state and there will be no schottky barrier at the interface.
Referring to fig. 2, the embodiment of the invention also provides a refinement preparation method of the gallium nitride power electronic device, which comprises the following steps:
step S20: a gallium nitride single crystal substrate is provided.
Step S21: an n-type gallium nitride drift layer is epitaxially grown on the top surface of the gallium nitride single crystal substrate.
Specifically, the thickness of the n-type GaN drift layer may be 20 μm, and the n-type GaN drift layer may be doped with Si, ge, mg, be, zn, C, etc., for example, the Si doping amount may be 2×10 16 cm -3 . The n-type gallium nitride drift layer may be grown on the cleaned gallium nitride single crystal substrate by a Metal Organic Chemical Vapor Deposition (MOCVD) method or a Hydride Vapor Phase Epitaxy (HVPE) method.
Step S22: and implanting ions according to a first preset pattern on one side of the n-type gallium nitride drift layer far away from the gallium nitride single crystal substrate to form a terminal protection ring with a box-shaped outline.
Specifically, the step S22 includes the following steps:
step S220: a first preset pattern is prepared on one side of the n-type gallium nitride drift layer away from the gallium nitride single crystal substrate.
Specifically, a first preset pattern is prepared on one side of the n-type gallium nitride drift layer, which is far away from the gallium nitride single crystal substrate, through first photoetching.
Step S221: and forming the mesa structure by plasma etching according to the first preset pattern.
Specifically, the plasma may be BCl 3 /Cl 2 The etching depth may be 1 μm; the mesa structure on the n-type gallium nitride drift layer is specifically formed by plasma etchingThe islands are independent of each other, devices can be manufactured on each island, so that more devices can be manufactured, and the devices cannot interfere with each other, so that the mesa structure plays a role of an isolation region and a role of a mark point.
Step S222: a second predetermined pattern is prepared on the mesa structure.
Specifically, the photoresist is removed and then a second predetermined pattern is prepared on the mesa structure by a second photolithography.
Step S223: ion implantation is performed on the mesa structure according to a second preset pattern to form a terminal guard ring with a box-shaped outline.
Specifically, he ions are implanted at room temperature at an incident angle of 7 ° and a dose of 1×10 15 cm -2 Two energy levels of 150keV and 50keV are implanted down to form a termination guard ring with a box-like profile of depth 0.8 μm. Wherein He ions may be replaced with Mg, C, H, F plasma.
Step S23: and transferring the two-dimensional material film to the bottom surface of the gallium nitride single crystal substrate by utilizing wet transfer to obtain an insertion layer.
Specifically, the step S23 specifically includes the following steps:
step S230: and (5) epitaxially growing on the gallium nitride single crystal substrate to obtain the gallium nitride epitaxial wafer.
Specifically, the gallium nitride single crystal substrate can be grown on the cleaned gallium nitride single crystal substrate by a Metal Organic Chemical Vapor Deposition (MOCVD) method or a Hydride Vapor Phase Epitaxy (HVPE) method.
Step S231: and preprocessing the gallium nitride epitaxial wafer.
Specifically, the pretreatment is to clean and air-dry the bottom surface of the gallium nitride epitaxial wafer, the cleaning mode can be that ultrasonic cleaning is firstly carried out, for example, a gallium nitride single crystal substrate is put into ethanol to carry out ultrasonic cleaning for 20min, the ultrasonic frequency is 50 KHz-70 KHz, then the gallium nitride single crystal substrate is cleaned in a deionized water beaker, and nitrogen is adopted to blow and dry after the cleaning is finished, so that the pretreatment of the bottom surface of the gallium nitride single crystal substrate is finished, and the gallium nitride single crystal substrate after the pretreatment is beneficial to improving the bonding strength between the two-dimensional material and the gallium nitride single crystal substrate.
Step S232: and spin-coating PMMA (polymethyl methacrylate) on the surface of the metal matrix with the two-dimensional material film to obtain the PMMA film.
Specifically, the two-dimensional material includes any one of metallic transition metal chalcogenide, half metallic transition metal chalcogenide, borane, and half metallic chloride; wherein the Metallic transition metal chalcogenide can be Metallic TMCs, MTMCs, etc., and the semi-Metallic transition metal chalcogenide can be 1T phase MoTe 2 1T phase TaS 2 1T phase CrTe 2 PtTe of 1T phase 2 FeTe, etc., the borane may be 2-Pmmn phase, beta 12 Phase, χ 3 Phase and honeycomb phase, the half metallic chloride may be 1T phase CrCl 2 ，FeCl 2 And CoCl 2 Etc.
Step S233: the metal matrix is heated to cure the PMMA film.
Specifically, after heating the metal substrate, the PMMA film is fixed on a two-dimensional material film.
Step S234: and (3) putting the cured metal matrix into an etching solution to etch and remove the metal layer, thereby obtaining the PMMA-two-dimensional material composite film.
Step S235: and drying the PMMA-two-dimensional material composite film, placing the dried PMMA-two-dimensional material composite film on the bottom surface of the gallium nitride epitaxial wafer, and removing the PMMA film to obtain the insert layer attached to the bottom surface of the gallium nitride epitaxial wafer.
Specifically, the PMMA film can be removed by washing with acetone, so that the PMMA is used as a transfer medium, and the two-dimensional material film is attached to the bottom surface of the gallium nitride epitaxial wafer to obtain the insertion layer. The thickness of the intercalating layer is in the range of 0.5nm to 10nm, for example, 0.5nm, 1.5nm, 3nm, 5nm, 7nm, 10nm, etc., preferably 3nm.
Step S24: and evaporating a metal film on one side of the insertion layer away from the gallium nitride single crystal substrate.
Specifically, ti/Al/Ni/Au is deposited by using a vacuum thermal evaporation coating instrument to form a metal film.
Step S25: and annealing the metal film to obtain the bottom electrode.
Specifically, when the rapid annealing furnace is heated to 800 ℃, the metal film and the gallium nitride single crystal substrate are put into the rapid annealing furnace together and kept for 60 seconds to finish the rapid annealing, and the bottom electrode is obtained. Wherein the bottom electrode serves as the cathode.
Step S26: and evaporating a metal film on one side of the terminal guard ring far away from the n-type gallium nitride drift layer to form a top electrode, thereby obtaining the gallium nitride power electronic device.
Specifically, a mask pattern with the diameter of 100 mu m is prepared on one side of the terminal protection ring far away from the n-type gallium nitride drift layer through a photoetching process, and then a vacuum thermal evaporation coating instrument is used for depositing metal Ni/Au, so that a top electrode is obtained. Wherein the top electrode acts as an anode.
In a specific example, as shown in fig. 3, the preparation method of the gallium nitride power electronic device is as follows:
1) A single crystal substrate of gallium nitride having a thickness of 300 μm was provided, si was doped into the single crystal substrate, and both the top and bottom surfaces of the single crystal substrate of gallium nitride were polished.
2) Growing an n-type gallium nitride drift layer with the thickness of 20 mu m on the cleaned gallium nitride single crystal substrate by adopting a Metal Organic Chemical Vapor Deposition (MOCVD) method, wherein the n-type gallium nitride drift layer is doped with Si, and the Si doping amount is 2 multiplied by 10 16 cm -3 。
3) And spin-coating photoresist on one side of the n-type gallium nitride drift layer far away from the gallium nitride monocrystalline substrate, and performing mask exposure on the first preset pattern.
4) With plasma BCl 3 Dry etching was performed to form a step, and an etching depth was measured by an atomic force microscope and was 1 μm.
5) Removing photoresist, preparing a second preset pattern on the step by photoetching, and injecting He ions on the step according to the second preset pattern, wherein the incident angle is 7 degrees, and the dosage is 1 multiplied by 10 15 cm -2 Two energy levels of 150keV and 50keV are implanted down to form a termination guard ring with a box-like profile of depth 0.8 μm.
6) And (5) obtaining the gallium nitride epitaxial wafer on the gallium nitride substrate through MOCVD or HVPE epitaxial growth.
7) And carrying out ultrasonic cleaning and air drying on the bottom surface of the gallium nitride epitaxial wafer.
8) And spin-coating PMMA (polymethyl methacrylate) on the surface of the metal matrix with the two-dimensional material film to obtain the PMMA film.
9) Heating the metal matrix to solidify the PMMA film so that the PMMA film is fixed in the 1T phase MoTe 2 And on the membrane.
10 Placing the solidified metal matrix into an etching solution to etch and remove the metal layer to obtain PMMA-1T phase MoTe 2 And (3) a composite membrane.
11 PMMA-1T phase MoTe 2 And drying the composite film, placing the composite film on the bottom surface of the gallium nitride epitaxial wafer, and removing the PMMA film to obtain the insert layer attached to the bottom surface of the gallium nitride epitaxial wafer.
12 Ti film is formed by depositing Ti by a vacuum thermal evaporation film plating instrument, and the thickness of the Ti film is 25nm.
13 When the temperature of the rapid annealing furnace is raised to 800 ℃, the Ti film and the gallium nitride single crystal substrate are put into the rapid annealing furnace together and kept for 60 seconds to finish the rapid annealing, and the bottom electrode is obtained.
14 Preparing a mask pattern with the diameter of 100 mu m on one side of the terminal protection ring far away from the n-type gallium nitride drift layer through a photoetching process, and then depositing metal Ni (20 nm) by utilizing a vacuum thermal evaporation coating instrument to obtain a top electrode, thereby completing the preparation of the gallium nitride power electronic device.
Referring to fig. 4, the embodiment of the present invention further provides a gallium nitride power electronic device, which is manufactured by adopting the manufacturing method of the gallium nitride power electronic device shown in fig. 1 or fig. 2, and the gallium nitride power electronic device includes a bottom electrode 3, an insertion layer 2, a gallium nitride single crystal substrate 1, an n-type gallium nitride drift layer 4, a terminal guard ring 5 and a top electrode 6 stacked from bottom to top; wherein, the n-type gallium nitride drift layer 4 has a mesa structure on the side far away from the gallium nitride single crystal substrate 1, and the terminal guard ring 5 is matched with the mesa structure and has a box-shaped outline. The two-dimensional material with metallic or semi-metallic structure is adopted as the metal-semiconductor contact interface of the insertion layer 2, so that the influence caused by the interface MIGS can be well regulated, the Schottky barrier height is adjustable, the Schottky barrier height approaching zero is hopefully realized, and the method has a large development prospect for the formation and optimization of ohmic contact.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A method for manufacturing a gallium nitride power electronic device, comprising:
providing a gallium nitride single crystal substrate;
preparing an insertion layer on the bottom surface of the gallium nitride single crystal substrate; wherein the insertion layer comprises a two-dimensional material having metallic or semi-metallic properties;
and preparing a bottom electrode on one side of the insertion layer far away from the gallium nitride single crystal substrate, and preparing a top electrode on the top surface of the gallium nitride single crystal substrate to obtain the gallium nitride power electronic device.
2. The method of fabricating a gallium nitride power electronic device according to claim 1, wherein the step of fabricating an interposer on the bottom surface of the gallium nitride single crystal substrate comprises:
and transferring the two-dimensional material film to the bottom surface of the gallium nitride single crystal substrate by utilizing wet transfer to obtain an insertion layer.
3. The method of manufacturing a gallium nitride power electronic device according to claim 2, wherein the transferring the two-dimensional material film to the bottom surface of the gallium nitride substrate by wet transfer to obtain the insertion layer comprises:
epitaxially growing on the gallium nitride single crystal substrate to obtain a gallium nitride epitaxial wafer;
preprocessing the gallium nitride epitaxial wafer;
spin-coating PMMA on the surface of a metal matrix with a two-dimensional material film to obtain a PMMA film;
heating the metal matrix to solidify the PMMA film;
placing the cured metal matrix into an etching solution to etch and remove the metal layer, so as to obtain the PMMA-two-dimensional material composite film;
and drying the PMMA-two-dimensional material composite film, placing the dried PMMA-two-dimensional material composite film on the bottom surface of the gallium nitride epitaxial wafer, and removing the PMMA film to obtain the insert layer attached to the bottom surface of the gallium nitride epitaxial wafer.
4. The method of manufacturing a gallium nitride power electronic device according to claim 1, wherein the two-dimensional material comprises any one of metallic transition metal chalcogenide, semi-metallic transition metal chalcogenide, borane, and semi-metallic chloride.
5. The method for manufacturing a gallium nitride power electronic device according to claim 1, wherein the thickness of the insertion layer ranges from 0.5nm to 10nm.
6. The method of manufacturing a gallium nitride power electronic device according to claim 1, wherein the step of manufacturing a bottom electrode on a side of the insertion layer remote from the gallium nitride single crystal substrate comprises:
evaporating a metal film on one side of the insertion layer far away from the gallium nitride single crystal substrate;
and annealing the metal film to obtain the bottom electrode.
7. The method of manufacturing a gallium nitride power electronic device according to claim 1, wherein before the step of manufacturing an insertion layer on the bottom surface of the gallium nitride single crystal substrate, further comprising:
epitaxially growing an n-type gallium nitride drift layer on the top surface of the gallium nitride single crystal substrate;
and implanting ions into one side of the n-type gallium nitride drift layer, which is far away from the gallium nitride single crystal substrate, according to a first preset pattern to form a terminal protection ring with a box-shaped outline.
8. The method of fabricating a gan power electronic device of claim 7, wherein said forming a terminal guard ring having a box-like profile by ion implantation according to a first predetermined pattern on a side of said n-type gan drift layer remote from said gan single crystal substrate comprises:
preparing a first preset pattern on one side of the n-type gallium nitride drift layer far away from the gallium nitride single crystal substrate;
forming a mesa structure by plasma etching according to the first preset pattern;
preparing a second preset pattern on the mesa structure;
and implanting ions on the mesa structure according to the second preset pattern to form a terminal protection ring with a box-shaped outline.
9. The method of fabricating a gallium nitride power electronic device according to claim 7, wherein the step of fabricating a top electrode on the top surface of the gallium nitride single crystal substrate comprises:
and evaporating a metal film on one side of the terminal guard ring far away from the n-type gallium nitride drift layer to form a top electrode.
10. Gallium nitride power electronic device, characterized in that it is manufactured by adopting the manufacturing method of the gallium nitride power electronic device according to any one of claims 1-9, and comprises a gallium nitride single crystal substrate, an insertion layer, a bottom electrode, an n-type gallium nitride drift layer, a terminal guard ring and a top electrode, wherein the bottom electrode, the insertion layer, the gallium nitride single crystal substrate, the n-type gallium nitride drift layer, the terminal guard ring and the top electrode are stacked from bottom to top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311395016.2A CN117577530A (en) | 2023-10-25 | 2023-10-25 | Preparation method of gallium nitride power electronic device and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311395016.2A CN117577530A (en) | 2023-10-25 | 2023-10-25 | Preparation method of gallium nitride power electronic device and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117577530A true CN117577530A (en) | 2024-02-20 |
Family
ID=89887126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311395016.2A Pending CN117577530A (en) | 2023-10-25 | 2023-10-25 | Preparation method of gallium nitride power electronic device and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117577530A (en) |
-
2023
- 2023-10-25 CN CN202311395016.2A patent/CN117577530A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110190116A (en) | A kind of high threshold voltage normally-off high electron mobility transistor and preparation method thereof | |
| KR101142545B1 (en) | Solar cell and manufacturing method of the same | |
| JP7470458B2 (en) | GaN/2D AlN heterojunction rectifier on silicon substrate and method for fabricating same | |
| CN109037326A (en) | A kind of enhanced HEMT device and preparation method thereof with p type buried layer structure | |
| CN107706245B (en) | Nitride planar structure resonant tunneling diode and preparation method thereof | |
| KR101100414B1 (en) | Solar cell and manufacturing method of the same | |
| WO2021139041A1 (en) | Gallium oxide schottky diode and preparation method therefor | |
| CN114566544A (en) | High-mobility spin field effect transistor and preparation method thereof | |
| CN117577530A (en) | Preparation method of gallium nitride power electronic device and device | |
| CN105514176B (en) | A kind of terahertz GaN Gunn diode and preparation method thereof | |
| CN109285894B (en) | Diamond-based multi-channel barrier regulation field effect transistor and preparation method thereof | |
| WO2019218907A1 (en) | Two-dimensional material transistor for regulating back gate on the basis of two-dimensional electron gas, manufacturing method, and application | |
| CN112018177A (en) | Full-vertical Si-based GaN UMOSFET power device and preparation method thereof | |
| CN113097313B (en) | YAlN/GaN double-barrier resonance tunneling diode with InGaN sub-well structure and manufacturing method thereof | |
| CN113451129B (en) | High electron mobility transistor and preparation method thereof | |
| CN109378312B (en) | Body-doped diamond-based normally-off field effect transistor and preparation method thereof | |
| CN108597997B (en) | Preparation method of ohmic contact electrode of GaN-based device | |
| CN111653613A (en) | Two-dimensional material superlattice device and manufacturing method thereof | |
| CN107527949B (en) | Heterojunction spin field effect transistor based on Cr-doped 4H-SiC substrate and preparation method thereof | |
| CN107425059B (en) | Cr-doped heterojunction spin field effect transistor and preparation method thereof | |
| CN113451128B (en) | High electron mobility transistor and preparation method thereof | |
| CN111863938A (en) | Gallium nitride-based Schottky diode and preparation method thereof | |
| WO2021139039A1 (en) | Gallium oxide schottky diode and manufacturing method therefor | |
| CN205264759U (en) | Terahertz is gaN gunn diode now | |
| CN111243960A (en) | Preparation method of semiconductor nanowire and field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |