CN114566544A - High-mobility spin field effect transistor and preparation method thereof - Google Patents
High-mobility spin field effect transistor and preparation method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66984—Devices using spin polarized carriers
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention discloses a high-mobility spin field effect transistor which comprises a source electrode, a drain electrode, a gate electrode, a semiconductor channel and a substrate. Compared with the existing spin field effect transistor based on a single semiconductor channel, the semiconductor channel structure has the advantages of adjustable energy band structure, high mobility, adjustable carrier concentration and type, long spin diffusion length and the like; compared with a spin field effect transistor with a traditional substrate, the substrate with piezoelectric property is introduced, the spin transport of a current carrier in a semiconductor channel can be regulated and controlled through a surface polarized electric field of the substrate, the on-off voltage can be effectively reduced, and the control effect of a grid electrode is improved; compared with the existing spin field effect transistor preparation process, the invention can optimize the crystal quality of the spin tunneling layer, improve the spin polarizability of carriers, further improve the on-off ratio of the device and reduce the working current.
Description
Technical Field
The invention relates to the technical field of spin field effect transistors, in particular to a high-mobility spin field effect transistor and a preparation method thereof.
Background
The rapid development of current generation information technology is not free from the continuous progress of logic operation, information transmission and data storage technology. Over the past fifty years, the shrinking of semiconductor process technology has driven the ever increasing density of transistors and memory cells to follow moore's law. The spintronics opens up a new dimension for the utilization of the carriers by controlling, transmitting and detecting the spin property of the carriers, so that the spintronics becomes a new scheme expected to exceed the physical limit of the moore's law. The energy consumed to change only the spin state of the electrons is lower than to control the flow of charge. Besides, the electron spin can be coupled with the photon helicity, so that the instant transmission of data is realized. Therefore, the spintronic device is expected to become a low-energy-consumption and high-speed system solution for future information technology.
Among many spintronic devices, spin field effect transistors based on semiconductor channel materials such as InGaAs, InAs, etc. were the first to enter the field of view. Spin field effect transistors are first proposed by s. Datta and b. Das. Unlike conventional field effect transistors, spin field effect transistors employ magnetic materials as the source and drain. The spin precession of electrons is controlled by a grid electric field, so that when the spin electrons diffuse from a source electrode to a drain electrode, the spin polarization direction is the same as or opposite to the magnetization direction of the drain electrode, and the channel is switched on and off. However, only a few documents report that spin field effect transistors prepared by experiments have weak device signals and poor switching, wherein the main reasons include low polarizability of spin injection and detection, poor efficiency of semiconductor spin transport, and dependence of spin state regulation on large gate voltage. In order to solve these problems, the following aspects need to be addressed:
first, in order to achieve effective regulation of electron spin, electrons are required to have a large spin diffusion length and a large spin relaxation time in semiconductors. The conventional semiconductor material has short carrier spin relaxation time (tau s) (GaN) -22.5 ps, tau s (GaAs) -86 ps and tau s (InAs) -10 ps) and spin diffusion length (lambda s (GaN) -137 nm, lambda s (GaAs) -1 mu m and lambda s (InAs) -1.3 mu m) at room temperature. Therefore, finding a semiconductor material with longer spin relaxation time, longer spin diffusion length, and higher carrier mobility is an important prerequisite for improving the performance of the spintronic device.
Second, high performance spin field effect transistors rely on high polarizability injection and detection of the spinning electrons. Due to the impedance discontinuity effect of the semiconductor/ferromagnetic metal interface, the highest spin polarizability is achieved only if the contact resistance is close to the spin channel resistance. Usually, a very thin (1-2 nm) dielectric layer is inserted into the interface to form a magnetic tunnel junction as a spin detection electrode. The magnetic tunneling electrode adopting the MgO (001) tunneling layer has extremely high spin polarizability (92.6% at room temperature and corresponding tunneling magnetoresistance of 604%), and is a spin injection and detection structure commonly used in semiconductor spin devices. The MgO thin film grown by the conventional method is generally amorphous, and high temperature annealing under vacuum is required in order to convert it into a polycrystalline or single crystal structure having a lattice orientation of (001). However, ferromagnetic metals generally cannot withstand high temperatures, and the annealing temperature needs to be limited to 350 degrees or less, which affects the crystalline quality of the dielectric thin film, resulting in generally low polarizability for spin injection and detection. Therefore, the annealing treatment process needs to be designed reasonably, and the crystal quality of the tunneling layer needs to be improved as much as possible on the premise of not influencing the magnetic characteristics of the ferromagnetic metal.
Finally, the traditional Datta-Das spin field effect transistor mainly depends on the spin polarization direction of the spin electrons when the spin electrons drift from the source to the drain under the regulation of the precession of the electric field by the electric field of the grid. Due to the short spin diffusion length of the semiconductor, a large gate field is typically required to flip the spin polarization of the electrons within a finite drift distance. This results in a spin field effect transistor requiring a large turn-off voltage, limiting its performance. Therefore, it is necessary to explore how to obtain the gate electric field as large as possible under reasonable gate voltage conditions.
Disclosure of Invention
In view of the above technical problems in the related art, the present invention provides a high mobility spin field effect transistor and a method for fabricating the same, which can solve the above problems.
The invention faces the problems faced by the existing spin field effect transistor structure and preparation technology:
problem 1: the implementation of the spin field effect transistor depends on the high-efficiency transport of spin electrons in a semiconductor channel, however, the spin relaxation time of a carrier of a conventional semiconductor material at room temperature is short and is often in the order of ps. As a result, the carriers lose spin polarization after a short time of transport in the semiconductor channel and are therefore not detectable. Therefore, it is necessary to select a suitable semiconductor material or structure as a carrier transport channel to ensure that spin polarization is not lost during the carrier drift from the source to the drain.
The solution is as follows: in order to solve the problem of poor electron spin transport efficiency in the spin field effect transistor device, it is proposed to use a semiconductor heterojunction, a quantum well, or a two-dimensional electron gas structure in a two-dimensional material as a semiconductor channel (see fig. 3-8). In this structure, the transport of carriers is confined to a thin two-dimensional space, and a two-dimensional electron gas or a two-dimensional hole gas is characterized. The semiconductor channel may comprise at least one semiconductor A thin film layer, a heterojunction comprising a combination of at least one semiconductor B thin film layer and at least one semiconductor C thin film layer (wherein the forbidden bandwidths of the semiconductor B thin film layer and the semiconductor C thin film layer are generally different and form an I-type heterojunction), or a quantum well comprising a combination of at least one semiconductor D thin film layer, a semiconductor E thin film layer and a semiconductor E thin film layer (wherein the forbidden bandwidths of the semiconductor D thin film layer and the semiconductor E thin film layer are greater than those of the semiconductor E thin film layer).
Problem 2, the high performance spin field effect transistor needs to inject carriers with high spin polarization rate into the semiconductor channel, and can realize sensitive detection on the spin polarization direction of the carriers. At present, a spin tunneling electrode having a ferromagnetic metal/dielectric material structure is generally used as an injection and detection electrode for a spin current. In the current manufacturing process, in order to improve the crystal quality of the dielectric material, vacuum annealing is usually performed after depositing the dielectric material and the ferromagnetic metal. However, the magnetic metal layer cannot endure high temperature, the annealing temperature is limited below 350 ℃, so that the dielectric film cannot be completely crystallized, and the spin injection and detection efficiency is still poor.
The solution is as follows: spintronics devices rely on a spin tunneling layer with a ferromagnetic metal/dielectric material structure to inject spin current into the semiconductor channel, limited by the crystal quality of the dielectric material, and generally suffer from poor spin injection efficiency. In order to improve the crystal quality of the dielectric material, a vacuum annealing mode is generally adopted, however, the magnetic metal layer cannot resist high temperature, the annealing temperature is limited below 350 ℃, and the crystal quality of the dielectric thin film is affected. The invention provides an in-situ layering annealing process for growing a source electrode and a drain electrode, wherein a tunneling layer is grown or transferred on the surface of a semiconductor channel, the tunneling layer is fully crystallized through in-situ high-temperature annealing, a magnetic layer and a cover layer are grown after the temperature is reduced, and finally the magnetic anisotropy of the magnetic layer is regulated and controlled through low-temperature magnetic field annealing.
Problem 3: the traditional Datta-Das spin field effect transistor mainly depends on regulating the precession of spin electrons under an electric field through a grid electric field, and further controlling the spin polarization direction when the spin electrons drift from a source electrode to a drain electrode. Due to the short spin diffusion length of the semiconductor, a large gate voltage is usually required to flip the spin polarization of the electrons within a limited drift distance. Higher gate voltages affect the performance of the device and also increase the risk of gate leakage.
The solution is as follows: the traditional Datta-Das spin field effect transistor mainly depends on the spin polarization direction of spin electrons when the spin electrons drift from a source electrode to a drain electrode through the regulation and control of the precession of a gate electrode electric field under the electric field. Due to the short spin diffusion length of the semiconductor, a large gate voltage is usually required to flip the spin polarization of the electrons within a limited drift distance. In the present invention, the semiconductor channel is grown on a piezoelectric material substrate, wherein the substrate may be a thin sheet of material having piezoelectric properties, or a piezoelectric film is grown on another substrate. When grid voltage is applied, the surface of the piezoelectric material can generate a surface polarization field which is several times of that of a grid electric field, so that the precession of electron spin can be effectively regulated and controlled under the condition of lower grid voltage.
The invention has the beneficial effects that: (1) compared with the existing spin field effect transistor based on a single semiconductor channel, the semiconductor channel structure has the advantages of adjustable energy band structure, high mobility, adjustable carrier concentration and type, long spin diffusion length and the like; (2) compared with a spin field effect transistor with a traditional substrate, the substrate with piezoelectric property is introduced, the spin transport of a current carrier in a semiconductor channel can be regulated and controlled through a surface polarized electric field of the substrate, the on-off voltage can be effectively reduced, and the control effect of a grid electrode is improved; (3) compared with the existing spin field effect transistor preparation process, the invention can optimize the crystal quality of the spin tunneling layer, improve the spin polarizability of carriers, further improve the on-off ratio of the device and reduce the working current.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
The invention is explained in further detail below with reference to the drawing.
FIG. 1 is a high mobility spin field effect transistor (gate electrode on semiconductor channel) according to an embodiment of the present invention;
FIG. 2 is a high mobility spin field effect transistor (gate electrode on substrate) according to an embodiment of the present invention;
FIG. 3 is a schematic view of a semiconductor first thin film layer according to an embodiment of the present invention;
FIG. 4 is a schematic view of the combined layer structure of the semiconductor second thin film layer and the semiconductor third thin film layer according to the embodiment of the present invention;
FIG. 5 is a simplified diagram of the structure of the semiconductor thin film layer, semiconductor thin film layer and semiconductor thin film layer combination according to the embodiment of the present invention;
FIG. 6 is a schematic diagram of a band structure corresponding to the structure of FIG. 3 according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a band structure corresponding to the structure of FIG. 4 according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a band structure corresponding to the structure of FIG. 5 according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a source or drain electrode according to an embodiment of the present invention;
FIG. 10 is a schematic view of a thin film layer of a magnetic material according to an embodiment of the present invention;
FIG. 11 is a schematic view showing the structure of a thin film layer combination of a magnetic material, a thin film layer, and a non-magnetic material according to an embodiment of the present invention;
FIG. 12 is a schematic view showing the structure of a combined layer of a third thin film layer of a magnetic material and a third thin film layer of a magnetic material according to an embodiment of the present invention;
fig. 13 is a flow chart of a method for fabricating a high mobility spin field effect transistor according to an embodiment of the present invention.
In the figure: 10. a source electrode; 11. a cap layer; 12. a magnetic layer; 13. a tunneling layer; 20. a drain electrode; 21. a first thin film layer of a magnetic material; 22. a magnetic material B film layer; 23. a thin film layer of non-magnetic material; 24. a third film layer of magnetic material; 25. a magnetic material butyl thin film layer; 30. a gate electrode; 40. a semiconductor channel; 41. a semiconductor first thin film layer; 42. a semiconductor second thin film layer; 43. a semiconductor third film layer; 44. a semiconductor thin film layer; 45. a semiconductor penta-thin film layer; 46. a semiconductor polysilicon thin film layer; 50. a substrate; eCA guide belt bottom; eV、A valence band top; eF、The fermi level.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
As shown in fig. 1 to 13, a high mobility spin field effect transistor according to an embodiment of the present invention includes a source electrode 10, a drain electrode 20, a gate electrode 30, a semiconductor channel 40, and a substrate 50, where the substrate (50 includes a thin film or sheet made of a material having piezoelectric characteristics, the semiconductor channel 40 is located on the substrate 50, the semiconductor channel 40 is made of a semiconductor material having a two-dimensional electron gas structure or a semiconductor material having a heterojunction, the source electrode 10 and the drain electrode 20 are located on the semiconductor channel 40, each of the source electrode 10 and the drain electrode 20 includes a cap layer 11, a magnetic layer 12, and a tunneling layer 13, the gate electrode 30 is located on the semiconductor channel 40 or on the substrate 50, and the gate electrode 30 includes an electrode layer and an insulating layer.
In one embodiment of the present invention, the substrate 50 may be a thin sheet of material having piezoelectric properties, or a piezoelectric film may be grown on another substrate, the piezoelectric material including SiO2、GaN、ZnO、BaTiO3、PbZrxTi1-xO3、LiGaO2、GeLi2O3、Pb(Mg1/3Nb2/3)O3And polyvinylidene fluoride (PVDF) and its cognate compounds or polymers. When grid voltage is applied, the surface of the piezoelectric material can generate a surface polarization field which is several times of that of a grid electric field, so that the precession of electron spin can be effectively regulated and controlled under the condition of lower grid voltage.
In one embodiment of the present invention, the semiconductor channel 40 is made of a semiconductor material or a heterojunction having a two-dimensional electron gas structure, and the semiconductor channel 40 may comprise at least one semiconductor a thin film layer 41, a heterojunction comprising a combination of at least one semiconductor b thin film layer 42 and at least one semiconductor c thin film layer 43 (wherein the forbidden bandwidths of the semiconductor b thin film layer 42 and the semiconductor c thin film layer 43 are generally different and form an I-type heterojunction), or a quantum well comprising a combination of at least one semiconductor d thin film layer 44, a semiconductor e thin film layer 45 and a semiconductor e thin film layer 46 (wherein the forbidden bandwidths of the semiconductor d thin film layer 44 and the semiconductor e thin film layer 46 are greater than that of the semiconductor e thin film layer 45), and the thickness of each thin film layer is 0.1-100 nm. Among them, the semiconductor first thin film layer 41, the semiconductor second thin film layer 42, the semiconductor third thin film layer 43, the semiconductor third thin film layer 44, the semiconductor fifth thin film layer 45, and the semiconductor sixth thin film layer 46 may be: elemental semiconductors (e.g., Si, Ge, B, Sn, Te, Se, Sb, and compounds thereof), group III-V compound semiconductors (e.g., GaN, AlN, AlxGa(1-x)N、GaAs、InAs、GaP, InP and compounds thereof), group IIB-VIA compound semiconductor (e.g., ZnO and the like), group III-VI compound semiconductor (Ga)2O3And the like), group IV-IV compound semiconductors (e.g., SiC and the like), two-dimensional semiconductors (e.g., layered Sn, Te, Se, Sb, black phosphorus). The semiconductor channel 40 may be a planar or curved film, or may be a three-dimensional fin-shaped thin layer, a nano-sheet, or a nano-wire.
In one embodiment of the present invention, the source electrode 10 and the drain electrode 20 are each a multi-layer thin film structure composed of the cap layer 11, the magnetic layer 12 and the tunneling layer 13, wherein the tunneling layer 13 is in contact with the semiconductor channel 40, and depending on the shape of the semiconductor channel 40, the source electrode 10 and the drain electrode 20 may be stacked on top of the semiconductor channel 40, or may be in contact with the sides or partially or completely wrapped. The source electrode 10 and the drain electrode 20 are spaced apart by 1 to 2000 nm, and may be the same, partially the same or different in material composition. The cap layer 11 is usually one or more layers of metals and their alloys or non-metallic materials with high stability, such as Au, Ru, Al, Rh, Ir, Os, Re, Cd, Mo, Zr, Ta, Pt, Ag, Cu, Hf, W, Pd, Cr, V, Ta2O5、Al2O3、TiO2MgO, with a thickness of about 1-100 nm. The magnetic layer 12 is usually one or more layers of ferromagnetic or ferrimagnetic materials, and the magnetic layer 12 includes at least one layer of a magnetic material a thin film layer 21, at least one group of a magnetic material b thin film layer 22 and a non-magnetic material b thin film layer 23, or at least one group of a magnetic material c thin film layer 24 and a magnetic material d thin film layer 25 (the magnetic material c thin film layer 24 and the magnetic material d thin film layer 25 are two different materials, and by this structure, a composite magnetic film can be constructed by using two or more materials with different magnetic anisotropy and saturation magnetization to freely adjust and control the easy magnetization axis direction and saturation magnetization of the composite magnetic film). Wherein the first magnetic material film layer 21, the second magnetic material film layer 22, the third magnetic material film layer 24, and the fourth magnetic material film layer 25 may be Fe, Co, Ni, Mn, FeCo, NiFe, CoFeB, NiFeCuMo, Ni2MnGa、Co2FeAl、Co2CrSi、NiMnSb、Co2(Fe,Mn)Si、Co2Fe(AlSi)、Co2Fe (GeGa) or an alloy containing the above materials, each layer having a thickness of about 0.1 to 50 nm; the nonmagnetic material 23 may be Au, Ru, Rh, Al, Ir, Os, Re, Cd, Mo, Zr, Ta, Pt, Ag, Cu, Hf, W, Pd, Cr, V, Ta2O5、Al2O3、TiO2MgO, each thin film layer has a thickness of about 0.1-50 nm. The tunneling layer 13 is typically a relatively thin insulator or semiconductor material such as MgO, AlOx, SiO2、MgAl2O4、AlN、TiO2Or two-dimensional material, typically 0.1-5 nm thick.
In one embodiment of the present invention, the gate electrode 30 is generally between the source electrode 10 and the drain electrode 20, and is comprised of an electrode layer and an insulating layer, which may be above the semiconductor channel 40 or below the substrate 50, wherein the insulating layer is in contact with the semiconductor channel 40 or the substrate 50. Depending on the shape of the semiconductor channel 40, the gate electrode 30 may be stacked over the semiconductor channel 40, may be laterally contacted or may be partially or fully wrapped. Wherein the electrode layer is made of conductive metal or semiconductor and has a thickness of 1-100 nm, and the insulating layer is made of semiconductor or insulator with poor conductivity and has a thickness of 1-100 nm.
A high mobility spin field effect transistor and a method of fabricating the same includes preparing a substrate; growing a semiconductor channel; surface treatment of a semiconductor channel; growing a tunneling layer of the source and drain electrodes; annealing at high temperature; growing a magnetic layer and a cover layer of the source and drain electrodes; photoetching, etching and defining a source-drain electrode pattern; growing and stripping a gate electrode; low-temperature magnetic field annealing and the like.
The substrate preparation refers to cleaning and surface treatment of the substrate 50, and specifically includes processing a silicon wafer, sapphire or glass substrate by RCA cleaning process, and growing the piezoelectric film on the surface thereof (to generate a substrate having piezoelectric characteristics), or cleaning a piezoelectric material sheet cut into a sheet shape (directly using the piezoelectric material sheet as a substrate having piezoelectric characteristics), and performing pretreatment such as plasma treatment, ultraviolet irradiation, etc. on the surface thereof to remove organic contamination and oxidation on the surface.
The semiconductor channel 40 growing refers to growing the semiconductor channel 40 on the substrate 50 by using a pulsed laser deposition, a chemical vapor deposition, a magnetron sputtering, an atomic layer deposition, a molecular beam epitaxy, a metal-organic chemical vapor phase epitaxy, a thermal evaporation, an electron beam evaporation and other thin film growth processes, wherein the semiconductor channel 40 may be one or more materials and includes the materials and structural layers in the semiconductor channel 40.
The surface treatment of the semiconductor channel 40 refers to removing pollutants and oxide layers on the surface of the semiconductor channel 40 by means of plasma treatment, particle beam bombardment, high-energy ray irradiation and the like, and is beneficial to subsequent contact with a source electrode and a drain electrode.
The growth of the tunneling layer 13 of the source and drain electrodes refers to the growth of the tunneling layer 13 in the source electrode 10 and the drain electrode 20 on the surface of the semiconductor channel by using film growth processes such as magnetron sputtering, atomic layer deposition, thermal evaporation, electron beam evaporation and the like; or transferring the grown tunneling layer 13 to the surface of the semiconductor channel 40 by means of physical-chemical transfer. The physical transfer can use dry transfer, the dry transfer is an experimental method for preparing Van der Waals heterojunction, in particular to an experimental method for transferring any two-dimensional material to the surface of another material by adopting adhesive polymer, the materials are combined by weak Van der Waals force, and any lattice matching is not needed; the chemical transfer may use etching, electrochemical bubbling, or the like.
The high temperature annealing refers to annealing in vacuum or atmosphere, the annealing temperature is suitable for obtaining the best crystal quality of the tunneling layer 13, and is generally 200 ℃ to 500 ℃ and the annealing time is 10 to 240 minutes. Before the specified annealing temperature is reached, the temperature needs to be increased from the room temperature to the specified temperature in a gradient manner, the temperature increasing rate is 0.1-20 ℃ per minute, after the annealing is finished, the temperature also needs to be gradually decreased to the room temperature, and the temperature decreasing rate is 0.1-20 ℃ per minute, so that the crystal quality is improved, and the internal stress of the film is reduced.
The growth of the magnetic layer and the cover layer of the source and drain electrodes means that the magnetic layer 12 and the cover layer 11 are sequentially grown on the tunneling layer 13 by using the film growth processes of pulse laser deposition, chemical vapor deposition, magnetron sputtering, atomic layer deposition, molecular beam epitaxy, metal-organic chemical vapor epitaxy, thermal evaporation, electron beam evaporation and the like; or transferring the grown magnetic layer 12 or the cap layer 11 to the surface of the tunneling layer 13 by physical and chemical transfer.
The steps of photoetching, etching and defining the source and drain electrode patterns refer to defining the shapes of the source electrode 10 and the drain electrode 20 in the modes of optical exposure, electron beam exposure, ion beam exposure, hard mask and the like, and removing the cover layer, the magnetic layer and the tunneling layer film outside the region of the source and drain electrode by means of etching processes such as plasma etching, chemical corrosion, ion milling, laser stripping and the like, and only keeping the part of the source and drain electrode defined by photoetching.
The gate electrode growth and lift-off means that the shape and position of the gate electrode 30 are defined on the back surface of the substrate 50 or the surface of the semiconductor channel 40 by means of optical exposure, electron beam exposure, ion beam exposure, hard mask and the like, and then the insulating layer and the electrode layer in the gate electrode 30 are sequentially grown on the back surface of the substrate 50 or the upper surface of the semiconductor channel 40 by using the film growth processes such as pulsed laser deposition, chemical vapor deposition, magnetron sputtering, atomic layer deposition, molecular beam epitaxy, metal-organic chemical vapor phase epitaxy, thermal evaporation, electron beam evaporation and the like. Subsequently, based on a chemical lift-off process, the photoresist or the hard mask defined previously, and the insulating layer and the electrode film attached to the surface thereof are removed by using an organic solution, and finally the gate electrode 30 is prepared in the device.
The low-temperature magnetic field annealing refers to annealing in vacuum or atmosphere, and a magnetic field with a size of 0.01-20T can be applied during the annealing process, so that the magnetic layer 12 in the source electrode 10 and the drain electrode 20 can obtain relatively uniform magnetization. The annealing temperature is suitable for not causing the characteristics of the metal material to be obviously reduced, generally at the temperature of 100-350 ℃, and the annealing time is 30-120 minutes. Before the temperature reaches the specified annealing temperature, the temperature needs to be increased from the room temperature to the specified temperature in a gradient manner, the temperature increasing rate is 0.1-20 ℃ per minute, after the annealing is finished, the temperature also needs to be gradually decreased to the room temperature, and the temperature decreasing rate is 0.1-20 ℃ per minute, so that the crystal quality is improved, and the internal stress of the film is reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. A high mobility spin field effect transistor comprising a source electrode (10), a drain electrode (20), a gate electrode (30), a semiconductor channel (40), a substrate (50), characterized in that: the substrate (50) comprises a film or a sheet made of a material with piezoelectric characteristics, the semiconductor channel (40) is located on the substrate (50), the semiconductor channel (40) is made of a semiconductor material with a two-dimensional electron gas structure or a heterojunction semiconductor material, the source electrode (10) and the drain electrode (20) are located on the semiconductor channel (40), the source electrode (10) and the drain electrode (20) respectively comprise a cover layer (11), a magnetic layer (12) and a tunneling layer (13), the gate electrode (30) is located on the semiconductor channel (40) or on the substrate (50), and the gate electrode (30) comprises an electrode layer and an insulating layer.
2. A high mobility spin field effect transistor according to claim 1, wherein: the semiconductor channel (40) is in the shape of a plane, a curved surface film, a three-dimensional fin-shaped thin layer, a nano sheet or a nano wire; the semiconductor channel (40) is of a multilayer thin film structure and comprises at least one semiconductor A thin film layer (41), at least one combination layer of a semiconductor B thin film layer (42) and a semiconductor C thin film layer (43) or at least one combination layer of a semiconductor D thin film layer (44), a semiconductor E thin film layer (45) and a semiconductor F thin film layer (46); the thicknesses of the semiconductor first thin film layer (41), the semiconductor second thin film layer (42), the semiconductor third thin film layer (43), the semiconductor third thin film layer (44) and the semiconductor fifth thin film layer (45) are all 0.1-100 nm.
3. A high mobility spin field effect transistor according to claim 2, wherein: the semiconductor first thin film layer (41), the semiconductor second thin film layer (42), the semiconductor third thin film layer (43), the semiconductor third thin film layer (44), the semiconductor fifth thin film layer (45) and the semiconductor sixth thin film layer (46) are element semiconductors, III-V group compound semiconductors, IIB-VIA group compound semiconductors, III-VI group compound semiconductors, IV-IV group compound semiconductors or two-dimensional semiconductors; the semiconductor second thin film layer (42) and the semiconductor third thin film layer (43) form an I-type heterojunction, and the forbidden bandwidth of the semiconductor third thin film layer (44) and the semiconductor sixth thin film layer (46) is larger than that of the semiconductor fifth thin film layer (45).
4. A high mobility spin field effect transistor according to claim 1, wherein: the cover layer (11) is made of a material with high stability, and the thickness is 1-100 nm; the magnetic layer (12) is of a multilayer thin film structure and comprises at least one layer of a magnetic material A thin film layer (21), at least one group of combined layers of a magnetic material B thin film layer (22) and a non-magnetic material thin film layer (23) or at least one group of combined layers of a magnetic material C thin film layer (24) and a magnetic material D thin film layer (25); the thicknesses of the magnetic material A thin film layer (21), the magnetic material B thin film layer (22), the non-magnetic material thin film layer (23), the magnetic material C thin film layer (24) and the magnetic material D thin film layer (25) are all 0.1-50 nm; the tunneling layer (13) is made of a thin insulator or semiconductor material and has a thickness of 0.1-5 nm.
5. A high mobility spin field effect transistor according to claim 1, wherein: the electrode layer is made of conductive metal or semiconductor and has the thickness of 1-100 nm; the insulating layer is made of a semiconductor or an insulator with poor conductivity and has a thickness of 1-100 nm.
6. A method for preparing a high-mobility spin field effect transistor is characterized by comprising the following steps: the method comprises the following steps:
s1, processing a silicon wafer, sapphire or glass substrate by an RCA cleaning process, growing a film with piezoelectric property on the surface of the processed silicon wafer, sapphire or glass substrate to generate a substrate (50) with piezoelectric property, or transferring a grown thin layer with piezoelectric property on the surface of the processed silicon wafer, sapphire or glass substrate in a physical and chemical transfer mode, and performing plasma treatment and ultraviolet irradiation pretreatment on the whole surface of the piezoelectric property substrate to remove organic contamination and oxidation on the surface;
s2, growing a semiconductor channel (40) on the substrate (50) by utilizing a thin film growth process; or transferring the grown semiconductor channel (40) to the substrate (50) by means of physical-chemical transfer;
s3, removing pollutants and an oxide layer on the surface of the semiconductor channel (40) by using plasma treatment, particle beam bombardment or high-energy ray irradiation means;
s4, growing a tunneling layer (13) of a source electrode (10) and a drain electrode (20) on the surface of the semiconductor channel (40) by using a thin film growth process, or transferring the grown tunneling layer (13) to the surface of the semiconductor channel (40) in a physical and chemical transfer mode;
s5, annealing the tunneling layer (13) in vacuum or in an atmosphere, wherein the annealing temperature is 200-500 ℃, the annealing time is 10-240 minutes, before the annealing temperature reaches the specified annealing temperature, the temperature needs to be increased from the room temperature to the specified annealing temperature in a gradient manner, the temperature rising rate is 0.1-20 degrees/min, after the annealing is finished, the annealing temperature needs to be gradually decreased to the room temperature, and the temperature decreasing rate is 0.1-20 degrees/min;
s6, sequentially growing a magnetic layer (12) and a cover layer (11) on the tunneling layer (13) by using a film growth process, or sequentially transferring the grown magnetic layer (12) thin layer or the cover layer (11) thin layer to the surface of the tunneling layer (13) in a physical and chemical transfer mode;
s7, defining the shapes of the source electrode (10) and the drain electrode (20) through a photoetching process, and removing the thin film of the cover layer (11), the magnetic layer (12) and the tunneling layer (13) outside a photoetching process defined area in the step through an etching process, wherein only the parts of the source electrode (10) and the drain electrode (20) defined by the photoetching process in the step are reserved;
s8, defining the shape and the position of a gate electrode (30) on the back of the substrate (50) or the surface of the semiconductor channel (40) through a photoetching process, sequentially growing an insulating layer (31) and an electrode layer (32) in the gate electrode (30) on the back of the substrate (50) or the upper surface of the semiconductor channel (40) through a film growing process, removing the film of the insulating layer (31) and the electrode layer (32) outside a photoetching process defined area in the step through an organic solution based on a chemical stripping process, and finally preparing the gate electrode (30) in the device;
s9, annealing in vacuum or atmosphere, wherein a magnetic field of 0.01-20T is applied in the annealing process, the annealing temperature is 100 DEG and 350 ℃, the annealing time is 30-120 minutes, the annealing temperature needs to be increased from room temperature gradient to the specified annealing temperature before reaching the specified annealing temperature, the temperature rising rate is 0.1-20℃/min, after the annealing is finished, the annealing temperature needs to be gradually reduced to the room temperature, and the temperature reducing rate is 0.1-20℃/min.
7. The method of claim 6, wherein said step of forming said high mobility spin field effect transistor comprises: the piezoelectric property substrate in step S1 can also be directly made by cutting a sheet of piezoelectric material into a sheet shape.
8. The method of claim 6, wherein said step of forming said high mobility spin field effect transistor comprises: the film growth process in S2, S4, S6 and S8 includes pulsed laser deposition, chemical vapor deposition, magnetron sputtering, atomic layer deposition, molecular beam epitaxy, metal-organic chemical vapor epitaxy, thermal evaporation or electron beam evaporation.
9. The method of claim 6, wherein said step of forming said high mobility spin field effect transistor comprises: the photolithography process in the steps S7 and S8 includes optical exposure, electron beam exposure, ion beam exposure, or hard mask; the etching process in step S7 includes plasma etching, chemical etching, ion milling, or laser lift-off.
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| CN118231239A (en) * | 2024-05-21 | 2024-06-21 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor structure and semiconductor device |
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| CN117279480A (en) * | 2023-09-21 | 2023-12-22 | 大连理工大学 | Two-dimensional electron gas side wall injection type spin information device structure and preparation method thereof |
| CN118231239A (en) * | 2024-05-21 | 2024-06-21 | 湖北江城芯片中试服务有限公司 | Method for manufacturing semiconductor structure and semiconductor device |
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