CN117575886A - Image edge detector, detection method, electronic equipment and medium - Google Patents

Image edge detector, detection method, electronic equipment and medium Download PDF

Info

Publication number
CN117575886A
CN117575886A CN202410051039.XA CN202410051039A CN117575886A CN 117575886 A CN117575886 A CN 117575886A CN 202410051039 A CN202410051039 A CN 202410051039A CN 117575886 A CN117575886 A CN 117575886A
Authority
CN
China
Prior art keywords
image
edge
transistor
matched
detection unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202410051039.XA
Other languages
Chinese (zh)
Other versions
CN117575886B (en
Inventor
顾佳妮
陈佳佳
金成吉
许嘉诚
陈博闻
玉虓
韩根全
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Lab
Original Assignee
Zhejiang Lab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Lab filed Critical Zhejiang Lab
Priority to CN202410051039.XA priority Critical patent/CN117575886B/en
Publication of CN117575886A publication Critical patent/CN117575886A/en
Application granted granted Critical
Publication of CN117575886B publication Critical patent/CN117575886B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/13—Edge detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10004—Still image; Photographic image
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Image Analysis (AREA)

Abstract

The invention discloses an image edge detector, a detection method, electronic equipment and a medium, wherein the image edge detector is formed by stacking a plurality of layers of memory transistors (NAND) arrays; the detection method comprises the following steps: pre-storing edge characteristic values in an image edge detector; acquiring an image to be matched; traversing the image to be matched through the SUSAN template to obtain a gray difference value corresponding to each pixel point in the image to be matched; comparing the gray difference value corresponding to each pixel point in the image to be matched with a pre-defined gray difference threshold value to obtain an image characteristic value corresponding to each pixel point in the image to be matched; and writing the two image characteristic values into an image edge detector as a group, and comparing the two image characteristic values with edge characteristic values prestored in the image edge detector to obtain edge information of the image to be matched. The method has simple algorithm and low hardware cost, and has great application potential in the field of image research.

Description

Image edge detector, detection method, electronic equipment and medium
Technical Field
The invention belongs to the technical field of semiconductors and integrated circuits, and particularly relates to an image edge detector, a detection method, electronic equipment and a medium.
Background
The image edge detection technology is an important foundation in the image analysis fields such as image segmentation, target recognition, region morphology extraction and the like. In order to obtain a better edge effect, a plurality of edge detection operators have been developed, including Roberts operator, sobel operator, prewitt operator based on the first derivative, canny operator, LOG operator based on the second derivative, etc., however, most of these edge detection operators need to perform complex operations such as convolution operation, differential operation, gradient processing, etc., resulting in a large data calculation amount. Meanwhile, in the traditional image detector, a data storage unit and a data processing unit are often separated, and the data transmission processing causes higher power consumption and higher hardware cost, so that the traditional image detector is quite unfriendly to the energy-efficient image data processing.
Disclosure of Invention
Aiming at the problems of the existing image edge detector, the invention provides an image edge detector, a detection method, electronic equipment and a medium.
In a first aspect, an embodiment of the present invention provides an image edge detector, including: a plurality of layers of memory integrated transistor NAND arrays; each layer of memory integrated transistor NAND array is formed by cascading n rows by m columns of memory integrated transistors;
the memory integrated transistors among different layers in the same column share one matching line;
the memory transistors between different columns and the same row of the memory transistor NAND array of each layer share a search line, and the memory transistors T are all i,j Gate and memory integrated transistor T i,j+1 Is connected with the grid electrode, i is more than or equal to 1 and less than or equal to n, j is more than or equal to 1 and less than or equal to m;
each layer of memory integrated transistor NAND array is different from the same columnThe memory transistors between rows share a bit line, the memory transistor T i,j Source and storage integrated transistor T i+1,j The drains of the transistors are connected to form a series structure;
first memory integrated transistor T in each column 1,j The drain electrode of the (a) is connected in series with the first gating transistor, and the n-th integrated transistor T n,j Is connected in series with the second gating transistor;
two adjacent transistors in each column are used as an image detection unit.
In a second aspect, an embodiment of the present invention provides an image edge detection method, implemented based on the image edge detector, where the method includes:
pre-storing edge characteristic values in an image edge detector;
acquiring an image to be matched; traversing the image to be matched through the SUSAN template to obtain a gray difference value corresponding to each pixel point in the image to be matched;
comparing the gray difference value corresponding to each pixel point in the image to be matched with a pre-defined gray difference threshold value to obtain an image characteristic value corresponding to each pixel point in the image to be matched;
and writing the two image characteristic values into an image edge detector as a group, and comparing the two image characteristic values with edge characteristic values prestored in the image edge detector to obtain edge information of the image to be matched.
Further, pre-storing the edge feature values in the image edge detector includes:
inputting different pulse voltages to the grid electrode of the integrated transistor in each image detection unit to adjust the threshold voltage of the integrated transistor so as to pre-store the edge characteristic value in the image edge detector;
the edge characteristic value consists of 0 and 1, wherein 1 represents a pixel homogeneous region, and 0 represents a pixel heterogeneous region.
Further, inputting different pulse voltages to the gates of the integrating transistors in each image detection unit to adjust the threshold voltages of the integrating transistors to realize pre-storing edge feature values in the image edge detector includes:
setting a first pulse voltage, a second pulse voltage, a third pulse voltage and a fourth pulse voltage; wherein, the first pulse voltage is larger than the second pulse voltage, the third pulse voltage is larger than the fourth pulse voltage;
setting the threshold voltage of a first integral transistor in the image detection unit to be a fourth pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be the first pulse voltage, so that the '00' edge characteristic value is stored in the image detection unit;
setting the threshold voltage of a first integral transistor in the image detection unit to be a third pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be a second pulse voltage, so that an edge characteristic value of '01' is stored in the image detection unit;
setting the threshold voltage of the first integrated transistor in the image detection unit to be a second pulse voltage, and setting the threshold voltage of the second integrated transistor in the image detection unit to be a third pulse voltage, so that the '10' edge characteristic value is stored in the image detection unit;
setting the threshold voltage of a first integral transistor in the image detection unit to be a first pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be a fourth pulse voltage, so as to store an 11-edge characteristic value in the image detection unit;
setting the threshold voltage of a first integral transistor in the image detection unit to be a fourth pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be a fourth pulse voltage, so as to store an xx edge characteristic value in the image detection unit; where "x" represents a blur feature value, and when the image feature value is compared with an edge feature value pre-stored in the image edge detector, the pre-stored edge feature value "xx" and the written image feature value "00", "01", "10" or "11" can be successfully matched.
Further, traversing the image to be matched through the SUSAN template, and obtaining the gray difference value corresponding to each pixel point in the image to be matched comprises the following steps:
acquiring pixel points at the central intersection of the SUSAN templates and pixel points at the non-central intersection of each SUSAN template; the SUSAN template adopts a cross template, is formed by intersecting a transverse pixels and a longitudinal pixels, and a is a positive integer;
and calculating the difference value between the pixel point at the non-center intersection of each SUSAN template and the pixel point at the center intersection in each SUSAN template to obtain the gray level difference value corresponding to each pixel point in the image to be matched.
Further, comparing the gray difference value corresponding to each pixel point in the image to be matched with a predefined gray difference threshold value, and obtaining an image characteristic value corresponding to each pixel point in the image to be matched comprises the following steps:
when the gray difference value corresponding to the pixel point in the image to be matched is smaller than or equal to a pre-defined gray difference threshold value, the image characteristic value corresponding to the current pixel point is 1;
when the gray level difference value corresponding to the pixel point in the image to be matched is larger than the pre-defined gray level difference threshold value, the image characteristic value corresponding to the current pixel point is 0.
Further, writing the two image feature values into the image edge detector as a group, comparing the two image feature values with edge feature values pre-stored in the image edge detector, and obtaining edge information of the image to be matched comprises:
taking two image characteristic values as one group, comparing a plurality of groups of image characteristic values with edge characteristic values prestored in an image edge detector in a parallel mode through search lines;
judging whether the matching line is an image edge according to the current of each matching line; comprising the following steps: when the image characteristic value is matched with the edge characteristic value pre-stored in the image edge detector, the current of the current matching line reaches the maximum value; when the image characteristic value does not match the edge characteristic value pre-stored in the image detector, the current of the current match line is almost 0.
Further, the process of writing the two image feature values as a set to the image edge detector includes:
setting a first grid input voltage corresponding to a first integrative transistor in the image detection unit and a second grid input voltage corresponding to a second integrative transistor;
the sum of the first gate input voltage and the second gate input voltage in each image detection unit in the image edge detector is a fixed value.
In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, the memory being coupled to the processor; the memory is used for storing program data, and the processor is used for executing the program data to realize the image edge detection method.
In a fourth aspect, an embodiment of the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the image edge detection method described above.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides an image edge detector and an image edge detection method, wherein in the image edge detection method, a SUSAN template does not need to carry out convolution operation to obtain a gray level difference value and an image characteristic value, the two image characteristic values are written into the image edge detector as a group, and the two image characteristic values are compared with edge characteristic values pre-stored in the image edge detector to obtain edge information of an image to be matched; the image edge detector can directly process information and make decisions on the basis of directly storing image sensing data, data are not required to be transmitted to other processing units, and the image edge detector is matched with a SUSAN template and a feature matching method without convolution operation, so that the image data processing efficiency and the hardware resource utilization rate are improved, and the application of higher efficiency, real-time, safety and privacy protection is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of an image edge detector based on a memory transistor according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an image edge detection method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an image edge detector and edge feature value pre-storing according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a SUSAN template provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of an image to be matched and an image feature value according to an embodiment of the present invention;
FIG. 6 is a graph of a comparison result of an image feature value and a pre-stored edge feature value provided by an embodiment of the present invention;
fig. 7 is a schematic diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and the described embodiments are only some, but not all, of the possible embodiments of the present invention, and are intended to provide a basic understanding of the present invention, and are not intended to identify key or critical elements of the present invention or to define the scope of the present invention. It is easy to understand that, according to the technical solution of the present invention, those skilled in the art may propose other implementations that can be replaced with each other without changing the true spirit of the present invention. Accordingly, the following detailed description and drawings are merely illustrative of the invention and are not intended to be exhaustive or to limit the invention to the precise form disclosed.
As shown in fig. 1, the present invention provides an image edge detector based on a memory transistor, which is formed by three-dimensionally and vertically stacking a plurality of layers of memory transistor NAND arrays; each layer of memory integrated transistor NAND array is formed by cascading n rows by m columns of memory integrated transistors;
not in the same columnMemory integrated transistors between the same layers share the same matching line ML j 。
The memory transistors of the same row and different columns of the memory transistor NAND array of each layer share a search line SL i Memory integrated transistor T i,j Gate and memory integrated transistor T i,j+1 Is connected with the grid electrode, i is more than or equal to 1 and less than or equal to n, j is more than or equal to 1 and less than or equal to m;
the memory transistors of the same column and different rows of the memory transistor NAND array of each layer share a bit line BL j Memory integrated transistor T i,j Source and storage integrated transistor T i+1,j The drains of the transistors are connected to form a series structure;
first memory integrated transistor T in each column 1,j The drain electrode of the (a) is connected in series with the first gating transistor, and the n-th integrated transistor T n,1 The first gating transistor SGD is used for selecting whether a bit line signal is connected or not, and the second gating transistor SGS is used for selecting whether a source line signal is connected or not;
the adjacent transistors in each column are used as an image detection unit.
It should be noted that, by designing the image edge detector, the image edge features with a large scale compared with the image edge detector can be searched in one period, thereby greatly improving the data retrieval efficiency.
As shown in fig. 2, an embodiment of the present invention provides an image edge detection method, which is implemented based on the above-mentioned image edge detector based on a memory transistor, and the method specifically includes:
step S1, pre-storing edge characteristic values in an image edge detector based on a memory transistor.
Further, the edge characteristic value consists of 0 and 1, wherein 1 represents a pixel homogeneous region, and 0 represents a pixel heterogeneous region; the threshold voltage of the integrated transistor is regulated and controlled by inputting different pulse voltages to the grid electrode of the integrated transistor in each image detection unit, so that the storage of different edge characteristic values 0 or 1 is realized.
Referring to FIG. 3, a schematic diagram of a small-scale image edge detector and edge feature value pre-storage according to an embodiment of the present invention; the threshold state is adjusted by inputting different pulse voltages to the grid electrode of the integrating transistor so as to realize the storage of the image edge characteristic values in different detection units.
Four threshold states are achieved by inputting different pulse voltages to the gate of the integrating transistor: first pulse voltage V t1 Second pulse voltage V t2 Third pulse voltage V t3 Fourth pulse voltage V t4 The method comprises the steps of carrying out a first treatment on the surface of the Wherein V is t4 <V t3 <V t2 <V t1 。
Each image detection unit can store 5 edge characteristic values, which is specifically defined as follows:
setting the threshold voltage of the first integrating transistor in the image detection unit to the fourth pulse voltage V t4 The threshold voltage of the second integrated transistor in the image detection unit is set to be the first pulse voltage V t1 Defining the unit to store a '00' edge characteristic value;
setting the threshold voltage of the first integrating transistor in the image detection unit to be the third pulse voltage V t3 The threshold voltage of the second integrated transistor in the image detection unit is set to be the second pulse voltage V t2 Defining the unit to store a '01' edge characteristic value;
setting the threshold voltage of the first integrating transistor in the image detection unit to the second pulse voltage V t2 The threshold voltage of the second integrated transistor in the image detection unit is set to be the third pulse voltage V t3 Defining the unit to store a 10 edge characteristic value;
setting the threshold voltage of the first integrating transistor in the image detection unit to be the first pulse voltage V t1 The threshold voltage of the second integrated transistor in the image detection unit is set to the fourth pulse voltage V t4 Defining the unit to store an 11 edge characteristic value;
integrating the first memory in the image detection unitThe threshold voltage of the body tube is set to be the fourth pulse voltage V t4 The threshold voltage of the second integrated transistor in the image detection unit is set to the fourth pulse voltage V t4 Defining the unit to store an "xx" edge feature value, wherein "x" represents a fuzzy feature value and can simultaneously represent a "0/1" feature value, namely when the image feature value is compared with an edge feature value pre-stored in an image edge detector, the pre-stored edge feature value "xx" can be successfully matched with the written image feature value "00", "01", "10" or "11".
Illustratively, a first pulse voltage V t1 Set to 1.50V, the second pulse voltage V t2 Set to 1.05V, the third pulse voltage V t3 Set to 0.50V, fourth pulse voltage V t4 Set to-0.15V;
will T 1,1 The threshold voltage is set to be-0.15V, T 2,1 The threshold voltage is set to be 1.50V so as to store an edge characteristic value of '00';
will T 3,1 The threshold voltage is set to be-0.15V, T 4,1 The threshold voltage is set to be-0.15V so as to store an edge characteristic value 'xx';
will T 1,2 The threshold voltage is set to be-0.15V, T 2,2 The threshold voltage is set to be-0.15V so as to store an edge characteristic value 'xx';
will T 3,2 The threshold voltage is set to be-0.15V, T 4,2 The threshold voltage is set to be 1.50V so as to store an edge characteristic value of '00';
will T 1,3 The threshold voltage is set to 0.50V, T 2,3 The threshold voltage is set to be 1.05V so as to store an edge characteristic value of '01';
will T 3,3 The threshold voltage is set to 1.50V, T 4,3 The threshold voltage is set to be-0.15V so as to store an edge characteristic value of 11;
will T 1,4 The threshold voltage is set to 1.50V, T 2,4 The threshold voltage is set to be-0.15V so as to store an edge characteristic value of 11;
will T 3,4 The threshold voltage is set to 1.05V, T 4,4 The threshold voltage is set to 0.50V to store the edge bitsThe sign value "10".
Referring to fig. 3, fig. 3 shows image edge feature values according to an embodiment of the present invention, such that the edge feature values F are 4 groups, respectively, a first edge feature value F1 (00 xx), a second edge feature value F2 (xx 00), a third edge feature value F3 (0111), and a fourth edge feature value F4 (1110).
S2, obtaining an image to be matched; traversing the image to be matched through the SUSAN template to obtain a gray level difference value corresponding to each pixel point in the image to be matched.
Referring to fig. 4, fig. 4 shows a SUSAN template according to an embodiment of the present invention, where the SUSAN template is a cross-shaped template, and is formed by intersecting a horizontal pixels with a vertical pixel centers, and a is a positive integer; in this example, a=5 is set, which is formed by intersecting 5 horizontal pixels with 5 vertical pixel centers, and the pixel point at the intersection of the centers of the cross-shaped templates is P 0 The pixel point at the non-central intersection is P q (q=1, 2,3, … …,2 a-1), and calculating the pixel point P at each non-center intersection in the template q Pixel point P at crossing with center 0 And obtaining the gray level difference value corresponding to each pixel point.
Gray difference= |p q -P 0 |。
Step S3, comparing the gray difference value corresponding to each pixel point in the image to be matched with a pre-defined gray difference threshold value to obtain an image characteristic value corresponding to each pixel point in the image to be matched;
specifically, when the gray level difference value of the corresponding pixel is equal to or less than the gray level difference threshold TH, the pixel is identified as a homogeneous point, and the image characteristic value I thereof n Is marked as 1; when the gray level difference value of the corresponding pixel point is larger than or equal to the gray level difference threshold value TH, the pixel point is identified as a heterogeneous point, and the image characteristic value I thereof n And marking as 0, and traversing and scanning the pictures to be matched to obtain all image characteristic values.
In this embodiment, the gray level difference threshold TH is 20, and the calculated partial image feature values are shown in fig. 5.
And S4, writing the two image characteristic values into an image edge detector as a group, and comparing the two image characteristic values with edge characteristic values pre-stored in the image edge detector to obtain edge information of the image to be matched.
Specifically, a first gate input voltage V corresponding to a first integrating transistor in the image detection unit is set SL A second gate input voltage corresponding to the second integrated transistorThe method comprises the steps of carrying out a first treatment on the surface of the Wherein the first gate input voltage V in each image detection unit in the image edge detector SL And a second gate input voltage->Sum V cc Is a fixed value.
Taking two image characteristic values as one group, and passing multiple groups of image characteristic values through search lines SL n In parallel with the image characteristic values stored in the image detector and based on each match line ML n To determine whether it is an image edge. When the image characteristic value is completely matched with the edge characteristic value pre-stored in the image detector, the current of the matched line is maximum; when the image characteristic value does not match the edge characteristic value pre-stored in the image detector, the current of the match line is negligible.
Wherein V is SL00 Andinput of corresponding image characteristic value 00, V SL01 And->Input corresponding to image characteristic value 01, V SL10 And->Input of corresponding image characteristic value 10, V SL11 And->Input of corresponding image feature values 11; wherein V is SL00 >V t1 ，V SL01 >V t2 ，V SL10 >V t3 ，V SL11 >V t4 。
Illustratively, according to this embodiment, the integral transistor characteristics, V SL00 =1.8V，=0.3V；V SL01 =1.3V，/>=0.8V；V SL10 =0.8V，/>=1.3V；V SL11 =0.3V，/>=1.8V；V cc =2.1v. Referring to fig. 6, which is a comparison result diagram of the image feature value and the pre-stored edge feature value according to the embodiment of the present invention, it can be found that the matching line ML when the input image feature value completely matches the pre-stored edge feature value in the image detector n Is the largest current; match line ML when the image feature value does not match the edge feature value pre-stored in the image detector n The current of (2) is negligible.
It should be noted that, the data scale of the image feature values may be adapted to the scale of the image detector, and multiple image feature values may be searched in parallel in the image detectors of different layers at a time, so as to implement highly parallel image edge search.
The present specification also provides a computer readable storage medium storing a computer program operable to perform the above method of data synchronization.
The present specification also provides a schematic structural diagram of the electronic device shown in fig. 7. At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile storage, as described in fig. 7, although other hardware required by other services may be included. The processor reads the corresponding computer program from the nonvolatile memory into the memory and then runs the computer program to realize the data synchronization method.
Of course, other implementations, such as logic devices or combinations of hardware and software, are not excluded from the present description, that is, the execution subject of the following processing flows is not limited to each logic unit, but may be hardware or logic devices.
In the 90 s of the 20 th century, improvements to one technology could clearly be distinguished as improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) or software (improvements to the process flow). However, with the development of technology, many improvements of the current method flows can be regarded as direct improvements of hardware circuit structures. Designers almost always obtain corresponding hardware circuit structures by programming improved method flows into hardware circuits. Therefore, an improvement of a method flow cannot be said to be realized by a hardware entity module. For example, a programmable logic device (Programmable Logic Device, PLD) (e.g., a field programmable gate array (Field Programmable gate array, FPGA)) is an integrated circuit whose logic function is determined by the user programming the device. A designer programs to "integrate" a digital system onto a PLD without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Moreover, nowadays, instead of manually manufacturing integrated circuit chips, such programming is mostly implemented by using "logic compiler" software, which is similar to the software compiler used in program development and writing, and the original code before the compiling is also written in a specific programming language, which is called hardware description language (Hardware Description Language, HDL), but not just one of the hdds, but a plurality of kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware DescriptionLanguage), confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), lava, lola, myHDL, PALASM, RHDL (RubyHardware Description Language), etc., VHDL (Very-High-SpeedIntegrated Circuit Hardware Description Language) and Verilog are currently most commonly used. It will also be apparent to those skilled in the art that a hardware circuit implementing the logic method flow can be readily obtained by merely slightly programming the method flow into an integrated circuit using several of the hardware description languages described above.
The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller may thus be regarded as a kind of hardware component, and means for performing various functions included therein may also be regarded as structures within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present specification.
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing is merely exemplary of the present disclosure and is not intended to limit the disclosure. Various modifications and alterations to this specification will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, or the like, which are within the spirit and principles of the present description, are intended to be included within the scope of the claims of the present description.

Claims (10)

1. An image edge detector, comprising: a plurality of layers of memory integrated transistor NAND arrays; each layer of memory integrated transistor NAND array is formed by cascading n rows by m columns of memory integrated transistors;
the memory integrated transistors among different layers in the same column share one matching line;
the memory transistors between different columns and the same row of the memory transistor NAND array of each layer share a search line, and the memory transistors T are all i,j Gate and memory integrated transistor T i,j+1 Is connected with the grid electrode, i is more than or equal to 1 and less than or equal to n, j is more than or equal to 1 and less than or equal to m;
the memory transistors between different rows of the same column of the memory transistor NAND array of each layer share a bit line, and the memory transistors T are all i,j Source and storage integrated transistor T i+1,j The drains of the transistors are connected to form a series structure;
first memory integrated transistor T in each column 1,j The drain electrode of the (a) is connected in series with the first gating transistor, and the n-th integrated transistor T n,j Is connected in series with the second gating transistor;
two adjacent transistors in each column are used as an image detection unit.
2. An image edge detection method, characterized in that it is implemented based on the image edge detector of claim 1, the method comprising:
pre-storing edge characteristic values in an image edge detector;
acquiring an image to be matched; traversing the image to be matched through the SUSAN template to obtain a gray difference value corresponding to each pixel point in the image to be matched;
comparing the gray difference value corresponding to each pixel point in the image to be matched with a pre-defined gray difference threshold value to obtain an image characteristic value corresponding to each pixel point in the image to be matched;
and writing the two image characteristic values into an image edge detector as a group, and comparing the two image characteristic values with edge characteristic values prestored in the image edge detector to obtain edge information of the image to be matched.
3. The image edge detection method according to claim 2, wherein pre-storing edge feature values in the image edge detector comprises:
inputting different pulse voltages to the grid electrode of the integrated transistor in each image detection unit to adjust the threshold voltage of the integrated transistor so as to pre-store the edge characteristic value in the image edge detector;
the edge characteristic value consists of 0 and 1, wherein 1 represents a pixel homogeneous region, and 0 represents a pixel heterogeneous region.
4. The image edge detection method according to claim 3, wherein inputting different pulse voltages to the gates of the integrating transistors in each image detection unit to adjust the threshold voltages of the integrating transistors to realize pre-storing edge feature values in the image edge detector comprises:
setting a first pulse voltage, a second pulse voltage, a third pulse voltage and a fourth pulse voltage; wherein, the first pulse voltage is larger than the second pulse voltage, the third pulse voltage is larger than the fourth pulse voltage;
setting the threshold voltage of a first integral transistor in the image detection unit to be a fourth pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be the first pulse voltage, so that the '00' edge characteristic value is stored in the image detection unit;
setting the threshold voltage of a first integral transistor in the image detection unit to be a third pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be a second pulse voltage, so that an edge characteristic value of '01' is stored in the image detection unit;
setting the threshold voltage of the first integrated transistor in the image detection unit to be a second pulse voltage, and setting the threshold voltage of the second integrated transistor in the image detection unit to be a third pulse voltage, so that the '10' edge characteristic value is stored in the image detection unit;
setting the threshold voltage of a first integral transistor in the image detection unit to be a first pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be a fourth pulse voltage, so as to store an 11-edge characteristic value in the image detection unit;
setting the threshold voltage of a first integral transistor in the image detection unit to be a fourth pulse voltage, and setting the threshold voltage of a second integral transistor in the image detection unit to be a fourth pulse voltage, so as to store an xx edge characteristic value in the image detection unit; where "x" represents a blur feature value, and when the image feature value is compared with an edge feature value pre-stored in the image edge detector, the pre-stored edge feature value "xx" and the written image feature value "00", "01", "10" or "11" can be successfully matched.
5. The method for detecting an image edge according to claim 2, wherein traversing the image to be matched through the SUSAN template to obtain a gray level difference value corresponding to each pixel point in the image to be matched comprises:
acquiring pixel points at the central intersection of the SUSAN templates and pixel points at the non-central intersection of each SUSAN template; the SUSAN template adopts a cross template, is formed by intersecting a transverse pixels and a longitudinal pixels, and a is a positive integer;
and calculating the difference value between the pixel point at the non-center intersection of each SUSAN template and the pixel point at the center intersection in each SUSAN template to obtain the gray level difference value corresponding to each pixel point in the image to be matched.
6. The method for detecting an image edge according to claim 2, wherein comparing the gray difference value corresponding to each pixel in the image to be matched with a predefined gray difference threshold value to obtain an image feature value corresponding to each pixel in the image to be matched comprises:
when the gray difference value corresponding to the pixel point in the image to be matched is smaller than or equal to a pre-defined gray difference threshold value, the image characteristic value corresponding to the current pixel point is 1;
when the gray level difference value corresponding to the pixel point in the image to be matched is larger than the pre-defined gray level difference threshold value, the image characteristic value corresponding to the current pixel point is 0.
7. The image edge detection method according to claim 2, wherein writing the two image feature values as a set into the image edge detector, comparing with edge feature values pre-stored in the image edge detector, and obtaining edge information of the image to be matched includes:
taking two image characteristic values as one group, comparing a plurality of groups of image characteristic values with edge characteristic values prestored in an image edge detector in a parallel mode through search lines;
judging whether the matching line is an image edge according to the current of each matching line; comprising the following steps: when the image characteristic value is matched with the edge characteristic value pre-stored in the image edge detector, the current of the current matching line reaches the maximum value; when the image characteristic value does not match the edge characteristic value pre-stored in the image detector, the current of the current match line is almost 0.
8. The image edge detection method of claim 2, wherein writing two image feature values as a set to the image edge detector comprises:
setting a first grid input voltage corresponding to a first integrative transistor in the image detection unit and a second grid input voltage corresponding to a second integrative transistor;
the sum of the first gate input voltage and the second gate input voltage in each image detection unit in the image edge detector is a fixed value.
9. An electronic device comprising a memory and a processor, wherein the memory is coupled to the processor; wherein the memory is configured to store program data and the processor is configured to execute the program data to implement the image edge detection method of any of the preceding claims 2-8.
10. A computer readable storage medium having stored thereon a computer program, wherein the program when executed by a processor implements the image edge detection method according to any of claims 2-8.
CN202410051039.XA 2024-01-15 2024-01-15 Image edge detector, detection method, electronic equipment and medium Active CN117575886B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410051039.XA CN117575886B (en) 2024-01-15 2024-01-15 Image edge detector, detection method, electronic equipment and medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410051039.XA CN117575886B (en) 2024-01-15 2024-01-15 Image edge detector, detection method, electronic equipment and medium

Publications (2)

Publication Number Publication Date
CN117575886A true CN117575886A (en) 2024-02-20
CN117575886B CN117575886B (en) 2024-04-05

Family

ID=89895848

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410051039.XA Active CN117575886B (en) 2024-01-15 2024-01-15 Image edge detector, detection method, electronic equipment and medium

Country Status (1)

Country Link
CN (1) CN117575886B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102999886A (en) * 2012-10-31 2013-03-27 长春光机数显技术有限责任公司 Image edge detector and ruler raster grid line precision detection system
WO2019019160A1 (en) * 2017-07-28 2019-01-31 深圳配天智能技术研究院有限公司 Method for acquiring image information, image processing device, and computer storage medium
WO2022226751A1 (en) * 2021-04-27 2022-11-03 中国科学院微电子研究所 Memristor, hamming distance calculation method, and integrated storage and computation application
CN115830048A (en) * 2021-09-18 2023-03-21 中国移动通信有限公司研究院 Image edge detection method and device and related equipment
CN116805370A (en) * 2022-03-15 2023-09-26 清华大学 Image recognition method, device and related equipment
CN117333529A (en) * 2023-11-30 2024-01-02 之江实验室 Template matching-based vascular ultrasonic intima automatic measurement method and system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102999886A (en) * 2012-10-31 2013-03-27 长春光机数显技术有限责任公司 Image edge detector and ruler raster grid line precision detection system
WO2019019160A1 (en) * 2017-07-28 2019-01-31 深圳配天智能技术研究院有限公司 Method for acquiring image information, image processing device, and computer storage medium
WO2022226751A1 (en) * 2021-04-27 2022-11-03 中国科学院微电子研究所 Memristor, hamming distance calculation method, and integrated storage and computation application
CN115830048A (en) * 2021-09-18 2023-03-21 中国移动通信有限公司研究院 Image edge detection method and device and related equipment
CN116805370A (en) * 2022-03-15 2023-09-26 清华大学 Image recognition method, device and related equipment
CN117333529A (en) * 2023-11-30 2024-01-02 之江实验室 Template matching-based vascular ultrasonic intima automatic measurement method and system

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
YONGBIN YU等: "Design of multilayer cellular neural network based on memristor crossbar and its application to edge detection", JOURNAL OF SYSTEMS ENGINEERING AND ELECTRONICS, vol. 34, no. 3, 9 November 2022 (2022-11-09), pages 641 *
张乐平;: "忆阻图像处理器结构设计分析", 石家庄学院学报, no. 03, 20 May 2017 (2017-05-20) *
李锟;曹荣荣;孙毅;刘森;李清江;徐晖;: "基于忆阻器的感存算一体技术研究进展", 微纳电子与智能制造, no. 04, 15 December 2019 (2019-12-15) *
罗忠亮;: "基于改进SUSAN算子的图像边缘检测算法", 重庆工学院学报(自然科学版), no. 05, 15 May 2009 (2009-05-15) *

Also Published As

Publication number Publication date
CN117575886B (en) 2024-04-05

Similar Documents

Publication Publication Date Title
CN108170667B (en) Word vector processing method, device and equipment
CN109034183B (en) Target detection method, device and equipment
CN112347512A (en) Image processing method, device, equipment and storage medium
US11543299B2 (en) Method, apparatus, touch chip and electronic device for determining temperature status of touch screen
CN117575886B (en) Image edge detector, detection method, electronic equipment and medium
CN116757278B (en) Training method and device of prediction model, storage medium and electronic equipment
CN111476729B (en) Target identification method and device
CN115830633B (en) Pedestrian re-recognition method and system based on multi-task learning residual neural network
CN116341642B (en) Data processing method and device, storage medium and electronic equipment
CN114371232B (en) Chromatographic filtering method, device, medium and system based on Kalman filtering algorithm
CN116030309A (en) Method and device for generating countermeasure sample, storage medium and electronic equipment
CN116342888A (en) Method and device for training segmentation model based on sparse labeling
CN116805393A (en) Hyperspectral image classification method and system based on 3DUnet spectrum-space information fusion
CN116308375A (en) Data processing method, device and equipment
WO2021239000A1 (en) Method and apparatus for identifying motion blur image, and electronic device and payment device
CN115880685B (en) Three-dimensional target detection method and system based on volntet model
CN111898615A (en) Feature extraction method, device, equipment and medium of object detection model
CN112115952B (en) Image classification method, device and medium based on full convolution neural network
CN116363390B (en) Infrared dim target detection method and device, storage medium and electronic equipment
CN116451808B (en) Model training method and device, storage medium and electronic equipment
CN116152274B (en) Image segmentation method, device, equipment and storage medium
CN117392688A (en) Image classification method, device, storage medium and electronic equipment
CN113887326B (en) Face image processing method and device
CN116721412B (en) Pod key point detection method and system based on structural priori from bottom to top
CN114268965B (en) Mobile communication network coverage rate calculation method and device based on deep learning

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant