CN116805370A - Image recognition method, device and related equipment - Google Patents
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Abstract
The application provides an image recognition method, an image recognition device and related equipment, wherein the method comprises the steps of obtaining a target image, inputting the target image into an edge detection module, and obtaining an edge node diagram. And inputting the edge node diagram into a matching module to obtain an image recognition result, wherein the edge detection module is a module comprising a first memristor set based on an edge detection operator, and the matching module is a module comprising a second memristor set based on a template image. The image recognition method provided by the embodiment of the application improves the speed of image recognition.
Description
Technical Field
The present application relates to the field of computer vision, and in particular, to an image recognition method, apparatus and related device.
Background
Image recognition technology refers to technology that processes, analyzes, and understands images with a computer to recognize targets and objects of various modes. Image recognition is typically based on a machine learning implementation, the computing architecture of which includes a storage module and a computing module.
At present, the storage module and the calculation module are independent from each other, and weight data needs to be transmitted back and forth between the storage module and the calculation module every time a calculation task is executed, so that the calculation speed is reduced, and the image recognition speed is lower.
Disclosure of Invention
The embodiment of the application provides an image recognition method, an image recognition device and related equipment, which solve the problem of slower image recognition speed.
To achieve the above object, in a first aspect, an embodiment of the present application provides an image recognition method, including:
acquiring a target image;
inputting the target image into an edge detection module to obtain an edge node diagram;
inputting the edge node diagram into a matching module to obtain an image recognition result;
the edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image.
In a second aspect, an embodiment of the present application provides an image recognition apparatus, including:
the first acquisition module is used for acquiring a target image;
the second acquisition module is used for inputting the target image into the edge detection module to obtain an edge node diagram;
the third acquisition module is used for inputting the edge node diagram into the matching module to obtain an image recognition result;
the edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image.
In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, and a computer program stored on the memory and executable on the processor, the computer program implementing the steps in the image recognition method according to the first aspect when executed by the processor.
In a fourth aspect, an embodiment of the present application provides a readable storage medium having a program stored thereon, which when executed by a processor, implements the steps in the image recognition method according to the first aspect.
In the embodiment of the application, the edge node diagram is obtained by acquiring the target image and inputting the target image into the edge detection module. And inputting the edge node diagram into a matching module to obtain an image recognition result. The edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image. The image recognition result can be obtained based on the edge detection module and the matching module which have the storage and calculation functions at the same time, so that weight data required by a calculation task does not need to be transmitted back and forth between the storage module and the calculation module, the calculation speed is improved, and the problem of slower image recognition speed is solved.
In addition, the storage module and the calculation module in the prior art are mutually independent, weight data are required to be transmitted back and forth between the storage module and the calculation module when one calculation task is executed, so that energy consumption is increased.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the following description will be given with reference to the accompanying drawings, which are obvious to one skilled in the art only, and other drawings can be obtained according to the listed drawings without inventive effort.
FIG. 1 is a schematic flow chart of an image recognition method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first subunit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of obtaining a third matrix provided by an embodiment of the present application;
FIG. 4 is a schematic flow chart of a convolution operation according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a memory array according to an embodiment of the present application;
FIG. 6 is a flow chart of a method for obtaining a target result based on a memory array according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an image recognition device according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art without the exercise of inventive faculty, are intended to be within the scope of the application.
The image recognition method provided by the embodiment of the application can be used in a scene of real-time target detection. At present, machine learning is widely used in the field of real-time target detection, by which a target object can be identified from an image. The image recognition method provided by the embodiment of the application realizes the computer vision operators in machine learning such as edge detection, template matching and the like based on the memory integrated array, improves the calculation speed through parallel calculation and algorithm improvement, and can meet the requirements of real-time performance and accuracy in a target detection scene.
Referring to fig. 1, fig. 1 is one of the flow charts of the image recognition method according to the embodiment of the present application, as shown in fig. 1, the image recognition method may include the following steps:
step 101, obtaining a target image;
the target image is an image to be identified, and may be one or more images. In specific implementation, the target image can be acquired in real time through a camera of a scene or a product to be detected, and can also be read from a memory storing the image to be identified.
102, inputting the target image into an edge detection module to obtain an edge node diagram;
the edges of an image are where the attributes in the image are abrupt and where the information in the image is most concentrated. The edges of an image may contain all information of the image under certain conditions. The edges of the image are formed by edge nodes, and the edge node diagram can be used for representing the edges of the image.
The edge detection module is a module comprising a first memristor and arranged based on an edge detection operator and is used for obtaining an edge node diagram of a target image. Due to the characteristics of memristors, an edge detection module comprising the first memristor and arranged based on an edge detection operator has the functions of storage and calculation. In this way, in the process that the edge detection module carries out calculation tasks on the target image to obtain the edge node diagram, weight data required by the calculation tasks do not need to be transmitted back and forth between the storage module and the calculation module, so that the calculation speed is improved, and the problem that the image recognition speed is lower is solved.
Step 103, inputting the edge node diagram into a matching module to obtain an image recognition result;
in particular, the matching module can perform matching based on gray information of the image, and can also perform matching based on feature space information of the image. Compared with the former, the image-based feature space information matching has better robustness and consistency, but the realization process is more complex and is not suitable for hardware migration.
The matching is carried out based on the gray information of the image, complex preprocessing is not needed for the image, the similarity between the image and the template image can be measured by utilizing certain statistical feature quantity of the gray of the image, and a certain searching method is adopted for matching. The algorithm is simple and feasible, can perform parallel processing, and is convenient to improve the operation speed by using a hardware algorithm. The embodiment of the application adopts the gray information based on the image for matching.
The template matching algorithm is the most basic algorithm in matching based on the gray information of an image, and searches a given set of known small images in a large image. The matching module is used for matching the edge node map of the target image with the template image, if the position of the circular object in the target image needs to be identified, the circular template image can be used for matching with the edge node map of the target image, so that the position of the circular object in the target image can be determined, and the position is the image identification result.
The matching module is a module comprising a second memristor and arranged based on the template image. Due to the characteristics of the memristors, the module comprising the second memristor, which is arranged based on the template image, has the functions of storage and calculation. In this way, in the calculation process that the matching module matches the edge node diagram of the target image with the template image to obtain the image recognition result, weight data required by the calculation task does not need to be transmitted back and forth between the storage module and the calculation module, so that the calculation speed is improved, and the problem of slower image recognition speed is solved.
In the embodiment of the application, the edge node diagram is obtained by acquiring the target image and inputting the target image into the edge detection module. And inputting the edge node diagram into a matching module to obtain an image recognition result. The edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image. The image recognition result can be obtained based on the edge detection module and the matching module which have the storage and calculation functions at the same time, so that weight data required by a calculation task does not need to be transmitted back and forth between the storage module and the calculation module, the calculation speed is improved, and the problem of slower image recognition speed is solved.
In addition, the storage module and the calculation module in the prior art are mutually independent, weight data are required to be transmitted back and forth between the storage module and the calculation module when one calculation task is executed, so that energy consumption is increased.
Optionally, the step 101 includes:
collecting an initial image of a target object;
inputting the initial image into a preprocessing module to obtain the target image;
the preprocessing module is a module comprising a third memristor and arranged based on a Gaussian operator.
In particular, a photograph of the target object may be acquired as an initial image by the image capturing apparatus. The target object may be a specific scene or product, etc. The initial image is input into a preprocessing module based on Gaussian operator setting for processing, so that a target image is obtained, and the image effect of the target image under different proportions and sizes can be enhanced, so that a better image recognition effect is achieved.
Furthermore, the preprocessing module is a module comprising a third memristor set based on a gaussian operator. Due to the characteristics of memristors, a module comprising a third memristor based on Gaussian operator setting has the functions of storage and calculation. In this way, in the calculation process of preprocessing the initial image by the preprocessing module, weight data required by a calculation task does not need to be transmitted back and forth between the storage module and the calculation module, so that the calculation speed is improved, and the image recognition speed is further improved.
Optionally, the acquiring process of the preprocessing module includes:
decomposing a first matrix corresponding to the Gaussian operator into linear combinations of a plurality of first submatrices, wherein elements in each first submatrix are 0 or 1;
and determining the preprocessing module according to the first submatrices.
The process of inputting the initial image into the preprocessing module to obtain the target image is a Gaussian blur process of the target image. From a mathematical perspective, the gaussian blur process of the target image is the convolution of the target image with a normal distribution. The embodiment of the application takes 3*3 neighborhood Gaussian operators as an example, and describes how to finish Gaussian smoothing (namely, how to preprocess an initial image).
The weight matrix for characterizing the gaussian operator is:
first, the weight matrix is decomposed into a plurality of first sub-matrices composed of only two elements of 0 and 1, and the linear combination is as follows:
and then mapping the decomposed first submatrices into an integrated memory array based on the third memristor setting to obtain a preprocessing module, and finally inputting the initial image into the preprocessing module to calculate convolution results of the first submatrices respectively and performing linear combination to obtain a target image.
The image effect of the target image under different proportion sizes can be enhanced by obtaining the target image after the initial image is preprocessed through Gaussian smoothing.
Optionally, the preprocessing module includes a first sub-module corresponding to a target first sub-matrix, where the first sub-module includes a plurality of first sub-units, each first sub-unit corresponds to one element in the target first sub-matrix, and an arrangement sequence of each first sub-unit corresponds to an arrangement sequence of elements in the target first sub-matrix;
the target first sub-matrix is any one of the plurality of first sub-matrices, and each first sub-unit comprises at least two transistors and at least two memristors.
In particular, when the target first sub-matrix corresponds to a column of first sub-modules formed by connecting a plurality of first sub-units in series, the arrangement sequence of each first sub-unit corresponds to the arrangement sequence of elements in the target first sub-matrix, and the arrangement sequence of the first sub-units corresponds to the arrangement sequence of the first sub-matrix according to the sequence of the first sub-matrix rows. If the target first sub-matrix is a 2×2 matrix, the elements of the first row and the first column correspond to the first sub-unit in the first sub-module; the elements of the first row and the second column correspond to a second first subunit in the first sub-module; the elements of the second row and the first column correspond to a third first subunit in the first subunit; the elements of the second row and the second column correspond to a fourth first subunit in the first subunit.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a first subunit according to an embodiment of the present application, where the first subunit may be formed by sequentially connecting a first memristor 11, a first transistor 12, a second transistor 13, and a second memristor 14 in series. The values of the elements characterized by the first subunit may be changed by adjusting the resistance values of the first memristor 1 and the second memristor 14.
Optionally, the step 102 includes:
obtaining the edge detection module according to a second matrix corresponding to the edge detection operator;
inputting the target image into the edge detection module to obtain a horizontal gray value and a vertical gray value of each first pixel point in the target image;
determining the gradient of each first pixel point according to the transverse gray value and the longitudinal gray value;
determining the first pixel point as an edge node under the condition that the gradient is larger than a first preset value;
and determining the edge node diagram according to the edge node.
In specific implementation, the embodiment of the application takes three-order sobel (sobel) edge detection operators Hx and Hy as shown below as an example, wherein a represents a target image, gx represents a transverse gray value of the target image after edge detection, and Gy represents a longitudinal gray value of the target image after edge detection. The second matrix corresponding to the edge detection operator is Hx and Hy.
To improve the accuracy of the computation, the matrices Hx, hy characterizing the sobel edge detection operator are decomposed into a plurality of sub-matrices composed of only 0, 1 elements, the linear combination of which is as follows:
the matrices Hx and Hy (i.e., the second matrix) of the decomposed edge detection operator are respectively mapped into the memory integrated array based on the first memristor, and the mapping rule can be consistent with the rule that the first matrix is mapped to the preprocessing module, which is not described herein. And then, respectively calculating convolution results of all the submatrices for the target image, and performing linear combination to obtain Gx and Gy.
According to the horizontal gray value and the vertical gray value of each pixel point in the target image, calculating the gradient G of each pixel point by the following formula:
and sequentially calculating the gradient of each pixel point in the target image, determining the pixel point as an edge node under the condition that the gradient is larger than a first preset value, and determining an edge node diagram according to all the edge nodes in the target image.
Optionally, referring to fig. 3, fig. 3 is a schematic diagram of obtaining a third matrix according to an embodiment of the present application, where the obtaining process of the matching module includes:
respectively translating and copying the gray matrix corresponding to the template image leftwards and rightwards according to a preset rule to obtain a third matrix;
and obtaining the matching module according to the third matrix.
In specific implementation, the gray value matrix corresponding to the template image is respectively translated and copied leftwards and rightwards in a mode shown in fig. 3, so as to obtain a third matrix. The third matrix is mapped to the memory integrated array based on the second memristor setting to obtain the matching module, and the mapping rule can be consistent with the rule that the first matrix is mapped to the preprocessing module, which is not described herein. In this way, when convolution operation is performed, the sliding window size is changed from m×n to m×n+2, and the horizontal sliding is performed once by sliding three grids, so that the matching speed can be improved by three times based on the parallel calculation of the storage and calculation integrated array, and the speed of image recognition is further improved. If the size of the integrated array allows, longitudinal copying (i.e. copying the gray matrix corresponding to the template image in an upward and downward translation way according to a preset rule) can be performed, so that the matching speed of the target image and the template image is further improved.
Optionally, the step 103 includes:
inputting the edge node diagram into a matching module to obtain matching values of the edge node diagram and each second pixel point in the template image;
for each second pixel point, determining the position of the second pixel point as a target position under the condition that the matching value is larger than a second preset value;
and determining an image recognition result according to the target position.
In specific implementation, the following expression 1 may be used to obtain a matching value R (x, y) between the edge node map and each second pixel point in the template image:
R(x,y)＝∑ x′,y′ (T (x ', y'). I (x+x ', y+y')) (expression 1)
Wherein R (x, y) represents the matching value of the pixel points in the x-th row and the y-th column, T (x ', y') represents the gray value of the pixel points in the x-th row and the y-th column in the template image, and I (x+x ', y+y') represents the gray value of the pixel points in the x+x 'row and the y+y' column in the target image.
And calculating a matching value of each pixel point in the template image and the target image based on the expression 1, and determining the position of the pixel point as the target position if the matching value is larger than a second preset value. In the practical application process, only one target position may be obtained, or a plurality of target positions may be obtained, if only one target position is obtained, the target position is the center position of the object to be identified, and if a plurality of target positions are obtained, the range determined by the plurality of target positions is the position of the object to be identified.
In order to reduce the calculation noise of the memristor and further improve the speed and accuracy of image recognition, the embodiment of the application further provides a method for obtaining a preprocessing module/an edge detection module/a matching module and obtaining a target result based on the preprocessing module/the edge detection module/the matching module.
The preprocessing module/the edge detection module/the matching module are all obtained based on mapping a matrix into a memory and calculation integrated array based on memristor setting, and the initial image is input into the preprocessing module to obtain the target image; inputting the target image into an edge detection module to obtain an edge node diagram; the edge node diagram is input into a matching module, and the process of obtaining an image recognition result is a convolution operation process based on a memory integrated array. Therefore, the matrix can be amplified by a plurality of times to reduce calculation noise and further improve the speed and accuracy of image recognition. The input signals are mapped to the amplified matrix to obtain a memory integrated array, and the output signals are converted and re-output according to the converted measuring range, so that a target result can be obtained, which is described in detail below.
As shown in fig. 4, fig. 4 is a schematic flow chart of a convolution operation provided in an embodiment of the present application, the convolution operation slides from top to bottom on an image (input matrix X) from left to right by using a matrix (weight matrix W) called a convolution kernel, multiplies each element of the convolution kernel matrix by an element of a corresponding position covered on the image by the element, and then sums the elements to obtain an output pixel value (output matrix Y). However, the convolution multiplication and addition method is difficult to realize by using a traditional storage array, and has the main difficulty that product values in different rows cannot be simply overlapped together, and a plurality of convolution output values cannot be simply calculated at the same time.
The memory-calculation integrated array is taken as a novel computing architecture, and the problems are perfectly overcome. The calculation form of the output current of the integrated array is as follows:
this is the same as the calculation form of convolution, and therefore, taking the expression 3 as shown below as an example, only the convolution kernel matrix needs to be correspondingly straightened into the form of a right column vector and stored in the cell device [ R11, R21, …, R91] of the storage-calculation-integrated array as shown in fig. 5, so that the corresponding calculation can be performed based on the form of the expression by utilizing the analog characteristics of the memristor.
Compared with the traditional computer architecture with separate calculation, the convolution calculation is completed by using the integrated calculation array, the back and forth movement of weight data is not needed, the signals are only needed to be input at the input end, the convolution result can be output in the form of current, and the calculation speed can be remarkably improved. In addition, the embodiment of the application can adopt a memory calculation integrated calculation array based on two transistors and two memristor (2T 2R) units, and one 2T2R unit can store data with the numerical range of-8 to 7 (4 bits), so that the calculation efficiency is further improved.
In addition, aiming at the problem that noise is generated in the convolution calculation process due to unstable hardware and quantization noise of peripheral circuits, the weight decomposition scaling operation in the integrated memory-calculation array provided by the embodiment of the application can effectively improve the accuracy of the convolution calculation result of the integrated memory-calculation array, and is specifically as follows:
the result of the integrated array output current is distinguished from the theoretical value in expression 2 in view of the limited range during analog-to-digital conversion (ADC). Through experimental tests, the integrated memory array used in the application has the best linearity when the integral time of analog-to-digital conversion is adjusted to enable the theoretical current output value of the memristor array to be 3 times of the actual output value, so that the calculated actual output value is shown as the following formula:
since the input and output are integers, based on expression 3, in order to avoid the loss of the output value and make the actual current value equal to the theoretical value, the convolution kernel needs to be amplified three times to map, i.e. 3*w ij As a weight matrix to the computationally intensive array.
In the actual test process, the output result deviation is found to be very large, and the calculation accuracy cannot be effectively improved only by the method, so that the calculation accuracy is replaced by sacrificing the range. Specifically, the convolution kernels are repeatedly mapped three times in the same column, i.e., [ … 3*w ] ij …]Duplicate as [ … 3*w ] ij …3*w ij …3*w ij …]And input data is input after corresponding copying.
At this time, the weight matrix is amplified by 9 times and mapped, so that the input/output ranges are compressed from-8 to-7 to-2 to 2, and the specific output range correspondence is shown in table 1. The weight matrix W also needs to be decomposed, and the absolute value of the sum of elements with the same sign in the decomposed matrix is less than or equal to 2. When the decomposed weight matrix is subjected to weight mapping, the element positions are the same and must be mapped to the same row of the memory integrated array.
Table 1 (ADC measuring range compression contrast table)
After the weight is amplified by 9 times, the base value of the weight can be slightly adjusted, and the output is positioned in a given theoretical interval as much as possible. For example, when the partial convolution result is large, fine tuning as shown in expression 5 can be performed, and the fine tuning is only for the ADC range, regardless of the process of mapping the weight matrix into the memory array:
9×w ij -1 (expression 5)
Wherein, let w ij Is a positive weight. The above decomposition and scaling operation on the convolution kernel weight matrix W is equivalent to modeling some adjustable parameters, and on the premise of reducing the influence on the output result to the greatest extent, the interference of non-ideal factors such as device characteristics and ADC noise on the output result is weakened as much as possible.
Referring to fig. 6, fig. 6 is a flowchart of a method for obtaining a target result based on a storage-in-one array according to an embodiment of the present application.
As shown in fig. 6, a method for obtaining a target result based on a storage-calculation integrated array according to an embodiment of the present application includes the following steps:
step 201, performing convolution kernel preprocessing, and decomposing the convolution kernel into a plurality of matrixes with absolute values of elements not more than 2;
step 202, amplifying a plurality of matrixes obtained by decomposition by 3 times, repeating each matrix for 3 times, and then mapping the matrix into the same column of a memory integrated array; it will be appreciated that all of the plurality of matrices are mapped in this manner into different columns in the computationally intensive array;
step 203, inputting signals and performing convolution operation;
and 204, converting and re-outputting the output signal according to the converted measuring range to obtain a convolution result.
The above steps will be described below using a pretreatment module as an example. The convolution kernel refers to the first matrix.
The first matrix may be decomposed into 5 first sub-matrices, the first sub-matrix repeated 3 times mapped to a first column of the preprocessing module; the second first sub-matrix is repeated 3 times to the second column of the pre-processing module and so on, and the fifth first sub-matrix is repeated 3 times to the fifth column of the pre-processing module. If the first sub-matrix corresponds to the first sub-module, the first sub-matrix is repeated 3 times and mapped to the first column of the preprocessing module to indicate that three first sub-modules are connected in series.
In the process of inputting an initial image into a preprocessing module to obtain the target image, an input signal refers to the initial image, and a convolution result refers to the target image.
Referring to fig. 7, an embodiment of the present application provides an image recognition apparatus 300, including:
a first acquiring module 301, configured to acquire a target image;
a second obtaining module 302, configured to input the target image into an edge detection module, and obtain an edge node map;
a third obtaining module 303, configured to input the edge node map into a matching module, and obtain an image recognition result;
the edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image.
Optionally, the first obtaining module 301 includes:
collecting an initial image of a target object;
inputting the initial image into a preprocessing module to obtain the target image;
the preprocessing module is a module comprising a third memristor and arranged based on a Gaussian operator.
Optionally, the acquiring process of the preprocessing module includes:
decomposing a first matrix corresponding to the Gaussian operator into linear combinations of a plurality of first submatrices, wherein elements in each first submatrix are 0 or 1;
and determining the preprocessing module according to the first submatrices.
Optionally, the preprocessing module includes a first sub-module corresponding to a target first sub-matrix, where the first sub-module includes a plurality of first sub-units, each first sub-unit corresponds to one element in the target first sub-matrix, and an arrangement sequence of each first sub-unit corresponds to an arrangement sequence of elements in the target first sub-matrix;
the target first sub-matrix is any one of the plurality of first sub-matrices, and each first sub-unit comprises at least two transistors and at least two memristors.
Optionally, the second obtaining module 302 includes:
obtaining the edge detection module according to a second matrix corresponding to the edge detection operator;
inputting the target image into the edge detection module to obtain a horizontal gray value and a vertical gray value of each first pixel point in the target image;
determining the gradient of each first pixel point according to the transverse gray value and the longitudinal gray value;
determining the first pixel point as an edge node under the condition that the gradient is larger than a first preset value;
and determining the edge node diagram according to the edge node.
Optionally, the obtaining process of the matching module includes:
respectively translating and copying the gray matrix corresponding to the template image leftwards and rightwards according to a preset rule to obtain a third matrix;
and obtaining the matching module according to the third matrix.
Optionally, the third obtaining module 303 includes:
inputting the edge node diagram into a matching module to obtain matching values of the edge node diagram and each second pixel point in the template image;
for each second pixel point, determining the position of the second pixel point as a target position under the condition that the matching value is larger than a second preset value;
and determining an image recognition result according to the target position.
The image recognition device 300 provided in the embodiment of the present application can implement each process that can be implemented in the embodiment of the image recognition method of the present application, and achieve the same beneficial effects, and for avoiding repetition, a detailed description is omitted herein.
The embodiment of the application provides electronic equipment. As shown in fig. 8, the electronic device 400 includes: a processor 401, a memory 402 and a computer program stored on the memory 402 and executable on the processor, the various components in the electronic device 400 are coupled together by a bus system 403. It is understood that the bus system 403 is used to enable connected communications between these components.
Wherein, the processor 401 is configured to acquire a target image;
inputting the target image into an edge detection module to obtain an edge node diagram;
inputting the edge node diagram into a matching module to obtain an image recognition result;
the edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image.
Optionally, the processor 401 is further configured to acquire an initial image of the target object;
inputting the initial image into a preprocessing module to obtain the target image;
the preprocessing module is a module comprising a third memristor and arranged based on a Gaussian operator.
Optionally, the processor 401 is further configured to decompose the first matrix corresponding to the gaussian operator into a linear combination of a plurality of first sub-matrices, where an element in each of the first sub-matrices is 0 or 1;
and determining the preprocessing module according to the first submatrices.
Optionally, the preprocessing module includes a first sub-module corresponding to a target first sub-matrix, where the first sub-module includes a plurality of first sub-units, each first sub-unit corresponds to one element in the target first sub-matrix, and an arrangement sequence of each first sub-unit corresponds to an arrangement sequence of elements in the target first sub-matrix;
the target first sub-matrix is any one of the plurality of first sub-matrices, and each first sub-unit comprises at least two transistors and at least two memristors.
Optionally, the processor 401 is further configured to obtain the edge detection module according to a second matrix corresponding to the edge detection operator;
inputting the target image into the edge detection module to obtain a horizontal gray value and a vertical gray value of each first pixel point in the target image;
determining the gradient of each first pixel point according to the transverse gray value and the longitudinal gray value;
determining the first pixel point as an edge node under the condition that the gradient is larger than a first preset value;
and determining the edge node diagram according to the edge node.
Optionally, the processor 401 is further configured to translate and copy the gray matrix corresponding to the template image to the left and right according to a preset rule, so as to obtain a third matrix;
and obtaining the matching module according to the third matrix.
Optionally, the processor 401 is further configured to input the edge node map into a matching module, and obtain a matching value of the edge node map and each second pixel point in the template image;
for each second pixel point, determining the position of the second pixel point as a target position under the condition that the matching value is larger than a second preset value;
and determining an image recognition result according to the target position.
The electronic device 400 provided in the embodiment of the present application can implement each process that can be implemented in the embodiment of the image recognition method of the present application, and achieve the same beneficial effects, and in order to avoid repetition, no description is given here.
The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the processes of the above-mentioned image recognition method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here. Wherein the computer readable storage medium is selected from Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.
Claims (10)
1. An image recognition method, comprising:
acquiring a target image;
inputting the target image into an edge detection module to obtain an edge node diagram;
inputting the edge node diagram into a matching module to obtain an image recognition result;
the edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image.
2. The method of claim 1, wherein the acquiring the target image comprises:
collecting an initial image of a target object;
inputting the initial image into a preprocessing module to obtain the target image;
the preprocessing module is a module comprising a third memristor and arranged based on a Gaussian operator.
3. The method of claim 2, wherein the acquiring of the preprocessing module comprises:
decomposing a first matrix corresponding to the Gaussian operator into linear combinations of a plurality of first submatrices, wherein elements in each first submatrix are 0 or 1;
and determining the preprocessing module according to the first submatrices.
4. A method according to claim 3, wherein the pre-processing module comprises a first sub-module corresponding to a target first sub-matrix, the first sub-module comprising a plurality of first sub-units, each first sub-unit corresponding to an element in the target first sub-matrix, the arrangement of each first sub-unit corresponding to the arrangement of elements in the target first sub-matrix;
the target first sub-matrix is any one of the plurality of first sub-matrices, and each first sub-unit comprises at least two transistors and at least two memristors.
5. The method of claim 1, wherein inputting the target image into an edge detection module, obtaining an edge node map, comprises:
obtaining the edge detection module according to a second matrix corresponding to the edge detection operator;
inputting the target image into the edge detection module to obtain a horizontal gray value and a vertical gray value of each first pixel point in the target image;
determining the gradient of each first pixel point according to the transverse gray value and the longitudinal gray value;
determining the first pixel point as an edge node under the condition that the gradient is larger than a first preset value;
and determining the edge node diagram according to the edge node.
6. The method of claim 1, wherein the process of obtaining the matching module comprises:
respectively translating and copying the gray matrix corresponding to the template image leftwards and rightwards according to a preset rule to obtain a third matrix;
and obtaining the matching module according to the third matrix.
7. The method of claim 6, wherein inputting the edge node map to a matching module to obtain an image recognition result comprises:
inputting the edge node diagram into a matching module to obtain matching values of the edge node diagram and each second pixel point in the template image;
for each second pixel point, determining the position of the second pixel point as a target position under the condition that the matching value is larger than a second preset value;
and determining an image recognition result according to the target position.
8. An image recognition apparatus, comprising:
the first acquisition module is used for acquiring a target image;
the second acquisition module is used for inputting the target image into the edge detection module to obtain an edge node diagram;
the third acquisition module is used for inputting the edge node diagram into the matching module to obtain an image recognition result;
the edge detection module is a module comprising a first memristor and set based on an edge detection operator, and the matching module is a module comprising a second memristor and set based on a template image.
9. An electronic device comprising a processor, a memory and a computer program stored on the memory and executable on the processor, which when executed by the processor performs the steps in the image recognition method according to any one of claims 1 to 7.
10. A readable storage medium, characterized in that the readable storage medium has stored thereon a program which, when executed by a processor, implements the steps in the image recognition method according to any one of claims 1 to 7.
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