CN117572409A - Large dynamic range S mode ADS-B signal decoding method and system - Google Patents

Large dynamic range S mode ADS-B signal decoding method and system Download PDF

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CN117572409A
CN117572409A CN202311311642.9A CN202311311642A CN117572409A CN 117572409 A CN117572409 A CN 117572409A CN 202311311642 A CN202311311642 A CN 202311311642A CN 117572409 A CN117572409 A CN 117572409A
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signal
ads
pulse
bit
mode
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王维
曹徵鉴
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Dfine Technology Co Ltd
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Dfine Technology Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/74Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems
    • G01S13/76Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems wherein pulse-type signals are transmitted
    • G01S13/78Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems wherein pulse-type signals are transmitted discriminating between different kinds of targets, e.g. IFF-radar, i.e. identification of friend or foe
    • G01S13/781Secondary Surveillance Radar [SSR] in general
    • G01S13/784Coders or decoders therefor; Degarbling systems; Defruiting systems
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a method and a system for decoding an S-mode ADS-B signal with a large dynamic range, wherein the method comprises the following steps: according to the output amplitude data of the ADS-B receiver, static threshold setting and dynamic threshold calculation are carried out to obtain a static threshold and a dynamic threshold; the ADC output signal of the ADS-B receiver is subjected to delay of the same clock and then is compared with the static threshold and the dynamic threshold, so that the demodulation of the input S-mode ADS-B signal is completed, and a demodulation signal is obtained; adopting a narrow interference pulse elimination technology to eliminate narrow interference pulses from the demodulation signal to obtain a demodulation signal after narrow interference elimination; and according to the demodulation signal after the narrow interference is eliminated, synchronous head detection and data block recovery decoding are carried out based on the format of the S-mode ADS-B signal. The invention expands the decoding dynamic range of the ADS-B receiver and also relaxes the requirement on IQ leakage control of the ADS-B transmitter.

Description

Large dynamic range S mode ADS-B signal decoding method and system
Technical Field
The invention relates to the technical field of air-traffic secondary radars, in particular to a large dynamic range S-mode ADS-B signal decoding method and system.
Background
The ADS-B signal modulation mode based on the S mode is binary amplitude modulation, and the receiver is mainly used for judging whether the amplitude of the pulse exceeds an amplitude threshold or not when demodulating. On the one hand, the transmission of ADS-B signals in a wireless fading channel may cause distortion of pulse level and edge, and the signal to noise ratio is seriously deteriorated; on the other hand, if the ADS-B transmitter adopts the zero intermediate frequency scheme, the threshold capacity between the low level and the high level becomes smaller due to IQ leakage (IQ: in-phase/quadrature) problem, and finally the dynamic range of decoding the S-mode signal by the ADS-B receiver is severely compressed.
Disclosure of Invention
The invention aims to provide a large dynamic range S-mode ADS-B signal decoding method and system, which utilize a dynamic threshold to realize the judgment of the high level and the low level of an S-mode ADS-B signal, effectively solve the problem that the high signal low level is higher than the low signal high level due to IQ leakage of an ADS-B transmitter which is caused by the fact that the traditional ADS-B receiver only uses a static threshold, expand the decoding dynamic range of the ADS-B receiver and also relax the requirement on IQ leakage control of the ADS-B transmitter.
Meanwhile, the invention utilizes the elimination technology of narrow interference pulse, completes the error correction of binary bit stream before decoding, reduces decoding burden and enhances the anti-interference capability of the system.
In addition, the invention also provides a method for detecting the S-mode ADS-B signal synchronous head for resisting pulse width distortion and a method for recovering the timing of the data block based on the unchanged pulse position characteristic, which greatly simplifies the decoding logic and enhances the selective fading resistance of the system.
The invention is realized by the following technical scheme:
in a first aspect, the present invention provides a method for decoding a large dynamic range S-mode ADS-B signal, the method comprising:
according to the output amplitude data of the ADS-B receiver, static threshold setting and dynamic threshold calculation are carried out to obtain a static threshold and a dynamic threshold;
the method comprises the steps of utilizing a static threshold and a dynamic threshold to delay an ADC output signal of an ADS-B receiver by the same clock, and then comparing the delayed ADC output signal with the static threshold and the dynamic threshold to finish demodulation of an input S-mode ADS-B signal to obtain a demodulation signal;
adopting a narrow interference pulse elimination technology to eliminate narrow interference pulses from the demodulation signal to obtain a demodulation signal after narrow interference elimination;
and according to the demodulation signal after the narrow interference is eliminated, synchronous head detection and data block recovery decoding are carried out based on the format of the S-mode ADS-B signal.
Further, the static threshold is a noise floor and a signal for distinguishing the ADS-B receiver, wherein the signal comprises an ADS-B high level signal, an ADS-B low level signal and other interference signals;
the dynamic threshold is used to distinguish between high and low levels of the S-mode ADS-B signal when different power conditions are received.
Further, the static threshold is set according to the noise floor amplitude level of the ADS-B receiver.
Further, the calculation method of the dynamic threshold is as follows:
establishing a detection window according to an S-mode ADS-B signal which is captured by an ADS-B receiver and is interfered by a wireless channel, IQ leakage of a transmitter and noise of the receiver; at least one complete high level and low level is contained in the detection window; the length of the detection window covers at least 4.5us;
searching the detection window in real time by adopting a sliding search mode, and searching the maximum value and the minimum value of the S mode ADS-B signal within preset time;
taking a median value for the maximum value and the minimum value, and multiplying the median value by a dynamic threshold coefficient to obtain a dynamic threshold;
wherein the dynamic threshold coefficient is related to the threshold capacity between the high and low levels of the transmitter.
Further, demodulation of the input S-mode ADS-B signal includes:
when the amplitude of the ADC output signal delayed and output by the ADS-B receiver is larger than the static threshold and the dynamic threshold, the input S-mode ADS-B signal is demodulated to be '1', otherwise, the input S-mode ADS-B signal is demodulated to be '0'.
Further, the narrow interference pulse cancellation technique is adopted to cancel the narrow interference pulse of the demodulation signal, including:
step 11: detecting the rising edge of the demodulation signal, if the rising edge is detected, entering step 12, wherein the output pulse_o after eliminating the narrow interference pulse is 0'; the demodulated signal is a bit stream pulsi output after demodulation;
step 12: counting the duration of Bit of the demodulation signal being '1', returning to step 11 if the duration of Bit being '1' is smaller than the first length, otherwise entering step 13, and outputting '0' by output pulse_o after eliminating the narrow interference pulse;
step 13: continuously detecting whether the bit stream puls_i output after demodulation is '1', if so, starting to output '1' by the output puls_o after eliminating the narrow interference pulse, otherwise, entering step 14;
step 14: maintaining the output pulse_o output '1' after the narrow interference pulse is eliminated, and returning to the step 11 after the duration is the first length;
wherein the first length is the pulse width T1 of the short-time interference pulse.
Further, performing synchronous header detection and data block recovery decoding based on the format of the S-mode ADS-B signal, comprising:
step 21: detecting the rising edge of the demodulated signal after the narrow interference is eliminated (namely, the bit stream pulse_o after the short interference pulse is eliminated), and entering step 22 after the rising edge is detected;
step 22: counting the duration of the leading P1 pulse Bit of the S mode ADS-B signal being '1', if the duration of Bit being '1' is within the first range, entering step 23, otherwise returning to step 21;
step 23: counting the duration of the leading P1 pulse Bit of the S mode ADS-B signal being '0', and returning to the step 21 if the duration of the Bit being '0' exceeds a third length; otherwise, if the duration of Bit being '0' is within the first range, go to step 24, otherwise, return to step 21;
step 24: counting the duration of the leading P2 pulse Bit of the S mode ADS-B signal being '1', if the duration of the Bit being '1' is within a first range, entering step 25, otherwise returning to step 21;
step 25: counting the duration of the leading P1 pulse Bit of the S mode ADS-B signal being '0', and returning to the step 21 if the duration of the Bit being '0' exceeds the fourth length; otherwise, if the duration of Bit being '0' is within the second range, then step 26 is entered, otherwise, step 21 is returned;
step 26: counting the duration of the leading P3 pulse Bit of the S mode ADS-B signal being '1', if the duration of the Bit being '1' is within a first range, entering step 27, otherwise returning to step 21;
step 27: counting the duration of the leading P3 pulse Bit of the S mode ADS-B signal being '0', and returning to the step 21 if the duration of the Bit being '0' exceeds a third length; otherwise, if the duration of Bit being '0' is within the first range, then step 28 is entered, otherwise, step 21 is returned;
step 28: counting the duration of the leading P4 pulse Bit of the S mode ADS-B signal being '1', if the duration of the Bit is within a first range, entering step 29, otherwise returning to step 21;
step 29: after the synchronization head is detected, the step 210 is entered after waiting for a preset time period (for example, 3 us), and the data recovery is started;
step 210: starting to perform cycle counting, wherein the cycle number is 224, the counting period is 0.5us, the value of the output pulse_o after the narrow interference pulse is eliminated is output to a shift register at the position of 0.25us in each counting, and the step 211 is performed after the cycle is finished;
step 211: the value in the shift register of 224 is decided every 2Bit, and if '01' is decoded to output '0', and if '10' is decoded to output '1', and finally the decoded output of S mode ADS-B with 112Bit length is obtained, and the process returns to step 21.
Further, the first range is the leading P pulse width±the second length; the second length is a range T2 in which the length of pulse width distortion is allowed to be formed;
the second range is a range of low level time + -second length between the preambles P2 and P3;
the third length is the low level timeout length T3 between the P1 pulse and the P2 pulse of the synchronous head;
the fourth length is the low level timeout length T4 between the sync header P2 pulse and the P3 pulse.
In a second aspect, the present invention further provides a large dynamic range S-mode ADS-B signal decoding system using a large dynamic range S-mode ADS-B signal decoding method as described above; the system comprises:
the threshold calculation unit is used for carrying out static threshold setting and dynamic threshold calculation according to the output amplitude data of the ADS-B receiver to obtain a static threshold and a dynamic threshold;
the signal demodulation unit is used for delaying the ADC output signal of the ADS-B receiver by using the static threshold and the dynamic threshold and then comparing the delayed ADC output signal with the static threshold and the dynamic threshold to complete demodulation of the input S-mode ADS-B signal and obtain a demodulation signal;
the interference elimination unit is used for eliminating the narrow interference pulse of the demodulation signal by adopting a narrow interference pulse elimination technology to obtain the demodulation signal after the narrow interference elimination;
and the signal decoding unit is used for carrying out synchronous head detection and data block recovery decoding based on the format of the S-mode ADS-B signal according to the demodulation signal after the narrow interference is eliminated.
Further, the setting of the static threshold is to set the threshold of the static threshold according to the noise floor amplitude level of the ADS-B receiver;
the calculation method of the dynamic threshold is as follows:
establishing a detection window according to an S-mode ADS-B signal which is captured by an ADS-B receiver and is interfered by a wireless channel, IQ leakage of a transmitter and noise of the receiver; at least one complete high level and low level is contained in the detection window;
searching the detection window in real time by adopting a sliding search mode, and searching the maximum value and the minimum value of the S mode ADS-B signal within preset time;
taking a median value for the maximum value and the minimum value, and multiplying the median value by a dynamic threshold coefficient to obtain a dynamic threshold;
wherein the dynamic threshold coefficient is related to the threshold capacity between the high and low levels of the transmitter.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the invention provides a large dynamic range S-mode ADS-B signal decoding method and system, and provides a real-time dynamic threshold calculation method, wherein the dynamic threshold is utilized to realize the judgment of the high level and the low level of an S-mode ADS-B signal. The problem that the high signal low level is higher than the low signal high level due to IQ leakage of the ADS-B transmitter can not be solved by using the static threshold of the traditional ADS-B receiver is effectively solved, the decoding dynamic range of the ADS-B receiver is expanded, and the requirement on IQ leakage control of the ADS-B transmitter is also relaxed.
2. The invention provides a method and a system for decoding an S-mode ADS-B signal with a large dynamic range, which provides a narrow interference pulse elimination technology, completes the error correction of binary bit streams before decoding, reduces decoding burden and enhances the anti-interference capability of a system.
3. The invention provides a large dynamic range S-mode ADS-B signal decoding method and a system, and provides an anti-pulse width distortion S-mode ADS-B signal synchronous head detection method and a data block timing recovery method based on pulse position invariance characteristics, which greatly simplify decoding logic and enhance the selective fading resistance of the system.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
FIG. 1 is a flow chart of a method for decoding an ADS-B signal with a large dynamic range S mode according to the present invention;
FIG. 2 is a schematic diagram of a data format of an S-mode ADS-B signal;
FIG. 3 is a block diagram illustrating a large dynamic range S-mode ADS-B signal decoding system according to the present invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Example 1
As shown in fig. 1, the present invention is a method for decoding a large dynamic range S-mode ADS-B signal, the method comprising:
step 1, according to output amplitude data of an ADS-B receiver, static threshold setting and dynamic threshold calculation are carried out, and a static threshold and a dynamic threshold are obtained;
specifically, in the process of receiving the ADS-B signal, the signal output by the digital part ADC may be approximately decomposed into 4 parts: receiver noise floor, ADS-B high level signal, ADS-B low level signal, and other interfering signals. The noise floor of the receiver can be determined when the receiver is shipped from a factory, and is generally obviously smaller than the high level of the ADS-B signal when the receiver is sensitive. Thus, a static threshold (i.e., a minimum threshold) may be predetermined, and set based on the noise floor amplitude level of the ADS-B receiver, for distinguishing between noise floor and signal of the receiver, where a signal refers to an ADS-B high level signal, an ADS-B low level signal, and other interfering signals.
On the basis of determining the static threshold, a dynamic threshold is also calculated in real time, and is used for distinguishing the high level and the low level of the S-mode ADS-B signal under the condition of receiving different powers. The dynamic threshold calculation principle is as follows: searching a maximum value (P_MAX) and a minimum value (P_MIN) of the ADS-B signal in real time according to the S-mode ADS-B signal which is captured by the receiver and is interfered by a wireless channel, IQ leakage of a transmitter and noise of the receiver, taking the maximum value (P_MAX) and the minimum value (P_MIN) as high-level and low-level amplitude values of the ADS-B signal, calculating a median value according to the high-level and low-level amplitude values, and multiplying a dynamic threshold coefficient as a dynamic threshold value of demodulation; wherein the dynamic threshold coefficient alpha (0 < alpha < 1) is related to the threshold capacity between the high and low levels of the transmitter.
As shown in fig. 2, fig. 2 is a data format of an S-mode ADS-B signal; as can be seen from the data format of the S-mode ADS-B signal of fig. 2, it is mainly composed of 4 preamble P pulses and 112bit data bits. Wherein the preamble P pulse width is fixed 0.5us, the interval between the P1 and P2 pulses is 1us, the interval between the P3 and P4 pulses is 1us, the interval between the P2 and P3 pulses is 2.5us, and the interval between the P4 preamble pulse and the first data bit is 3.5us. The data block has a bit width of 1us per bit and consists of a high level of 0.5us and a low level of 0.5 us.
To search for the high and low levels of the ADS-B signal captured by the receiver, a detection window is established, and at least one complete high level and low level should be included in the detection window. As can be seen from fig. 2, the high-low level interval in the entire ADS-B signal is furthest located at the leading P4 pulse and the first data bit (3.5 us), so the search window is minimum 4.5us.
The detection window adopts a sliding search mode, and each clock of the FPGA enters into one piece of latest data and pops up one piece of oldest data. In order to save search time and ensure decoding instantaneity of ADS-B signals, a pipeline comparison mode of 'area change speed' is adopted for 4.5us data in a window, and a maximum value and a minimum value are output by each clock after a plurality of stages of pipelines.
And taking the amplitude median value of the maximum value and the minimum value output by the detection window, and multiplying the median value by a coefficient alpha to serve as a real-time dynamic threshold of demodulation.
Step 2, the static threshold and the dynamic threshold are utilized to delay the ADC output signal of the ADS-B receiver by the same clock, and then the delayed ADC output signal is compared with the static threshold and the dynamic threshold, so that the demodulation of the input S-mode ADS-B signal is completed, and a demodulation signal is obtained;
specifically, in the process of searching and calculating the dynamic threshold, the searching and the threshold calculation of the high and low levels can bring a plurality of clocks to delay, and the delay amount is mainly determined by the depth of a pipeline and the implementation mode of the threshold calculation. Therefore, the ADC output signal of the ADS-B receiver needs to be delayed by the same clock and then compared and demodulated with the threshold.
The specific demodulation method comprises the following steps:
when the amplitude of the ADC output signal delayed and output by the ADS-B receiver is larger than the static threshold and the dynamic threshold, the input S-mode ADS-B signal is demodulated to be '1', otherwise, the input S-mode ADS-B signal is demodulated to be '0'.
Step 3, adopting a narrow interference pulse elimination technology to eliminate narrow interference pulses from the demodulation signal, and obtaining the demodulation signal after narrow interference elimination;
since the ADS-B signal captured by the receiver may be subject to interference from an external burst signal or receiver noise floor near sensitivity, the '01' bit stream output after demodulation is embodied as short-time or discontinuous narrow-pulse interference. To eliminate the effect on subsequent decoding, these short or discontinuous narrow pulses need to be eliminated. Here, it is shown that: the first length is the pulse width T1 of the short duration disturbance pulse, and any pulse with a pulse width less than T1 will be considered a disturbance pulse and should be eliminated. Simultaneously, the following expressions are shown: the bit stream of the demodulated output is pulse_i, and the output after the narrow interference pulse is eliminated is pulse_o.
Specifically, the narrow interference pulse cancellation technique is used to cancel the narrow interference pulse of the demodulation signal, including:
step 11: detecting a rising edge of the bit stream puls_i outputted by demodulation, and if the rising edge is detected, proceeding to step 12, wherein puls_o is '0';
step 12: counting the duration of Bit '1' of pulse_i, returning to step 11 if the duration of Bit '1' is less than the first length, otherwise entering step 13, and outputting '0' during pulse_o;
step 13: continuing to detect whether the pulse_i is '1', if so, starting to output '1' by the pulse_o, otherwise, entering step 14;
step 14: the pulse_o output '1' is maintained for a first length of time and then returns to step 11.
And 4, according to the demodulation signal after the narrow interference elimination, carrying out synchronous head detection and data block recovery decoding based on the format of the S-mode ADS-B signal.
Specifically, decoding of the S-mode ADS-B signal is completed, and first the synchronization header needs to be detected. An important basis for sync head detection is that the pulse width and the interval between pulses need to conform to the signal format definition of the S-mode. The level width of the ADS-B signal may be distorted due to interference from the radio transmission channel, and may be lengthened or shortened after decision, but the overall interval between pulse sequences may not be changed. Here, it is shown that: the second length is a length T2 for allowing pulse width distortion, the third length is a low level timeout length T3 between the synchronous heads P1 and P2, and the fourth length is a low level timeout length T4 between the synchronous heads P2 and P3.
Specifically, the synchronous header detection and data block recovery decoding based on the format of the S-mode ADS-B signal includes:
step 21: detecting the rising edge of the demodulated signal after the narrow interference is eliminated (namely, the bit stream pulse_o after the short interference pulse is eliminated), and entering step 22 after the rising edge is detected;
step 22: counting the duration of the leading P1 pulse Bit of the S mode ADS-B signal being '1', if the duration of Bit being '1' is within 0.5us + -T2, then entering step 23, otherwise returning to step 21;
step 23: counting the duration of the leading P1 pulse Bit of the S mode ADS-B signal being '0', and returning to the step 21 if the duration of the Bit being '0' exceeds a third length; otherwise, if the duration of Bit being '0' is within 0.5us + -T2, then step 24 is entered, otherwise, step 21 is returned;
step 24: counting the duration of the leading P2 pulse Bit of the S mode ADS-B signal with '1', if the duration of the Bit with '1' is within 0.5us + -T2, entering step 25, otherwise returning to step 21;
step 25: counting the duration of the leading P2 pulse Bit of the S mode ADS-B signal being '0', and returning to the step 21 if the duration of the Bit being '0' exceeds the fourth length; otherwise, if the duration of Bit being '0' is within 2us + -T2, then step 26 is entered, otherwise, step 21 is returned;
step 26: counting the duration of the leading P3 pulse Bit of the S mode ADS-B signal being '1', if the duration of the Bit being '1' is within 0.5us + -T2, entering step 27, otherwise returning to step 21;
step 27: counting the duration of the leading P3 pulse Bit of the S mode ADS-B signal being '0', and returning to the step 21 if the duration of the Bit being '0' exceeds a third length; otherwise, if the duration of Bit being '0' is within 0.5us + -T2, then step 28 is entered, otherwise, step 21 is returned;
step 28: counting the duration of the leading P4 pulse Bit of the S mode ADS-B signal being '1', if the duration of the Bit is within 0.5us + -T2, entering step 29, otherwise returning to step 21;
step 29: after the synchronous head detection is completed and 3us is waited, the step 210 is entered, and the data recovery is started;
step 210: starting to perform cycle counting, wherein the cycle number is 224, the counting period is 0.5us, the value of the output pulse_o after the narrow interference pulse is eliminated is output to a shift register at the position of 0.25us in each counting, and the step 211 is performed after the cycle is finished;
step 211: the value in the shift register of 224 is decided every 2Bit, and if '01' is decoded to output '0', and if '10' is decoded to output '1', and finally the decoded output of S mode ADS-B with 112Bit length is obtained, and the process returns to step 21.
The specific implementation is as follows:
(1) Setting the sampling rate of the ADC and the working clock of the FPGA to be 100MHz, each clock is 10ns. To optimize storage resources and search speed, the detection window length was set to 512, with a corresponding search duration of 5.12us.
(2) In order to cope with the situation that the received pulse is faded, the dynamic threshold coefficient alpha is set to 0.75, namely, the calculation mode of the dynamic threshold is as follows: 0.5 (p_max+p_min) 0.75.
(3) The receiver low noise maximum after quantization of a 14bit wide ADC is 15, and to preserve sufficient margin, a static threshold (minimum threshold) is set to 30.
(4) Setting the pulse width T1 of the disturbing narrow pulse to 200ns, i.e. a pulse smaller than 200ns, will be cancelled.
(5) The synchronization pulse skew T2 is set to 200ns, i.e., pulses with pulse width lengths between 300ns and 700ns will be considered valid pulses.
(6) The low-level timeout length T3 between the sync heads P1 and P2 is set to 800ns, and the low-level timeout length T4 between the sync heads P2 and P3 is set to 2.8us.
The steps 1 to 4 are performed.
The invention has the following advantages:
(1) The invention provides a calculation method of a real-time dynamic threshold, which utilizes the dynamic threshold to realize the judgment of the high level and the low level of an S-mode ADS-B signal. The problem that the high signal low level is higher than the low signal high level due to IQ leakage of the ADS-B transmitter can not be solved by using the static threshold of the traditional ADS-B receiver is effectively solved, the decoding dynamic range of the ADS-B receiver is expanded, and the requirement on IQ leakage control of the ADS-B transmitter is also relaxed.
(2) The invention provides a narrow interference pulse eliminating technology, which completes the error correction of binary bit stream before decoding, reduces decoding load and enhances the anti-interference capability of the system.
(3) The invention provides a pulse width distortion resistant S-mode ADS-B signal synchronous head detection method and a pulse position invariant characteristic-based data block timing recovery method, which greatly simplify decoding logic and enhance the selective fading resistance of a system.
Example 2
As shown in fig. 3, the present embodiment is different from embodiment 1 in that the present embodiment provides a large dynamic range S-mode ADS-B signal decoding system using a large dynamic range S-mode ADS-B signal decoding method of embodiment 1; the system comprises:
the threshold calculation unit is used for carrying out static threshold setting and dynamic threshold calculation according to the output amplitude data of the ADS-B receiver to obtain a static threshold and a dynamic threshold;
the signal demodulation unit is used for delaying the ADC output signal of the ADS-B receiver by using the static threshold and the dynamic threshold and then comparing the delayed ADC output signal with the static threshold and the dynamic threshold to complete demodulation of the input S-mode ADS-B signal and obtain a demodulation signal;
the interference elimination unit is used for eliminating the narrow interference pulse of the demodulation signal by adopting a narrow interference pulse elimination technology to obtain the demodulation signal after the narrow interference elimination;
and the signal decoding unit is used for carrying out synchronous head detection and data block recovery decoding based on the format of the S-mode ADS-B signal according to the demodulation signal after the narrow interference is eliminated.
In the embodiment, the setting of the static threshold is to set the threshold of the static threshold according to the noise floor amplitude level of the ADS-B receiver;
the calculation method of the dynamic threshold is as follows:
establishing a detection window according to an S-mode ADS-B signal which is captured by an ADS-B receiver and is interfered by a wireless channel, IQ leakage of a transmitter and noise of the receiver; at least one complete high level and low level is contained in the detection window; the length of the detection window covers at least 4.5us;
searching the detection window in real time by adopting a sliding search mode, and searching the maximum value and the minimum value of the S mode ADS-B signal within preset time;
taking a median value for the maximum value and the minimum value, and multiplying the median value by a dynamic threshold coefficient to obtain a dynamic threshold;
wherein the dynamic threshold coefficient is related to the threshold capacity between the high and low levels of the transmitter.
The execution process of each unit is performed according to the steps of the large dynamic range S-mode ADS-B signal decoding method in embodiment 1, and the details are not repeated in this embodiment.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (10)

1. A method for decoding a large dynamic range S-mode ADS-B signal, the method comprising:
according to the output amplitude data of the ADS-B receiver, static threshold setting and dynamic threshold calculation are carried out to obtain a static threshold and a dynamic threshold;
the ADC output signal of the ADS-B receiver is subjected to delay of the same clock and then is compared with the static threshold and the dynamic threshold, so that the demodulation of the input S-mode ADS-B signal is completed, and a demodulation signal is obtained;
adopting a narrow interference pulse elimination technology to eliminate narrow interference pulses from the demodulation signal to obtain a demodulation signal after narrow interference elimination;
and according to the demodulation signal after the narrow interference is eliminated, synchronous head detection and data block recovery decoding are carried out based on the format of the S-mode ADS-B signal.
2. A method of decoding an ADS-B signal in a high dynamic range S mode as claimed in claim 1, wherein the static threshold is a noise floor and a signal for distinguishing between ADS-B receivers, the signal including ADS-B high level signals, ADS-B low level signals and other interference signals;
the dynamic threshold is used to distinguish between high and low levels of the S-mode ADS-B signal when different powers are received.
3. A method of decoding a high dynamic range S-mode ADS-B signal according to claim 2, wherein the setting of the static threshold is a threshold setting of the static threshold according to a noise floor amplitude level of the ADS-B receiver.
4. The method for decoding a large dynamic range S-mode ADS-B signal according to claim 2, wherein the method for calculating the dynamic threshold is as follows:
establishing a detection window according to an S-mode ADS-B signal which is captured by an ADS-B receiver and is interfered by a wireless channel, IQ leakage of a transmitter and noise of the receiver; at least one complete high level and low level is contained within the detection window;
searching the detection window in real time by adopting a sliding search mode, and searching the maximum value and the minimum value of the S mode ADS-B signal within preset time;
taking a median value from the maximum value and the minimum value, and multiplying the median value by a dynamic threshold coefficient to obtain a dynamic threshold;
wherein the dynamic threshold coefficient is related to a threshold capacity between high and low levels of the transmitter.
5. A method of decoding a large dynamic range S-mode ADS-B signal according to claim 1, wherein demodulating the input S-mode ADS-B signal includes:
when the amplitude of the ADC output signal delayed and output by the ADS-B receiver is larger than the static threshold and the dynamic threshold, the input S-mode ADS-B signal is demodulated to be '1', otherwise, the input S-mode ADS-B signal is demodulated to be '0'.
6. The method for decoding a large dynamic range S-mode ADS-B signal according to claim 1, wherein the step of canceling the narrow interference pulses of the demodulated signal by using a narrow interference pulse cancellation technique includes:
step 11: detecting the rising edge of the demodulation signal, if the rising edge is detected, entering step 12, wherein the output after eliminating the narrow interference pulse is '0'; the demodulation signal is a bit stream output after demodulation;
step 12: counting the duration of Bit of the demodulation signal being '1', returning to step 11 if the duration of Bit being '1' is smaller than the first length, otherwise entering step 13, and eliminating the output '0' after narrow interference pulse;
step 13: continuously detecting whether the bit stream output after demodulation is '1', if so, starting to output '1' after eliminating the narrow interference pulse, otherwise, entering step 14;
step 14: maintaining the output '1' after the elimination of the narrow interference pulse for a first length of time, and then returning to step 11;
wherein the first length is the pulse width of the short duration disturbance pulse.
7. The method for decoding a large dynamic range S-mode ADS-B signal according to claim 1, wherein the synchronization header detection and the data block recovery decoding are performed based on a format of the S-mode ADS-B signal, comprising:
step 21: detecting the rising edge of the demodulation signal after the narrow interference is eliminated, and entering step 22 after the rising edge is detected;
step 22: counting the duration of the leading P1 pulse Bit of '1', if the duration of Bit of '1' is within a first range, proceeding to step 23, otherwise returning to step 21;
step 23: counting the duration of the leading P1 pulse Bit of '0', and returning to the step 21 if the duration of the Bit of '0' exceeds a third length; otherwise, if the duration of Bit being '0' is within the first range, go to step 24, otherwise, return to step 21;
step 24: counting the duration of the leading P2 pulse Bit of '1', if the duration of the Bit of '1' is within a first range, entering step 25, otherwise returning to step 21;
step 25: counting the duration of the leading P1 pulse Bit of '0', and returning to the step 21 if the duration of the Bit of '0' exceeds the fourth length; otherwise, if the duration of Bit being '0' is within the second range, then step 26 is entered, otherwise, step 21 is returned;
step 26: counting the duration of the leading P3 pulse Bit of '1', if the duration of the Bit of '1' is within a first range, entering step 27, otherwise returning to step 21;
step 27: counting the duration of the leading P3 pulse Bit of '0', and returning to the step 21 if the duration of the Bit of '0' exceeds a third length; otherwise, if the duration of Bit being '0' is within the first range, then step 28 is entered, otherwise, step 21 is returned;
step 28: counting the duration of the leading P4 pulse Bit of '1', if the duration of the Bit is within a first range, entering step 29, otherwise returning to step 21;
step 29: after the synchronous head detection is completed and waiting for a preset time length, the step 210 is carried out, and data recovery is started;
step 210: starting to perform cycle counting, wherein the cycle number is 2 x the Bit number of the data block, the counting period is the leading P pulse width, outputting an output value after eliminating the narrow interference pulse to a shift register at a position of half of the leading P pulse width in each counting, and entering step 211 after the cycle is finished;
step 211: and judging the value in the shift register of Bit number of the 2-by-2 Bit, decoding and outputting '0' if the value is '01', and decoding and outputting '1' if the value is '10', finally obtaining the decoding and outputting of S mode ADS-B of Bit number length of the data block Bit, and returning to the step 21.
8. The method of decoding a large dynamic range S-mode ADS-B signal of claim 7, wherein the first range is a preamble P pulse width ± second length; the second length is a range of length formations that allow pulse width distortion;
the second range is a range of low level time + -second length between the preambles P2 and P3;
the third length is the low level timeout length between the P1 pulse and the P2 pulse of the synchronous head;
the fourth length is the low level timeout length between the sync header P2 pulse and the P3 pulse.
9. A high dynamic range S-mode ADS-B signal decoding system, wherein the system uses a high dynamic range S-mode ADS-B signal decoding method as claimed in any one of claims 1 to 8; the system comprises:
the threshold calculation unit is used for carrying out static threshold setting and dynamic threshold calculation according to the output amplitude data of the ADS-B receiver to obtain a static threshold and a dynamic threshold;
the signal demodulation unit is used for delaying the ADC output signal of the ADS-B receiver by the same clock and then comparing the delayed ADC output signal with the static threshold and the dynamic threshold to complete demodulation of the input S-mode ADS-B signal and obtain a demodulation signal;
the interference elimination unit is used for eliminating the narrow interference pulse of the demodulation signal by adopting a narrow interference pulse elimination technology to obtain the demodulation signal after the narrow interference elimination;
and the signal decoding unit is used for carrying out synchronous head detection and data block recovery decoding based on the format of the S-mode ADS-B signal according to the demodulation signal after the narrow interference is eliminated.
10. A high dynamic range S-mode ADS-B signal decoding system as in claim 9, wherein the static threshold is set based on a noise floor level of the ADS-B receiver;
the calculation method of the dynamic threshold is as follows:
establishing a detection window according to an S-mode ADS-B signal which is captured by an ADS-B receiver and is interfered by a wireless channel, IQ leakage of a transmitter and noise of the receiver; at least one complete high level and low level is contained within the detection window;
searching the detection window in real time by adopting a sliding search mode, and searching the maximum value and the minimum value of the S mode ADS-B signal within preset time;
taking a median value from the maximum value and the minimum value, and multiplying the median value by a dynamic threshold coefficient to obtain a dynamic threshold;
wherein the dynamic threshold coefficient is related to a threshold capacity between high and low levels of the transmitter.
CN202311311642.9A 2023-10-10 2023-10-10 Large dynamic range S mode ADS-B signal decoding method and system Pending CN117572409A (en)

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