CN117560961A

CN117560961A - Display panel and display device

Info

Publication number: CN117560961A
Application number: CN202311441802.1A
Authority: CN
Inventors: 陈杰; 吴川; 曹中林; 李瑶; 韦东梅; 冯亚娟; 易文玉; 袁晓晓; 谢俊烽
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2023-10-31
Filing date: 2023-10-31
Publication date: 2024-02-13

Abstract

The application provides a display panel and a display device. According to the method, the first connecting wires and the second connecting wires are arranged in a staggered mode, so that the number of film layers where the connecting wires are located is increased, compared with the mode that the connecting wires are wired in the same layer in the prior art, the width of a stretching area where the connecting wires are located is reduced, the bending resistance of the stretching area is improved, and the risk of fracture failure of the display panel in the stretching process is reduced; further, the first connecting wire and the grid electrode are formed through the first metal layer in a patterning mode, and the second connecting wire and the source drain electrode layer are formed through the second metal layer in a patterning mode, so that the first connecting wire and the grid electrode can be directly connected in a lap joint mode without through holes, the second connecting wire and the source drain electrode layer can be directly connected in a lap joint mode without through holes, and the manufacturing process of the connecting wire is simplified under the condition that normal display of the display panel is not affected.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

The flexible stretchable display screen is widely focused by consumers as a novel display device, and is applicable to practical application of multiple scenes due to the advantages of being foldable, convenient to carry, wide in application range and the like. As a stretchable display product, when the screen is stretched, the screen is inevitably subjected to complex external forces such as stretching, and the inside of the stretchable flexible screen can be stretched and deformed to different degrees, and when the screen is stretched and deformed to a certain strain value, a thin film field effect transistor (thin film transistor, tft) and a pixel display device layer in the stretchable flexible screen are extremely fragile, so that the stretchable flexible screen can be directly caused to be unable to normally light.

Disclosure of Invention

The technical problem that this application mainly solves is to provide a display panel and display device, solves the unable problem of normal lighting of stretchable flexible screen of prior art.

In order to solve the technical problem, the first technical scheme provided by the application is as follows: providing a display panel having island regions and a stretched region between adjacent ones of the island regions; wherein, include:

a plurality of pixel islands located in the island region and including sub-pixels and thin film transistors connected to the sub-pixels;

a connecting wire located in the stretching region; each connecting wire is connected with two adjacent pixel islands; the connecting wires comprise first connecting wires and second connecting wires which are arranged in a staggered manner; the first connection line is used for being electrically connected with the grid electrode of the thin film transistor; the second connecting wire is used for electrically connecting the source electrode layer and the drain electrode layer of the thin film transistor;

the circuit layer comprises a first metal layer and a second metal layer which are stacked;

a flat layer located at the island region and the tensile region, and located at the upper surface of the wiring layer and covering the wiring layer;

wherein the first metal layer is used for forming the first connection line and the gate electrode; the second metal layer is used for forming the second connecting line and the source drain electrode layer.

The connecting wires further comprise third connecting wires which are staggered with the first connecting wires and the second connecting wires, and the third connecting wires are used for being electrically connected with cathodes of the sub-pixels.

Wherein the third connecting wire and the cathode are formed by patterning the same conductive layer.

The pixel island further comprises a conductive isolation structure arranged on the side edge of the sub-pixel, the conductive isolation structure comprises a conductive part and an insulating part arranged on the upper surface of the conductive part and shielding the conductive part, and the conductive part is electrically connected with the cathode of the sub-pixel to realize mutual electrical connection between the cathodes of the sub-pixels in the pixel island.

The third connecting wire and the conductive part are formed by patterning the same conductive layer.

At least two connecting wires are arranged between two adjacent pixel islands.

Wherein the pixel islands are distributed in an array; the first connecting line is positioned in the stretching area between two adjacent pixel islands in the row direction; the second connecting line is positioned in the stretching area between two adjacent pixel islands in the column direction; the third connecting line is positioned in the stretching area between two adjacent pixel islands.

Wherein the circuit layer further comprises a gate insulating layer and an interlayer insulating layer; the gate insulating layer, the first metal layer, the interlayer insulating layer and the second metal layer are stacked in sequence towards the direction close to the flat layer;

an opening penetrating through the gate insulating layer and the interlayer insulating layer is formed in the circuit layer, and the opening is located in the stretching region; defining openings in the stretched regions between adjacent pixel islands in the row direction as first openings, and defining openings in the stretched regions between adjacent pixel islands in the column direction as second openings;

the first connecting wire part is arranged in the first opening; the flat layer part is filled in the first opening and is in contact with the part of the first connecting line in the first opening;

the second connecting wire part is arranged in the second opening, and the flat layer part is filled in the second opening and is in contact with the part of the second connecting wire in the second opening.

The display panel further comprises a pixel definition layer arranged on one side of the flat layer, far away from the line layer, wherein a pixel opening positioned in the island region is arranged on the pixel definition layer, and the sub-pixel is positioned in the pixel opening; the conductive isolation structure is arranged on the upper surface of the pixel definition layer; the pixel definition layer is further provided with a third opening penetrating through the upper surface of the pixel definition layer and the lower surface of the pixel definition layer, the third connecting line is partially arranged in the third opening, and the flat layer and the portion, located in the third opening, of the third connecting line are in contact arrangement.

In order to solve the technical problem, the second technical scheme provided by the application is as follows: there is provided a display device including the above display panel.

The beneficial effects of this application: in contrast to the prior art, the present application provides a display panel and a display device, the display panel having islands and a stretched region between the islands. The display panel includes a plurality of pixel islands, connection wires, and a planarization layer. The plurality of pixel islands are located in the island region and include sub-pixels and thin film transistors connected to the sub-pixels. The connecting wires are positioned in the stretching area. Each connecting wire connects two adjacent pixel islands. The connecting wires comprise first connecting wires and second connecting wires which are arranged in a staggered mode. The first connection line is used for being electrically connected with the gate electrode of the thin film transistor. The second connecting wire is used for being electrically connected with the source electrode and the drain electrode layer of the thin film transistor. The circuit layer comprises a first metal layer and a second metal layer which are arranged in a laminated mode. The flat layer is positioned on the island region and the stretching region, is positioned on the upper surface of the circuit layer and covers the circuit layer. The first metal layer is used for forming a first connecting wire and a grid electrode. The second metal layer is used for forming a second connecting wire and the source drain electrode layer. According to the method, the first connecting wires and the second connecting wires are arranged in a staggered mode, so that the number of film layers where the connecting wires are located is increased, compared with the mode that the connecting wires are wired in the same layer in the prior art, the width of a stretching area where the connecting wires are located is reduced, the bending resistance of the stretching area is improved, and the risk of fracture failure of the display panel in the stretching process is reduced; further, the first connecting wire and the grid electrode are formed through the first metal layer in a patterning mode, and the second connecting wire and the source drain electrode layer are formed through the second metal layer in a patterning mode, so that the first connecting wire and the grid electrode can be directly connected in a lap joint mode without through holes, the second connecting wire and the source drain electrode layer can be directly connected in a lap joint mode without through holes, and the manufacturing process of the connecting wire is simplified under the condition that normal display of the display panel is not affected.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without any inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an embodiment of a display panel provided in the present application;

FIG. 2 is an enlarged view of a portion of FIG. 1 at A1;

FIG. 3 is a schematic cross-sectional view of the structure at E-E in FIG. 2;

FIG. 4 is a schematic cross-sectional view of the structure shown at F-F in FIG. 2;

FIG. 5 is a schematic cross-sectional view of the structure H-H of FIG. 2;

FIG. 6 is an enlarged view of a portion of FIG. 1 at A2;

FIG. 7 is a schematic cross-sectional view of the structure at K-K in FIG. 6;

FIG. 8 is a schematic cross-sectional view of the structure L-L of FIG. 6;

FIG. 9 is a schematic cross-sectional view of the structure at I-I in FIG. 2;

fig. 10 is a schematic view of a sectional structure at J-J in fig. 2.

Reference numerals illustrate:

10. a pixel island; 11. a sub-pixel; 111. an anode; 112. a light emitting layer; 113. a cathode; r, red pixel; G. a green pixel; B. a blue pixel; 12. a thin film transistor; 121. a gate; 122. a source/drain layer; 123. a source electrode; 124. a drain electrode; 125. an active layer; 13. a conductive isolation structure; 131. a conductive portion; 132. an insulating part; 20. connecting wires; 21. a first connecting line; 22. a second connecting line; 23. a third connecting line; 30. a circuit layer; 31. a first metal layer; 32. a second metal layer; 33. a gate insulating layer; 34. an interlayer insulating layer; 35. a first opening; 36. a second opening; 37. an opening; 40. a flat layer; 50. a pixel definition layer; 51. a pixel opening; 52. a third opening; 60. a passivation layer; 70. a buffer layer; 80. a substrate; 100. island regions; 200. stretching region.

Detailed Description

The following describes the embodiments of the present application in detail with reference to the drawings.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms "first," "second," "third," and the like in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1 to 8, fig. 1 is a schematic structural diagram of an embodiment of a display panel provided in the present application, fig. 2 is a partially enlarged view of a portion A1 in fig. 1, fig. 3 is a schematic sectional structure of a portion E-E in fig. 2, fig. 4 is a schematic sectional structure of a portion F-F in fig. 2, fig. 5 is a schematic sectional structure of a portion H-H in fig. 2, fig. 6 is a partially enlarged view of a portion A2 in fig. 1, fig. 7 is a schematic sectional structure of a portion K-K in fig. 6, and fig. 8 is a schematic sectional structure of a portion L-L in fig. 6.

The present application provides a display panel having island regions 100 and a stretched region 200 between the island regions 100. The display panel includes a plurality of pixel islands 10, connection wires 20, and a planarization layer 40. The plurality of pixel islands 10 are located in the island region 100 and include sub-pixels 11 and thin film transistors 12 connected to the sub-pixels 11. The connecting wire 20 is located in the stretch zone 200. Each connection wire 20 connects two adjacent pixel islands 10. The connection wire 20 includes a first connection wire 21 and a second connection wire 22 arranged in a staggered manner. The first connection line 21 is for electrically connecting with the gate electrode 121 of the thin film transistor 12. The second connection line 22 is used for electrically connecting the source/drain layer 122 of the thin film transistor 12. The wiring layer 30 includes a first metal layer 31 and a second metal layer 32 which are stacked. The planarization layer 40 is located at the island region 100 and the tensile region 200, and is located at the upper surface of the wiring layer 30 and covers the wiring layer 30. Wherein the first metal layer 31 is used to form the first connection line 21 and the gate electrode 121. The second metal layer 32 is used to form the second connection line 22 and the source drain layer 122.

According to the method, the first connecting wires 21 and the second connecting wires 22 are arranged in a staggered mode, so that the number of film layers where the connecting wires 20 are located is increased, and compared with the mode that the connecting wires 20 are wired in the same layer in the prior art, the width of the stretching area 200 where the connecting wires 20 are located is reduced, so that the bending resistance of the stretching area 200 is improved, and the risk of fracture failure of the display panel in the stretching process is reduced; further, the first connection line 21 and the gate electrode 121 are formed by patterning the first metal layer 31, and the second connection line 22 and the source drain electrode layer 122 are formed by patterning the second metal layer 32, so that the first connection line 21 and the gate electrode 121 can be directly overlapped without being connected through a via hole, and the second connection line 22 and the source drain electrode layer 122 can be directly overlapped without being connected through a via hole, and the manufacturing process of the connection wire 20 is simplified under the condition of not affecting the normal display of the display panel.

The display panel of the present application is a stretchable display panel. The portion of the display panel located at the island region 100 is not deformed during stretching, but is deformed slightly, and is negligible. The portion of the display panel located in the stretching region 200 may be deformed and recovered during the stretching process to achieve the stretching deformation of the display panel.

The pixel island 10 includes a sub-pixel 11 and a thin film transistor 12 connected to the sub-pixel 11. Each pixel island 10 comprises at least one sub-pixel 11. The sub-pixel 11 includes an anode 111, a light emitting layer 112, and a cathode 113, which are sequentially stacked. The sub-pixel 11 is an OLED (Organic Light-Emitting Diode). The anode 111 of the sub-pixel 11 is electrically connected to the source/drain layer 122 of the thin film transistor 12. One subpixel 11 corresponds to one color pixel. The shape and size of the sub-pixels 11 and the arrangement of the sub-pixels 11 are not limited, and may be selected according to practical requirements. The number of sub-pixels 11 within each pixel island 10 is not limited here. The number of sub-pixels 11 in different pixel islands 10 may or may not be the same, and is not limited herein.

The thin film transistor 12 includes an active layer 125 in addition to the gate electrode 121 and the source and drain electrode layer 122. The material and type of the thin film transistor 12 are not limited too much, and are selected according to practical requirements. The number of the thin film transistors 12 is plural, and one thin film transistor 12 is provided corresponding to one sub-pixel 11.

The source/drain electrode layer 122 refers to the source electrode 123 and the drain electrode 124, and in this application, the source/drain electrode layer 122 of the thin film transistor 12 and the source/drain electrode layer 122 are electrically connected to one of the source electrode 123 and the drain electrode 124, and are not electrically connected to both the source electrode 123 and the drain electrode 124.

In the present application, the pixel islands 10 are arranged in an array. The sub-pixels 11 are rectangular. Each pixel island 10 comprises three sub-pixels 11 of different colors. The arrangement of the sub-pixels 11 within each pixel island 10 is the same. Within each pixel island 10, three sub-pixels 11 of different colors are arranged side by side in the row direction in sequence. The three different color sub-pixels 11 are red, green and blue pixels R, G and B, respectively. The red pixel R, the green pixel G, and the blue pixel B in each pixel island 10 are sequentially arranged side by side.

It should be understood that in other embodiments, the sub-pixels 11 may be pixels of other colors, which are not limited herein, and are selected according to actual needs.

It is emphasized that the row direction of the present application refers to the row direction of the pixel islands 10 and the column direction refers to the column direction of the pixel islands 10.

Each connection wire 20 is connected to two adjacent pixel islands 10, which means that two ends of each connection wire 20 are respectively connected to cathodes 113 of two adjacent pixel islands 10, or two ends of each connection wire 20 are respectively connected to gates 121 of two adjacent pixel islands 10, or two ends of each connection wire 20 are respectively connected to source/drain layers 122 of two adjacent pixel islands 10.

The two ends of each connection wire 20 are respectively connected to the source/drain electrode layers 122 of two adjacent pixel islands 10, which means that the two ends of each connection wire 20 are respectively connected to the source electrodes 123 of two adjacent pixel islands 10, or the two ends of each connection wire 20 are respectively connected to the drain electrodes 124 of two adjacent pixel islands 10.

The first metal layer 31 is used to form the first connection line 21 and the gate electrode 121. It will be appreciated that the first connection line 21 and the gate electrode 121 are patterned through the first metal layer 31 such that the first connection line 21 may directly overlap the gate electrode 121 without being connected through a via hole. The second metal layer 32 is used to form the second connection line 22 and the source drain layer 122. It is understood that the second connection line 22 and the source drain layer 122 are patterned through the second metal layer 32, so that the second connection line 22 may directly overlap the source drain layer 122 without being connected through a via hole. That is, the connection wire 20 and the thin film transistor 12 do not need to be connected through a via hole, so that the manufacturing process of the connection wire 20 can be simplified.

Referring to fig. 3, 9 and 10, fig. 9 is a schematic sectional view of fig. 2 at I-I, and fig. 10 is a schematic sectional view of fig. 2 at J-J.

The connection wire 20 further includes a third connection line 23 provided in a staggered manner with the first connection line 21 and the second connection line 22, and the third connection line 23 is used for electrically connecting with the cathode 113 of the subpixel 11. The cathodes 113 of different pixel islands 10 are electrically connected to each other via a third connection line 23. The third connection line 23 may directly overlap the cathode 113 to form an electrical connection, or the third connection line 23 may also be electrically connected to the cathode 113 through other electrical conductors, without being limited thereto.

The material of the third connection line 23 may be the same as that of the cathode 113 or may be different from that of the cathode 113. When the material of the third connection line 23 is the same as that of the cathode 113, the third connection line 23 and the cathode 113 are patterned by the same conductive layer, so that the third connection line 23 and the cathode 113 can be directly overlapped without connecting through a via hole, and the preparation process of the third connection line 23 can be simplified.

In the present embodiment, the third connection line 23 is electrically connected to the cathode 113 through another electric conductor. The pixel island 10 further includes a conductive isolation structure 13 disposed on a side of the sub-pixel 11, where the conductive isolation structure 13 includes a conductive portion 131 and an insulating portion 132 disposed on an upper surface of the conductive portion 131 and shielding the conductive portion 131, and the conductive portion 131 is electrically connected to the cathode 113 of the sub-pixel 11 to realize mutual electrical connection between the cathodes 113 of the sub-pixels 11 in the pixel island 10. The material of the conductive portion 131 is not limited herein, and is selected according to actual requirements. The insulating portion 132 protrudes from the upper surface of the conductive portion 131, and extends out of the conductive portion 131 toward the adjacent conductive isolation structure 13. That is, the projection area of the insulating portion 132 is larger than the projection area of the conductive portion 131, so that when the sub-pixel 11 is evaporated, the evaporation angle of the cathode 113 and the light emitting layer 112 can be adjusted by the insulating portion 132, so as to ensure that the cathode 113 covers the light emitting layer 112 and forms a good overlap joint with the conductive portion 131. The shape of the insulating portion 132 is not limited here, and is selected according to actual requirements.

In this embodiment, the third connection line 23 and the conductive portion 131 are patterned by the same conductive layer, so that the third connection line 23 can directly overlap the conductive portion 131 without being connected through a via hole. The third connection line 23 is electrically connected to the cathode 113 through the conductive portion 131.

It should be appreciated that in other embodiments, the third connection lines 23 may be patterned by the same conductive layer as the cathode 113 even though the pixel island 10 includes the conductive isolation structures 13. The third connection line 23 may overlap the conductive portion 131 such that an electrical connection is made between the third connection line 23 and the cathode 113 through the conductive portion 131.

In this embodiment, the conductive isolation structure 13 is disposed in the pixel island 10, so that the sub-pixels 11 in the pixel island 10 can be electrically connected with each other through the conductive isolation structure 13, thereby implementing the removal of fine metal mask and significantly improving the pixel aperture 51 ratio; further, the conductive portion 131 in the conductive isolation structure 13 has better toughness than the organic layer and the inorganic layer, so that the structural rigidity of the pixel island 10 can be improved, the stretching deformation occurs in the stretching region 200 instead of the island region 100, the thin film transistor 12 and the sub-pixel 11 are protected from being damaged, the normal display of the display panel is ensured, and the quality of the display panel is improved.

At least two connection wires 20 are provided between two adjacent pixel islands 10. The pixel islands 10 are distributed in an array. The first connection line 21 is located in the stretched region 200 between two adjacent pixel islands 10 in the row direction. The second connection line 22 is located in the stretched region 200 between two adjacent pixel islands 10 in the column direction. The third connection line 23 is located in the stretched region 200 between two adjacent pixel islands 10.

It can be understood that at least one first connection line 21 and at least one third connection line 23 are provided in the stretching region 200 between two adjacent pixel islands 10 in the row direction; in the column direction, at least one second connection line 22 and at least one third connection line 23 are provided in the stretched region 200 between two adjacent pixel islands 10. The number of the first connection lines 21 and the number of the third connection lines 23 in each of the stretching regions 200 are not limited, and the number of the second connection lines 22 and the number of the third connection lines 23 in each of the stretching regions 200 are not limited, and are selected according to actual needs. The first connection line 21 and the third connection line 23 may be at least partially overlapped or may be offset in a direction perpendicular to the flat layer 40, which is not limited herein and is selected according to practical requirements. Similarly, in the direction perpendicular to the flat layer 40, the second connection line 22 and the third connection line 23 may be at least partially overlapped, or may be staggered, which is not limited herein, and may be selected according to practical requirements.

In the present embodiment, a plurality of first connection lines 21 and a plurality of third connection lines 23 are provided in the stretched region 200 between two adjacent pixel islands 10 in the row direction; in the column direction, a plurality of second connection lines 22 and a plurality of third connection lines 23 are disposed in the extension region 200 between two adjacent pixel islands 10 to ensure good overlap between the connection wires 20 and the pixel islands 10, and prevent the connection wires 20 from breaking to cause poor display.

The planarization layer 40 is an organic material. The material of the planarization layer 40 is not limited herein, and is selected according to actual needs.

The wiring layer 30 further includes a gate insulating layer 33 and an interlayer insulating layer 34. The gate insulating layer 33, the first metal layer 31, the interlayer insulating layer 34, and the second metal layer 32 are stacked in this order in a direction toward the flat layer 40. The wiring layer 30 is provided with an opening 37 penetrating the gate insulating layer 33 and the interlayer insulating layer 34, and the opening 37 is located in the tensile region 200. The openings 37 in the stretched regions 200 between the adjacent pixel islands 10 in the row direction are defined as first openings 35, and the openings 37 in the stretched regions 200 between the adjacent pixel islands 10 in the column direction are defined as second openings 36.

The first connecting line 21 is partially disposed in the first opening 35. The flat layer 40 is partially filled in the first opening 35 and is disposed in contact with a portion of the first connection line 21 located in the first opening 35. The second connection line 22 is partially disposed in the second opening 36, and the flat layer 40 is partially filled in the second opening 36 and is disposed in contact with a portion of the second connection line 22 located in the second opening 36. It can be understood that the portion of the circuit layer 30 located in the stretching region 200 is designed to be open, so that the flat layer 40 can be filled in the stretching region 200 as much as possible to improve the stretchability of the display panel.

The display panel further includes a pixel defining layer 50 disposed on a side of the planarization layer 40 away from the circuit layer 30, and a pixel opening 51 disposed in the island region 100 is disposed on the pixel defining layer 50, and the sub-pixel 11 is disposed in the pixel opening 51. The conductive isolation structure 13 is disposed on the upper surface of the pixel defining layer 50. The pixel defining layer 50 is further provided with a third opening 52 penetrating the upper surface of the pixel defining layer 50 and the lower surface of the pixel defining layer 50, the third connecting line 23 is partially disposed in the third opening 52, and the flat layer 40 is disposed in contact with a portion of the third connecting line 23 located in the third opening 52.

The display panel further includes a passivation layer 60, a buffer layer 70, and a substrate 80, the passivation layer 60 being disposed between the planarization layer 40 and the wiring layer 30. The buffer layer 70 is disposed between the substrate 80 and the wiring layer 30. The materials of the passivation layer 60, the buffer layer 70 and the substrate 80 are not limited herein, and are selected according to actual needs.

It should be appreciated that in other embodiments, the display panel may not include the buffer layer 70.

The application provides a display device, which comprises the display panel.

The foregoing is only the embodiments of the present application, and therefore, the patent protection scope of the present application is not limited thereto, and all equivalent structures or equivalent processes using the contents of the present application specification and the drawings are included in the patent protection scope of the present application, or directly or indirectly applied to other related technical fields.

Claims

1. A display panel having islands and stretched regions between adjacent ones of the islands; characterized by comprising the following steps:

2. The display panel of claim 1, wherein the connection wire further comprises a third connection wire staggered from the first connection wire and the second connection wire, the third connection wire for electrically connecting with a cathode of the subpixel.

3. The display panel of claim 2, wherein the third connection line and the cathode are patterned by the same conductive layer.

4. The display panel of claim 2, wherein the pixel island further comprises a conductive isolation structure disposed on a side of the sub-pixel, the conductive isolation structure comprising a conductive portion and an insulating portion disposed on an upper surface of the conductive portion and shielding the conductive portion, the conductive portion being electrically connected to the cathode of the sub-pixel to achieve mutual electrical connection between the cathodes of the sub-pixels within the pixel island.

5. The display panel according to claim 4, wherein the third connection line and the conductive portion are patterned by the same conductive layer.

6. The display panel of claim 4, wherein at least two of the connection wires are disposed between two adjacent pixel islands.

7. The display panel of claim 6, wherein the pixel islands are distributed in an array; the first connecting line is positioned in the stretching area between two adjacent pixel islands in the row direction; the second connecting line is positioned in the stretching area between two adjacent pixel islands in the column direction; the third connecting line is positioned in the stretching area between two adjacent pixel islands.

8. The display panel according to claim 7, wherein the wiring layer further comprises a gate insulating layer and an interlayer insulating layer; the gate insulating layer, the first metal layer, the interlayer insulating layer and the second metal layer are stacked in sequence towards the direction close to the flat layer;

9. The display panel of claim 8, further comprising a pixel definition layer disposed on a side of the planarization layer away from the line layer, the pixel definition layer having a pixel opening disposed therein, the sub-pixel being disposed within the pixel opening; the conductive isolation structure is arranged on the upper surface of the pixel definition layer; the pixel definition layer is further provided with a third opening penetrating through the upper surface of the pixel definition layer and the lower surface of the pixel definition layer, the third connecting line is partially arranged in the third opening, and the flat layer and the portion, located in the third opening, of the third connecting line are in contact arrangement.

10. A display device comprising the display panel according to any one of claims 1 to 9.