CN117559987A - Driving circuit, level conversion circuit thereof and electronic device - Google Patents

Abstract

A driving circuit, a level conversion circuit thereof and an electronic device are provided, and belong to the technical field of electronics. The level shift circuit includes a level shift module and a feedback control module. The level conversion module can perform level conversion on a pair of input signals to generate a pair of output signals. The feedback control module is capable of extracting an actual common mode signal in the pair of output signals and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal to control the common mode signal in the output signals generated by the level conversion module to be equal to the ideal common mode signal. Therefore, the reliable level conversion can be realized aiming at the levels of signals with different frequencies without setting a capacitor with a larger area, and the circuit design is facilitated.

Description

Driving circuit, level conversion circuit thereof and electronic device

Technical Field

The disclosure relates to the field of electronic technology, and in particular, to a driving circuit, a level conversion circuit thereof, and an electronic device.

Background

With the development of high-speed serial interface technology, the level will change in the process of multi-stage signal transmission, so that the level requirement of the post-stage circuit on the common mode signal is not necessarily matched with the common mode signal output by the pre-stage circuit, and therefore, a level conversion circuit is often required to be arranged for 'blocking and crossing' level conversion.

In the related art, the level conversion is usually performed by capacitive coupling, that is, the level conversion circuit generally includes a coupling capacitor. However, in order to realize level conversion of signals with different frequencies, such as high-frequency signals and low-frequency signals, a capacitor with a larger area is often required, which is not beneficial to circuit design.

Disclosure of Invention

The driving circuit, the level conversion circuit and the electronic device thereof can solve the problems that in the related art, in order to realize the level conversion of different frequency signals such as high-frequency signals and low-frequency signals, a capacitor with a larger area is needed, and the circuit design is not facilitated. The technical scheme is as follows:

in one aspect, there is provided a level shift circuit including:

a level shift module configured to: receiving a pair of input signals, and performing level conversion on the pair of input signals to generate a pair of output signals; wherein the pair of input signals and the pair of output signals each include a common mode signal;

a feedback control module configured to: and receiving an ideal common mode signal and the pair of output signals, extracting an actual common mode signal in the pair of output signals, and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal so as to control the common mode signal in the pair of output signals generated by the level conversion module to be equal to the ideal common mode signal.

Optionally, the pair of input signals are differential input signals; the pair of output signals is a pair of differential output signals.

Optionally, the feedback control module includes:

an extraction unit configured to: receiving the pair of output signals and extracting an actual common mode signal in the pair of output signals;

a control unit configured to: and receiving the ideal common mode signal and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal.

Optionally, the extracting unit includes: a pair of common mode resistors with equal resistance values; the control unit includes: an amplifier;

wherein a first end of the pair of common mode resistors receives the pair of output signals; the second ends of the pair of common mode resistors output the actual common mode signals to the first input end of the amplifier; a second input of the amplifier receives the ideal common mode signal; the output end of the amplifier outputs the feedback control signal.

Optionally, the level conversion module includes:

a first level shift unit configured to: receiving one input signal of the pair of input signals, and performing level conversion on the one input signal to generate an output signal;

a second level shift unit configured to: the other input signal of the pair of input signals is received and level-converted to produce the other output signal.

Optionally, the first level conversion unit and the second level conversion unit each include a switch portion and an impedance portion;

the control end of the switch part receives the feedback control signal, one end of the input end and the output end of the switch part receives a power supply signal, and the other end receives an input signal through the impedance part and generates an output signal;

the feedback control signal is used for controlling the current generated by the switching part so that the common mode signal of the pair of output signals generated by the level conversion module is equal to the ideal common mode signal.

Optionally, the switch part includes a P-type transistor; the impedance part comprises an RC parallel circuit;

the grid electrode of the P-type transistor is used as the control end of the switch part, one of the first pole and the second pole of the P-type transistor is used as the input end, and the other pole is used as the output end.

Optionally, the level shift circuit is configured to: outputting the pair of output signals to a coupled pair of output terminals;

the level shift circuit further includes: a load capacitor connected in series between each of the pair of output terminals and ground; and a comparison capacitor connected in series between the control end and the ground end of the switch part.

In another aspect, there is provided a driving circuit including:

a level shift circuit as described in the above aspect;

an output driving circuit configured to: a pair of driving signals is output based on a pair of output signals generated by the level shift circuit.

In yet another aspect, an electronic device is provided, the electronic device comprising:

a load;

the driving circuit as described in the above another aspect, configured to: a pair of drive signals is output to the load to drive the load to operate.

In summary, the beneficial effects brought by the technical scheme provided by the disclosure at least may include:

a driving circuit, a level shift circuit thereof, and an electronic device are provided. The level shift circuit includes a level shift module and a feedback control module. The level conversion module can perform level conversion on a pair of input signals to generate a pair of output signals. The feedback control module is capable of extracting an actual common mode signal in the pair of output signals and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal to control the common mode signal in the output signals generated by the level conversion module to be equal to the ideal common mode signal. Therefore, the reliable level conversion can be realized aiming at the levels of signals with different frequencies without setting a capacitor with a larger area, and the circuit design is facilitated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 shows a schematic circuit diagram of an output driving circuit provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of transistor size as a function of common mode voltage of an input signal according to an embodiment of the present disclosure;

FIG. 3 shows a schematic circuit diagram of a capacitively coupled level shifter circuit of the related art;

FIG. 4 is a schematic diagram showing a comparison of an input voltage and an output voltage in the related art;

fig. 5 shows a schematic circuit diagram of a level shifter circuit of a CMOS logic in the related art;

FIG. 6 shows a schematic block diagram of a level shifter circuit provided by an embodiment of the present disclosure;

FIG. 7 shows a schematic block diagram of another level shifter circuit provided by an embodiment of the present disclosure;

FIG. 8 shows a schematic block diagram of yet another level shifter circuit provided by an embodiment of the present disclosure;

fig. 9 shows a schematic circuit diagram of a level shifter circuit provided by an embodiment of the present disclosure;

FIG. 10 shows a schematic block diagram of a driving circuit provided by an embodiment of the present disclosure;

fig. 11 shows a schematic block diagram of an electronic device provided by an embodiment of the disclosure.

Detailed Description

For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.

It should be noted that, the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain thereof are interchangeable, wherein the source is referred to as a first pole and the drain is referred to as a second pole, or wherein the drain is referred to as a first pole and the source is referred to as a second pole. The middle terminal of the transistor is defined as a gate, the signal input terminal is a source, and the signal output terminal is a drain according to the form in the figure. Further, the switching transistor employed in the embodiments of the present disclosure may include any one of a P-type transistor and an N-type transistor or a combination thereof. The P-type transistor is turned on when the grid is at low voltage, turned off when the grid is at high voltage, and turned on when the grid is at high voltage, and turned off when the grid is at low voltage.

Typically, a level shifter circuit may be coupled to the output driver circuit to input a desired common mode signal, also known as a common mode voltage, to the output driver circuit.

Fig. 1 shows a schematic circuit diagram of an output driving circuit provided by an embodiment of the present disclosure.

As shown in fig. 1, the output driving circuit may include two amplifying transistors M1 and M2, a tail current transistor M3, and two resistors Rd, and the coupling manner of each part is shown in fig. 1 and will not be described again. The level shift circuit may transmit a pair of input signals to the gates (identified as input terminal DIN in the figure) of the two amplifying transistors M1 and M2, so that the two amplifying transistors M1 and M2 output a pair of driving signals to the output terminals TXp and TXn.

Alternatively, in some embodiments, the output drive circuit of FIG. 1 has a maximum output swing of 900 millivolts (mV) on a single end. At this swing, it is difficult to achieve with a supply voltage of 1.1 volt (V) from the supply terminal v_h, so a supply voltage of 1.8V is required, which is the voltage supplied to one terminal of the resistor Rd. In order for both the amplifying transistor and the wake-up transistor to operate in saturation, the common mode voltage Vcm of the input signal should be greater than vth+2vov (Vth refers to the threshold current of the amplifying transistor and Vov refers to the voltage generated across the wake-up transistor M3). In a 1.8V high voltage transistor, the threshold voltage may be as high as 750mV or more at SS coupler, while if the input signal is at a logic level of 0-1.1V, the common mode voltage is about 550mV, which causes the amplifying transistor and the wake-up transistor to enter the linear region. In addition, since the transconductance of the amplifying transistor in the linear region is smaller, the size of the amplifying transistor needs to be increased to obtain a larger current. SS burner refers to a process corner design of Slow N Slow P to form an N-type or P-type transistor with a slower processing speed (S). Accordingly, there is also a TT corn design for forming a Typical N-type or P-type transistor (T) that is not slow or fast in processing speed.

By way of example, taking TT counter and fixed output swing as an example, fig. 2 shows a schematic diagram of transistor size versus common mode voltage variation of an input signal provided by an embodiment of the present disclosure. The abscissa is used for representing the common mode voltage of an input signal, namely the common mode voltage of the input signal, and the unit is V; the ordinate is used to indicate that the normalized size of the output differential pair, i.e., the transistor size, is the aspect ratio of the transistor. As can be seen with reference to fig. 2, increasing the common mode voltage of the input signal can effectively reduce the transistor size. For this reason, as described in the above embodiments, it is considered to provide a level shift circuit before the input drive circuit to boost the common mode voltage of the input signal transmitted to the output drive circuit.

Fig. 3 shows a schematic circuit diagram of a capacitive-coupled level shifter circuit in the related art. As shown in fig. 3, the level shift circuit includes a coupling capacitor Cac, a constant resistor R1, and a variable resistor R2. The coupling manner of each part is shown in fig. 3, and will not be described again. The input terminal IN may receive an input signal, and the output terminal OUT may be coupled to the input terminal DIN of the output driving circuit shown IN fig. 1. The level conversion circuit can be used for realizing common-mode voltage lifting by transmitting an input signal level from an input end IN to an input end DIN of the output driving circuit through an output end OUT after level conversion.

It can be seen that the structure shown in fig. 3 has a lower cut-off frequency, cut-off frequency f _-3dB Can satisfy the following conditions:

where R10 denotes the resistance of the resistor R1, R20 denotes the resistance of the resistor R2, and Cac0 denotes the capacitance of the coupling capacitor Cac. Since the MIPI-a-PHY protocol, a data transmission protocol of a processor interface in the mobile industry, needs to support low-speed data with a rate of 5 megabits per second (Mbps), in order to achieve such a transmission rate, the capacitance value of the coupling capacitor Cac needs to be at least 1 nano-farad (nF) in the case that the parallel resistor r10||r20 is 100 kiloohms (kΩ), and it is currently difficult to implement such a large capacitance on a chip.

In addition, at the time of power-up, since the common mode signal needs to be gradually established, the output of the coupling capacitor Cac in the structure shown in fig. 3 will exceed the supply voltage during the process of establishing the common mode signal, that is, an overvoltage abnormality occurs. In particular, fig. 4 shows a schematic diagram of comparison of an input voltage and an output voltage. Wherein the abscissa in FIG. 4 is used to represent time in microseconds (μs); the ordinate is used to represent voltage in volts V, and the bold line segment represents the output voltage; the thin line segment represents the input voltage, where the thick line segment and the thin line segment are relatively speaking. Referring to table 4, it can be seen that during the process of establishing the common mode signal, the output voltage is far greater than the input voltage, and an overvoltage abnormality, i.e., an overvoltage problem, occurs.

Fig. 5 shows a schematic circuit diagram of a level shift circuit of a CMOS logic in the related art. As shown in fig. 5, the level shift circuit includes four switching transistors M1 to M4, and three inverters F1 to F3. The input terminal IN may receive an input signal, and the output terminal OUT may be coupled to the input terminal DIN of the output driving circuit shown IN fig. 1. The level conversion circuit is used for level converting an input signal from an input end IN and transmitting the level converted input signal to an input end DIN of the output driving circuit through an output end OUT so as to realize common-mode voltage lifting.

However, the structure shown in fig. 5 generates large dynamic power consumption in the level conversion process, and delay is generated due to the existence of the inverter, so that output jitter is caused. For this reason, two identical structures as shown in fig. 5 are required to achieve differential output. In addition, the common mode voltage of the output signal of the CMOS (complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, abbreviated as CMOS) logic data including both P-type transistor and N-type transistor) is 0.9V, which cannot meet the requirement of SS burner.

In fig. 5, transistors M1 and M2 are P-type transistors, and transistors M3 and M4 are N-type transistors.

It should be noted that in the structure shown in fig. 5, the inverter may also be coupled to the power terminal v_l. V_l may be a pull-down power terminal that may provide a pull-down voltage that is less than the supply voltage provided by the supply terminal v_h. Accordingly, h may refer to a short for high (high); l may refer to a low (low) abbreviation.

As is clear from the above description, in the prior art, the level shift circuit is often difficult to realize in practical applications according to the frequency required by the protocol and the limitation of the on-chip capacitance. Based on this, the embodiment of the disclosure provides a new level conversion circuit, which can solve the above problems existing in the current level conversion circuit, and has better applicability.

Fig. 6 shows a schematic block diagram of a level shifter circuit provided by an embodiment of the present disclosure. As shown in fig. 6, the level shift circuit includes: a level conversion module 01 and a feedback control module 02.

For example, the level shift module 01 can be configured to: a pair (i.e., two) of input signals is received and level converted to produce a pair of output signals.

For example, referring to fig. 6, the level conversion module 01 may be coupled to a pair of input terminals INP and INM to receive a pair of input signals from the pair of input terminals INP and INM. And, the level conversion module 01 may be further coupled to a pair of output terminals OUTP and OUTM to output a pair of output signals generated based on the received pair of input signals through the pair of output terminals OUTP and OUTM. For example, the pair of output terminals OUTP and OUTM may be coupled to the gates of the two amplifying transistors M1 and M2 in the output driving circuit shown in fig. 1 in a one-to-one correspondence manner, so as to output a pair of output signals generated by the level conversion to the output driving circuit, so that the output driving circuit further outputs a pair of driving signals to the output terminals TXp and TXn based on the pair of output signals. That is, the pair of output signals may be input signals received by the output driving circuit.

Alternatively, the pair of input terminals INP and INM may be in one-to-one correspondence with the pair of output terminals OUTP and OUTM. That is, the input terminal INP corresponds to the output terminal OUTP; the input terminal INM corresponds to the output terminal OUT. The level conversion module 01 may perform level conversion on the input signal from the input terminal INP to generate an output signal, and output the output signal to the corresponding output terminal OUTP, and perform level conversion on the input signal from the input terminal INM to generate an output signal, and output the output signal to the corresponding output terminal OUTM.

Wherein the pair of input signals and the pair of output signals each comprise a common mode signal.

For example, the feedback control module 02 can be configured to: and receiving the ideal common mode signal and a pair of output signals, extracting an actual common mode signal in the pair of output signals, and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal so as to control the common mode signal in the pair of output signals generated by the level conversion module to be equal to the ideal common mode signal.

For example, with continued reference to fig. 6, the feedback control module 02 may be coupled to a desired (desired, simply de) ideal common mode terminal vcm_de to receive an ideal common mode signal provided by the ideal common mode terminal vcm_de, the ideal common mode signal belonging to a predetermined value. The feedback control module 02 may be coupled to a pair of output terminals OUTP and OUTM to receive a pair of output signals output via the pair of output terminals OUTP and OUTM and extract an actual common mode signal of the pair of output signals. And, the feedback control module 02 may also be coupled to the level shift module 01 to transmit a feedback control signal to the level shift module 01 based on the ideal common mode signal and an actual common mode signal extracted from a pair of output signals. The feedback control signal can control the current generated by the level conversion module 01, so that the common mode signal in the pair of generated output signals is equal to the ideal common mode signal, namely, the set value is reached, and reliable level conversion is realized.

In summary, the embodiments of the present disclosure provide a level shifter circuit. The level shift circuit includes a level shift module and a feedback control module. The level conversion module can perform level conversion on a pair of input signals to generate a pair of output signals. The feedback control module is capable of extracting an actual common mode signal in the pair of output signals and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal to control the common mode signal in the output signals generated by the level conversion module to be equal to the ideal common mode signal. Therefore, the reliable level conversion can be realized aiming at the levels of signals with different frequencies without setting a capacitor with a larger area, and the circuit design is facilitated.

Alternatively, in embodiments of the present disclosure, the pair of input signals may be differential input signals. The pair of output signals may be a pair of differential output signals. That is, the pair of input signals are identical in magnitude and opposite in polarity; the pair of output signals are identical in magnitude and opposite in polarity.

Fig. 7 shows a schematic block diagram of another level shifter circuit provided by an embodiment of the present disclosure. As shown in fig. 7, the level shift module 01 may include: a first level shift unit 011 and a second level shift unit 012.

For example, the first level converting unit 011 can be configured to: one input signal of a pair of input signals is received and level-converted to an output signal.

For example, referring to fig. 7, the first level converting unit 011 may be coupled to the input terminal INP and the output terminal OUTP in a one-to-one correspondence, respectively, to receive an input signal from the input terminal INP and output an output signal generated by level converting the input signal via the output terminal OUTP.

For example, the second level shift unit 012 can be configured to: the other input signal of the pair of input signals is received and level-converted to produce the other output signal.

For example, referring to fig. 7, the second level converting unit 012 may be coupled to the input terminal INM and the output terminal OUTM, respectively, to receive an input signal from the input terminal INM, and output an output signal generated by level converting the input signal via the output terminal OUTM.

Optionally, with continued reference to fig. 7, in an embodiment of the present disclosure, the feedback control module 02 may include: an extraction unit 021 and a control unit 022.

For example, the extraction unit 021 can be configured to: a pair of output signals is received and an actual common mode signal of the pair of output signals is extracted.

For example, referring to fig. 7, the extraction unit 021 in the feedback control module 02 may be coupled to a pair of output terminals OUTP and OUTM to receive a pair of output signals output via the pair of output terminals OUTP and OUTM and to further extract an actual common mode signal of the pair of output signals.

For example, the control unit 022 can be configured to: the ideal common mode signal is received and a feedback control signal is output to the level shift module 01 based on the actual common mode signal and the ideal common mode signal.

For example, with continued reference to fig. 7, the control unit 022 in the feedback control module 02 may be coupled with the extraction unit 021, the ideal common mode terminal vcm_de, and the level conversion module 01 (including the first level conversion unit 011 and the second level conversion unit 012), respectively, to receive an actual common mode signal extracted by the extraction unit 021, to receive an ideal common mode signal provided by the ideal common mode terminal vcm_de, and to output a feedback control signal to the level conversion module 01 based on the received actual common mode signal and the ideal common mode signal. In other words, it can also be understood that the extraction unit 021 outputs the extracted actual common mode signal to the control unit 022.

Fig. 8 shows a schematic block diagram of yet another level shifter circuit provided by an embodiment of the present disclosure. As shown in fig. 8, each of the first level converting unit 011 and the second level converting unit 012 may include: a switch section K1 and an impedance section Z1.

For example, the control terminal of the switching section K1 can receive a feedback control signal, one of the input terminal and the output terminal of the switching section K1 can receive a power supply signal, and the other can receive an input signal and generate an output signal via the impedance section Z1.

For example, referring to fig. 8, the control terminal of the switching part K1 may be coupled to the feedback control module 02, and in particular, may be coupled to the control unit 022 in the feedback control module 02 to receive the feedback control signal output by the control unit 022. One of the input end and the output end of the switch part K1 can be coupled with the power supply end V_h to receive a power supply signal provided by the power supply end V_h; the other end may be coupled to the input terminal INP/INM and the output terminal OUTP/OUTM via the impedance portion Z1, respectively, to receive the input signal from the input terminal via the impedance portion Z1 and generate the output signal. Therefore, the method can play roles in delaying and filtering signals and the like, and improves signal transmission capacity and anti-interference capacity.

The power supply signal may be used for the level conversion circuit to work, and belongs to the power supply voltage described in the above embodiment. The feedback control signal may be used to control the current generated by the switching section K1 so that the common mode signal of the pair of output signals generated by the level shift module 01 is equal to the ideal common mode signal. Furthermore, referring to fig. 8, it can be further seen that the level shifter circuit may be grounded and coupled to the ground GND.

Fig. 9 shows a schematic circuit diagram of a level shifter circuit according to an embodiment of the present disclosure, based on fig. 8. As shown in fig. 9, the switching section K1 may include a P-type transistor t1_p. The impedance Z1 may include an RC parallel circuit. The extraction unit 021 may include a pair of common-mode resistors Rcm having equal resistance values. The control unit 022 may include an Amplifier (AMP).

The gate of the P-type transistor t1_p may be used as the control terminal of the switch portion K1, and one of the first and second poles of the P-type transistor t1_p may be used as the input terminal, and the other pole may be used as the output terminal.

Alternatively, the P-type transistor may be a Metal-Oxide-Semiconductor (MOS) field effect transistor, which may also be referred to as a PMOS transistor.

For example, a first terminal of a pair of common mode resistors Rcm (reference numeral 021 in the drawing) can receive a pair of output signals, and a second terminal of the pair of common mode resistors Rcm can output an actual common mode signal to a first input terminal (in-phase terminal in the drawing) of the amplifier AMP. Specifically, the pair of common-mode resistors Rcm may be configured to receive a pair of output signals and extract a common-mode signal thereof as an actual common-mode signal. Here, a pair of common-mode resistances Rcm can extract a desired common-mode signal by the superposition theorem.

For example, the second input (e.g., the inverting terminal, vcm_de terminal in the figure) of the amplifier AMP is capable of receiving the desired common mode signal. The output terminal of the amplifier AMP can output a feedback control signal. Specifically, the amplifier AMP may be configured to receive an ideal common mode signal and an actual common mode signal and output a feedback control signal to the level conversion module 01 based on the ideal common mode signal and the actual common mode signal.

Alternatively, referring to fig. 9, the first input of the amplifier AMP may be a positive phase input (indicated by "+" in the drawing) and the second input may be a negative phase input (indicated by "-" in the drawing).

For example, an RC parallel circuit, i.e., an RC impedance circuit, includes a resistor R0 and a capacitor Cac0. As described above, taking the first level conversion unit 011 as an example, it can be seen in conjunction with the description of the above embodiment and fig. 9:

the gate of the P-type transistor t1_p may be coupled to the output terminal of the amplifier AMP, the first pole of the P-type transistor t1_p may be coupled to the power supply terminal v_h, and the second pole of the P-type transistor t1_p may be coupled to the input terminal INP and the output terminal OUTP, respectively, which are in one-to-one correspondence, via the RC parallel circuit. Specifically, in the RC parallel circuit, the second pole of the P-type transistor t1_p may be coupled to the first end of the resistor R0 and the first end of the capacitor Cac0 in the RC parallel circuit, the second end of the resistor R0 and the second end of the capacitor Cac0 may be coupled to each other and to the input terminal INP, and the first end of the capacitor Cac0 may be further coupled to the output terminal OUTP. The coupling manner of each part in the second level shifter 012 is the same and will not be described again. The first level shift unit 011 and the second level shift unit 012 can be regarded as two parts symmetrically disposed.

In addition, a first terminal of the pair of common mode resistors Rcm may be coupled to the pair of output terminals OUTP and OUTM in a one-to-one correspondence to receive a pair of output signals from the pair of output terminals OUTP and OUTM. The second terminals of the pair of common-mode resistors Rcm may be coupled to each other and to the non-inverting input terminal of the amplifier AMP. The negative input of the amplifier AMP may be coupled to the ideal common mode terminal vcm_de. And, as described in the above embodiments, the output terminal of the amplifier AMP may be coupled to the gate of the P-type transistor t1_p.

That is, referring to fig. 9, a first end of one common mode resistor Rcm of the pair of common mode resistors Rcm may be coupled to one output terminal OUTP of the pair of output terminals OUTP and OUTM, and a first end of the other common mode resistor Rcm may be coupled to the other output terminal OUTM of the pair of output terminals OUTP and OUTM; and, the second terminal of the one common mode resistor Rcm and the second terminal of the other common mode resistor Rcm may be coupled and simultaneously coupled with the non-inverting input terminal of the amplifier AMP.

Optionally, as described in the above embodiments, the level shifter circuit provided in the embodiments of the present disclosure can be configured to: a pair of output signals is output to a coupled pair of output terminals OUTP and OUTM. On this basis, as can be seen with continued reference to fig. 9, the level shift circuit may further include: a load capacitor Cload connected in series between each of the pair of output terminals OUTP and OUTM and the ground GND, and a comparison capacitor Ccomp connected in series between the control terminal of the switching section K1 (i.e., the gate of the P-type transistor t1_p) and the ground GND.

The load capacitor Cload can play a role in stabilizing the voltage wave, so that the signal output by the output end can be ensured to be more stable, and the precision is higher. The comparison capacitor Ccomp can be a large capacitor with a larger capacitance value relative to the load capacitor Cload, and can play a role in stabilizing the level at the gate of the P-type transistor t1_p, and a smaller pole (also called as a dominant pole) is generated at the gate of the P-type transistor t1_p, so that the purpose of dominant pole compensation is achieved, and the level at the gate is ensured not to fluctuate.

The following briefly describes the operation of the level shift circuit in conjunction with fig. 9:

first, a pair of common-mode resistors Rcm may extract a common-mode signal (i.e., a common-mode voltage) of an output signal output to a pair of output terminals OUTP and OUTM, and transmit the extracted common-mode signal to a non-inverting input terminal of an amplifier AMP.The amplifier AMP may then transmit a feedback control signal to the gates of the P-type transistors t1_p in the two level shift units 011 and 012 according to an ideal common mode signal (i.e., an ideal common mode voltage) provided by an ideal common mode terminal vcm_de to which the negative phase input terminal is coupled, and the common mode voltage received by the positive phase input terminal to control the currents of the P-type transistors t1_p in the two level shift units 011 and 012. When the current Id of the P-type transistor t1_p satisfies: idr (Idr) ₀₀ When=vcm_de0-vcm_in, the common-mode voltage in the output signal can reach the ideal common-mode voltage, i.e. the set value. Therein, in combination with the diagram 9,r ₀₀ Refers to the resistance value of the resistor R0 in the impedance portion Z1; vcm_de0 refers to the ideal common mode voltage; vcm_in refers to the common mode voltage of the input signal. It follows that in the configuration shown in fig. 9, a common mode feedback loop from input to output is implemented.

To ensure that the common mode feedback loop has sufficient phase margin, it also uses a dominant pole compensation approach.

Specific:

first, the loop gain T(s) of the common mode feedback loop may satisfy:

wherein A is ₀ ＝g _m1 r _o1 g _m2 r ₀₀ r _cm0 ；

Wherein,

the A is as described above ₀ May refer to loop amplification; s refers to the laplace operator; omega _p1 And omega _p2 The pole frequencies of different poles are referred to; g _m1 Refers to the transconductance of the amplifier AMP; r is (r) _o1 Refers to the transimpedance of the P-type transistor t1_p; g _m2 Refers to the transconductance of the P-type transistor t1_p; r is (r) ₀₀ Refers to the resistance value of the resistor R0 in the impedance portion Z1; r is (r) _cm0 The resistance value of the common mode resistor Rcm; c (C) _comp0 Refers to comparing the capacitance value of the capacitor Ccomp; c (C) _ac00 Refers toThe capacitance value of the capacitor Cac 0; c (C) _load0 Refers to the capacitance of the load capacitor Cload.

Secondly, the transfer function H(s) from the input to the output may satisfy:

wherein,ω _p1 ＝1/(C _ac00 +C _load0 )·(r ₀₀ ||r _cm0 )；

omega above _z1 Refers to the zero frequency. As can be seen from the transfer function H(s) described above, the low-frequency gain when s is made to approach 0 can be equivalent to the divided voltage of the two resistances of the resistor R0 and the common-mode resistor Rcm in the impedance portion Z1; to make s approach +++. Time-to-high frequency gain can be equivalent to the impedance Z1 the partial voltage of the two capacitors, namely, the middle capacitor Cac0 and the load capacitor Cload. Thereby introducing a pair of zeros and poles in the level shifting circuit. When the low frequency gain is greater than the high frequency gain, the pole frequency may be less than the zero frequency. In contrast, when the high frequency gain is greater than the low frequency gain, the zero frequency may be greater than the pole frequency.

As can be seen from the description of the above embodiments, the common mode feedback loop according to the embodiments of the present disclosure adopts a dominant pole compensation manner, so that a common mode signal can be flexibly set, and under the condition that the phase margin of the common mode feedback loop is sufficient, the output voltage does not exceed the supply voltage, thereby avoiding the problem of overvoltage. In addition, at the time of low frequency signal input, the capacitor can be regarded as an open circuit, thereby forming a direct current path constructed by the resistors R0 and Rcm, so that the level shifter circuit can not have the problem of lower limit cut-off frequency, and low-speed data, such as 5Mbps data, can be reliably transmitted. In a word, for the high-speed interface circuit of the bidirectional transmission, the level conversion circuit provided by the embodiment of the disclosure can adopt a small capacitor to realize the level change of the low-frequency signal, and meanwhile, various overvoltage problems possibly existing in the traditional circuit can be eliminated, so that the safety and the reliability are improved. In addition, aiming at conversion functions under different common mode requirements, the integrated circuit can be integrated in a chip, and is realized by configuring ideal common mode signals, so that the realization conditions of level conversion are simplified, plate making requirements can be reduced to a certain extent, and the configuration process is simplified.

In summary, the embodiments of the present disclosure provide a level shifter circuit. The level shift circuit includes a level shift module and a feedback control module. The level conversion module can perform level conversion on a pair of input signals to generate a pair of output signals. The feedback control module is capable of extracting an actual common mode signal in the pair of output signals and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal to control the common mode signal in the output signals generated by the level conversion module to be equal to the ideal common mode signal. Therefore, the reliable level conversion can be realized aiming at the levels of signals with different frequencies without setting a capacitor with a larger area, and the circuit design is facilitated.

Fig. 10 shows a schematic block diagram of a driving circuit provided by an embodiment of the present disclosure. As shown in fig. 10, the driving circuit includes:

such as the level shifter circuit shown in any of the above-described fig. 6-9.

Such as the output driver circuit shown in fig. 1 described above. The output drive circuit can be configured to: a pair of driving signals is output based on a pair of output signals generated by the level shift circuit.

For example, referring to fig. 10, a level shifter circuit may be coupled to the output driver circuit to transmit a generated pair of output signals to the output driver circuit. Also, in connection with fig. 1 and 6, the level shift circuit may be coupled to the input terminal DIN of the output driving circuit through a pair of output terminals OUTP and OUTM, that is, to the gates of the amplifying transistors M1 and M2 in the output driving circuit.

Fig. 11 shows a schematic block diagram of an electronic device provided by an embodiment of the disclosure. As shown in fig. 11, the electronic device includes:

a load;

such as the drive circuit shown in fig. 10. The drive circuit can be configured to: a pair of driving signals is output to the load to drive the load to operate.

For example, referring to fig. 11, a driving circuit may be coupled with a load to output a driving signal to the load. And, in connection with fig. 1 and 6, the driving circuit may be coupled to the load through the output terminals TXp and TXn of the output driving circuit.

Alternatively, the electronic device described in the embodiments of the present disclosure may be a microelectronic device (i.e., a microelectronic device).

It is to be understood that the terminology used in the implementations of the disclosure is for the purpose of describing embodiments of the disclosure and is not intended to be limiting of the disclosure. Unless defined otherwise, technical or scientific terms used in embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

For example, in the presently disclosed embodiments, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims (10)

1. A level shifter circuit, the level shifter circuit comprising:

a level shift module configured to: receiving a pair of input signals, and performing level conversion on the pair of input signals to generate a pair of output signals; wherein the pair of input signals and the pair of output signals each include a common mode signal;

a feedback control module configured to: and receiving an ideal common mode signal and the pair of output signals, extracting an actual common mode signal in the pair of output signals, and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal so as to control the common mode signal in the pair of output signals generated by the level conversion module to be equal to the ideal common mode signal.

2. The level shifter circuit of claim 1, wherein the pair of input signals are differential input signals; the pair of output signals is a pair of differential output signals.

3. The level shift circuit of claim 1, wherein the feedback control module comprises:

an extraction unit configured to: receiving the pair of output signals and extracting an actual common mode signal in the pair of output signals;

a control unit configured to: and receiving the ideal common mode signal and outputting a feedback control signal to the level conversion module based on the actual common mode signal and the ideal common mode signal.

4. A level shift circuit according to claim 3, wherein the extraction unit comprises: a pair of common mode resistors with equal resistance values; the control unit includes: an amplifier;

wherein a first end of the pair of common mode resistors receives the pair of output signals; the second ends of the pair of common mode resistors output the actual common mode signals to the first input end of the amplifier; a second input of the amplifier receives the ideal common mode signal; the output end of the amplifier outputs the feedback control signal.

5. The level shift circuit of any one of claims 1 to 4, wherein the level shift module comprises:

a first level shift unit configured to: receiving one input signal of the pair of input signals, and performing level conversion on the one input signal to generate an output signal;

a second level shift unit configured to: the other input signal of the pair of input signals is received and level-converted to produce the other output signal.

6. The level shift circuit of claim 4, wherein the first level shift unit and the second level shift unit each include a switching section and an impedance section;

the control end of the switch part receives the feedback control signal, one end of the input end and the output end of the switch part receives a power supply signal, and the other end receives an input signal through the impedance part and generates an output signal;

the feedback control signal is used for controlling the current generated by the switching part so that the common mode signal of the pair of output signals generated by the level conversion module is equal to the ideal common mode signal.

7. The level shift circuit according to claim 6, wherein the switching section includes a P-type transistor; the impedance part comprises an RC parallel circuit;

the grid electrode of the P-type transistor is used as the control end of the switch part, one of the first pole and the second pole of the P-type transistor is used as the input end, and the other pole is used as the output end.

8. The level shifter circuit of claim 6, wherein the level shifter circuit is configured to: outputting the pair of output signals to a coupled pair of output terminals;

the level shift circuit further includes: a load capacitor connected in series between each of the pair of output terminals and ground; and a comparison capacitor connected in series between the control end and the ground end of the switch part.

9. A driving circuit, characterized in that the driving circuit comprises:

a level shifter circuit as claimed in any one of claims 1 to 8;

an output driving circuit configured to: a pair of driving signals is output based on a pair of output signals generated by the level shift circuit.

10. An electronic device, the electronic device comprising:

a load;

the drive circuit of claim 9, configured to: a pair of drive signals is output to the load to drive the load to operate.