CN117558704A - Semiconductor power module - Google Patents

Semiconductor power module Download PDF

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Publication number
CN117558704A
CN117558704A CN202311637547.8A CN202311637547A CN117558704A CN 117558704 A CN117558704 A CN 117558704A CN 202311637547 A CN202311637547 A CN 202311637547A CN 117558704 A CN117558704 A CN 117558704A
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CN
China
Prior art keywords
ceramic substrate
emitter
metallized ceramic
power module
silicon carbide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311637547.8A
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Chinese (zh)
Inventor
倪佳悦
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Star Semiconductor Co ltd
Original Assignee
Star Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Star Semiconductor Co ltd filed Critical Star Semiconductor Co ltd
Priority to CN202311637547.8A priority Critical patent/CN117558704A/en
Publication of CN117558704A publication Critical patent/CN117558704A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32052—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48739—Silver (Ag) as principal constituent

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The invention provides a semiconductor power module, which relates to the technical field of power semiconductors and comprises the following components: the silicon carbide chip is welded on the emitter of the metallized ceramic substrate, a silver paste layer is formed on the emitter of the silicon carbide chip by sintering, the silver paste layer is connected with the emitter of the metallized ceramic substrate through a bonding wire, and the gate of the silicon carbide chip is connected with the emitter of the metallized ceramic substrate through a bonding wire; and the bottom of the power terminal is welded on the emitter of the metallized ceramic substrate. The method has the beneficial effects that the problems of insufficient on-resistance, higher power loss, short service life and the like of the direct combination of the silver wire and the chip can be solved by sintering the silver paste layer on the silicon carbide chip and then bonding the silver alloy bonding wire; the silver alloy bonding wire and the silver paste layer belong to the same material, the combination is more reliable, and correspondingly, the combination force between the silver alloy bonding wire and the silicon carbide chip is firmer.

Description

Semiconductor power module
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a semiconductor power module.
Background
With the vigorous development of the microelectronic industry, the requirements on the packaging technology are higher and higher, the packaging technology is developed towards high density, miniaturization and adaptation to high heating, and the requirements on bonding wires are also higher and higher. The bonding alloy wire is widely used in middle-high end products in the packaging industry due to good corrosion resistance and high reliability, but gold wires are expensive in cost, various alternatives for gold wires are sequentially introduced in the market to reduce the packaging cost, the excellent resistivity and the relatively low price of the silver wire are paid attention to in the industry, the silver wire is directly combined with a chip, the mechanical property is not very good, the on-resistance of a semiconductor power module is not low enough, the power loss is high, and the service life is not long.
Disclosure of Invention
In view of the problems existing in the prior art, the present invention provides a semiconductor power module, comprising:
the silicon carbide chip is welded on the emitter of the metallized ceramic substrate, a silver paste layer is formed on the emitter of the silicon carbide chip through sintering, and the gate of the silicon carbide chip is connected with the emitter of the metallized ceramic substrate through a bonding wire;
the silver paste layer is bonded with the emitter electrode of the metallized ceramic substrate by adopting a silver alloy bonding wire, and the silver alloy bonding wire is bonded with the silver paste layer and the emitter electrode of the metallized ceramic substrate by an ultrasonic bonding process;
and a power terminal, wherein the bottom of the power terminal is welded on an emitter of the metallized ceramic substrate.
Preferably, the metallized ceramic substrate comprises a first metal layer, an intermediate ceramic layer and a second metal layer from top to bottom.
Preferably, the first metal layer and the second metal layer are both copper layers.
Preferably, a bonding wire between the gate electrode of the silicon carbide chip and the emitter electrode of the metallized ceramic substrate is a soft aluminum wire.
Preferably, the power terminal further comprises a housing, wherein the metallized ceramic substrate is encapsulated in the housing, a plurality of openings are respectively formed in the housing corresponding to the power terminals, and the top of each power terminal extends out of the corresponding opening.
Preferably, the soft aluminum wire is prepared by adopting a continuous casting and rolling process.
Preferably, the silver alloy bonding wire is prepared by adopting continuous smelting, drawing casting, wire drawing and annealing processes.
Preferably, the first metal layer, the intermediate ceramic layer and the second metal layer are prepared into the metallized ceramic substrate by adopting a direct copper coating process or an active metal brazing process.
The technical scheme has the following advantages or beneficial effects:
1) The problems of insufficient on-resistance, higher power loss, short service life and the like caused by the fact that a silver wire is directly combined with a chip in the prior art can be solved by sintering a silver paste layer on a silicon carbide chip and then bonding a silver alloy bonding wire;
2) The silver alloy bonding wire and the silver paste layer belong to the same material, the combination is more reliable, and correspondingly, the combination force between the silver alloy bonding wire and the silicon carbide chip is firmer.
Drawings
FIG. 1 is a schematic diagram of a semiconductor power module according to a preferred embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a semiconductor power module according to a preferred embodiment of the invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and specific examples. The present invention is not limited to the embodiment, and other embodiments may fall within the scope of the present invention as long as they conform to the gist of the present invention.
In a preferred embodiment of the present invention, based on the above-mentioned problems occurring in the prior art, there is now provided a semiconductor power module, as shown in fig. 1 and 2, comprising:
the silicon carbide chip 1 is welded on the emitter of the metallized ceramic substrate 2, the emitter of the silicon carbide chip 1 is sintered to form the silver paste layer 3, the silver paste layer is connected with the emitter of the metallized ceramic substrate 2 through a bonding wire, and the gate of the silicon carbide chip 1 is connected with the emitter of the metallized ceramic substrate 2 through a bonding wire;
and a power terminal 4, wherein the bottom of the power terminal 4 is welded on the emitter of the metallized ceramic substrate 2.
The bonding wire between the silver paste layer 3 and the emitter electrode of the metallized ceramic substrate 2 adopts a silver alloy bonding wire, and the silver alloy bonding wire is bonded with the silver paste layer and the emitter electrode of the metallized ceramic substrate through an ultrasonic bonding process.
Specifically, in the prior art, the bonding alloy wire is widely used in middle-high end products in the packaging industry because of good corrosion resistance and high reliability, the effect of bonding by adopting a gold wire is best, but the gold wire is expensive in manufacturing cost, various alternatives of gold wires are sequentially introduced in the market to reduce the packaging cost, wherein the excellent resistivity and relatively low price of the silver wire are paid attention to in the industry, the silver wire is often used as a preferred alternative of the gold wire, but the silver wire is directly combined with a chip, the mechanical property is not very good, and the on-resistance of a semiconductor power module is not low enough, the power loss is higher and the service life is not long, so in the embodiment, a silver paste layer is formed on an emitter of the silicon carbide chip through a silver paste sintering process, and then the silver paste layer is connected with an emitter of a metallized ceramic substrate through the bonding wire, so that compared with the traditional way of combining the silver wire with the chip in the semiconductor power module, the silicon carbide chip and the metallized ceramic substrate can have better mechanical property;
and adopt silver alloy bonding wire as the bonding material that bonds with silver thick liquid layer to carry out ultrasonic bonding, can make semiconductor power module obtain lower on resistance, reduce power loss, prolong semiconductor power module's life, and silver alloy bonding wire and silver thick liquid layer belong to same material, combine more reliably each other.
In the preferred embodiment of the present invention, the metallized ceramic substrate 2 comprises a first metal layer, an intermediate ceramic layer, and a second metal layer from top to bottom.
In a preferred embodiment of the present invention, the first metal layer and the second metal layer are both copper layers.
In a preferred embodiment of the present invention, the first metal layer, the intermediate ceramic layer and the second metal layer are prepared into a metallized ceramic substrate using a direct copper-clad process or an active metal brazing process.
Specifically, in this embodiment, the cermet substrate is made by adopting a three-layer design (a layer of ceramic is sandwiched between two layers of copper layers), and adopting a ceramic metallization process, where the ceramic metallization process may adopt a direct bonding copper process (DBC, or direct copper-clad process), or an Active Metal Brazing (AMB) process, or other suitable processes;
the DBC process and the AMB process are two methods for manufacturing the ceramic copper substrate, and each method has the advantages and the disadvantages and mainly has the following points:
the DBC technology is to combine copper directly with AI by hot melting at high temperature 2 O 3 The composite substrate combined with the AIN ceramic surface has higher heat conductivity, insulativity and reliability, and is suitable for small and medium power electronic products such as refrigerators, air conditioners and the like.
The AMB technology is a method for combining ceramic and metal by utilizing active metal elements (such as Ti/Ag/Zr/Cu) in the solder, and the ceramic forms a reaction layer which can be wetted by liquid solder, has higher adhesive strength and thermal cycle performance, and is suitable for high-power electronic products such as electric automobiles, electric locomotives and the like.
The DBC process has the advantages of mature process, low cost and simple operation.
The AMB process has the advantage that the interface strength between the copper layer and the ceramic layer is high, and can withstand higher temperature and voltage.
In a preferred embodiment of the invention, the bond wire between the gate of the silicon carbide chip 1 and the emitter of the metallized ceramic substrate 2 is a soft aluminum wire.
In a preferred embodiment of the invention, the soft aluminum wire is prepared by a continuous casting and rolling process.
In a preferred embodiment of the present invention, as shown in fig. 2, the metallized ceramic substrate 2 further includes a housing 5, wherein the metallized ceramic substrate 2 is encapsulated in the housing 5, and a plurality of openings are respectively formed on the housing 5 corresponding to each power terminal 4, and the top of each power terminal extends out of the corresponding opening.
Specifically, in this embodiment, the casing disposed outside the metallized ceramic substrate is used to protect the metallized ceramic substrate, and the power terminals and SiC chip disposed on the metallized ceramic substrate, so as to reduce the influence of the external environment on the semiconductor power module, and the metallized ceramic substrate 2 and the casing 5 are sealed by the sealant.
In the preferred embodiment of the invention, the silver alloy bonding wire is prepared by adopting continuous smelting, drawing casting, wire drawing and annealing processes.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations herein, which should be included in the scope of the present invention.

Claims (8)

1. A semiconductor power module, comprising:
the silicon carbide chip is welded on the emitter of the metallized ceramic substrate, a silver paste layer is formed on the emitter of the silicon carbide chip through sintering, and the gate of the silicon carbide chip is connected with the emitter of the metallized ceramic substrate through a bonding wire;
the silver paste layer is bonded with the emitter electrode of the metallized ceramic substrate by adopting a silver alloy bonding wire, and the silver alloy bonding wire is bonded with the silver paste layer and the emitter electrode of the metallized ceramic substrate by an ultrasonic bonding process;
and a power terminal, wherein the bottom of the power terminal is welded on an emitter of the metallized ceramic substrate.
2. The semiconductor power module of claim 1 wherein the metallized ceramic substrate comprises a first metal layer, an intermediate ceramic layer, and a second metal layer from top to bottom.
3. The semiconductor power module of claim 2, wherein the first metal layer and the second metal layer each employ a copper layer.
4. The semiconductor power module of claim 1, wherein a bond wire between a gate of the silicon carbide chip and an emitter of the metallized ceramic substrate is a soft aluminum wire.
5. The semiconductor power module of claim 1, further comprising a housing, wherein the metallized ceramic substrate is encapsulated in the housing, wherein a plurality of openings are respectively formed in the housing corresponding to each of the power terminals, and wherein a top portion of each of the power terminals extends from the corresponding opening.
6. The semiconductor power module of claim 4 wherein the soft aluminum wire is prepared using a continuous casting process.
7. The semiconductor power module of claim 1, wherein the silver alloy bond wire is prepared by continuous melting, casting, wire drawing, and annealing processes.
8. The semiconductor power module of claim 2, wherein the first metal layer, the intermediate ceramic layer, and the second metal layer are prepared as the metallized ceramic substrate using a direct copper-on-metal process or an active metal brazing process.
CN202311637547.8A 2023-12-01 2023-12-01 Semiconductor power module Pending CN117558704A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311637547.8A CN117558704A (en) 2023-12-01 2023-12-01 Semiconductor power module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311637547.8A CN117558704A (en) 2023-12-01 2023-12-01 Semiconductor power module

Publications (1)

Publication Number Publication Date
CN117558704A true CN117558704A (en) 2024-02-13

Family

ID=89820445

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311637547.8A Pending CN117558704A (en) 2023-12-01 2023-12-01 Semiconductor power module

Country Status (1)

Country Link
CN (1) CN117558704A (en)

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