CN117558325A

CN117558325A - Application circuit, solid state disk, electronic equipment and data reading and writing method

Info

Publication number: CN117558325A
Application number: CN202311850442.0A
Authority: CN
Inventors: 刘福东
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-02-13
Anticipated expiration: 2043-12-29
Also published as: CN117558325B

Abstract

The invention provides an application circuit, a solid state disk, electronic equipment and a data read-write method, and relates to the technical field of storage. According to the application circuit, the solid state disk, the electronic equipment and the data read-write method, the application circuit can realize connection of the solid state disk controller and different NAND particles, when the solid state disk controller is connected with different NAND particles based on the application circuit, the data storage capacity and the data transmission rate which can be realized are the same, the solid state disk controller can be compatible with different NAND particles under the same design standard, the supply risk of the NAND particles after the solid state disk product is reduced, the cost control of the solid state disk product is facilitated, and the comprehensive competitiveness of the solid state disk product can be improved.

Description

Application circuit, solid state disk, electronic equipment and data reading and writing method

Technical Field

The present invention relates to the field of storage technologies, and in particular, to an application circuit, a solid state disk, an electronic device, and a data reading and writing method.

Background

Among core materials required for manufacturing the solid state disk (Solid State Drive, SSD), the cost of the SSD controller, the NAND (Not AND) particles AND the DRAM (Dynamic Random Access Memory ) particles is about 90% to 95%, wherein the cost of the NAND particles is highest.

For solid state disk manufacturers, the solid state disk controller can be compatible with NAND particles manufactured by different NAND particle manufacturers under the same design standard, so that the supply risk of NAND particles after the production of the solid state disk product can be reduced, and the cost control of the solid state disk product is facilitated by providing the NAND particles by a plurality of NAND particle manufacturers.

However, the pin definition of NAND die manufactured by different NAND die manufacturers in the related art is not the same as the internal bus topology of the chip, resulting in that it is difficult for the solid state disk controller to be compatible with NAND die manufactured by different NAND die manufacturers under the same design standard.

Disclosure of Invention

The invention provides an application circuit, a solid state disk, electronic equipment and a data read-write method, which are used for solving the defect that a solid state disk controller is difficult to be compatible with NAND particles manufactured by different NAND particle manufacturers under the same design standard in the prior art, and realizing that the solid state disk controller is difficult to be compatible with the NAND particles manufactured by different NAND particle manufacturers under the same design standard.

The invention provides an application circuit which is used for connecting a solid state disk controller with a plurality of NAND particles;

the application circuit comprises: the circuit groups are in one-to-one correspondence with the target channels in the solid state disk controller; the target channel comprises a first number of chip select signal port groups, each chip select signal port group comprises four chip select signal ports, and different chip select signal ports in different chip select signal port groups are used for outputting different chip select signals, wherein the first number is positive integer multiple of 2;

the circuit group comprises a first number of sub-circuit groups, and the sub-circuit groups are respectively in one-to-one correspondence with the chip selection signal port groups and the NAND particles;

the sub-line group comprises four lines, each line in the sub-line group is used for connecting one chip selection signal port in the chip selection signal port group corresponding to the sub-line group, and two chip selection signal pins with corresponding relation with the chip selection signal port in NAND particles corresponding to the sub-line group;

different chip select signal pins in the NAND particle are used for receiving different chip select signals; the correspondence between the chip select signal ports in the chip select signal port group and the chip select signal pins in the NAND particles is determined based on the correspondence between different chip select signal pins and different chip select signals in different NAND particles.

According to the application circuit provided by the invention, the correspondence between the chip selection signal ports in the chip selection signal port group and the chip selection signal pins in the NAND particle comprises: a first chip select signal port in any one of the chip select signal port groups corresponds to a first chip select signal pin and a second chip select signal pin in the NAND die,

a third chip select signal port of the set of any chip select signal ports corresponds to a third chip select signal pin and a fourth chip select signal pin of the NAND die,

the second chip select signal port in the set of any chip select signal ports corresponds to a fifth chip select signal pin and a sixth chip select signal pin in the NAND die,

a fourth chip select signal port in the arbitrary chip select signal port group corresponds to a seventh chip select signal pin and an eighth chip select signal pin in the NAND particle;

wherein, the firstiThe first chip select signal port groupjThe chip select signal port is used for outputting the firstkThe chip select signal is used to select the chip,，/>，/>，Irepresenting the first number.

According to the application circuit provided by the invention, under the condition that the NAND particles are of the first packaging type, two rows of edge bonding pads positioned on the left side and the right side of the printed circuit board are suspended, and pins of the NAND particles are correspondingly welded with the rest bonding pads on the printed circuit board one by one.

According to the application circuit provided by the invention, under the condition that the NAND particles are of the second packaging type, pins of the NAND particles are welded with bonding pads on the printed circuit board in a one-to-one correspondence manner.

According to the present invention, there is provided an application circuit, the sub-line group includes: a first line, a second line, a third line, and a fourth line,

one end of the first circuit is connected with a first chip selection signal port in the chip selection signal port group corresponding to the sub-circuit group, the other end of the first circuit is respectively connected with a first chip selection signal pin and a second chip selection signal pin in the NAND particle corresponding to the sub-circuit group,

one end of the second circuit is connected with a second chip selection signal port in the chip selection signal port group corresponding to the sub-circuit group, the other end of the second circuit is respectively connected with a fifth chip selection signal pin and a sixth chip selection signal pin in the NAND particle corresponding to the sub-circuit group,

one end of the third circuit is connected with a third chip selection signal port in the chip selection signal port group corresponding to the sub-circuit group, the other end of the third circuit is respectively connected with a third chip selection signal pin and a fourth chip selection signal pin in the NAND particle corresponding to the sub-circuit group,

One end of the fourth circuit is connected with a fourth chip selection signal port in the chip selection signal port group corresponding to the sub-circuit group, and the other end of the third circuit is respectively connected with a seventh chip selection signal pin and an eighth chip selection signal pin in the NAND particle corresponding to the sub-circuit group.

According to the application circuit provided by the invention, when the NAND particle is a first NAND particle, the first chip select signal pin and the fifth chip select signal pin in the NAND particle correspond to the first chip select signal, the third chip select signal pin and the seventh chip select signal pin in the NAND particle correspond to the second chip select signal, the second chip select signal pin and the sixth chip select signal pin in the NAND particle correspond to the third chip select signal, and the fourth chip select signal pin and the eighth chip select signal pin in the NAND particle correspond to the fourth chip select signal.

According to the application circuit provided by the invention, when the NAND particle is the second NAND particle, the first chip selection signal pin in the NAND particle corresponds to the first chip selection signal, the fifth chip selection signal pin in the NAND particle corresponds to the second chip selection signal, and the chip selection signal pins except the first chip selection signal pin and the fifth chip selection signal pin in the NAND particle are suspended.

According to the application circuit provided by the invention, when the NAND particle is a third NAND particle, a first chip select signal pin in the NAND particle corresponds to the first chip select signal, a fifth chip select signal pin in the NAND particle corresponds to the third chip select signal, the third chip select signal pin in the NAND particle corresponds to the third chip select signal, a fourth chip select signal pin in the NAND particle corresponds to the fourth chip select signal, and the fifth chip select signal pin, the sixth chip select signal pin, the seventh chip select signal pin and the eighth chip select signal pin in the NAND particle are suspended.

According to the application circuit provided by the invention, the sub-line group further comprises: a NAND bus;

the NAND buses in the sub-line groups are used for connecting each storage unit in the NAND particles corresponding to the sub-line groups with the data bus ports in the target channels corresponding to the sub-line groups.

According to the application circuit provided by the invention, under the condition that the NAND grain is the first NAND grain, each piece of selection signal pin in the NAND grain corresponds to one storage unit respectively.

According to the application circuit provided by the invention, when the NAND grain is the second NAND grain, the first chip selection signal pin and the fifth chip selection signal pin in the NAND grain respectively correspond to four storage units.

According to the application circuit provided by the invention, when the NAND particle is a third NAND particle, the first chip selection signal pin, the third chip selection signal pin, the fifth chip selection signal pin and the seventh chip selection signal pin in the NAND particle respectively correspond to two storage units.

According to the application circuit provided by the invention, the first packaging type is a ball grid array packaging BGA132 packaging type; the second package type is a BGA152 package type.

According to the application circuit provided by the invention, the target channels comprise all channels in the solid state disk controller.

According to the application circuit provided by the invention, the first NAND grain, the second NAND grain and the third NAND grain are produced by different NAND grain manufacturers.

The invention also provides a solid state disk, comprising: a solid state disk controller, a plurality of NAND particles, and an application circuit as described in any of the above;

the application circuit is used for connecting the solid state disk controller with each NAND particle.

The invention also provides a data reading and writing method which is applied to the solid state disk, and the method comprises the following steps:

acquiring an address of a target storage unit needing to perform target operations, wherein the target operations comprise data reading operations and/or data storage operations;

Generating a target chip selection signal corresponding to the target storage unit based on the address of the target storage unit and NAND particles where the target storage unit is located, wherein the target chip selection signal is of a low level;

transmitting the target chip selection signal to the target storage unit through the application circuit so that the target storage unit is switched to a gating state under the condition that the target chip selection signal is received;

and carrying out the target operation on the target storage unit.

According to the data read-write method provided by the invention, before generating the target chip selection signal corresponding to the target storage unit based on the address of the target storage unit and the NAND grain where the target storage unit is located in the case that the NAND grain in the solid state disk is the first NAND grain, the method further comprises:

and reassigning the address of each storage unit in each NAND particle based on the corresponding relation between the chip select signal port in the chip select signal port group in the solid state disk controller of the solid state disk and the chip select signal pin in the NAND particle.

According to the data read-write method provided by the invention, the reassigning the address of each memory cell in each NAND particle based on the correspondence between the chip select signal ports in the chip select signal port group and the chip select signal pins in the NAND particle in the solid state disk controller of the solid state disk comprises the following steps:

Under the condition that each NAND particle is powered on, carrying out power-on reset operation on each NAND particle;

acquiring an address of each storage unit in each NAND particle;

and under the condition that each NAND particle does not read and write data, reassigning the address of each storage unit in each NAND particle based on the corresponding relation between the chip select signal port in the chip select signal port group and the chip select signal pin in the NAND particle in the solid state disk controller of the solid state disk.

The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a data read-write method as described in any of the above.

The invention also provides a computer program product comprising a computer program which, when executed by a processor, implements a data read-write method as described in any one of the above.

The application circuit provided by the invention can realize the connection between the solid state disk controller and different NAND particles, and the solid state disk controller has the same data storage capacity and the same data transmission rate when the solid state disk controller is connected with different NAND particles based on the application circuit provided by the invention, so that the solid state disk controller can be compatible with different NAND particles under the same design standard, the supply risk of the NAND particles after the solid state disk product quantity can be reduced, the cost control of the solid state disk product is facilitated, and the comprehensive competitiveness of the solid state disk product can be improved.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an application circuit according to the present invention;

FIG. 2 is a schematic diagram of a pin arrangement of a first NAND die;

FIG. 3 is a second schematic diagram of the application circuit according to the present invention;

FIG. 4 is a schematic diagram of a pin arrangement of a second NAND die;

FIG. 5 is a third schematic circuit diagram of the application circuit according to the present invention;

FIG. 6 is a schematic diagram of a pin arrangement of a third NAND die;

FIG. 7 is a fourth schematic diagram of the application circuit provided by the present invention;

FIG. 8 is a pin distribution on a printed circuit board of NAND particles of a first package type;

FIG. 9 is a pin layout on a printed circuit board of a NAND die of a second package type;

FIG. 10 is a schematic flow chart of a data read/write method according to the present invention;

FIG. 11 is a schematic flow chart of reassigning addresses of each memory cell in each NAND granule in the data read-write method provided by the invention.

Reference numerals:

101: a solid state disk controller; 102: NAND particles; 106: a chip select signal port group; 103: a chip select signal port; 105: a line; 104: a chip select signal pin; and K5: a first slice select signal pin; and H3: a second chip select signal pin; k6: a third chip select signal pin; h4: a fourth chip select signal pin; h9: a fifth chip select signal pin; k11: a sixth chip select signal pin; h8: a seventh chip select signal pin; k10: an eighth chip select signal pin; 107: a first line; 108: a second line; 109: a third line; 110: a fourth line; lun: a storage unit; 111: a NAND bus; 112: a data bus port; 113: a first chip select signal port group in the target channel; 114: the second chip in the target channel selects the signal port group.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

In the description of the present application, the terms "first," "second," and the like are used for distinguishing between similar objects and not for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. In addition, in the description of the present application, "and/or" means at least one of the connected objects, and the character "/", generally means a relationship in which the front and rear associated objects are one kind of "or".

It should be noted that, compared with a Hard Disk Drive (HDD), a solid state Disk has great advantages in terms of speed, power consumption, capacity, noise, reliability, and the like. Therefore, although the mechanical hard disk has a certain advantage in price, with the continuous iteration of the process and lamination of the NAND particles, the capacity density of the single NAND particle is continuously increased, so that the single-disk capacity of the solid state hard disk is also increased, the price of the solid state hard disk corresponding to the unit capacity is also reduced, and the solid state hard disk is widely applied to servers and storage equipment.

In the core materials required for manufacturing the solid state disk, the cost ratio of the SSD controller, the NAND particles and the DRAM particles reaches about 90 to 95 percent, wherein the cost ratio of the NAND particles is the highest, and the cost ratio of the NAND particles is about 70 percent.

For SSD manufacturers, SSD controllers can be compatible with NAND particles manufactured by different NAND particle manufacturers under the same design standard, so that not only can the supply risk of NAND particles after SSD product quantity be reduced, but also the provision of NAND particles by a plurality of NAND particle manufacturers is more beneficial to the cost control of SSD products. The design criteria may include, among other things, data storage capacity and data transfer rate.

However, the pin definition of NAND die manufactured by different NAND die manufacturers in the related art is not the same as the chip internal bus topology, making it difficult for the SSD controller to be compatible with NAND die manufactured by different NAND die manufacturers.

For example, in the case that the SSD controller includes 16 channels, each channel may support 8 Chip Enable (CE) signals, if the first NAND granule manufactured by the first NAND granule manufacturer includes 4 Chip Enable signal pins, any channel in the SSD controller may be adapted to two first NAND granules, if the capacity of a single first NAND granule is 1TB, the storage capacity corresponding to each channel of the SSD controller is 2TB, and the total storage capacity corresponding to the SSD controller is 32TB;

however, if the second NAND grain manufactured by the second NAND grain manufacturer includes 8 chip select signal pins, any channel in the SSD controller can only be adapted to one second NAND grain, if the capacity of a single second NAND grain is also 1TB, the storage capacity corresponding to each channel of the SSD controller is 1TB, the total storage capacity corresponding to the SSD controller is 16TB, and the total storage capacity corresponding to the SSD controller is reduced by half compared with the case of adapting to two first NAND grains;

If the third NAND grain manufactured by the third NAND grain manufacturer includes 4 chip select signal pins, any channel in the SSD controller may be adapted to four third NAND grains, if the capacity of a single second NAND grain is also 1TB, the storage capacity corresponding to each channel of the SSD controller is 4TB, the total storage capacity corresponding to the SSD controller is 64TB, and the total storage capacity corresponding to the SSD controller is doubled compared with the case of adapting to two first NAND grains.

In addition, the package types of NAND particles manufactured by different NAND particle manufacturers are also not the same, and common package types include ball grid array package (Ball Grid Array Package, BGA) 132 type (size 18mm×12 mm), BGA152 package type (size 18mm×14 mm), and the like. Different package types can also make it difficult for SSD controllers to be compatible with NAND die manufactured by different NAND die manufacturers.

Fig. 1 is a schematic circuit diagram of an application circuit according to the present invention. The application circuit provided by the present invention is described below with reference to fig. 1. The application circuit provided by the invention is used for connecting the solid state disk controller 101 and a plurality of NAND particles 102;

as shown in fig. 1, the application circuit includes: the line groups are in one-to-one correspondence with target channels in the solid state disk controller 101; the target channel comprises a first number of chip select signal port groups 106, each chip select signal port group 106 comprises four chip select signal ports 103, and different chip select signal ports 103 in different chip select signal port groups 106 are used for outputting different chip select signals, wherein the first number is positive integer multiple of 2;

The line groups comprise a first number of sub-line groups, and the sub-line groups are respectively in one-to-one correspondence with the chip selection signal port groups 106 and the NAND particles 102;

the sub-line group comprises four lines 105, wherein each line 105 in the sub-line group is used for connecting one chip select signal port 103 in a chip select signal port group 106 corresponding to the sub-line group, and two chip select signal pins 104 with a corresponding relation with the chip select signal port 103 in the NAND particle 102 corresponding to the sub-line group;

different chip select signal pins 104 in the NAND particle 102 are used to receive different chip select signals; the correspondence between the chip select signal ports 103 in the chip select signal port group 106 and the chip select signal pins 104 in the NAND die 102 is determined based on the correspondence between the different chip select signal pins 104 and the different chip select signals in the different NAND die 102.

Specifically, based on the application circuit provided by the present invention, the target channel in the solid state disk controller 101 may be connected to the first number of NAND particles 102, where each NAND particle 102 may include a plurality of partially different or all different NAND particles.

That is, in the case where each NAND pellet 102 includes part or all of the first NAND pellet, the second NAND pellet, the third NAND pellet, or the like, the target channel in the solid state disk controller 101 may be connected with the first number of NAND pellets 102 based on the application circuit provided by the present invention. In addition, when the target channels in the solid state disk controller 101 are connected with different NAND particles 102 based on the application circuit provided by the invention, the data storage capacity and the data transmission rate which can be realized are the same, and the solid state disk controller 101 can be compatible with different NAND particles 102 under the same design standard.

It should be noted that, in the embodiment of the present invention, different NAND dies 102 may be manufactured by different NAND die 102 manufacturers, or may be different NAND dies 102 manufactured by the same NAND die 102 manufacturer.

As an alternative embodiment, the first NAND die 102, the second NAND die 102, and the third NAND die 102 are produced by different NAND die 102 manufacturers.

It should be noted that, in the embodiment of the present invention, the target channel in the solid state disk controller 101 may be determined according to actual requirements. In the embodiment of the present invention, the target channel in the solid state disk controller 101 is not specifically limited.

It is understood that the number of target channels in the solid state disk controller 101 may be one or more.

As an alternative embodiment, the target channels include all channels in the solid state disk controller 101.

It should be noted that, in the embodiment of the present invention, the number of chip select signals that can be supported by the target channel is the second number, and each chip select signal is output through one chip select signal port 103, so the number of chip select signal ports 103 in the target channel in the embodiment of the present invention is also the second number. Wherein the second number may be a positive integer multiple of 8, e.g., the second number may be 8, 16, 32, etc.

The chip select signal ports 103 in the solid state disk controller 101 in the embodiment of the present invention may be divided into a first number of chip select signal port groups 106, where each chip select signal port group 106 includes four chip select signal ports 103, and the four chip select signal ports 103 in each chip select signal port group 106 are respectively used for outputting different chip select signals.

Note that, in the target channel, the firstiThe first chip select signal port groupjThe chip select signal port is used for outputting the firstkThe chip select signal is used to select the chip,，/>，/>，Irepresenting a first number.

Accordingly, in the embodiment of the present invention, the number of NAND particles 102 connected to the target channel by the application circuit provided by the present invention is referred to as a first number, and a specific value of the first number is determined based on a second number, for example, in the case that the second number is 8, the first number is 2; in the case of a second number of 16, the first number is 4.

As an alternative embodiment, the first number has a value of 2.

Alternatively, the number of chip select signals that can be supported by any channel in the solid state disk controller 101 is generally 8, so the application circuit provided by the present invention will be described below by taking the number of chip select signals that can be supported by the target channel as 8, and the number of NAND particles 102 connected to the target channel by the application circuit provided by the present invention is 2 as an example.

It should be noted that, because of limited space display, fig. 1 shows an application circuit in a case where the target channel in the solid state disk controller 101 is 1 and the target channel is the first channel (CH 0) in the solid state disk controller 101. In the case that the number of target channels in the solid state disk controller 101 is multiple, the circuit structure and the connection relationship of the line 105 group corresponding to each target channel in the application circuit provided by the present invention may be shown in fig. 1.

As shown in fig. 1, in the case where the target channel is the first channel (CH 0) in the solid state disk controller 101, the target channel includes two chip select signal port groups 106, that is, a first chip select signal port group 113 and a second chip select signal port group 114. The first chip select signal port group 113 and the second chip select signal port group 114 each include 4 chip select signal ports.

The first chip select signal port of the first chip select signal port group 113 is used for outputting the first chip select signal ch0_ce0_n in the target channel, the second chip select signal port of the first chip select signal port group 113 is used for outputting the second chip select signal ch0_ce1_n in the target channel, the third chip select signal port of the first chip select signal port group 113 is used for outputting the third chip select signal ch0_ce2_n in the target channel, and the fourth chip select signal port of the first chip select signal port group 113 is used for outputting the fourth chip select signal ch0_ce3_n in the target channel.

The first chip select signal port of the second chip select signal port group 114 is used to output the fifth chip select signal ch0_ce4_n in the target channel, the second chip select signal port of the second chip select signal port group 113 is used to output the sixth chip select signal ch0_ce5_n in the target channel, the third chip select signal port of the second chip select signal port group 113 is used to output the seventh chip select signal ch0_ce6_n in the target channel, and the fourth chip select signal port of the second chip select signal port group 113 is used to output the eighth chip select signal ch0_ce7_n in the target channel.

It should be noted that, in the embodiment of the present invention, the different NAND particles 102 include eight chip select signal pins 104, which are a first chip select signal pin K5, a second chip select signal pin H3, a third chip select signal pin K6, a fourth chip select signal pin H4, a fifth chip select signal pin H9, a sixth chip select signal pin K11, a seventh chip select signal pin H8, and an eighth chip select signal pin K10, respectively.

It is understood that the chip select signals corresponding to different chip select signal pins 104 in different NAND particles 102 are not the same.

In the embodiment of the invention, the corresponding relation between the chip select signal ports 103 in the chip select signal port group 106 and the chip select signal pins 104 in the NAND particles 102 can be determined by combining the design standard of the solid state disk based on the chip select signals corresponding to the different chip select signal pins 104 in the different NAND particles 102 through numerical calculation, mathematical statistics, deep learning technology and other modes.

As an alternative embodiment, as shown in fig. 1, the correspondence between the chip select signal ports 103 in the chip select signal port group 106 and the chip select signal pins 104 in the NAND particle 102 includes: the first chip select signal port 103 in any one of the chip select signal port groups 106 corresponds to the first chip select signal pin K5 and the second chip select signal pin H3 in the NAND pellet 102, the third chip select signal port 103 in any one of the chip select signal port groups 106 corresponds to the third chip select signal pin K6 and the fourth chip select signal pin H4 in the NAND pellet 102, the second chip select signal port 103 in any one of the chip select signal port groups 106 corresponds to the fifth chip select signal pin H9 and the sixth chip select signal pin K11 in the NAND pellet 102, and the fourth chip select signal port 103 in any one of the chip select signal port groups 106 corresponds to the seventh chip select signal pin H8 and the eighth chip select signal pin K10 in the NAND pellet 102;

wherein, the firstiThe first chip select signal port groupjIndividual piecesThe signal selecting port is used for outputting the firstkThe chip select signal is used to select the chip,，/>，/>，Irepresenting a first number.

Specifically, the correspondence between the chip select signal ports 103 in the chip select signal port group 106 and the chip select signal pins 104 in the NAND particles 102 in the embodiment of the present invention is shown in table 1.

TABLE 1 correspondence table between chip select signal ports in chip select signal port group and chip select signal pins in NAND granule

As an alternative embodiment, as shown in fig. 1, one end of each line 105 in the sub-line group is connected to one chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-line group, and the other end of each line 105 is connected to two chip select signal pins 104 having a corresponding relationship with the one chip select signal port 103 in the NAND particle 102 corresponding to the sub-line group.

Specifically, in the embodiment of the present invention, any one chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-line group may implement parallel connection of two chip select signal pins 104 corresponding to one chip select signal port 103 in the NAND particle 102 corresponding to the sub-line group through any one line 105 in the sub-line group.

As an alternative embodiment, as shown in fig. 1, the sub-line group includes: a first line 107, a second line 108, a third line 109, and a fourth line 110, one end of the first line 107 is connected to the first chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-line group, the other end of the first line 107 is connected to the first chip select signal pin K5 and the second chip select signal pin H3 in the NAND granule 102 corresponding to the sub-line group, respectively, one end of the second line 108 is connected to the second chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-line group, the other end of the second line 108 is connected to the fifth chip select signal pin H9 and the sixth chip select signal pin K11 in the NAND granule 102 corresponding to the sub-line group, respectively, one end of the third line 109 is connected to the third chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-line group, the other end of the third line 109 is connected to the third chip select signal pin K6 and the fourth chip select signal pin H4 in the NAND granule 102 corresponding to the sub-line group, respectively, and one end of the fourth line 110 is connected to the third chip select signal pin K9 and the eighth chip select signal pin 103 in the NAND granule 102 corresponding to the third chip select signal port 106 corresponding to the sub-line group, respectively.

Specifically, in order to make the solid state disk controller 101 compatible with different NAND particles 102, the first line 107 in the sub-line group in the application circuit provided by the present invention connects and combines the first chip select signal pin K5 and the second chip select signal pin H3 for receiving the first chip select signal CE (4i-4); the second line 108 in the sub-line group connects and combines the fifth chip select signal pin H9 and the sixth chip select signal pin K11 for receiving the second chip select signal CE (4i-3); the third line 109 in the sub-line group connects and combines the third chip select signal pin K6 and the fourth chip select signal pin H4 for receiving the third chip select signal CE (4i-2); the fourth line 110 in the sub-line group connects and combines the seventh chip select signal pin H8 and the eighth chip select signal pin K10 for receiving the fourth chip select signal CE (4i-1）。

The first line 107, the second line 108, the third line 109 and the fourth line 110 in the sub-line group in the application circuit provided by the invention are respectively connected with the first chip select signal port 103, the second chip select signal port 103, the third chip select signal port 103 and the fourth chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-line group in the target channel of the solid state disk controller 101, so that different NAND particles 102 can be electrically connected with the solid state disk controller 101.

It should be noted that, related command words such as the command and the address of different NAND grains 102 are different, and related operations need to be performed according to specifications of different NAND grains 102, which are not described in detail in the embodiment of the present invention.

As an alternative embodiment, in the case where the NAND pellet 102 is the first NAND pellet, the first chip select signal pin K5 and the fifth chip select signal pin H9 in the NAND pellet 102 correspond to the first chip select signal, the third chip select signal pin K6 and the seventh chip select signal pin H8 in the NAND pellet 102 correspond to the second chip select signal, the second chip select signal pin H3 and the sixth chip select signal pin K11 in the NAND pellet 102 correspond to the third chip select signal, and the fourth chip select signal pin H4 and the eighth chip select signal pin K10 in the NAND pellet 102 correspond to the fourth chip select signal.

FIG. 2 is a schematic diagram of a pin layout of a first NAND die. In the case where the NAND die 102 is the first NAND die, the pin arrangement of the NAND die 102 is as shown in fig. 2.

The correspondence between different chip select signal pins 104 and different chip select signals in the first NAND particle 102 in the embodiment of the invention is shown in table 2.

TABLE 2 correspondence table between different chip select signal pins 104 and different chip select signals in first NAND particle 102

The combination of the chip select signals ce0_1_n and ce0_0_n in table 2 corresponds to (4)i-3) chip select signal CE (4i-4); the combination of the chip select signal CE1_1_n and the chip select signal CE1_0_n corresponds to (4)i-2) chip select signal CE (4i-3); the combination of the chip select signal CE2_0_n and the chip select signal CE2_1_n corresponds to (4)i-1) chip select signal CE (4i-2); the combination of the chip select signal CE3_0_n and the chip select signal CE3_1_n corresponds to the 4 thiChip select signal CE (4i-1）。

FIG. 3 is a second schematic diagram of the application circuit according to the present invention.

It should be noted that, because of limited space, fig. 3 is a schematic circuit diagram of a connection between a chip select signal port group 106 in a target channel and a first NAND particle 102 through a sub-line group in an application circuit provided by the present invention in the case that the target channel in the solid state disk controller 101 is 1. The schematic circuit diagram of the connection between the other chip select signal port groups 106 in the target channels and the other first NAND particles 102 through the application circuits provided by the present invention, and the schematic circuit diagram of the connection between the other target channels in the solid state disk controller 101 and the other first NAND particles 102 through the application circuits provided by the present invention can also be shown in fig. 3.

As shown in fig. 3, when the solid state disk controller 101 is connected to the first NAND grain 102 through the application circuit provided by the present invention, all of the 8 chip select signal pins 104 in the NAND grain 102 are used.

For the first NAND particle 102, the first line 107 in the sub-line group in the application circuit provided by the invention connects the first chip select signal pin K5 and the second chip select signal pin H3, and the chip select signal ce0_1_n and the chip select signal ce0_0_n can be combined into the first chip select signal CE0; the second line 108 in the sub-line group connects the fifth chip select signal pin H9 and the sixth chip select signal pin K11, and may combine the chip select signal ce1_1—n and the chip select signal ce1_0_n into the second chip select signal CE2; the third line 109 in the sub-line group connects the third chip select signal pin K6 and the fourth chip select signal pin H4, and may combine the chip select signal ce2_0_n and the chip select signal ce2_1—n into the third chip select signal CE2; the fourth line 110 in the sub-line group connects the seventh chip select signal pin H8 and the eighth chip select signal pin K10, and may combine the chip select signal CE3_0_n and the chip select signal CE3_1—n into the fourth chip select signal CE3.

The first line 107, the second line 108, the third line 109 and the fourth line 110 in the sub-line group in the application circuit provided by the invention are respectively connected with the first chip select signal port 103, the second chip select signal port 103, the third chip select signal port 103 and the fourth chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-line group in the target channel of the solid state disk controller 101, so that the first NAND particle 102 can be electrically connected with the solid state disk controller 101.

As an alternative embodiment, as shown in fig. 3, in the case where the NAND die 102 is the first NAND die, each of the select signal pins 104 in the NAND die 102 corresponds to one of the memory cells lun, respectively.

It should be noted that, when the solid state disk controller 101 is connected to the first NAND grain 102 through the application circuit provided by the present invention, the address of the storage unit lun corresponding to each of the select signal pins 104 in the NAND grain 102 is changed, and the address of the storage unit lun corresponding to each of the select signal pins 104 in the NAND grain 102 needs to be reassigned after the NAND grain 102 is powered on.

As an alternative embodiment, in the case where the NAND die 102 is the second NAND die, the first chip select signal pin K5 in the NAND die 102 corresponds to the first chip select signal, the fifth chip select signal pin H9 in the NAND die 102 corresponds to the second chip select signal, and the chip select signal pins 104 in the NAND die 102 other than the first chip select signal pin K5 and the fifth chip select signal pin H9 are floating.

FIG. 4 is a schematic diagram of a pin layout of a second NAND die. In the case where the NAND die 102 is the second NAND die, the pin arrangement of the NAND die 102 is as shown in fig. 4.

The correspondence between different chip select signal pins 104 and different chip select signals in the second NAND particle 102 in the embodiment of the invention is shown in table 3.

TABLE 3 correspondence table between different chip select signal pins 104 and different chip select signals in the second NAND particle 102

Note that N.U in table 3 indicates suspension.

The chip select signal CE0_0 in Table 3 corresponds to the (4)i-3) chip select signal CE (4i-4) the chip select signal CE0_1 corresponds to the th #4i-2) chip select signal CE (4i-3）。

FIG. 5 is a third circuit diagram of the application circuit according to the present invention.

It should be noted that, because the space is limited, fig. 5 shows a schematic circuit diagram when the application circuit is used to connect the target channel in the solid state disk controller 101 with the second NAND particle 102 in the case that the target channel in the solid state disk controller 101 is 1 and the target channel is the first channel (CH 0) in the solid state disk controller 101. In the case that the number of target channels in the solid state disk controller 101 is plural, the schematic circuit diagram of the application circuit for connecting other target channels in the solid state disk controller 101 with the second NAND particle 102 can also be shown in fig. 5.

It should be noted that, since only the first chip select signal pin K5 and the fifth chip select signal pin H9 in the second NAND particle 102 are used for outputting the chip select signal, the other chip select signal pins 104 are suspended, and when the solid state disk controller 101 is connected to the second NAND particle 102 through the present invention to provide an application circuit, no signal is transmitted from the chip select signal pins except the first chip select signal pin K5 and the fifth chip select signal pin H9 even if they are connected to the line 105 in the application circuit.

Therefore, as shown in fig. 5, when the solid state disk controller 101 is connected to the second NAND pellet 102 through the application circuit provided by the present invention, one end of the first wire 107 in the sub-wire group is connected to the first chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-wire group, the other end of the first wire 107 is connected to the first chip select signal pin K5 in the NAND pellet 102 corresponding to the sub-wire group, one end of the second wire 108 in the sub-wire group is connected to the second chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-wire group, the other end of the second wire 108 is connected to the fifth chip select signal pin H9 in the NAND pellet 102 corresponding to the sub-wire group, and the other chip select signal ports 103 in the chip select signal port group 106 corresponding to the sub-wire group and the other chip select signal pins 104 in the NAND pellet 102 corresponding to the sub-wire group can be suspended.

For the second NAND particle 102, the first line 107 in the sub-line group in the application circuit is connected to the first chip select signal pin K5, and the chip select signal ce0_0 can be determined to be the first chip select signal CE0 to be output; the second line 108 of the sub-line group is connected to the fifth chip select signal pin H9, and the chip select signal ce0_1 may be determined to be the second chip select signal CE1 output.

The first circuit 107 and the second circuit 108 in the sub-circuit group in the application circuit provided by the invention are respectively connected with the first chip select signal port 103 and the second chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-circuit group in the target channel of the solid state disk controller 101, so that the first NAND particle 102 can be electrically connected with the solid state disk controller 101.

As an alternative embodiment, as shown in fig. 5, in the case where the NAND die 102 is the second NAND die, the first chip select signal pin K5 and the fifth chip select signal pin H9 in the NAND die 102 correspond to four memory cells lun, respectively.

It should be noted that, when the solid state disk controller 101 and the second NAND particle 102 are connected through the application circuit provided by the present invention, if the first chip select signal port ch0_ce0_n in the solid state disk controller 101 outputs a low level chip select signal, four storage units lun (lun 0-lun 3) corresponding to the first chip select signal pin K5 in the NAND particle 102 corresponding to the chip select signal port group 106 are gated, and in the operation process, lun 0-lun 3 may be distinguished by the lun address bit, and then the solid state disk controller 101 may implement the read-write erasing operation of the corresponding page and/or block under the specific storage unit lun in the storage unit lun corresponding to the chip select signal pin 104 according to the transmission data of the command+address+data signal. The operation types of the solid state disk controller 101 on the other storage units lun are not described in detail herein.

It should be noted that, considering the data transmission rate after the solid state disk controller 101 is connected to the NAND particles 102, in the embodiment of the present invention, the target channel in the solid state disk controller 101 may be connected to two second NAND particles 102 only through four chip select signal ports 103, and the same data storage capacity, data transmission rate and expansion capability as those of the first NAND particle 102 and the third NAND particle 102 may be realized.

As an alternative embodiment, in the case where the NAND pellet 102 is the third NAND pellet, the first chip select signal pin K5 in the NAND pellet 102 corresponds to the first chip select signal, the fifth chip select signal pin H9 in the NAND pellet 102 corresponds to the third chip select signal, the third chip select signal pin K6 in the NAND pellet 102 corresponds to the third chip select signal, the fourth chip select signal pin H4 in the NAND pellet 102 corresponds to the fourth chip select signal, and the fifth chip select signal pin H9, the sixth chip select signal pin K11, the seventh chip select signal pin H8, and the eighth chip select signal pin K10 in the NAND pellet 102 are suspended.

FIG. 6 is a schematic diagram of a pin layout of a third NAND die. In the case where the NAND die 102 is the third NAND die, the pin arrangement of the NAND die 102 is as shown in fig. 6.

The correspondence between different chip select signal pins 104 and different chip select signals in the third NAND particle 102 in the embodiment of the invention is shown in table 4.

TABLE 4 correspondence table between different chip select signal pins 104 and different chip select signals in third NAND particle 102

Note that N.U in table 4 indicates suspension.

Fig. 7 is a circuit schematic diagram of an application circuit provided by the present invention.

It should be noted that, because the space is limited, fig. 7 is a schematic circuit diagram when the application circuit is used to connect the target channel in the solid state disk controller 101 with the third NAND particle 102 in the case that the target channel in the solid state disk controller 101 is 1 and the target channel is the first channel (CH 0) in the solid state disk controller 101. In the case where the number of target channels in the solid state disk controller 101 is plural, the schematic circuit diagram of the application circuit for connecting other target channels in the solid state disk controller 101 with the third NAND particle 102 may also be shown in fig. 7.

It should be noted that, since only the seventh chip select signal pin H8, the fifth chip select signal pin H9, the first chip select signal pin K5, and the third chip select signal pin K6 in the third NAND particle 102 are used for outputting the chip select signal, the other chip select signal pins 104 are suspended, and when the solid state disk controller 101 is connected to the third NAND particle 102 through the application circuit provided by the present invention, the second chip select signal pin H3, the fourth chip select signal pin H4, the eighth chip select signal pin K10, and the sixth chip select signal pin K11 have no signal transmission even if they are connected to the line 105 in the application circuit.

Therefore, as shown in fig. 7, when the solid state disk controller 101 is connected to the third NAND pellet 102 through the application circuit provided by the present invention, one end of the first wire 107 in the sub-wire group is connected to the first chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-wire group, the other end of the first wire 107 is connected to the first chip select signal pin K5 in the NAND pellet 102 corresponding to the sub-wire group, one end of the second wire 108 in the sub-wire group is connected to the second chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-wire group, the other end of the second wire 108 is connected to the fifth chip select signal pin H9 in the NAND pellet 102 corresponding to the sub-wire group, one end of the third wire 109 in the sub-wire group is connected to the third chip select signal port 103 in the chip select signal port group 106 corresponding to the sub-wire group, the other end of the fourth wire 110 in the sub-wire group is connected to the third chip select signal pin K6 in the NAND pellet 102 corresponding to the sub-wire group, the other end of the fourth wire 110 in the sub-wire group is connected to the chip select signal port 103 in the chip select signal port 103 corresponding to the sub-wire group, and the other end of the chip select signal port 102 in the sub-wire group is connected to the other chip select signal port 102 in the sub-wire group is suspended state signal port 110 in the sub-group.

As an alternative embodiment, in the case where the NAND die 102 is the third NAND die, the first chip select signal pin K5, the third chip select signal pin K6, the fifth chip select signal pin H9, and the seventh chip select signal pin H8 in the NAND die 102 correspond to two memory cells lun, respectively.

It should be noted that, when the solid state disk controller 101 is connected to the third NAND granule 102 through the present invention by providing an application circuit, if the first chip select signal port ch0_ce0_n in any one of the chip select signal port groups 106 in the solid state disk controller 101 outputs a low level chip select signal, two storage units lun (lun 0/lun 1) corresponding to the first chip select signal pin K5 in the NAND granule 102 corresponding to the chip select signal port group 106 are gated, and in the operation process, lun0/lun1 may be distinguished by a lun address bit, and then the solid state disk controller 101 may implement the read-write operations of corresponding pages and/or blocks under specific storage units lun in the storage units lun corresponding to the chip select signal pin 104 according to the sending data of the command+address+data signal. The operation types of the solid state disk controller 101 on the other storage units lun are not described in detail herein.

As an alternative embodiment, the sub-line group further comprises: a NAND bus 111;

The NAND bus 111 in the sub-line group is used to connect each memory cell lun in the NAND die 102 corresponding to the sub-line group with the data bus port 112 in the target channel corresponding to the sub-line group.

Specifically, as shown in fig. 1, the sub-line group in the application circuit provided by the present invention further includes a NAND bus 111.

The NAND bus 111 in the sub-line group may be used to connect each of the memory cells lun in the NAND die 102 corresponding to the sub-line group, and the data bus port 112 in the target channel corresponding to the sub-line 105 group, so as to implement operations related to reading, writing, erasing, and the like of the NAND die 102 corresponding to the sub-line group.

It will be appreciated that the set of lines 105 includes a first number of sub-line sets, and thus the set of lines 105 includes a first number of NAND buses 111, each NAND bus 111 corresponding to one NAND die 102, each NAND bus 111 being connected to a data bus port 112 in the corresponding target channel of the set of lines 105.

Note that DQ [7:0] 0 and DQ [7:0] 1 in FIG. 5 are data bus representations that are commonly used to describe the data buses of DRAMs (dynamic random access memories) or other types of memory chips in computer systems. In this representation, DQ represents the Data Bus (Data Bus) and [7:0] represents the number of bits on the Data Bus, i.e., 8 bits. The last underline "_0" indicates that the data bus is that of one of the chips, there may be multiple chips, each with a similar data bus, and the numbers following the underline are used to identify the different data buses.

DQ [7:0] _0 thus represents the 8-bit data bus of the first chip. If there are multiple chips, there may also be representations of DQ [7:0] _1, DQ [7:0] _2, and the like, describing their respective data buses.

As an alternative embodiment, one end of the NAND bus 111 in the sub-line group is connected to the data bus port 112 in the corresponding target channel in the sub-line group, and the other end of the NAND bus 111 is connected to each memory cell lun in the corresponding NAND pellet 102 of the sub-line group, respectively.

Specifically, by connecting one end of the NAND bus 111 in the sub-line group with the data bus port 112 in the sub-line group corresponding target channel, and connecting the other end of the NAND bus 111 with each of the memory cells lun in the sub-line group corresponding NAND die 102, the data bus port 112 in the sub-line group corresponding target channel can be connected in parallel with each of the memory cells lun in the sub-line group corresponding NAND die 102.

As an alternative embodiment, in the case where the NAND pellet 102 is of the first package type, two columns of edge pads located on the left and right sides of the printed circuit board are suspended, and pins of the NAND pellet 102 are soldered in one-to-one correspondence with the remaining pads on the printed circuit board.

As an alternative embodiment, where the NAND die 102 is of the second package type, the pins of the NAND die 102 are soldered in a one-to-one correspondence with pads on the printed circuit board.

As an alternative embodiment, the first package type is a ball grid array package BGA132 package type; the second package type is a BGA152 package type.

Fig. 8 is a pin layout on a printed circuit board of a NAND die of the first package type. Fig. 9 is a pin layout on a printed circuit board of a NAND die of a second package type.

As shown in fig. 8 and 9, the BGA132 package type (first package type) typically has 132 pins. The BGA152 package type (second package type) typically has 152 pins.

Therefore, since the NAND particles 102 of the BGA152 package type (second package type) have two rows of pins suspended more than the BGA132 package type (first package type), in the embodiment of the present invention, for both the NAND particles 102 of the BGA152 package type (second package type) and the NAND particles 102 of the BGA132 package type (first package type), the NAND particles 102 are packaged according to the maximum package size corresponding to the BGA152 package type.

In the case where the package type of the NAND particle 102 is the BGA152 package type (second package type), pins of the NAND particle 102 are soldered in one-to-one correspondence with pads on a printed circuit board.

Therefore, in the embodiment of the present invention, in the case where the package type of the NAND particle 102 is the BGA152 package type (the second package type), two columns of edge pads located on the left and right sides of the printed circuit board are suspended, and pins of the NAND particle 102 are soldered in one-to-one correspondence with the remaining pads on the printed circuit board.

The application circuit in the embodiment of the invention can realize the connection of the solid state disk controller and different NAND particles, and when the solid state disk controller is connected with different NAND particles based on the application circuit provided by the invention, the realized data storage capacity and data transmission rate are the same, so that the solid state disk controller can be compatible with different NAND particles under the same design standard, the supply risk of the NAND particles after the solid state disk product is reduced, the cost control of the solid state disk product is facilitated, and the comprehensive competitiveness of the solid state disk product can be improved.

In the embodiment of the invention, aiming at NAND particles with different packaging types, circuit compatible design is carried out in the hardware design stage, so that a solid state disk controller can be compatible with different NAND particles under the same design standard.

The embodiment of the invention can realize the use of a set of hardware circuit and printed circuit board design, different FW firmware versions are used for the solid state disk controllers corresponding to different NAND particles to distinguish, the same solid state disk controller is compatible with different NAND particles, the compatibility and adaptability of the same generation of solid state disk products to different NAND particles are perfected, the supply risk of the NAND particles after the solid state disk product quantity is reduced, the cost control of the solid state disk products is reduced, and the comprehensive competitiveness of the solid state disk products is improved.

Based on the content of the foregoing embodiments, a solid state disk includes: a solid state disk controller, a plurality of NAND particles, and an application circuit as described in any of the above;

It should be noted that, the specific manner in which the solid state disk controller in the embodiment of the present invention is connected to the plurality of NAND particles through the application circuit provided by the present invention may refer to the content of each embodiment, which is not described in detail in the embodiments of the present invention.

The solid state disk in the embodiment of the invention comprises the solid state disk controller, the application circuit and a plurality of NAND particles, wherein the solid state disk controller can be connected with the plurality of NAND particles through the application circuit, and the same solid state disk controller is compatible with different NAND particles, so that the compatibility and the suitability of the same-generation solid state disk product to different NAND particles are perfected, the supply risk of the NAND particles after the solid state disk is measured and the cost control of the solid state disk are reduced, and the comprehensive competitiveness of the solid state disk is improved.

Based on the content of the above embodiments, an electronic device includes: the solid state disk as described above.

Alternatively, the electronic device in the embodiment of the present invention may include, but is not limited to, a computer, a server, and a mobile storage device.

The electronic equipment in the embodiment of the invention comprises the solid state disk, and the same solid state disk controller in the solid state disk is compatible with different NAND particles, so that compatibility and suitability of the same generation of solid state disk products for different NAND particles are perfected, supply risk of NAND particles after the electronic equipment is measured and cost control of the electronic equipment are reduced, and comprehensive competitiveness of the electronic equipment is improved.

Fig. 10 is a schematic flow chart of a data read-write method provided by the invention. The data read-write method of the present invention is described below with reference to fig. 10. The data read-write method provided by the invention is applied to the solid state disk provided by the invention. As shown in fig. 10, the method includes: step 1001, obtain the address of the destination storage unit lun that needs to perform the destination operation, where the destination operation includes a data reading operation and/or a data storing operation.

It should be noted that, the execution body of the embodiment of the present invention is a solid state disk controller.

Specifically, in the embodiment of the present invention, the address of the target storage unit lun that needs to perform data reading and/or data storage may be obtained based on the input of the user or based on the quality sent by other electronic facilities.

Step 1002, generating a target chip select signal corresponding to the target memory cell lun based on the address of the target memory cell lun and the NAND grain where the target memory cell lun is located, where the target chip select signal is at a low level.

Specifically, after the address of the destination memory cell lun is obtained, a destination chip select signal corresponding to the destination memory cell lun may be generated according to the address of the destination memory cell lun and the NAND grain in which the destination memory cell lun is located. Wherein the target chip select signal is low.

The NAND grains are different from each other, and the command word such as the command+address of the chip select signal for the strobe memory cell lun is different from each other.

Step 1003, sending, by the application circuit, the target chip select signal to the target memory unit lun, so that the target memory unit lun switches to the strobe state when receiving the target chip select signal.

Specifically, after generating the target chip select signal corresponding to the target memory cell lun, the application circuit provided by the invention may send the low-level target chip select signal to the target memory cell lun, so that the target memory cell lun switches from the ungated state to the gated state after receiving the low-level target chip select signal.

Step 1004, performing a destination operation on the destination storage unit lun.

Specifically, after the target memory cell lun is switched from the ungated state to the gated state, data may be read from and/or stored to the target memory cell lun.

According to the embodiment of the invention, after the address of the target storage unit lun needing to perform target operation is obtained, the target chip select signal of the low level corresponding to the target storage unit lun is generated based on the address of the target storage unit lun and the NAND particles of the target storage unit lun, and then the target chip select signal is sent to the target storage unit lun through the application circuit, so that the target storage unit lun is switched to a gating state under the condition that the target chip select signal is received, the target storage unit lun is subjected to target operation, and the solid state disk controller can realize normal data read-write of the solid state disk through the storage unit lun required by gating of the application circuit provided by the invention when the solid state disk controller in the solid state disk is compatible with different NAND particles, and the comprehensive competitiveness of the solid state disk can be improved.

As an optional embodiment, in the case that the NAND grain in the solid state disk is the first, before generating the target chip select signal corresponding to the target storage unit lun based on the address of the target storage unit lun and the NAND grain where the target storage unit lun is located, the method further includes: and reassigning the address of each storage unit lun in each NAND particle based on the corresponding relation between the chip select signal ports in the chip select signal port group in the solid state disk controller of the solid state disk and the chip select signal pins in the NAND particles.

It should be noted that, when the solid state disk controller is connected to the first NAND particle through the application circuit provided by the present invention, the address of the storage unit lun corresponding to each of the select signal pins in the NAND particle is changed, and the address of the storage unit lun corresponding to each of the select signal pins in the NAND particle needs to be reassigned after the NAND particle is powered on.

As an optional embodiment, reassigning the address of each storage unit lun in each NAND granule based on the correspondence between the chip select signal ports in the chip select signal port group and the chip select signal pins in the NAND granule in the solid state disk controller of the solid state disk includes: under the condition that each NAND particle is powered on, carrying out power-on reset operation on each NAND particle;

acquiring an address of each storage unit lun in each NAND particle;

under the condition that each NAND particle does not read and write data, reassigning the address of each storage unit lun in each NAND particle based on the corresponding relation between the chip select signal ports in the chip select signal port group and the chip select signal pins in the NAND particle in the solid state disk controller of the solid state disk.

Fig. 11 is a schematic flow chart of reassigning an address of each memory cell in each NAND grain in the data read-write method provided by the present invention. As shown in fig. 11, in the case that the NAND particles in the solid state disk are the first, the solid state disk is powered on, after the power supply time sequence and power supply of 2.5V/1.2V/12V of the NAND particles in the solid state disk are completed, the first chip select signal port ch0_ce0_n in the solid state disk controller of the solid state disk outputs a low-level chip select signal, and the solid state disk controller sends a 0xFF command to the NAND particles to perform the power-on reset operation.

The solid state disk controller sends a 0xFB command, and can acquire the address of each storage unit lun in each NAND particle connected with the first chip select signal port CH0_CE0_n.

Under the condition that each NAND particle connected with the first chip selection signal port CH0_CE0_n does not read and write data, the solid state disk controller reallocates the address of each storage unit lun in each NAND particle connected with the first chip selection signal port CH0_CE0_n based on the corresponding relation between the chip selection signal ports in the chip selection signal port group and the chip selection signal pins in the NAND particles in the solid state disk controller of the solid state disk. For example: the solid state disk controller can send data information such as 0xEF command/0 xFB address, 0x01/0x00/0x00/0x00 and the like to each storage unit lun in each NAND particle connected with the first chip select signal port CH0_CE0_n; where 0x01 indicates that 1 chip select signal pin corresponds to 2 memory cells lun,0x02 indicates that 1 chip select signal pin corresponds to 4 memory cells lun, and 0x03 indicates that 1 chip select signal pin corresponds to 8 memory cells lun.

After the address of each memory cell lun in each NAND particle connected to the first chip select signal port ch0_ce0_n is reassigned, the above steps are repeated, and the second chip select signal port ch0_ce1_n to the eighth chip select signal port ch0_ce7_n sequentially output low-level chip select signals, thereby completing the address assignment of the memory cell lun in the NAND particle connected to the first channel in the solid state disk controller.

And after the addresses of the storage units lun in the NAND particles connected with the first channel in the solid state disk controller are allocated, repeating the steps, and sequentially completing the address allocation of the storage units lun in the NAND particles connected with other channels in the solid state disk control.

In another aspect, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of executing the data reading and writing method provided by the above methods, the method comprising: acquiring an address of a target storage unit needing to perform target operation, wherein the target operation comprises data reading operation and/or data storage operation; generating a target chip selection signal corresponding to the target storage unit based on the address of the target storage unit and the NAND particle where the target storage unit is located, wherein the target chip selection signal is of a low level; transmitting the target chip selection signal to the target storage unit through the application circuit so that the target storage unit is switched to a gating state under the condition that the target chip selection signal is received; and performing target operation on the target storage unit.

In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the data read-write method provided by the above methods, the method comprising: acquiring an address of a target storage unit needing to perform target operation, wherein the target operation comprises data reading operation and/or data storage operation; generating a target chip selection signal corresponding to the target storage unit based on the address of the target storage unit and the NAND particle where the target storage unit is located, wherein the target chip selection signal is of a low level; transmitting the target chip selection signal to the target storage unit through the application circuit so that the target storage unit is switched to a gating state under the condition that the target chip selection signal is received; and performing target operation on the target storage unit.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. The application circuit is characterized by being used for connecting a solid state disk controller and a plurality of NAND particles;

different chip select signal pins in the NAND particle are used for receiving different chip select signals; the correspondence between the chip select signal ports in the chip select signal port group and the chip select signal pins in the NAND pellet is determined based on the correspondence between different chip select signal pins and different chip select signals in different NAND pellets.

2. The application circuit of claim 1, wherein the correspondence between chip select signal ports in the group of chip select signal ports and chip select signal pins in the NAND die comprises: a first chip select signal port in any one of the chip select signal port groups corresponds to a first chip select signal pin and a second chip select signal pin in the NAND die,

3. The application circuit according to claim 1, wherein in the case that the NAND particles are of the first package type, two rows of edge pads on the left and right sides of the printed circuit board are suspended, and pins of the NAND particles are soldered in one-to-one correspondence with the remaining pads on the printed circuit board.

4. The application circuit according to claim 3, wherein in case the NAND die is of the second package type, pins of the NAND die are soldered in one-to-one correspondence with pads on the printed circuit board.

5. The application circuit of claim 1, wherein the set of sub-lines comprises: a first line, a second line, a third line, and a fourth line,

6. The application circuit according to claim 5, wherein in the case where the NAND pellet is a first NAND pellet, a first chip select signal pin and a fifth chip select signal pin in the NAND pellet correspond to a first chip select signal, a third chip select signal pin and a seventh chip select signal pin in the NAND pellet correspond to a second chip select signal, a second chip select signal pin and a sixth chip select signal pin in the NAND pellet correspond to a third chip select signal, and a fourth chip select signal pin and an eighth chip select signal pin in the NAND pellet correspond to a fourth chip select signal.

7. The application circuit according to claim 6, wherein in the case where the NAND grain is a second NAND grain, a first chip select signal pin in the NAND grain corresponds to a first chip select signal, a fifth chip select signal pin in the NAND grain corresponds to a second chip select signal, and chip select signal pins other than the first chip select signal pin and the fifth chip select signal pin in the NAND grain are suspended.

8. The application circuit according to claim 7, wherein in the case where the NAND grain is a third NAND grain, a first chip select signal pin in the NAND grain corresponds to the first chip select signal, a fifth chip select signal pin in the NAND grain corresponds to the third chip select signal, a third chip select signal pin in the NAND grain corresponds to the third chip select signal, a fourth chip select signal pin in the NAND grain corresponds to the fourth chip select signal, and a fifth chip select signal pin, a sixth chip select signal pin, a seventh chip select signal pin, and an eighth chip select signal pin in the NAND grain are suspended.

9. The application circuit of claim 5, wherein the set of sub-lines further comprises: a NAND bus;

10. The application circuit according to claim 9, wherein in the case where the NAND die is a first NAND die, each of the select signal pins in the NAND die corresponds to a respective one of the memory cells.

11. The application circuit according to claim 9, wherein in the case where the NAND die is a second NAND die, a first chip select signal pin and a fifth chip select signal pin in the NAND die correspond to four memory cells, respectively.

12. The application circuit according to claim 9, wherein in the case where the NAND die is a third NAND die, the first chip select signal pin, the third chip select signal pin, the fifth chip select signal pin, and the seventh chip select signal pin in the NAND die correspond to two memory cells, respectively.

13. The application circuit of claim 4, wherein the first package type is a ball grid array package, BGA132, package type; the second package type is a BGA152 package type.

14. The application circuit of claim 1, wherein the target channels comprise all channels in the solid state disk controller.

15. The application circuit of claim 8, wherein the first NAND die, the second NAND die, and the third NAND die are produced by different NAND die manufacturers.

16. A solid state disk, comprising: a solid state disk controller, a plurality of NAND particles, and an application circuit as claimed in any one of claims 1 to 15;

17. An electronic device, comprising: the solid state disk of claim 16.

18. A data reading and writing method, which is applied to the solid state disk as claimed in claim 16, the method comprising:

and carrying out the target operation on the target storage unit.

19. The method for reading and writing data according to claim 18, wherein, in the case where the NAND grain in the solid state disk is the first NAND grain, before generating the target chip select signal corresponding to the target storage unit based on the address of the target storage unit and the NAND grain where the target storage unit is located, the method further includes:

20. The method of claim 19, wherein reassigning the address of each memory cell in each NAND grain based on the correspondence between the chip select signal ports in the chip select signal port group and the chip select signal pins in the NAND grain in the solid state disk controller of the solid state disk comprises:

acquiring an address of each storage unit in each NAND particle;