CN117556752A - FFT and IFFT digital simulation verification method based on third-party language and related equipment - Google Patents
FFT and IFFT digital simulation verification method based on third-party language and related equipment Download PDFInfo
- Publication number
- CN117556752A CN117556752A CN202311558347.3A CN202311558347A CN117556752A CN 117556752 A CN117556752 A CN 117556752A CN 202311558347 A CN202311558347 A CN 202311558347A CN 117556752 A CN117556752 A CN 117556752A
- Authority
- CN
- China
- Prior art keywords
- fft
- ifft
- data
- digital simulation
- tested
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012795 verification Methods 0.000 title claims abstract description 140
- 238000000034 method Methods 0.000 title claims abstract description 79
- 238000004088 simulation Methods 0.000 title claims abstract description 64
- 238000013461 design Methods 0.000 claims abstract description 36
- 238000012360 testing method Methods 0.000 claims abstract description 18
- 238000004590 computer program Methods 0.000 claims description 25
- 230000005284 excitation Effects 0.000 claims description 9
- 238000013515 script Methods 0.000 claims description 8
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 230000003993 interaction Effects 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000004422 calculation algorithm Methods 0.000 abstract description 41
- 238000004364 calculation method Methods 0.000 abstract description 28
- 238000007689 inspection Methods 0.000 abstract description 4
- 230000006870 function Effects 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 5
- 230000000007 visual effect Effects 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000013473 artificial intelligence Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a method for verifying FFT and IFFT digital simulation based on a third party language and related equipment, belonging to the field of integrated circuit digital simulation verification, wherein the method generates random data by the third party language, builds an FFT/IFFT reference model based on the third party language, and inputs the generated random data into the FFT/IFFT reference model and the design to be tested respectively when the test is required to be verified, and the digital simulation verification of the design to be tested is completed through the comparison result of the reference data and the data to be tested; the method can effectively cover the effective inspection of the calculation results of various operation modes of the FFT/IFFT algorithm module, effectively solves the problem that the complex algorithm lacks an adaptable VIP, and realizes a collaborative verification method combining the traditional verification method with various mathematical algorithms provided by a third party language.
Description
Technical Field
The invention belongs to the field of integrated circuit digital simulation verification, and particularly relates to an FFT (fast Fourier transform) and IFFT (inverse fast Fourier transform) digital simulation verification method based on a third party language and related equipment.
Background
The development is rapid based on the progress of brain science, the artificial intelligence technology is also rapidly developed, the demands on chips and hardware based on artificial intelligence are more remarkable, and the functional verification of complex mathematical algorithms serving as the cores of the artificial intelligence technology is one of the problems to be solved in the current chip verification field.
In the traditional digital chip design, algorithms are fewer or are generally simpler, verification objects are generally various peripheral function modules with fewer algorithm functions, and verification of corresponding functions can be realized by means of a large number of commercial VIP (Verifiction IP). However, in the face of function verification of various complex and more intelligent algorithm modules in the current chip, because of lacking an adaptable VIP, a great deal of time is required to develop an adaptable and highly-trusted verification model, so that a new verification method technology is required to realize function verification of an intelligent function module core algorithm so as to meet the verification requirement of an intelligent chip.
Disclosure of Invention
In order to overcome the defects of the technology, the invention provides an FFT and IFFT digital simulation verification method based on a third-party language and related equipment, which can solve the technical problem that the traditional digital simulation verification needs to use commercial VIP and cannot be applied to digital simulation verification of various complex and intelligent algorithm modules.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an FFT, IFFT digital simulation verification method based on a third party language comprises the following steps:
the random data are respectively input into an FFT/IFFT reference model and a design to be tested, and reference data and data to be tested are output;
comparing the output reference data with the data to be tested, outputting a comparison result, and completing digital simulation verification;
wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
Further, the third party language adopts a Python language.
Further, based on scripts developed by Python language, switching between two working modes of FFT and IFFT is realized.
Further, based on scripts developed by Python language, random data with different operation points and data lengths are generated by transmitting different parameters.
Further, according to the interface configuration of the design to be tested, the interface configuration is set for the FFT/IFFT reference model, so that the interface configuration of the FFT/IFFT reference model and the interface configuration of the FFT/IFFT reference model are the same.
Further, the method further comprises the following steps:
and visually displaying the output comparison result.
Further, the method further comprises the following steps: the test excitation callback process specifically comprises the following steps:
when the design to be tested and the verification platform perform data interaction, the design to be tested is modified through the test excitation callback so as to meet the verification of the abnormal design.
The FFT and IFFT digital simulation verification system based on the third party language is used for realizing the steps of the FFT and IFFT digital simulation verification method based on the third party language, and comprises the following steps:
the data operation module is used for respectively inputting random data into the FFT/IFFT reference model and the design to be tested and outputting reference data and the data to be tested;
the data comparison module is used for comparing the output reference data with the data to be tested, outputting a comparison result and completing digital simulation verification;
wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
An apparatus, comprising:
a memory for storing a computer program;
and the processor is used for realizing the steps of the FFT and IFFT digital simulation verification method based on the third party language when executing the computer program.
A computer readable storage medium storing a computer program for implementing the steps of the above described third party language based FFT, IFFT digital emulation verification method when executed by a processor.
Compared with the prior art, the invention has the following beneficial effects:
the invention also provides a FFT and IFFT digital simulation verification method based on the third party language, which comprises the steps of generating random data by the third party language, constructing an FFT/IFFT reference model based on the third party language, inputting the generated random data into the FFT/IFFT reference model and the design to be tested respectively when the test is required to be verified, and completing the digital simulation verification of the design to be tested through the comparison result of the reference data and the data to be tested; the method can effectively cover the effective inspection of the calculation results of various operation modes of the FFT/IFFT algorithm module, effectively solves the problem that the complex algorithm lacks an adaptable VIP, and realizes a collaborative verification method combining the traditional verification method with various mathematical algorithms provided by a third party language.
Compared with the traditional VIP-based verification method for verifying the lack of the VIP in the complex algorithm, the verification platform constructed by the verification method can effectively solve the construction of the reference model of the complex algorithm.
Compared with the traditional verification method, the method is limited to simulation waveforms and text files in checking the calculation results of the complex algorithm, and the verification platform constructed based on the verification method is lack of checking the calculation accuracy of the simulation complex algorithm, so that the method can meet the checking compatible with the traditional verification method, can realize the more visual representation of the calculation accuracy of the algorithm in a graphical mode, and greatly improves the visual property of checking the calculation results.
Compared with the verification platform constructed by the traditional verification method, the verification platform constructed by the verification method disclosed by the invention uses parameterized configuration, and can realize the selection of different working modes and different operation data amounts of the covered double paths, so that the number of test cases can be effectively reduced, the verification period is greatly shortened, and the verification efficiency is improved.
In the invention, a callback mechanism added based on the verification method is arranged in an interactive link driver of the verification platform and the design to be tested, and can modify the test excitation with special requirements to realize the abnormal test case, thereby enhancing the expandability and reusability of the verification environment.
Drawings
Fig. 1 is a flowchart of a Python-based FFT and IFFT digital simulation verification method in the FFT and IFFT digital simulation verification method based on a third party language according to an embodiment of the present invention;
fig. 2 is a verification environment diagram of an FFT and IFFT digital simulation verification method based on a third party language according to an embodiment of the present invention;
FIG. 3 is a diagram of FFT operation results obtained by the present digital simulation verification method according to an embodiment of the present invention;
fig. 4 is a diagram of an IFFT operation result using the present digital simulation verification method according to an embodiment of the present invention;
FIG. 5 is a flow chart of a third party language based FFT, IFFT digital simulation verification method provided by the invention;
fig. 6 is a schematic structural diagram of an FFT and IFFT digital simulation verification system based on a third party language according to the present invention.
Detailed Description
The invention provides a FFT and IFFT digital simulation verification method based on a third party language, which is shown in figure 5 and comprises the following steps:
s1, inputting random data into an FFT/IFFT reference model and a design to be tested respectively, and outputting reference data and data to be tested.
The third party language adopts Python language.
Based on scripts developed by Python language, the switching between the two working modes of FFT and IFFT is realized.
Meanwhile, based on scripts developed by Python language, random data with different operation points and data lengths are generated by transmitting different parameters.
And setting interface configuration for the FFT/IFFT reference model according to the interface configuration of the design to be tested, so that the interface configuration of the FFT/IFFT reference model and the interface configuration of the FFT/IFFT reference model are the same.
And S2, carrying out data comparison on the output reference data and the data to be tested, and outputting a comparison result to finish digital simulation verification.
Further comprises:
and visually displaying the output comparison result.
And a test stimulus callback process, specifically:
when the design to be tested and the verification platform perform data interaction, the design to be tested is modified through the test excitation callback so as to meet the verification of the abnormal design.
Wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
As shown in fig. 6, the present invention further provides an FFT and IFFT digital simulation verification system based on a third party language, including: the data operation module is used for respectively inputting random data into the FFT/IFFT reference model and the design to be tested and outputting reference data and the data to be tested; the data comparison module is used for comparing the output reference data with the data to be tested, outputting a comparison result and completing digital simulation verification; wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
The invention also provides an apparatus comprising: a memory for storing a computer program; and the processor is used for realizing the steps of the FFT and IFFT digital simulation verification method based on the third party language when executing the computer program.
The processor executes the computer program to implement the steps of FFT and IFFT digital simulation verification based on the third party language, for example: the random data are respectively input into an FFT/IFFT reference model and a design to be tested, and reference data and data to be tested are output; comparing the output reference data with the data to be tested, outputting a comparison result, and completing digital simulation verification; wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
Alternatively, the processor may implement functions of each module in the above system when executing the computer program, for example: the data operation module is used for respectively inputting random data into the FFT/IFFT reference model and the design to be tested and outputting reference data and the data to be tested; the data comparison module is used for comparing the output reference data with the data to be tested, outputting a comparison result and completing digital simulation verification; wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
The computer program may be divided into one or more modules/units, which are stored in the memory and executed by the processor to accomplish the present invention, for example. The one or more modules/units may be a series of computer program instruction segments capable of performing a predetermined function, the instruction segments describing the execution of the computer program in the third party language based FFT, IFFT digital emulation verification device. For example, the computer program may be divided into a data operation module and a data comparison module; the specific functions of each module are as follows: the data operation module is used for respectively inputting random data into the FFT/IFFT reference model and the design to be tested and outputting reference data and the data to be tested; the data comparison module is used for comparing the output reference data with the data to be tested, outputting a comparison result and completing digital simulation verification; wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
The FFT and IFFT digital simulation verification equipment based on the third party language can be computing equipment such as a desktop computer, a notebook computer, a palm computer and a cloud server. The third party language based FFT, IFFT digital emulation verification device can include, but is not limited to, a processor, memory. It will be appreciated by those skilled in the art that the foregoing is an example of a third party language based FFT, IFFT digital emulation verification device, and is not limiting of the third party language based FFT, IFFT digital emulation verification device, and may include more components than those described above, or may combine certain components, or different components, e.g., the third party language based FFT, IFFT digital emulation verification device may also include an input-output device, a network access device, a bus, etc.
The processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. The general processor may be a microprocessor or the processor may also be any conventional processor, etc., and the processor is a control center of the FFT and IFFT digital simulation verification device based on the third party language, and various interfaces and lines are used to connect various parts of the whole FFT and IFFT digital simulation verification device based on the third party language.
The memory may be used to store the computer program and/or module, and the processor may implement various functions of the third party language based FFT, IFFT digital emulation verification device by running or executing the computer program and/or module stored in the memory and invoking data stored in the memory.
The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like; the storage data area may store data (such as audio data, phonebook, etc.) created according to the use of the handset, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.
The invention also provides a computer readable storage medium storing a computer program which when executed by a processor implements the steps of the FFT and IFFT digital simulation verification method based on a third party language.
The modules/units integrated by the FFT, IFFT digital emulation and verification system based on the third party language, if implemented in the form of software functional units, and sold or used as a stand-alone product, can be stored in a computer readable storage medium.
Based on such understanding, the implementation of all or part of the above-mentioned FFT and IFFT digital simulation verification method based on the third party language may also be accomplished by instructing related hardware by a computer program, where the computer program may be stored in a computer readable storage medium, and the computer program may implement the steps of the above-mentioned FFT and IFFT digital simulation verification method based on the third party language when executed by a processor. The computer program comprises computer program code, and the computer program code can be in a source code form, an object code form, an executable file or a preset intermediate form and the like.
The computer readable storage medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth.
It should be noted that the computer readable storage medium may include content that is subject to appropriate increases and decreases as required by jurisdictions and by jurisdictions in which such computer readable storage medium does not include electrical carrier signals and telecommunications signals.
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
examples
As described in the background, the verification object is generally various peripheral function modules with less algorithm functions, and the verification of the corresponding functions can be realized by a large number of commercial VIP (Verifiction IP). However, in the face of function verification of various complex and more intelligent algorithm modules in the current chip, because of lacking an adaptable VIP, a great deal of time is required to develop an adaptable and highly-trusted verification model, so that a new verification method technology is required to realize function verification of an intelligent function module core algorithm so as to meet the verification requirement of an intelligent chip.
In order to solve the problems, the implementation provides the FFT and IFFT digital simulation verification method based on the third-party language, and the adoption of the method can effectively improve the efficiency and the correctness of FFT/IFFT simulation verification and greatly shorten the simulation verification period. The method can effectively cover various functional configurations of the FFT/IFFT module and effective inspection of calculation results, can intuitively analyze and display the calculation results, effectively solves the limitation that the traditional functional verification cannot effectively verify a complex intelligent algorithm, and improves the simulation verification coverage and efficiency of various configurations of the algorithm.
As shown in fig. 1, the present embodiment provides a third-party language-based FFT and IFFT digital simulation verification method, which is mainly characterized in that selection of FFT and IFFT working modes is implemented through script; the random numbers with different data lengths are generated through the script; the same excitation configuration is realized, and the excitation configuration is configured to a Python developing FFT/IFFT algorithm structure and an FFT algorithm module to be tested; the comparison and check of FFT/IFFT test results are realized through a test comparison program developed by Python; visual display of the test comparison result is realized through Python. Aiming at the complexity of the implementation of the FFT/IFFT algorithm, the verification method provided by the embodiment can effectively cover various functional configurations of the FFT module and effective checking of the calculation result, and can intuitively analyze and display the calculation result, effectively solves the limitation that the traditional functional verification cannot effectively verify the complex intelligent algorithm, and improves the simulation verification coverage and efficiency for various configurations of the algorithm. In this embodiment, the method is carried on the verification platform for implementation, and the specific steps are as follows:
first, the verification method constructs a verification platform. The generation of random data is realized by combining Python with a mathematical algorithm in a test platform, the random data is used as the input of a design to be tested and a reference model, and when the random data is generated, the generation of different random data can be realized by transmitting different parameters.
And secondly, constructing an FFT/IFFT reference model by adopting Python, wherein various mathematical structures in a mathematical toolkit of Python language are adopted, and the interface configuration of the reference model is consistent with the setting to be tested, so that the consistency of the reference model and the working mode of the design to be tested is ensured.
After the generated random data respectively enter a reference model constructed by Python and the design to be tested, the design to be tested data is fed back to a verification environment after simulation operation, and the data is compared with the data generated by the reference model as shown in fig. 2.
In this embodiment, when the environment is used, the environment can be configured as required according to the calculation requirement, and the "input data file" in the verification environment can specify the data file for calculation, and in default, the data file is an "src.dat" file under the current path, and the format of the data file is hexadecimal data; the "FFT calculation result" may specify a Python FFT calculation result output data file, which is named "FFT. Dat" by default; the "input points" mainly set the points to be operated in the same units as the points of the data to be calculated (one point corresponds to 64-bit data) and the register configuration units to be designed. The input data length designates the length of the data which is required to be calculated currently, and can be configured according to the requirement, wherein the unit is the point number; the "DUT calculation result" points to paths where the FFT result and the IFFT result after the design calculation to be measured are located, after the corresponding configuration is completed, FFT calculation can be generated by selecting the "FFT operation" button, the analysis result of the FFT calculation is shown in FIG. 3, IFFT calculation can be generated by selecting the "IFFT operation" button, and the analysis result of the IFFT calculation is shown in FIG. 4. Specifically, in fig. 3, the FFT calculation analysis result is: the data length is 32768 points, the operation point is 8192 points, and the error of the FFT operation result is between 0.0010 and 0.0015; in fig. 4, the IFFT calculation analysis results are: the data length is 32768 points, the operation point is 8192 points, and the error of the IFFT operation result is between 0.0010 and 0.0015.
In the implementation, the visual verification platform, the generation of the configurable pseudo random number, the construction of the complex mathematical algorithm reference model, the effective checking of the calculation result of the to-be-tested design and the like are realized through the verification environment, so that the whole verification platform has the advantages of flexible configuration, the visibility of the complex algorithm result checking and the like.
The invention is applied to a multi-core task parallel multi-core processor chip based on a 28nm process, as shown in fig. 3 and 4, the correctness of the FFT/IFFT algorithm can be effectively verified by applying the invention, and the graphical checking result can be intuitively given. The chip has been successfully diced at present. In addition, the verification method can be popularized to other integrated circuit designs comprising complex algorithm designs, and has good popularization and application values.
In summary, the invention provides an FFT and IFFT digital simulation verification method based on a third party language, which has the following advantages compared with the existing detection method:
the digital simulation verification method of the single-precision FFT/IFFT algorithm module with the configurable FFT and IFFT different operation modes, operation points and data length is realized, the effective inspection of the calculation results of various operation modes of the FFT/IFFT algorithm module is effectively covered based on the method, the problem that a complex algorithm lacks an adaptable VIP is effectively solved, and the collaborative verification method of combining the traditional verification method with various mathematical algorithms provided by a third party language is realized. The effects obtained are as follows:
1) Compared with the conventional VIP-based verification method for verifying the lack of the VIP for the complex algorithm, the verification platform constructed by the verification method can effectively solve the construction of the reference model of the complex algorithm.
2) Compared with the traditional verification method, the method is limited to simulation waveforms and text files for checking the calculation results of the complex algorithm, and the verification platform constructed based on the verification method is lack of checking the calculation accuracy of the simulation complex algorithm, so that the method can meet the checking compatible with the traditional verification method, and meanwhile, the calculation accuracy of the algorithm can be displayed in a graphical and more visual mode, and the intuitiveness of checking the calculation results of the verification is greatly improved.
3) Compared with the verification platform constructed by the traditional verification method, the verification platform constructed by the verification method disclosed by the invention uses parameterized configuration, and can realize the selection of different working modes and different operation data amounts of the covered double paths, so that the number of test cases can be effectively reduced, the verification period is greatly shortened, and the verification efficiency is improved.
4) The callback mechanism added based on the verification method is arranged in an interaction link driver of the verification platform and the design to be tested, and can modify the special test excitation to realize the abnormal test case, so that the expandability and reusability of the verification environment are enhanced.
The above embodiment is only one of the implementation manners capable of implementing the technical solution of the present invention, and the scope of the claimed invention is not limited to the embodiment, but also includes any changes, substitutions and other implementation manners easily recognized by those skilled in the art within the technical scope of the present invention.
Claims (10)
1. The FFT and IFFT digital simulation verification method based on the third party language is characterized by comprising the following steps of:
the random data are respectively input into an FFT/IFFT reference model and a design to be tested, and reference data and data to be tested are output;
comparing the output reference data with the data to be tested, outputting a comparison result, and completing digital simulation verification;
wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
2. The FFT, IFFT digital simulation verification method based on a third party language according to claim 1, wherein the third party language uses Python language.
3. The method for verifying FFT and IFFT digital simulation based on the third party language according to claim 2, wherein the switching between the two working modes of FFT and IFFT is realized based on scripts developed by Python language.
4. The FFT and IFFT digital simulation verification method based on a third party language according to claim 2, wherein random data with different operation points and data lengths are generated by transferring different parameters based on scripts developed by Python language.
5. The method for simulating and verifying FFT and IFFT digital based on third party language according to claim 1, wherein the interface configuration is set for the FFT/IFFT reference model according to the interface configuration of the design to be tested, so that the interface configuration is the same.
6. The FFT, IFFT digital simulation verification method based on a third party language according to claim 1, further comprising:
and visually displaying the output comparison result.
7. The FFT, IFFT digital simulation verification method based on a third party language according to claim 1, further comprising: the test excitation callback process specifically comprises the following steps:
when the design to be tested and the verification platform perform data interaction, the design to be tested is modified through the test excitation callback so as to meet the verification of the abnormal design.
8. A third party language based FFT, IFFT digital simulation verification system for implementing the steps of the third party language based FFT, IFFT digital simulation verification method according to any of claims 1-7, comprising:
the data operation module is used for respectively inputting random data into the FFT/IFFT reference model and the design to be tested and outputting reference data and the data to be tested;
the data comparison module is used for comparing the output reference data with the data to be tested, outputting a comparison result and completing digital simulation verification;
wherein the random data is generated based on a third party language; the FFT/IFFT reference model is constructed based on a third party language.
9. An apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the FFT, IFFT digital simulation verification method based on a third party language as claimed in any one of claims 1-7 when executing the computer program.
10. A computer readable storage medium storing a computer program, characterized in that the computer program is executed by a processor for implementing the steps of the third party language based FFT, IFFT digital emulation verification method as claimed in any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311558347.3A CN117556752A (en) | 2023-11-21 | 2023-11-21 | FFT and IFFT digital simulation verification method based on third-party language and related equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311558347.3A CN117556752A (en) | 2023-11-21 | 2023-11-21 | FFT and IFFT digital simulation verification method based on third-party language and related equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117556752A true CN117556752A (en) | 2024-02-13 |
Family
ID=89820188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311558347.3A Pending CN117556752A (en) | 2023-11-21 | 2023-11-21 | FFT and IFFT digital simulation verification method based on third-party language and related equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117556752A (en) |
-
2023
- 2023-11-21 CN CN202311558347.3A patent/CN117556752A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109582525B (en) | Test code verification method, verification device, equipment and storage medium | |
| CN113032195A (en) | Chip simulation verification method, system, equipment and storage medium | |
| CN107807881B (en) | Code coverage rate testing method and device and computer equipment | |
| US10209306B2 (en) | Methods and systems for generating functional test patterns for manufacture test | |
| CN110377462B (en) | Interface testing method and device and terminal equipment | |
| CN112100079B (en) | Test method and system based on simulation data calling and electronic equipment | |
| CN113704043A (en) | Chip function verification method and device, readable storage medium and electronic equipment | |
| CN110806970A (en) | Client test method and device based on simulation server response and electronic equipment | |
| CN113342583B (en) | Chip verification system, method, device, equipment and storage medium | |
| CN111797020A (en) | Mock data method and device based on dynamic bytecode | |
| JP2023086678A (en) | Method and apparatus for generating and applying deep learning model based on deep learning framework | |
| CN111459814A (en) | Automatic test case generation method and device and electronic equipment | |
| CN111291443B (en) | Automatic generation method, device and equipment for I/O module model of vehicle control unit software | |
| CN117556752A (en) | FFT and IFFT digital simulation verification method based on third-party language and related equipment | |
| CN115576711A (en) | Method and system for simulating returned data and computing equipment | |
| CN111949510B (en) | Test processing method, device, electronic equipment and readable storage medium | |
| CN115599401A (en) | Publishing method, device, equipment and medium of user-defined model | |
| US20170060716A1 (en) | Persistent command parameter table for pre-silicon device testing | |
| KR102325612B1 (en) | Method, apparatus, device, and medium for implementing simulator | |
| CN115391168A (en) | Sandbox testing method, sandbox testing device, sandbox testing equipment and storage medium | |
| US20210303766A1 (en) | Pre-silicon chip model of extracted workload inner loop instruction traces | |
| CN114721286A (en) | Distributed compiled parallel real-time simulation system and simulation method | |
| CN112445711A (en) | Test method for generating simulation test scene based on visual dragging of Web page | |
| CN112507521A (en) | Digital simulation platform of steam generator | |
| CN113377648A (en) | Software system diagnosis method and device, electronic equipment and computer readable medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |