CN117544766A - Method, equipment and medium for testing audio and video data - Google Patents
Method, equipment and medium for testing audio and video data Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 230000005540 biological transmission Effects 0.000 claims abstract description 103
- 238000006243 chemical reaction Methods 0.000 claims description 51
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
- H04N21/4341—Demultiplexing of audio and video streams
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/439—Processing of audio elementary streams
- H04N21/4394—Processing of audio elementary streams involving operations for analysing the audio stream, e.g. detecting features or characteristics in audio streams
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/439—Processing of audio elementary streams
- H04N21/4398—Processing of audio elementary streams involving reformatting operations of audio signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/44008—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
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- General Health & Medical Sciences (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Abstract
The present disclosure provides a method, apparatus and medium for audio and video data testing, where the method includes: analyzing a video data stream and an audio data stream according to the original audio and video data output by the chip to be tested; respectively converting the video data stream and the audio data stream into video data to be transmitted and audio data to be transmitted which meet the set transmission specification; storing the video data to be transmitted and the audio data to be transmitted into a system memory according to a transmission mode corresponding to the transmission specification; and reading out the video data and the audio data stored in the system memory so as to test the audio and video data according to a set test strategy.
Description
Technical Field
The disclosure relates to the technical field of audio and video testing, and in particular relates to a method, equipment and medium for audio and video data testing.
Background
During chip production, system functional testing (System Level Test, SLT) of the produced chips is often required. For chips with audio/video output interfaces such as a high-definition multimedia interface (High Definition Multimedia Interface, HDMI) and a display interface (DP), whether the output function of audio/video data of the chip is normal or not needs to be tested, so as to judge whether the chip has the conditions of transistor damage and failure in the production process of a streaming sheet or not, and reject the chip with the conditions of transistor damage and failure.
At present, related schemes for testing the output function of audio and video data mainly utilize an external display to output image detection and an audio playing device to output audio detection, the schemes are identified by human eyes and ears, the correctness of the schemes is not high, and the output details such as color difference of individual pixels cannot be distinguished.
Disclosure of Invention
The present disclosure provides a method, apparatus, and medium for audio and video data testing; the chip can store the original data output by the audio and video output interfaces such as HDMI or DP, so as to carry out the audio and video data test subsequently, avoid the limitation of manual comparison test and improve the test accuracy.
The technical scheme of the present disclosure is realized as follows:
in a first aspect, the present disclosure provides a method for audio-video data testing, the method comprising:
analyzing a video data stream and an audio data stream according to the original audio and video data output by the chip to be tested;
respectively converting the video data stream and the audio data stream into video data to be transmitted and audio data to be transmitted which meet the set transmission specification;
storing the video data to be transmitted and the audio data to be transmitted into a system memory according to a transmission mode corresponding to the transmission specification;
and reading out the video data and the audio data stored in the system memory so as to test the audio and video data according to a set test strategy.
In a second aspect, the present disclosure provides an apparatus for audio-video data testing, the apparatus comprising: a data analysis part, a data conversion part, a data transmission part and a system memory; wherein,
the data analysis part is connected to an audio/video output interface of the chip to be tested and is used for receiving original audio/video data from the audio/video output interface and analyzing video data streams and audio data streams;
the data conversion part is connected to the data analysis part and is used for respectively converting the video data stream and the audio data stream into video data to be transmitted and audio data to be transmitted which meet the set transmission specification;
the data transmission part is connected to the data conversion part and is used for storing the video data to be transmitted and the audio data to be transmitted into the system memory according to the transmission mode corresponding to the transmission specification.
In a third aspect, the present disclosure provides a computer storage medium storing at least one instruction for execution by a processor to implement the method of audio video data testing of the first aspect.
The present disclosure provides a method, apparatus, and medium for audio and video data testing; after the original audio and video data output by the chip to be tested are analyzed to obtain a video data stream and an audio data stream, the video data stream and the audio data stream are converted according to a set transmission format, and the video data to be transmitted and the audio data to be transmitted are stored in a system memory by utilizing a corresponding transmission mode, so that the audio and video data are tested according to a set testing strategy by reading the video data and the audio data stored in the system memory. The chip can store the original data output by the audio and video output interfaces such as HDMI or DP, so as to carry out the audio and video data test subsequently, avoid the limitation of manual comparison test and improve the test accuracy.
Drawings
Fig. 1 is a flowchart of a method for audio and video data testing provided in the present disclosure.
Fig. 2 is a schematic flow chart of parsing out a video data stream and an audio data stream provided in the present disclosure.
Fig. 3 is a schematic flow chart of converting video data to be transmitted according to the present disclosure.
Fig. 4 is a schematic flow chart of converting audio data to be transmitted according to the present disclosure.
Fig. 5 is a schematic diagram of an apparatus structure for audio and video data testing provided in the present disclosure.
Fig. 6 is a schematic diagram of another device structure for audio and video data testing provided in the present disclosure.
Fig. 7 is a schematic diagram of a video conversion module provided in the present disclosure.
Fig. 8 is a schematic diagram of an audio conversion module according to the present disclosure.
Detailed Description
The technical solutions in the present disclosure will be clearly and completely described below with reference to the drawings in the present disclosure.
At present, the correctness of a related scheme of manual comparison test by human eyes and human ears is not high, and the situation that the output details such as color difference of individual pixels cannot be distinguished exists. In addition, the related solution may further use a protocol analyzer to perform a test, but in practical implementation, the protocol analyzer generally only can test one interface at a time due to the limitation of the test principle, and cannot perform a large-scale test in the chip mass production process, and the test efficiency may be reduced due to that the protocol analyzer is connected with the interfaces of the chip to be tested one by one. On the other hand, the protocol analyzer can only determine the condition of each pin of the interface according to the interface protocol. For example, when testing an HDMI interface, corresponding data of each pin corresponding to the HDMI protocol is generally generated, and the analysis result is not in one-to-one correspondence with the internal software and hardware faults of the interface of the chip to be tested, and further analysis is required, and even a final fault detection result still needs to be obtained through manual comparison test.
Based on this, referring to fig. 1, a method for audio and video data testing provided by the present disclosure is shown, and in the present disclosure, the method includes steps S101 to S104.
In step S101, a video data stream and an audio data stream are parsed according to original audio and video data output by a chip to be tested.
In the present disclosure, the chip to be tested may include, but is not limited to, a Graphics Processor (GPU), a video codec chip, a digital signal processor chip, a multimedia processor chip, etc., and the above-mentioned types of chips may output audio and video data through an audio and video output interface (e.g., an interface such as HDMI or DP) of the chip.
Currently, the format of audio and video data output by these chips belongs to the audio and video mixed format. In order to test audio format data and video format data in audio and video data respectively to obtain whether the output function of the audio and video data of the chip of the type is normal, the present disclosure analyzes the original audio and video data output by the chip to be tested to distinguish different format data, and obtains a video data stream and an audio data stream.
In some specific implementation processes, corresponding parameters may be configured for the parsing process according to parameter indexes representing the audio/video data output capability of the chip to be tested, where the parameters may include video resolution, video frame rate, audio channel number, audio sampling rate, and the like. For example, the specific information field of the original audio/video data output by the chip to be tested can be analyzed by configuring the video resolution (such as 720p, 1080p, 4K, etc.) and the frame rate (such as 30Hz, 60Hz, etc.) matched with the audio/video output capability of the chip to be tested, so as to obtain a video data Stream conforming to a set data format (such as advanced scalable interface data Stream (Advanced eXtensible InterfaceStream, AXI-Stream)). In addition, by configuring the number of channels (such as stereo, 5.1 channels, 7.1 channels, etc.) and the sampling rate (such as 44.1kHz, 48kHz, etc.) matched with the audio/video output capability of the chip to be tested, audio data streams with different numbers of channels and different sampling rates can be correctly separated and converted from the original audio/video data output by the chip to be tested, and the audio data streams can conform to the same data format as the video data streams, such as AXI-Stream.
In step S102, the video data stream and the audio data stream are respectively converted into video data to be transmitted and audio data to be transmitted that conform to the set transmission specification.
In the present disclosure, the set transfer specification includes a data specification conforming to a direct memory access (Direct Memory Access, DMA) transfer. For this transmission specification, conversion can be made from three aspects of clock domain, data bit width, and buffered data amount.
Specifically, first, the clock frequencies of the original audio and video data output by different chips to be tested are different, so that in order to facilitate the calculation and convergence process in the subsequent test process, the clock domains of the video data stream and the audio data stream analyzed in step S101 need to be converted into a fixed clock frequency, i.e. the clock frequency accords with the highest frequency clock frequency in the system used in the subsequent test process.
Then, the data bit width of the original audio/video data output by the chip to be tested is inconsistent with the data bit width during DMA transmission. In order to adapt to the requirements of DMA transfer, it is also necessary to convert the data bit widths of the video data stream and the audio data stream to adapt to the requirements of address alignment during DMA transfer.
Then, in the DMA transmission process, the data size of the single transmission is also required to be specific, so that the video data stream and the audio data stream also need to be buffered according to the data size of the single transmission set by the DMA transmission, so as to obtain the data to be transmitted of the video and the data to be transmitted of the audio.
In detail, for a video data stream, a start position of each line of data can be identified through an axis_tlast signal, and a start position of each frame of video can be identified through an axis_tser signal, and based on the identified position, the video data stream can be sampled and converted into data to be transmitted during the conversion process. For an audio data stream, the data of each channel can be distinguished by an axis_tid signal, and effective data of the channel can be identified by the axis_tdata signal and used for sampling the audio data stream by sampling start point control and converting the audio data stream into audio data to be transmitted.
In some examples, the external computing device may trigger, through the PCIE bus, to collect the video to-be-transmitted data and the audio to-be-transmitted data by using a first trigger signal (Start Writing Trigger) that starts writing, and after the collection is completed, transmit a second trigger signal (Finish Writing Tr igger) that completes writing back through the PCIE bus. In the acquisition process, the acquisition is required to be carried out after the audio and video of the chip to be detected are rendered, so that discrimination failure caused by acquisition of invalid data is avoided.
In step S103, the video data to be transmitted and the audio data to be transmitted are stored in the system memory according to the transmission mode corresponding to the transmission specification.
In the present disclosure, after the video Data to be transmitted and the audio Data to be transmitted are buffered in step S102, the buffered video Data to be transmitted and audio Data to be transmitted may be written into the system memory by DMA, such as Double Data Rate-Synchronous Dynamic Random Access Memory (DDR-SDRAM), based on the control command. For example, the control instructions may include control signals for indicating a start address of the write data and a total amount of the write data, and may include data signals adapted to the DMA data port. The audio and video data can be tested later by reading out the video data and the audio data in the system memory.
In step S104, the video data and the audio data stored in the system memory are read out to perform an audio/video data test according to the set test policy.
In the present disclosure, a computing device may read out video data and audio data stored in a system memory, and form a test instruction based on a preset test policy, and the computing device performs an audio-video data test using the video data and audio data read out from the system memory by executing the test instruction. In some examples, the computing device may be at least one of a smart phone, a smart watch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. For example, after the computing device reads the video data and the audio data stored in the system memory, the hash value may be used to perform verification comparison, and whether the original audio/video data output by the chip to be tested has a bit error is determined according to the comparison result.
According to the technical scheme shown in fig. 1, after the original audio/video data output by the chip to be tested is analyzed to obtain a video data stream and an audio data stream, the video data stream and the audio data stream are converted according to a set transmission format, and the video data to be transmitted and the audio data to be transmitted are stored in a system memory by utilizing a corresponding transmission mode, so that the audio/video data test is performed according to a set test strategy by reading the video data and the audio data stored in the system memory. The chip can store the original data output by the audio and video output interfaces such as HDMI or DP, so as to carry out the audio and video data test subsequently, avoid the limitation of manual comparison test and improve the test accuracy.
For the technical solution shown in fig. 1, in some possible implementations, as shown in fig. 2, the parsing the video data stream and the audio data stream according to the original audio/video data output by the chip to be tested includes:
s201: converting high-speed original audio and video data output by a chip to be tested into lower-speed audio and video data;
s202: and analyzing the video data stream and the audio data stream according to the parameter index representing the audio and video data output capacity of the chip to be tested by the audio and video data with lower speed.
For the above implementation, specifically, since the clock frequency of the chip is inconsistent with the clock frequency in the test environment, after receiving the high-speed original audio/video data, the primary task is to perform clock recovery, so as to ensure synchronization of the lower-speed audio/video data. Then, since the original audio-visual data may include a plurality of parallel channels, each channel transmits serial data, and each channel corresponds to a portion of the data bits. For example, in HDMI, in addition to including clock channels for synchronization, a plurality of (e.g., 3) data channels simultaneously transmit mixed format data of video and audio, and the data of each channel is decoded and recombined into complete lower-speed audio/video data.
For the lower-speed audio/video data obtained by the conversion, parameters representing the audio/video data output capability of the chip to be tested, such as video resolution, video frame rate, audio channel number, audio sampling rate and the like, can be configured to separate audio data from video data of the lower-speed audio/video data, so as to obtain a video data stream and an audio data stream. In some examples, the video data Stream and the audio data Stream conform to the same data format, such as AXI-Stream.
For the technical solution shown in fig. 1, in some possible implementations, converting the video data stream and the audio data stream into video to-be-transmitted data and audio to-be-transmitted data that conform to a set transmission specification, respectively, includes:
converting the video data stream into video data to be transmitted, which accords with the set transmission specification, according to the set first conversion strategy;
and converting the audio data stream into audio data to be transmitted, which accords with the set transmission specification, according to the set second conversion strategy.
For example, taking a data specification meeting the DMA transmission as an example, the above implementation manner converts the video data stream and the audio data stream according to the requirement of adapting the DMA transmission, and finally, the video data to be transmitted and the audio data to be transmitted meeting the DMA transmission specification can be obtained.
In some examples of the foregoing implementation, as shown in fig. 3, the converting the video data stream into the video data to be transmitted according to the set first conversion policy includes:
s301: converting the clock domain of the video data stream to a user clock domain suitable for testing requirements;
s302: converting the data bit width of the video data stream which is converted by the user clock domain into a transmission bit width which accords with the setting;
s303: and caching the video data stream conforming to the set transmission bit width according to the data quantity of single transmission to obtain the data to be transmitted of the video.
For the above example, in particular, in the test environment, the requirement of high-speed transmission is not required, so in order to reduce the requirement on data processing speed in the subsequent test process, the clock domain of the video data stream needs to be converted into the user clock domain suitable for the test requirement first, and it can be understood that the clock frequencies of different video format data are different, and the subsequent test process is performed by converting into the highest frequency clock frequency in the system used in the subsequent test process, so as to facilitate the timing convergence when the on-chip layout and wiring are performed. Taking DMA transfer as an example, after conversion to the user clock domain, there is also a case where the data bit width of the video data stream is inconsistent with the data bit width at the time of DMA transfer. To accommodate the demands of DMA transfers, it is also necessary to translate the data bit width to accommodate the demands of address alignment during DMA transfers. Finally, in the DMA transfer process, there is also a specific requirement for the data amount of a single transfer, so the above example also needs to buffer the video data stream according to the data amount of a single transfer set by the DMA transfer, so as to obtain the data to be transferred of the video, so that the DMA transfer of a single time or multiple times can be effectively completed. It should be noted that, in the above example, the system memory space occupied by the data to be transmitted by the video is as follows:
Data Bits＝Pixel hor ×Pixel ver ×BPC×NUM frame
wherein, pixel hor Representing the horizontal resolution of a video data stream, pixel ver Representing the vertical resolution of the video data stream, BPC represents the number of bits occupied by each color in each pixel, NUM frame Indicating the number of video frames that need to be saved.
In some examples of the foregoing implementation, as shown in fig. 4, the converting the audio data stream into the audio data to be transmitted according to the set second conversion policy includes:
s401: converting the clock domain of the audio data stream to a user clock domain suitable for testing requirements;
s402: dividing the audio data stream subjected to user clock domain conversion into audio component data of a plurality of channels according to the number of channels;
s403: and buffering the audio component data of each channel according to the data quantity of single transmission to obtain the audio to-be-transmitted data of each channel.
In the above example, since the audio data is generally multi-channel data, after the audio data stream is converted into the clock domain, the audio data stream may be separated according to channels, thereby obtaining audio component data of a plurality of channels, each corresponding to one channel. After the audio component data of each channel is obtained, since it is necessary to satisfy the demand for the data amount of the single transfer in the DMA transfer, it is also necessary to buffer the audio component data of each channel in accordance with the data amount of the single transfer set by the DMA transfer. It should be noted that, in the above example, the system memory space occupied by the data to be transmitted is shown in the following formula:
Data Bits＝f sample ×NUM channel ×T sample ×W data
wherein: f (f) sample Sample rate, NUM, representing an audio data stream channel Representing the number of channels of an audio data stream, T sample Representing the duration of audio samples, W data The bit width representing each sample point of the audio data stream.
For the technical solution shown in fig. 1, in some possible implementation manners, storing the video data to be transmitted and the audio data to be transmitted in the system memory according to the transmission manner corresponding to the transmission specification includes:
and writing the cached video to-be-transmitted data and the cached audio to-be-transmitted data into the system memory in a transmission mode corresponding to the transmission specification according to target memory addresses required to be stored by the video to-be-transmitted data and the audio to-be-transmitted data.
For the above implementation manner, taking DMA transfer as an example, after the video data to be transferred and the audio data to be transferred are buffered in the foregoing step S102, the video data to be transferred and the audio data to be transferred may be written into the system memory in a DMA manner based on the data transfer request or the command trigger.
Specifically, it is first determined that video to-be-transmitted data and audio to-be-transmitted data should be stored in a system memory, such as a memory address in a DDR, respectively, then the buffered video to-be-transmitted data and audio to-be-transmitted data are transmitted to an AXI-interconnect through an AXI-MM (AXI Memory Mapped) interface, and the buffered video to-be-transmitted data and audio to-be-transmitted data are decomposed into small data blocks according to the data amount written once through the AXI-interconnect, and the decomposed small data blocks are sequentially written into the DDR. It will be appreciated that after the write to DDR operation is completed, the written video data and audio data may be read from the DDR for testing. Because the content of the video data and the audio data is not changed in the whole process shown in fig. 1, the original information of the data is maintained in the test process, the integrity and the reliability of the data are ensured, and the test accuracy is improved in the process of testing the audio and video data.
Based on the same inventive concept as the previous technical solution, referring to fig. 5, there is shown an apparatus 5 for audio and video data testing, the apparatus 5 comprising: a data analysis unit 51, a data conversion unit 52, a data transmission unit 53, and a system memory 54.
In the apparatus 5 for testing audio/video data shown in fig. 5, the data parsing part 51 is connected to the audio/video output interface 6 of the chip to be tested, and is configured to receive the original audio/video data from the audio/video output interface 6 and parse out the video data stream and the audio data stream;
the data conversion part 52 is connected to the data analysis part 51, and is configured to convert the video data stream and the audio data stream into video data to be transmitted and audio data to be transmitted, which conform to a set transmission specification, respectively;
the data transmission portion 53 is connected to the data conversion portion 52, and is configured to store the video data to be transmitted and the audio data to be transmitted in the system memory 54 according to a transmission mode corresponding to the transmission specification.
For the above-mentioned device 5 for audio/video data testing shown in fig. 5, in some possible implementations, as shown in fig. 6, the data parsing part 51 includes: a physical layer conversion module 511 and an analysis module 512; the physical layer conversion module 511 is connected to the audio/video output interface 6 of the chip to be tested, and is configured to convert high-speed original audio/video data output by the chip to be tested into lower-speed audio/video data; the parsing module 512 is connected to the physical layer conversion module 511, and is configured to parse the audio/video data with a lower speed into a video data stream and an audio data stream according to a parameter index representing the audio/video data output capability of the chip to be tested.
For the above-mentioned device 5 for audio-video data testing shown in fig. 5, in some possible implementations, as shown in fig. 6, the data conversion portion 52 includes a video conversion module 521 for converting a video data stream into video data to be transmitted and an audio conversion module 522 for converting an audio data stream into audio data to be transmitted; accordingly, the data transmission part 53 includes a video transmission module 531, an audio transmission module 532, and a transmission interface 533 connected to the video transmission module 531 and the audio transmission module 532. The video transmission module 531 is connected to the video conversion module 521, and the audio transmission module 532 is connected to the audio conversion module 522.
Based on the above implementation, in some examples, as shown in fig. 7, the video conversion module 521 includes a first clock domain conversion unit 5211, a bit width conversion unit 5212, a video data buffer unit 5213, and a first finite state machine 5214 for video writing; the first clock domain converting unit 5211 is connected to the parsing module 512 of the data parsing unit 51, and is configured to convert the clock domain of the video data stream into a user clock domain suitable for testing requirements; the bit width conversion unit 5212 is connected to the first clock domain conversion unit 5211 and is configured to convert the data bit width of the video data stream subjected to the user clock domain conversion into a transmission bit width according with the set data bit width; the video data buffer unit 5213 is connected to the bit width conversion unit 5212, and is configured to buffer a video data stream according to a set transmission bit width according to a data amount of a single transmission, so as to obtain data to be transmitted of the video; the first finite state machine 5214 is connected to the video data buffer unit 5213, and is configured to trigger the video transmission module 531 to transmit the video data to be transmitted to the data transmission unit 53 according to a data transmission request or an instruction.
Based on the above implementation, in some examples, as shown in fig. 8, the audio conversion module 522 includes a second clock domain conversion unit 5221, a channel dividing unit 5222, a plurality of channel data buffering units 5223, and a second finite state machine 5224 for audio writing; the second clock domain converting unit 5221 is connected to the parsing module 512 of the data parsing unit 51, and is configured to convert the clock domain of the audio data stream into a user clock domain suitable for testing requirements; the channel dividing unit 5222 is connected to the second clock domain converting unit 5221 and is configured to divide the audio data stream subjected to the user clock domain conversion into audio component data of a plurality of channels according to the number of channels; the number of the channel data caching units 5223 is consistent with the number of the channels, each channel data caching unit 5223 corresponds to the audio component data of one channel, and each channel data caching unit is used for caching the audio component data of the corresponding channel according to the data quantity of single transmission to obtain the audio to-be-transmitted data of the corresponding channel; the second finite state machine 5224 is connected to the all-channel data buffering unit 5223, and is configured to trigger the audio transmission module 532 to transmit the audio data to be transmitted to the data transmission portion 53 according to a data transmission request or an instruction.
In combination with the above example, the video transmission module 531 is configured to write the buffered video to-be-transmitted data into the system memory 54 through the transmission interface 533 according to the target memory address where the video to-be-transmitted data needs to be stored in a transmission manner corresponding to the transmission specification.
The audio transmission module 532 is configured to write the buffered audio to-be-transmitted data into the system memory 54 through the transmission interface 533 according to the target memory address where the audio to-be-transmitted data is to be stored in a transmission manner corresponding to the transmission specification.
In some examples, the system memory 54 is a DDR.
Based on the above-mentioned audio and video data testing device 5, see fig. 6, further includes a PCIE bus 55, where the bus 55 is connected to the data parsing unit 51, the data converting unit 52 and the data transmitting unit 53, and the bus 55 is further connected to the aforementioned computing device 3 that executes a preset testing policy to perform audio and video data testing. The bus 55 is used for transmitting the test instruction issued by the computing device 3 to the data analysis part 51, the data conversion part 52 and the data transmission part 53, so as to trigger the data analysis part 51, the data conversion part 52 and the data transmission part 53 to execute the corresponding functions. For example, the computing device 3 triggers the data transmission portion 53 to collect the video data to be transmitted and the audio data to be transmitted of the data conversion portion 52 by using the first trigger signal (Start Writing Trigger) for starting writing through the PCIE bus, and after the collection, the data transmission portion 53 returns the second trigger signal (Finish Writing Trigger) for completing writing through the PCIE bus. In the acquisition process, the acquisition is required to be carried out after the audio and video of the chip to be detected are rendered, so that discrimination failure caused by acquisition of invalid data is avoided.
Based on the same inventive concept as the previous technical solutions, the present disclosure further provides a computer readable storage medium storing at least one instruction for being executed by a processor to implement the method for audio and video data testing according to the above embodiments.
Based on the same inventive concept as the previous technical solutions, the present disclosure further provides a computer program product comprising computer instructions stored in a computer-readable storage medium; the processor of the computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computing device to perform the method of audio-video data testing described in the above embodiments.
It should be noted that: the embodiments described in the present disclosure may be arbitrarily combined without any collision.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for testing audio-video data, the method comprising:
analyzing a video data stream and an audio data stream according to the original audio and video data output by the chip to be tested;
respectively converting the video data stream and the audio data stream into video data to be transmitted and audio data to be transmitted which meet the set transmission specification;
storing the video data to be transmitted and the audio data to be transmitted into a system memory according to a transmission mode corresponding to the transmission specification;
and reading out the video data and the audio data stored in the system memory so as to test the audio and video data according to a set test strategy.
2. The method according to claim 1, wherein the parsing the video data stream and the audio data stream according to the original audio/video data output by the chip to be tested comprises:
converting high-speed original audio and video data output by a chip to be tested into lower-speed audio and video data;
and analyzing the video data stream and the audio data stream according to the parameter index representing the audio and video data output capacity of the chip to be tested by the audio and video data with lower speed.
3. The method of claim 1, wherein converting the video data stream and the audio data stream into video to-be-transmitted data and audio to-be-transmitted data, respectively, that meet a set transmission specification, comprises:
converting the video data stream into video data to be transmitted, which accords with the set transmission specification, according to the set first conversion strategy;
and converting the audio data stream into audio data to be transmitted, which accords with the set transmission specification, according to the set second conversion strategy.
4. A method according to claim 3, wherein said converting the video data stream into video data to be transmitted conforming to a set transmission specification according to a set first conversion policy comprises:
converting the clock domain of the video data stream to a user clock domain suitable for testing requirements;
converting the data bit width of the video data stream which is converted by the user clock domain into a transmission bit width which accords with the setting;
and caching the video data stream conforming to the set transmission bit width according to the data quantity of single transmission to obtain the data to be transmitted of the video.
5. A method according to claim 3, wherein said converting the audio data stream into audio data to be transmitted according to the set transmission specification according to the set second conversion policy comprises:
converting the clock domain of the audio data stream to a user clock domain suitable for testing requirements;
dividing the audio data stream subjected to user clock domain conversion into audio component data of a plurality of channels according to the number of channels;
and buffering the audio component data of each channel according to the data quantity of single transmission to obtain the audio to-be-transmitted data of each channel.
6. The method of claim 1, wherein storing the video data to be transmitted and the audio data to be transmitted in the system memory according to the transmission mode corresponding to the transmission specification comprises:
and writing the cached video to-be-transmitted data and the cached audio to-be-transmitted data into the system memory in a transmission mode corresponding to the transmission specification according to target memory addresses required to be stored by the video to-be-transmitted data and the audio to-be-transmitted data.
7. An apparatus for audio video data testing, the apparatus comprising: a data analysis part, a data conversion part, a data transmission part and a system memory; wherein,
the data analysis part is connected to an audio/video output interface of the chip to be tested and is used for receiving original audio/video data from the audio/video output interface and analyzing video data streams and audio data streams;
the data conversion part is connected to the data analysis part and is used for respectively converting the video data stream and the audio data stream into video data to be transmitted and audio data to be transmitted which meet the set transmission specification;
the data transmission part is connected to the data conversion part and is used for storing the video data to be transmitted and the audio data to be transmitted into the system memory according to the transmission mode corresponding to the transmission specification.
8. The apparatus according to claim 7, wherein the data parsing section includes: a physical layer conversion module and an analysis module; wherein,
the physical layer conversion module is connected to the audio/video output interface of the chip to be tested and is used for converting high-speed original audio/video data output by the chip to be tested into lower-speed audio/video data;
the analysis module is connected to the physical layer conversion module and is used for analyzing the audio and video data with lower speed into a video data stream and an audio data stream according to the parameter index representing the audio and video data output capacity of the chip to be tested.
9. The apparatus according to claim 7, wherein the data converting section includes a video converting module for converting a video data stream into video data to be transmitted and an audio converting module for converting an audio data stream into audio data to be transmitted;
correspondingly, the data transmission part comprises a video transmission module, an audio transmission module and a transmission interface connected with the video transmission module and the audio transmission module, wherein the video transmission module is connected with the video conversion module, and the audio transmission module is connected with the audio conversion module.
10. A computer storage medium storing at least one instruction for execution by a processor to implement the method of audio video data testing of any one of claims 1 to 7.
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