CN117542827A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117542827A
CN117542827A CN202311006889.XA CN202311006889A CN117542827A CN 117542827 A CN117542827 A CN 117542827A CN 202311006889 A CN202311006889 A CN 202311006889A CN 117542827 A CN117542827 A CN 117542827A
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CN
China
Prior art keywords
layer
contact
passivation
metal
over
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CN202311006889.XA
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Chinese (zh)
Inventor
郑家峰
连刚逸
赖佳平
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US18/184,480 external-priority patent/US20240088074A1/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN117542827A publication Critical patent/CN117542827A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Abstract

According to embodiments of the present application, a semiconductor structure and a method of forming the same are provided. A semiconductor structure according to an embodiment of the present disclosure includes a metal feature in a dielectric layer, a passivation structure over the dielectric layer and the metal feature, a contact pad over the passivation structure, and a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad, wherein the metal feature includes a first thickness, wherein the contact pad includes a second thickness that is greater than the first thickness.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present application relate to semiconductor structures and methods of forming the same.
Background
The redistribution layer (RDL) includes at least one metal layer to redistribute input/output (I/O) pads of an Integrated Circuit (IC) chip. Thus, metal features in the RDL layer may be located between the interconnect structure and the solder bumps. Much effort has been devoted to strengthening and protecting the metal components in RDLs from the stresses created at the solder bumps.
Disclosure of Invention
According to one embodiment of the present application, there is provided a semiconductor structure including: a metal component in the dielectric layer; a passivation structure over the dielectric layer and the metal feature; a contact pad over the passivation structure; and a plurality of contact vias extending through the passivation structure and in contact with the metal member and the contact pads, wherein the metal member includes a first thickness, and wherein the contact pads include a second thickness that is greater than the first thickness.
According to another embodiment of the present application, there is provided a semiconductor structure including: a metal component in the dielectric layer; a passivation structure over the dielectric layer and the metal feature; a contact pad over the passivation structure; a plurality of contact vias extending through the passivation structure and in contact with the metal features and the contact pads; a protective layer disposed along sidewalls of the contact pads; the top passivation layer is arranged above the contact pad, the passivation structure and the protection layer; a polymer layer disposed over the top passivation layer; and a conductive post extending through the polymer layer and the top passivation layer to contact the contact pad.
According to yet another embodiment of the present application, there is provided a method for forming a semiconductor structure, comprising: providing a workpiece, the workpiece comprising: a metal feature, and a passivation structure over the metal feature. The method of forming a semiconductor structure further includes: forming a plurality of via openings through the passivation structure to expose the metal features; depositing a seed layer over the workpiece and the plurality of via openings; depositing a first photoresist layer over the seed layer; patterning the first photoresist layer to form a pad opening in the first photoresist layer over the plurality of via openings, wherein the pad opening undercuts the patterned first photoresist layer; depositing a conductive layer over the pad opening and the plurality of via openings; removing the patterned first photoresist layer to form a plurality of contact vias in the plurality of via openings and forming contact pads over the plurality of contact vias in contact with the plurality of contact vias; and forming a protective layer along sidewalls of the contact pads.
Embodiments of the present application relate to thick redistribution layer components.
Drawings
The disclosure is best understood from the following detailed description when read with the accompanying drawing figures. It is noted that the various components are not drawn to scale and are for illustrative purposes only, according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a flow chart of a method for fabricating a semiconductor structure in accordance with aspects of the present disclosure.
Fig. 2-23 are partial cross-sectional views of a workpiece at various stages of manufacture in the method of fig. 1 in accordance with an embodiment of the disclosure.
Fig. 24-27 illustrate alternative semiconductor structures that may be fabricated using the method of fig. 1, in accordance with embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, of the different components used to implement the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In addition, when numerical values or numerical ranges are described by "about," "approximately," etc., the term is intended to encompass numerical values within a reasonable range, taking into account variations inherently occurring during manufacture as understood by one of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer has a thickness of "about 5nm," which may encompass a size range from 4.25nm to 5.75nm, with a manufacturing tolerance of +/-15% known to one of ordinary skill in the art associated with depositing the material layer. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In Integrated Circuit (IC) fabrication, a redistribution layer (RDL) refers to an additional metal layer over the die for moving input/output (I/O) pads of devices in the die to different locations to improve access or connection. In some cases, the IO pads are part of the RDL and extend through the passivation structure between the overlying solder features and the underlying contact vias. The contact via may be located on the top metal layer of the interconnect structure. It has been observed that stresses generated around the solder components may cause defects near or around the vertical stack.
The present disclosure provides a semiconductor structure to prevent or reduce defects or malfunctions around RDL contact features. In one aspect, the RDL contact features of the present disclosure are much thicker than the top metal layer of the interconnect structure to reduce the stress exerted on the underlying contact via and passivation structure. RDL contact features may also include a wider base to distribute stress. In another aspect, the sidewalls of the RDL contact features are lined with a high density protective layer to prevent collapse of the RDL contact features. In yet another aspect, the RDL contact features of the present disclosure are electrically coupled to the top metal layer of the interconnect structure through more than one contact via. Electromigration is still threatening the integrity of the contact vias despite the use of a barrier layer. Additional excess contact vias are necessary to ensure electrical connection. In another aspect, the passivation structure comprises a metal-insulator-metal (MIM) structure. The MIM structure is sandwiched between two passivation layers formed of silicon nitride to provide better protection for the MIM structure.
Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, fig. 1 is a flow chart illustrating a method 100 for fabricating a semiconductor structure according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly described in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described herein may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The method 100 is described below in connection with fig. 2-24, with fig. 2-24 being partial cross-sectional views of a workpiece 200 at various stages of manufacture of the method 100 of fig. 1. Because the workpiece 200 is to be fabricated as a semiconductor structure, the workpiece 200 may be referred to herein as a semiconductor structure 200, depending on the context in which it is desired. Throughout this disclosure, like reference numerals refer to like parts unless otherwise specifically indicated.
Referring to fig. 1 and 2, the method 100 includes a block 102 in which a workpiece 200 is provided. The workpiece 200 includes various layers that have been formed thereon. The workpiece 200 includes a substrate 202, which may be made of silicon (Si) or other semiconductor material such as germanium (Ge) or silicon germanium (SiGe). In some embodiments, the substrate 202 may include a compound semiconductor, such as silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium sulfide (CdS), and/or cadmium telluride (CdTe)); alloy semiconductors such as silicon germanium (SiGe), silicon phosphorus carbide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP); other III-V materials; other group II-V materials; or a combination thereof. Alternatively, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In some embodiments, the substrate 202 may include an epitaxial layer, such as an epitaxial layer overlying a bulk semiconductor substrate. Various microelectronic elements may be formed in the substrate 202 or on the substrate 202, such as transistor elements including source/drain features, gate structures, gate spacers, source/drain contacts, gate contacts, isolation structures including Shallow Trench Isolation (STI), or any other suitable element. The transistors formed on the substrate 202 may include multi-gate devices such as fin field effect transistors (finfets) or multi-bridge channel (MBC) transistors. A FinFET has a raised channel wrapped by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate). MBC transistors have a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. MBC transistors may also be referred to as wrap gate transistors (SGT) or full-loop (GAA) transistors because their gate structure surrounds the channel region. MBC transistors may also be referred to as nanowire transistors, nanoplatelet transistors, or nanorod transistors due to the shape of the channel region.
The workpiece 200 also includes an interconnect structure 210. Interconnect structure 210 may also be referred to as a multi-layer interconnect (MLI) structure and is formed over substrate 202. The interconnect structure 210 may include a plurality of patterned dielectric layers and conductive layers that provide interconnections (e.g., routing) between the various microelectronic elements of the workpiece 200. Although interconnect structure 210 may include eight (8) to sixteen (16) metal layers, its thickness may still be significantly less than the thickness of substrate 202. The plurality of patterned dielectric layers may be referred to as inter-metal dielectric (IMD) layers and may include silicon oxide or a low-k dielectric material having a k value (dielectric constant) less than that of silicon oxide, which is about 4. In some embodiments, the low-k dielectric material includes a porous organosilicate film such as SiOCH, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silica such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass (PSG), fluorine doped silica, carbon doped silica, porous carbon doped silica, silicon carbonitride (SiCN), silicon oxynitride (SiOCN), spin-on silicon based polymer dielectrics, or combinations thereof. The conductive layer in interconnect structure 210 may include contacts, vias, or metal lines.
As shown in fig. 2, the workpiece 200 may include an Etch Stop Layer (ESL) 240 disposed on the interconnect structure 210. The ESL 240 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), or silicon nitride (SiN), or combinations thereof. The workpiece 200 also includes a first dielectric layer 250 disposed on the ESL 240. In some embodiments, the first dielectric layer 250 comprises undoped quartz glass (USG) or silicon oxide. In some embodiments, the thickness of the first dielectric layer 250 is about 800 to about 1000nm.
Still referring to fig. 2, the workpiece 200 includes one or more top metal contacts (such as 253, 254, and 255) in the first dielectric layer 250. Although top metal contact 253, top metal contact 254, and top metal contact 255 are not the top-most contact components in workpiece 200, they are referred to as Top Metal (TM) contacts because they are the top-most metal contacts of interconnect structure 210. Each of top metal contact 253, top metal contact 254, and top metal contact 255 may include a barrier layer 2050 and a metal fill layer. In some embodiments, barrier layer 2050 comprises titanium nitride (TiN), tantalum (Ta), titanium (Ti), tantalum nitride (TaN), a suitable metal nitride, or a combination thereof. In some embodiments, the metal fill layer comprises a metal or metal alloy, such as copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), tungsten (W), ruthenium (Ru), titanium (Ti), or a combination thereof. In the depicted embodiment, top metal contact 253, top metal contact 254, and top metal contact 255 are formed of copper (Cu).
Referring to fig. 1 and 3, the method 100 includes a block 104 in which a second dielectric layer 256 and a first passivation layer 258 are deposited over the top metal contact 253, the top metal contact 254, and the top metal contact 255. In some embodiments, the second dielectric layer 256 is about 65nm to about 85nm thick. The second dielectric layer 256 may include silicon carbonitride (SiCN), silicon nitride (SiN), and/or other suitable materials that may protect the top metal contact 253, the top metal contact 254, and the top metal contact 255 from oxidation. The second dielectric layer 256 may be deposited using Chemical Vapor Deposition (CVD). Further, at block 104, a first passivation layer 258 is deposited over the second dielectric layer 256. The first passivation layer 258 may include silicon nitride and the first passivation layer 258 may be deposited using Plasma Enhanced CVD (PECVD). The gaseous precursor used to form the first passivation layer 258 may include ammonia (NH 3 ) Silane (SiH) 4 ) And nitrogen (N) 2 ). In some embodiments, the first passivation layer 258 may be deposited at a process temperature between about 375 ℃ and about 425 ℃ and a process pressure between about 2.6Torr and about 3.0 Torr. The silicon nitride in the first passivation layer 258 has a greater density and may better protect the overlying MIM structure 260 (described below) from stress-related defects than silicon oxide-containing materials deposited using spin-on or flowable CVD. In some examples, the first passivation layer 258 has a thickness between about 5000nm and about 15000 nm.
Referring to fig. 1 and 4-8, the method 100 includes a block 106 in which a metal-insulator-metal (MIM) structure 260 is formed over the first passivation layer 258 (as shown in fig. 8). As shown in fig. 4-8, forming MIM structure 260 involves a number of processes including those used to form and pattern bottom conductor plate layer 262, middle conductor plate layer 266, and top conductor plate layer 269. Referring first to fig. 4, a patterned bottom conductor plate layer 262 is formed on the first passivation layer 258. The formation of the bottom conductor plate layer 262 itself may involve a number of processes such as deposition,Photolithography, development, and/or etching, etc. The bottom conductor plate layer 262 may be surface treated, such as with nitrous oxide (N) 2 O) sidewall passivation of the gas. Referring now to fig. 5, a first insulator layer 264 is formed on the bottom conductor plate layer 262. In an embodiment, the first insulator layer 264 is deposited to have a substantially uniform thickness over the top surface of the workpiece 200 (e.g., about the same thickness on the top surface and sidewall surfaces of the bottom conductor plate layer 262). Referring next to fig. 6, a patterned intermediate conductor plate layer 266 is formed on the first insulator layer 264. The middle conductor plate layer 266 may be formed in a similar manner to the bottom conductor plate layer 262, but the pattern of the middle conductor plate layer 266 may be different from the pattern of the bottom conductor plate layer 262. Referring now to fig. 7, a second insulator layer 268 is formed over the intermediate conductor plate layer 266. In an embodiment, the second insulator layer 268 is deposited to have a substantially uniform thickness over the top surface of the workpiece 200 (e.g., about the same thickness on the top surface and sidewall surfaces of the intermediate conductor plate layer 266). Referring to fig. 8, a patterned top conductor plate layer 269 is formed over second insulator layer 268. The top conductor plate layer 269 may be formed in a manner similar to the manner in which the middle conductor plate layer 266 or the bottom conductor plate layer 262 is formed, but the pattern of the top conductor plate layer 269 may be different from the pattern of the middle conductor plate layer 266 or the pattern of the bottom conductor plate layer 262.
As shown in fig. 8, MIM structure 260 includes a plurality of metal layers including a bottom conductor plate layer 262, a middle conductor plate layer 266, and a top conductor plate layer 269, which serve as the metal plates of the capacitor. MIM structure 260 also includes a plurality of insulator layers including a first insulator layer 264 disposed between bottom conductor plate layer 262 and middle conductor plate layer 266, and a second insulator layer 268 disposed between middle conductor plate layer 266 and top conductor plate layer 269. MIM structure 260 is used to implement one or more capacitors that may be connected to other electronic components such as transistors. The multi-layer MIM structure 260 allows the capacitor to be tightly sealed together in both the vertical and lateral directions, thereby reducing the amount of lateral space required for implementing the capacitor. As a result, MIM structure 260 may provide an ultra-high density capacitor and may be referred to as a MIM capacitor.
In some embodiments, to increase the capacitance value, the first insulator layer 264 and/or the second insulator layer 268 use a high-k dielectric material having a k value greater than that of silicon oxide. First insulator layer 264 and second insulator layer 268 may be relatively thin to increase the capacitance value but maintain a minimum thickness to avoid potential breakdown of the capacitor in MIM structure 260. Further, to optimize capacitor performance, in some embodiments, the first insulator layer 264 (or the second insulator layer 268) is a three-layer structure including, from bottom to top, a first zirconia (ZrO 2 ) Layer, alumina (Al) 2 O 3 ) Layer and second zirconia (ZrO 2 ) A layer.
Although MIM structure 260 is depicted as including three conductor plates, MIM structure 260 may include additional conductor plates. For example, MIM structure 260 may include four (4), five (5), six (6), or seven (7) conductor plates layers. As with MIM structure 260 described in this disclosure, adjacent conductor plates are spaced apart from each other and insulated from each other by at least one insulator layer.
It should be noted that the methods and structures of the present disclosure are applicable to structures that do not include MIM structure 260. For example, fig. 24 shows a semiconductor structure 200 in which a first passivation layer 258, a MIM structure 260, and a second passivation layer 267 are replaced with passivation layer 259, which may comprise silicon oxide, silicon nitride, or a suitable dielectric material.
Referring to fig. 1 and 9, the method 100 includes a block 108 in which a second passivation layer 267 is deposited over the MIM structure 260. In some embodiments, the second passivation layer 267 can be similar to the first passivation layer 258 in terms of formation process, process conditions, precursors, and thickness. For this reason, a detailed description of the second passivation layer 267 is omitted for brevity. In some embodiments, the deposition of the second passivation layer 267 is followed by a CMP process to provide a planar top surface. As shown in fig. 9, MIM structure 260 is sandwiched between first passivation layer 258 and second passivation layer 267 along the Z-direction. The first passivation layer 258 and the second passivation layer 267 may have the same composition. In some embodiments, the second dielectric layer 256, the first passivation layer 258, the MIM structure 260, and the second passivation layer 267 may be collectively referred to as a first passivation structure 270. The first passivation layer 258 and the second passivation layer 267 protect the MIM structure 260 from damage due to stress or crack propagation.
Referring to fig. 1 and 10, the method 100 includes a block 110 in which a plurality of via openings (such as via opening 271A, via opening 271B, via opening 272A, via opening 272B, via opening 273A, and via opening 273B) are formed to penetrate the second passivation layer 267, MIM structure 260, first passivation layer 258, and second dielectric layer 256 from top to bottom. In some embodiments, shown in fig. 10, two via openings are formed to expose a single top metal contact. For example, via openings 271A and 271B extend through the first passivation structure 270 to expose the top metal contact 253; the via openings 272A and 272B extend through the first passivation structure 270 to expose the top metal contact 254; and via openings 273A and 273B extend through the first passivation structure 270 to expose the top metal contact 255. According to the present disclosure, the via opening 271A and the via opening 271B are a pair of similar locations, the via opening 272A and the via opening 272B are a pair of similar locations, and the via opening 273A and the via opening 273B are a pair of similar locations. In some embodiments, a dry etching process such as Reactive Ion Etching (RIE) is performed to form opening 271, opening 272, and opening 273. Depending on the application, the sidewalls of each opening may expose a different conductor plate layer of MIM structure 260. The plurality of via openings, such as via opening 271A, via opening 271B, via opening 272A, via opening 272B, and via opening 273, may be formed using dry etching, such as Reactive Ion Etching (RIE). In some embodiments, the formation of the plurality of via openings may include the use of oxygen, an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF 4 、SF 6 、NF 3 、BF 3 、CH 2 F 2 、CHF 3 、CH 3 F、C 4 H 8 、C 4 F 6 And/or C 2 F 6 ) Carbon-containing gases (e.g. CO, CH 4 And/or C 3 H 8 ) Chlorine-containing gases (e.g. Cl 2 、CHCl 3 、CCl 4 And/or BCl 3 ) Bromine-containing gas (e.g. HBr and/orCHBr 3 ) Iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.
Referring to fig. 1 and 11, the method 100 includes a block 112 in which a barrier layer 274 and a seed layer 275 are formed over the workpiece 200. In some embodiments, the barrier layer 274 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), tungsten nitride (WN), and the seed layer 275 may include copper (Cu). The barrier 274 prevents or reduces electromigration of copper or oxygen diffusion into the copper. As shown in fig. 11, both the barrier layer 274 and the seed layer 275 may be conformally deposited over the second passivation layer 267 and into the via openings 271A, 271B, 272A, 272B, 273A and 273B using suitable deposition techniques, such as Atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD).
Referring to fig. 1 and 11-14, method 100 includes block 114 in which contact vias are formed in via opening 271A, via opening 271B, via opening 272A, via opening 272B, via opening 273A, and via opening 273B and contact pads 294, 296, and 298 are formed over the via openings. Operations at block 114 may include depositing a first photoresist layer 276 over the workpiece 200 (as shown in fig. 11), patterning the first photoresist layer 276 to form a pad opening defined by the photoresist feature (as shown in fig. 12), depositing a metal fill layer 292 over the via opening and the pad opening (as shown in fig. 13), and removing the photoresist feature (as shown in fig. 14). Referring now to fig. 11, a first photoresist layer 276 may be blanket deposited over the workpiece 200 using spin coating. Referring then to fig. 12, a photolithographic technique is used to pattern the first photoresist layer 276 to form a first photoresist feature 276 (for ease of reference, the same reference numerals are used) that defines a first pad opening 278, a second pad opening 280, and a third pad opening 282. As shown in fig. 12, the first pad opening 278 is in fluid communication with the via opening 271A and the via opening 271B, which exposes the top metal contact 253. The second pad opening 280 is in fluid communication with the via opening 272A and the via opening 272B, which exposes the top metal contact 254. The third pad opening 282 is in fluid communication with the via opening 273A and the via opening 273B, which exposes the top metal contact 255.
To form a contact pad having a wider base portion to prevent stress induced damage, each of the first pad opening 278, the second pad opening 280, and the third pad opening 282 undercut the first photoresist feature 276. In one example process, the first photoresist layer 276 shown in fig. 11 is a negative photoresist. During exposure, an upper portion of the first photoresist layer 276 is more strongly irradiated and has a higher degree of cross-linking, while a lower portion of the first photoresist layer 276 is less irradiated and has a lower degree of cross-linking. During subsequent development, the developer removes the lower portion more quickly to form the undercut 290 shown in fig. 12. Other arrangements are possible and first photoresist layer 276 may be a positive photoresist in other arrangements.
Reference is then made to fig. 13. After forming the undercut 290, a metal fill layer 292 is deposited on the seed layer 275 using a suitable deposition technique such as electroplating. The metal fill layer 292 may include copper (Cu), aluminum (Al), or an alloy thereof. In the depicted embodiment, the metal fill layer 292 is formed of copper (Cu). As shown in fig. 13, the metal filling layer 292 is allowed to fill the via openings 271A, 271B, 272A, 272B, 273A and 273B and the first, second and third pad openings 278, 280 and 282. After depositing the metal fill layer 292, the workpiece 200 is planarized to remove the excess metal fill layer 292 and provide a planar top surface. The metal fill layer 292 also fills the undercut 290.
Referring to fig. 14, the first photoresist component 276 is then selectively removed to form a first contact pad 294, a second contact pad 296, and a third contact pad 298. In addition, a first contact via 2942 and a second contact via 2944 are formed below the first contact pad 294 and in contact with the first contact pad 294; third contact via 2962 and fourth contact via 2964 are formed under second contact pad 296 and in contact with second contact pad 296; and fifth and sixth contact vias 2982 and 2984 are formed under the third contact pad 298 and in contact with the third contact pad 298. Because each contact pad and the underlying plurality of contact vias are formed in the same metal fill deposition process, they are a continuous structure as shown in fig. 13. Each of the first, second and third contact pads 294, 296 and 298 has a wider base portion in the X direction due to the formation of the undercut 290 shown in fig. 12. In some embodiments, shown in fig. 14, removing the photoresist features may also remove the seed layer 275 between adjacent pad features, leaving a barrier layer 274.
Referring to fig. 1 and 15, the method 100 includes a block 116 in which forming a protective layer 300 over the workpiece 200 includes forming the protective layer 300 over the contact pads and the barrier layer 274. In the embodiment shown in fig. 15, the protective layer 300 may comprise silicon nitride and may be conformally deposited over the workpiece 200 using PECVD, including over the top surfaces and sidewalls of the contact pads and over the barrier layer 274. Although the first passivation layer 258, the second passivation layer 267 and the protective layer 300 each include silicon nitride and are formed using PECVD, the density of the protective layer 300 is greater than that in the first passivation layer 258 and the second passivation layer 267. To achieve a higher density of the protective layer 300, higher Radio Frequency (RF) power is applied during deposition of the protective layer 300. In some cases, the RF power used to deposit protective layer 300 is about 1.4 times to about 1.6 times the RF power used to deposit first passivation layer 258 and second passivation layer 267. For example, when the RF power used to deposit the first passivation layer 258 and the second passivation layer 267 is between about 80W and about 100W, the RF power used to deposit the protective layer 300 is between about 100W and about 160W. In addition, in order to achieve a greater density, a gaseous precursor for forming the protective layer 300 (which may include ammonia (NH 3 ) Silane (SiH) 4 ) And nitrogen (N) 2 ) The flow rate may be 3% to about 10% greater than the flow rate used to deposit the first passivation layer 258 and the second passivation layer 267. In some embodiments, protective layer 300 may be deposited at a process temperature between about 375 ℃ and about 425 ℃ and at a process pressure between about 2.6Torr and about 3.0 Torr. In some examples, protective layer 300 has a thickness between about 2nm and about 2000 nm. In some casesIn case, the density of the protective layer 300 is about 2.5 times to about 5 times the density of the first passivation layer 258 and the second passivation layer 267. In other words, the ratio of the density of the protective layer 300 to the densities of the first passivation layer 258 and the second passivation layer 267 may be between about 2.5 and about 5. It is observed that the dense protective layer 300 may apply compressive stress to the contact pads, thereby preventing them from collapsing under pressure from the solder part above.
Referring to fig. 1 and 16, the method 100 includes a block 118 in which an etch back is performed. As shown in fig. 16, the etch back may remove the protective layer 300 deposited on top facing surfaces, such as the top surfaces of the contact pads (including the first contact pad 294, the second contact pad 296, and the third contact pad 298) and the top surface of the barrier layer 274, thereby forming the sidewall protective layer 302. In some alternative embodiments, shown in fig. 25, the protective layer 300 deposited on the top surface of the contact pad is only thinned but not completely removed. In those alternative embodiments, the sidewall protection layer 302 extends over the top surface of the contact pad.
As also shown in fig. 16, the sidewalls of the contact pads (including the first, second, and third contact pads 294, 296, 298) are protected with a protective layer 300, and an etch back may be performed to remove the barrier layer 274 between the contact pads. The barrier 274 is formed of a conductive material and may result in a short circuit or undesired electrical connection. The etch back at block 118 removes or at least breaks the barrier 274 between the contact pads to prevent shorting or undesired electrical connection.
Because both the barrier layer 274 and the protective layer 300 may include nitride (e.g., the barrier layer 274 may include tantalum nitride and the protective layer 300 may include silicon nitride), the etch back at block 118 may include a chemistry that is selective to metal nitride and silicon nitride. In some embodiments, the etch back at block 118 may include using nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) Fluorine-containing gas (e.g. CF 4 、SF 6 、NF 3 、BF 3 、CH 2 F 2 、CHF 3 、CH 3 F、C 4 H 8 、C 4 F 6 And/or C 2 F 6 ) Carbon-containing gases (e.g. CO, CH 4 And/or C 3 H 8 ) Chlorine-containing gases (e.g. Cl 2 、CHCl 3 、CCl 4 And/or BCl 3 ) Bromine-containing gases (e.g. HBr and/or CHBr 3 ) A dry etching process, an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.
Referring to fig. 1, 17 and 18, the method 100 includes a block 120 in which a second passivation structure 315 is formed over the workpiece 200. In some embodiments, the second passivation structure 315 includes a third passivation layer 312 and a polymer layer 314. In some embodiments, the third passivation layer 312 comprises silicon nitride (SiN), which may be formed by CVD, PECVD, or a suitable method. In some embodiments, the third passivation layer 312 may be formed to a thickness between about 25nm and about 200 nm. A polymer layer 314 is then formed over the third passivation layer 312. In some embodiments, the polymer layer 314 may include polyimide and may be deposited using spin coating. As shown in fig. 17, forming the third passivation layer 312 over the workpiece 200 includes forming the third passivation layer 312 over the sidewall protection layer 302, the contact pads (including the first contact pad 294, the second contact pad 296, and the third contact pad 298), and the second passivation layer 267. In the embodiment shown in fig. 18, the third passivation layer 312 is in contact with the second passivation layer 267, the sidewall of the barrier layer 274, the sidewall of the seed layer 275, the sidewall protection layer 302, and is disposed along the sidewalls of the upper contact pads and the top surfaces of the contact pads (including the first contact pad 294, the second contact pad 296, and the third contact pad 298).
In some embodiments, the third passivation layer 312 may be similar to the first passivation layer 258 in terms of formation process, process conditions, precursors, and thickness. In some examples, the density of the protective layer 300 is about 2.5 times to about 5 times the density of the third passivation layer 312. In other words, the ratio of the density of the protective layer 300 to the density of the third passivation layer 312 may be between about 2.5 and about 5.
Referring to fig. 1 and 19-23, method 100 includes block 122 where bump features are formed over contact pads. Operations at block 122 may include forming a pad via opening through the second passivation structure 315 (as shown in fig. 19), depositing a barrier layer 322 and a seed layer 323 (as shown in fig. 20), forming a patterned second photoresist layer 324 (as shown in fig. 21), forming copper pillars and solder features (as shown in fig. 22), performing an etch back to remove unwanted portions of the barrier layer 322 and the seed layer 323 (as shown in fig. 23), and reflowing the features (as shown in fig. 23).
Referring to fig. 19, pad channel openings 316, 318, and 320 are formed through the second passivation structure 315 to expose the first, second, and third contact pads 294, 296, and 298, respectively. In some embodiments, a dry etching process may be performed to etch through the polymer layer 314 and the third passivation layer 312. An example dry etching process may include using hydrogen (H 2 ) Fluorine-containing gas (e.g. CF 4 、SF 6 、NF 3 、BF 3 、CH 2 F 2 、CHF 3 、CH 3 F、C 4 H 8 、C 4 F 6 And/or C 2 F 6 ) Carbon-containing gases (e.g. CO, CH 4 And/or C 3 H 8 ) Chlorine-containing gases (e.g. Cl 2 、CHCl 3 、CCl 4 And/or BCl 3 ) Bromine-containing gases (e.g. HBr and/or CHBr 3 ) Iodine-containing gas. As shown in fig. 19, because the etch rate of the polymer layer 314 is greater than the etch rate of the third passivation layer 312, each of the pad channel opening 316, the pad channel opening 318, and the pad channel opening 320 has a wider opening in the polymer layer 314 and a narrower opening in the third passivation layer 312.
Referring to fig. 20, the barrier layer 322 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), tungsten nitride (WN), and the seed layer 323 may include copper (Cu). The barrier layer 322 prevents or reduces electromigration of copper or oxygen diffusion into copper. As shown in fig. 20, both the barrier layer 322 and the seed layer 323 may be conformally deposited over the pad channel opening 316, the pad channel opening 318, and the pad channel opening 320, including on the exposed portions of the first contact pad 294, the second contact pad 296, and the third contact pad 298. Barrier layer 322 and seed layer 323 may be deposited using a suitable deposition technique, such as Atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD).
Referring to fig. 21, a patterned second photoresist layer 324 is formed over the workpiece 200 to define the boundaries of the copper pillars and solder features to be formed. In an example process, a second photoresist layer is blanket deposited over the workpiece 200 using spin coating. As shown in fig. 21, the second photoresist layer 324 is patterned using a photolithographic technique to form photoresist features around the pad channel openings 316, 318, and 320.
Referring to fig. 22, copper pillars 326, 328, and 330, and solder members 334, 336, and 338 are formed over the pad channel openings while being limited by patterned photoresist layer 324. In some embodiments, copper pillars 326, 328, and 330 may include copper (Cu), cobalt (Co), nickel (Ni), or combinations thereof, and may be deposited on exposed seed layer 323 using electroplating. After depositing copper pillars 326, 328, and 330, solder members 334, 336, and 338 are deposited over each of copper pillars 326, 328, and 330, respectively. In some embodiments, after the deposition of solder feature 334, solder feature 336, and solder feature 338, the top surface of patterned second photoresist layer 324 remains higher than the top surfaces of solder feature 334, solder feature 336, and solder feature 338. I.e., the patterned second photoresist layer 324 still separates the copper pillars 326, 328, and 330, and the solder members 334, 336, and 338 deposited thereon. In some embodiments, solder member 334, solder member 336, and solder member 338 may include nickel (Ni), tin (Sn), tin-lead (SnPb), gold (Au), silver (Ag), palladium (Pd), indium (In), nickel-palladium-gold (NiPdAu), nickel-gold (NiAu), snAg, snPb, snAgCu, or other suitable metal alloys. After depositing copper pillars 326, 328, and 330, and solder members 334, 336, and 338, patterned second photoresist layer 324 is removed by a request or selective etch.
Referring to FIG. 23, in order to remove the excess barrier layer 322 and seed layer 323 electrically coupling the copper pillars 326, 328 and 330, an etch back is performed on the workpiece 200. In some embodiments, the etch back at block 122 may include using nitrogen (N 2 ) Oxygen (O) 2 ) Hydrogen (H) 2 ) Fluorine-containing gas (e.g. CF 4 、SF 6 、NF 3 、BF 3 、CH 2 F 2 、CHF 3 、CH 3 F、C 4 H 8 、C 4 F 6 And/or C 2 F 6 ) Carbon-containing gases (e.g. CO, CH 4 And/or C 3 H 8 ) Chlorine-containing gases (e.g. Cl 2 、CHCl 3 、CCl 4 And/or BCl 3 ) Bromine-containing gases (e.g. HBr and/or CHBr 3 ) A dry etching process, an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. After the etch back, the solder member 334, the solder member 336, and the solder member 338 are reflowed to form a bump-like shape.
Still referring to fig. 23. It is observed that the contact pads must be thicker than the top metal contacts to prevent damage to MIM structure 260 and the top metal contacts. In the depicted embodiment, along the Z-direction, top metal contact 253, top metal contact 254, and top metal contact 255 have a first thickness T1 and contact pad 294, contact pad 296, and contact pad 298 have a second thickness T2. The second thickness T2 is between about 5 times and about 10 times the first thickness T1. This range is not trivial. It has been observed that MIM structure 260 and/or the top metal contact are susceptible to damage caused by stress at the solder part when the second thickness T2 is less than 5 times the first thickness T1. When the second thickness T2 is greater than 10 times the first thickness T1, the additional thickness no longer contributes to the stress distribution function of the contact pad. To provide sufficient space for forming a package or underfill, copper pillars 326, 328, and 330 tend to have a third thickness T3 that is greater than second thickness T2. As shown in fig. 24, the third thickness T3 of the copper pillars 326, 328, and 330 is measured from the bottom surface of each copper pillar to the top surface thereof. In some embodiments, the third thickness T3 is about 1.5 times to about 4 times the second thickness T2.
Fig. 24 illustrates an alternative embodiment in which semiconductor structure 200 does not include MIM structure 260. As shown in fig. 24, the first passivation layer 258, the MIM structure 260, and the second passivation layer 267 are replaced with the passivation layer 259. Passivation layer 259 may include silicon oxide or silicon nitride. In one embodiment, passivation layer 259 comprises silicon oxide.
Fig. 25 shows an alternative embodiment in which a portion of the sidewall protection layer 302 extends to the top surfaces of the contact pads 294, 296 and 298. Compared to the semiconductor structure 200 shown in fig. 23, the sidewall protection layer 302 in fig. 25 is subjected to a less aggressive etch back process such that portions of the sidewall protection layer 302 extend continuously over the top surfaces of the contact pads 294, 296 and 298. Due to the nature of the etch back process, the portion of the sidewall protection layer 302 above the top surface is thinner than the portion of the sidewall protection layer 302 extending along the sidewalls of the contact pad 294, and the contact pad 298.
Fig. 26 shows another alternative embodiment, wherein the sidewall protection layer comprises a multi-layer sidewall protection layer 304. In the depicted embodiment, the multi-layer sidewall protection layer 304 includes an inner layer 306 and an outer layer 308. Both the inner layer 306 and the outer layer 308 are similar to the protective layer 300 in terms of deposition process and density. The outer layer 308 covers the top surface of the inner layer 306. Neither the inner layer 306 nor the outer layer 308 extends above the top surfaces of the contact pads 294, 296, and 298. In an example process, a dielectric layer for the inner layer 306 is conformally deposited over the contact pads 294, 296, and 298, and subjected to an etch back process similar to the operations at block 118 described above to remove the inner layer 306 over the top surfaces of the contact pads. After the etch back of the inner layer, a dielectric layer for the outer layer 308 is conformally deposited over the contact pads 294, 296 and 298 and subjected to an etch back process similar to the operations at block 118 described above. Because the barrier 274 and seed 275 layers between the contact pads have been removed during the etch back of the inner layer 306, the etch back of the outer layer 308 may be less aggressive, leaving the top surfaces of the contact pads covered by the outer layer 308. Thus, the top surface 308T of the outer layer 308 is higher than the top surface 306T of the inner layer 306. Further, the top surface of the inner layer 306 resulting from the etch back process is now covered by the outer layer 308.
Fig. 27 shows yet another alternative embodiment, wherein the sidewall protection layer comprises a multi-layer sidewall protection layer 304. In the depicted embodiment, the multi-layer sidewall protection layer 304 includes an inner layer 306 and an outer layer 308. Both the inner layer 306 and the outer layer 308 are similar to the protective layer 300 in terms of deposition process and density. The outer layer 308 covers the top surface of the inner layer 306 and portions of the outer layer 308 remain disposed over the top surfaces of the contact pads 294, 296, and 298. In an example process, the dielectric layer for the inner layer 306 is conformally deposited over the contact pads 294, 296, and 298 using a process similar to that described at block 116 of the method 100, and subjected to an etch back process similar to that of block 118 of the method 100 to remove the inner layer 306 over the top surfaces of the contact pads. After the etch back of the inner layer 306, a dielectric layer for the outer layer 308 is conformally deposited over the contact pads 294, 296, and 298 and subjected to an etch back process similar to the operations at block 118 described above. Because the barrier 274 and seed 275 layers between the contact pads have been removed during the etch back of the inner layer 306, the etch back of the outer layer 308 may be less aggressive, leaving the top surfaces of the contact pads covered by the outer layer 308. Thus, the top surface 308T of the outer layer 308 is higher than the top surface 306T of the inner layer 306. In addition, the top surface of the inner layer 306 resulting from the etch back process is now covered by the outer layer 308.
One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a metal feature in a dielectric layer, a passivation structure over the dielectric layer and the metal feature, a contact pad over the passivation structure, and a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad. The metal component includes a first thickness and the contact pad includes a second thickness that is greater than the first thickness.
In some embodiments, the passivation structure includes a first passivation layer, a metal-insulator-metal (MIM) capacitor disposed over and in contact with the first passivation layer, and a second passivation layer disposed over and in contact with the MIM capacitor. In some embodiments, the MIM capacitor comprises a plurality of conductive plates interleaved by a plurality of insulator layers, and a plurality of contact vias extend through at least one of the plurality of conductive plates. In some cases, the first passivation layer and the second passivation layer comprise silicon nitride. In some embodiments, the semiconductor structure further includes a protective layer disposed along sidewalls of the contact pads. The protective layer includes an inner layer disposed on the sidewalls of the contact pads and an outer layer disposed on the inner layer. The outer layer is in contact with the inner layer and the sidewalls of the contact pads. In some embodiments, the uppermost surface of the outer layer is higher than the uppermost surface of the inner layer. In some embodiments, the inner and outer layers comprise silicon nitride. In some embodiments, the ratio of the second thickness to the first thickness is between about 5 and about 10.
Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a metal feature in a dielectric layer, a passivation structure over the dielectric layer and the metal feature, a contact pad over the passivation structure, a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad, a protective layer disposed along sidewalls of the contact pad, a top passivation layer disposed over the contact pad, the passivation structure and the protective layer, a polymer layer disposed over the top passivation layer, and a conductive post extending through the polymer layer and the top passivation layer to contact the contact pad.
In some embodiments, the top passivation layer and the protective layer comprise silicon nitride, the top passivation layer having a first density, and the protective layer having a second density greater than the first density. In some embodiments, the ratio of the second density to the first density is between about 2.5 and about 5. In some embodiments, the top passivation layer has a thickness between about 5 μm and about 15 μm, and the protective layer has a thickness between about 2nm and about 2000 nm. In some cases, the passivation structure includes a first passivation layer, a metal-insulator-metal (MIM) capacitor disposed over and in contact with the first passivation layer, and a second passivation layer disposed over and in contact with the MIM capacitor. In some embodiments, the first passivation layer, the second passivation layer, and the protective layer comprise silicon nitride, the first passivation layer and the second passivation layer have a first density, and the protective layer has a second density greater than the first density. In some embodiments, the ratio of the second density to the first density is between about 2.5 and about 5.
Yet another aspect of the disclosure relates to a method. The method includes providing a workpiece including a metal feature and a passivation structure over the metal feature, forming a plurality of via openings through the passivation structure to expose the metal feature, depositing a seed layer over the workpiece and the plurality of via openings, depositing a first photoresist layer over the seed layer, patterning the first photoresist layer to form a pad opening in the first photoresist layer over the plurality of via openings to undercut the patterned first photoresist layer, depositing a conductive layer over the pad opening and the plurality of via openings, removing the patterned first photoresist layer to form a plurality of contact vias in the plurality of vias, and forming a protective layer over the plurality of contact vias in contact with the plurality of contact vias, and along sidewalls of the contact pads.
In some embodiments, the method further includes depositing a barrier layer over the workpiece and the plurality of via openings, and depositing a seed layer over the barrier layer, prior to depositing the first photoresist layer. In some embodiments, forming the protective layer includes depositing an inner protective layer over the contact pad, etching back the deposited inner protective layer, depositing an outer protective layer over the inner protective layer after etching back the deposited inner protective layer, and etching back the deposited outer protective layer. In some embodiments, the inner and outer protective layers comprise silicon nitride. In some embodiments, the passivation structure includes a first passivation layer, a metal-insulator-metal (MIM) capacitor disposed over and in contact with the first passivation layer, and a second passivation layer disposed over and in contact with the MIM capacitor. The first passivation layer, the second passivation layer and the protective layer comprise silicon nitride. The first passivation layer and the second passivation layer have a first density, and the protective layer has a second density greater than the first density.
According to yet another embodiment of the present application, there is provided a method for forming a semiconductor structure, comprising: providing a workpiece, the workpiece comprising: a metal feature, and a passivation structure over the metal feature. The method of forming a semiconductor structure further includes: forming a plurality of via openings through the passivation structure to expose the metal features; depositing a seed layer over the workpiece and the plurality of via openings; depositing a first photoresist layer over the seed layer; patterning the first photoresist layer to form a pad opening in the first photoresist layer over the plurality of via openings, wherein the pad opening undercuts the patterned first photoresist layer; depositing a conductive layer over the pad opening and the plurality of via openings; removing the patterned first photoresist layer to form a plurality of contact vias in the plurality of via openings and forming contact pads over the plurality of contact vias in contact with the plurality of contact vias; and forming a protective layer along sidewalls of the contact pads.
In some embodiments, the method for forming a semiconductor structure further comprises: depositing a barrier layer over the workpiece and the plurality of via openings prior to depositing the first photoresist layer; and depositing a seed layer over the barrier layer.
In some embodiments, wherein forming the protective layer comprises: depositing an inner protective layer over the contact pads; etching back the deposited inner protection layer; depositing an outer protective layer over the inner protective layer after etching back of the deposited inner protective layer; and etching back the deposited outer protective layer.
In some embodiments, wherein the inner and outer protective layers comprise silicon nitride.
In some embodiments, wherein the passivation structure comprises: a first passivation layer, a metal-insulator-metal capacitor disposed over and in contact with the first passivation layer, and a second passivation layer disposed over and in contact with the metal-insulator-metal capacitor, and wherein the first passivation layer, the second passivation layer, and the protective layer comprise silicon nitride, wherein the first passivation layer and the second passivation layer have a first density, wherein the protective layer has a second density greater than the first density.
The foregoing disclosure outlines components of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a metal component in the dielectric layer;
a passivation structure over the dielectric layer and the metal feature;
a contact pad over the passivation structure; and
a plurality of contact vias extending through the passivation structure and contacting the metal member and the contact pads,
wherein the metal part comprises a first thickness,
wherein the contact pad includes a second thickness that is greater than the first thickness.
2. The semiconductor structure of claim 1, wherein the passivation structure comprises:
a first passivation layer;
a metal-insulator-metal capacitor disposed over and in contact with the first passivation layer; and
a second passivation layer disposed over and in contact with the metal-insulator-metal capacitor.
3. The semiconductor structure of claim 1,
wherein the metal-insulator-metal capacitor comprises a plurality of conductive plates interleaved by a plurality of insulator layers,
wherein the plurality of contact vias extend through at least one of the plurality of conductive plates.
4. The semiconductor structure of claim 2, wherein the first passivation layer and the second passivation layer comprise silicon nitride.
5. The semiconductor structure of claim 1, further comprising:
and a protective layer disposed along a sidewall of the contact pad, wherein the protective layer comprises:
an inner layer disposed on the side wall of the contact pad, an
And an outer layer disposed on the inner layer, wherein the outer layer is in contact with the inner layer and the sidewalls of the contact pads.
6. The semiconductor structure of claim 5, wherein a highest surface of the outer layer is higher than a highest surface of the inner layer.
7. The semiconductor structure of claim 5, wherein the inner layer and the outer layer comprise silicon nitride.
8. The semiconductor structure of claim 1, wherein a ratio of the second thickness to the first thickness is between about 5 and about 10.
9. A semiconductor structure, comprising:
a metal component in the dielectric layer;
a passivation structure over the dielectric layer and the metal feature;
a contact pad over the passivation structure;
a plurality of contact vias extending through the passivation structure and in contact with the metal features and the contact pads;
a protective layer disposed along a sidewall of the contact pad;
a top passivation layer disposed over the contact pad, the passivation structure, and the protective layer;
A polymer layer disposed over the top passivation layer; and
a conductive post extends through the polymer layer and the top passivation layer to contact the contact pad.
10. A method for forming a semiconductor structure, comprising:
providing a workpiece, the workpiece comprising:
metal component
A passivation structure over the metal feature;
forming a plurality of via openings through the passivation structure to expose the metal feature;
depositing a seed layer over the workpiece and the plurality of via openings;
depositing a first photoresist layer over the seed layer;
patterning the first photoresist layer to form a pad opening in the first photoresist layer over the plurality of via openings, wherein the pad opening undercuts the patterned first photoresist layer; depositing a conductive layer over the pad opening and the plurality of via openings;
removing the patterned first photoresist layer to form a plurality of contact vias in the plurality of via openings and to form contact pads over the plurality of contact vias in contact with the plurality of contact vias; and
and forming a protective layer along the side wall of the contact pad.
CN202311006889.XA 2022-09-09 2023-08-10 Semiconductor structure and forming method thereof Pending CN117542827A (en)

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US63/405,105 2022-09-09
US18/184,480 2023-03-15
US18/184,480 US20240088074A1 (en) 2022-09-09 2023-03-15 Thick redistribution layer features

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