CN117539826B - JTAG-based satellite-borne SRAM type FPGA loading configuration system - Google Patents
JTAG-based satellite-borne SRAM type FPGA loading configuration system Download PDFInfo
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Abstract
The invention discloses a satellite-borne SRAM type FPGA loading configuration system based on JTAG, which comprises an anti-fuse FPGA and a plurality of SRAM type FPGAs; the JTAG interface of the SRAM type FPGA is connected in a daisy chain through a first bus isolation driving chip; the JTAG interface of the anti-fuse FPGA is connected in a daisy chain through a second bus isolation driving chip, and the first bus isolation driving chip is connected with the second bus isolation driving chip; the SRAM type FPGA directly reads configuration software through a SelectMAP interface by default to carry out loading configuration and readback refreshing; or transmitting configuration software to the JTAG interface of the SRAM type FPGA through the JTAG interface of the antifuse type FPGA, and using the JTAG interface of the SRAM type FPGA as a redundant loading configuration mode.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a satellite-borne SRAM type FPGA loading configuration system based on JTAG.
Background
The SRAM type FPGA has wide application in satellite electronic equipment, and can realize various functions such as data interface, signal conditioning, data processing and the like. The requirements on the functional performance, the working mode and the like of the electronic equipment are higher and higher due to the improvement of the complexity of the satellite task at present, and the satellite-borne SRAM type FPGA is generally required to have an on-track reconstruction function. In order to cope with the influence of space single event effect, an anti-fuse FPGA or a special read-back refreshing circuit is matched with erasable programmable memories such as EEPROM, FLASH and the like, and the SRAM type FPGA is loaded, configured and read-back refreshed through a SelectMAP interface, and the on-track reconstruction function is realized.
The memory capacity of EEPROM, FLASH and the like for storing SRAM type FPGA software configuration items in the current on-orbit application is relatively small, if a plurality of software configuration items need to be stored, a plurality of memories need to be used, and the cost is high. In order to ensure the reliability of on-track reconstruction, multiple verification and validation of the uploading software data are generally required in the software uploading process, so that the speed of writing into a memory is slower.
The SRAM type FPGA is provided with a JTAG interface, a JTAG interface circuit is reserved on a circuit board generally, and in the development process of the satellite-borne electronic equipment, the SRAM type FPGA can be conveniently debugged through the JTAG interface before the single machine is covered, but after the single machine is covered, configuration software of the SRAM type FPGA can be changed only through uploading software, the process is complex, and the efficiency is low.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a satellite-borne SRAM type FPGA loading configuration method based on JTAG, which can improve the on-orbit reconstruction flexibility of the satellite-borne SRAM type FPGA, increase the loading configuration mode of the satellite-borne SRAM type FPGA on the premise of not reducing the reliability of the system, adapt to the storage and quick loading requirements of multiple configuration items and improve the debugging convenience of electronic equipment after closing the cover.
In order to achieve the technical purpose, the invention provides the following technical scheme: JTAG-based satellite-borne SRAM type FPGA loading configuration system comprises:
an antifuse FPGA and a plurality of SRAM type FPGAs;
The JTAG interface of the SRAM type FPGA is connected in a daisy chain through a first bus isolation driving chip; the JTAG interface of the anti-fuse FPGA is connected in a daisy chain through a second bus isolation driving chip, and the first bus isolation driving chip is connected with the second bus isolation driving chip;
the SRAM type FPGA directly reads configuration software through a SelectMAP interface by default to carry out loading configuration and readback refreshing; or transmitting configuration software to the JTAG interface of the SRAM type FPGA through the JTAG interface of the antifuse type FPGA, and using the JTAG interface of the SRAM type FPGA as a redundant loading configuration mode.
Optionally, the anti-fuse FPGA is further in communication with a telemetry and remote control platform through a bus transceiver, wherein data interaction between the anti-fuse FPGA and the telemetry and remote control platform is performed through the bus transceiver, and uploading software data is transmitted to the anti-fuse FPGA, wherein the telemetry and remote control platform comprises a star computer and ground detection equipment.
Optionally, the anti-fuse FPGA includes a measurement and control management module, where the measurement and control management module communicates with the telemetry and remote control platform, and receives a remote control instruction of the satellite computer or the ground detection device through the measurement and control management module to perform telemetry and remote control management on the anti-fuse FPGA.
Optionally, the anti-fuse FPGA comprises a mode selection module, an upper stream data analysis module, a cache read-write control module and a JTAG control module;
The system comprises a bus transceiver, a mode selection module, an upper data analysis module, a cache read-write control module and a JTAG control module, wherein the bus transceiver, the mode selection module, the upper data analysis module, the cache read-write control module and the JTAG control module are sequentially connected, the JTAG control module is connected with the mode selection module, and the cache read-write control module is connected with a memory;
The mode selection module is used for selecting a direct mode and an autonomous control mode according to a telemetry and remote control instruction;
In a through mode, the JTAG control module is used as a data connection path to transmit interaction data of the bus transceiver, and the interaction data is directly transmitted to a JTAG interface of the SRAM type FPGA through a JTAG interface of the antifuse type FPGA, so that direct interaction and control of the telemetry and remote control platform on the SRAM type FPGA are realized;
in the autonomous control mode, the data analysis is carried out on the uploading software data transmitted by the bus transceiver through the uploading data analysis module, and the analyzed data is stored into the memory through the cache read-write control module; when loading configuration, the buffer read-write control module is controlled by the JTAG control module to read configuration software from the memory, the configuration software is processed according to JTAG protocol, the configuration software is transmitted to the JTAG interface of the SRAM type FPGA through the JTAG interface of the antifuse type FPGA, and the configuration software is written into the configuration area of the SRAM type FPGA, so that the loading configuration of the SRAM type FPGA is realized.
Optionally, the antifuse FPGA includes a working state monitoring module, where the working state monitoring module is connected to the SRAM type FPGA, monitors an operation state of the SRAM type FPGA after loading and configuring the SRAM type FPGA through the working state monitoring module, and determines whether to need to reload the SRAM type FPGA according to working state information returned by the SRAM type FPGA.
Optionally, the JTAG interface includes a TCK interface, a TMS interface, a TDI interface, and a TDO interface, where the TCK interface, the TMS interface, the TDI interface, and the TDO interface are respectively configured to transmit a TCK signal, a TMS signal, a TDI signal, and a TDO signal;
the first bus isolation driving chip is connected with the second bus isolation driving chip through TCK signals, TMS signals, TDI signals and TDO signals.
Optionally, an automatic bypass circuit is connected to the TDI signal and TDO connection line between the second bus isolation driving chip and the first bus isolation driving chip, and the automatic bypass circuit is used for performing anomaly detection on the SRAM type FPGA unit, and when anomalies occur, the TDI pin and the TDO pin are automatically shorted.
Optionally, the automatic bypass circuit includes: the grid electrode of the PMOS tube is connected to the POWERGOOD signal of the power supply DCDC chip of the SRAM type FPGA unit, the source electrode of the PMOS tube is connected to the connecting line of the first TDI signal, the drain electrode of the PMOS tube is connected to the connecting line of the first TDO signal, and when the POWERGOOD signal of the power supply DCDC chip is at a high level, namely normal, the PMOS tube is in a cut-off state, otherwise the PMOS tube is in a conducting state.
Optionally, the antifuse FPGA includes a read-back refresh circuit control module, where the read-back refresh circuit control module is connected with a dedicated read-back refresh chip, where the dedicated read-back refresh chip is connected with a SelectMAP interface and a default memory of the SRAM FPGA, respectively, and the SelectMAP interface reads configuration software from the default memory; and the special read-back refreshing chip is controlled by the read-back refreshing circuit control module to carry out loading configuration and read-back refreshing by using the SelectMAP interface.
The invention has the following technical effects:
1) After the single satellite-borne electronic equipment is covered, the SRAM type FPGA can be debugged through the JTAG interface, so that the software development and debugging efficiency of the multi-FPGA system is improved, and internal faults can be positioned under the condition of not covering the cover by writing test software according to the information returned by the JTAG interface;
2) The on-orbit loading configuration mode of the satellite-borne SRAM type FPGA is added, on-orbit reconstruction of any SRAM type FPGA in the system can be realized by matching with high-capacity cache on the premise of not reducing the reliability of the system, after the software is uploaded, the on-orbit loading configuration mode can be loaded through a JTAG interface, the software configuration items can be iterated rapidly, and the functional performance of the software is verified;
3) The large-capacity cache can reduce the number requirement of the system on small-capacity memories such as EEPROM, FLASH and the like, save the cost and improve the storage and quick loading capacity of the SRAM type FPGA software configuration items of the system;
4) The JTAG signal through mode only needs the bus transceiver to have three-receiving and transmitting capacity, so that other systems such as ground detection equipment and the like can be connected with JTAG signals of the SRAM type FPGA, and the three-receiving and transmitting bus interface after being switched into the autonomous control mode can also be used for other data interaction functions such as software uploading and the like, so that interface time-sharing multiplexing is realized;
5) The automatic bypass circuit can automatically detect and skip the abnormal SRAM type FPGA unit, and does not affect the work of other normal units on the JTAG daisy chain.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic block diagram of a system provided by an embodiment of the present invention;
FIG. 2 is a block diagram of a specific architecture based on the system principle according to an embodiment of the present invention;
FIG. 3 is a schematic block diagram of an example architecture provided by an embodiment of the present invention;
Fig. 4 is a schematic block diagram of an automatic bypass circuit according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention discloses a satellite-borne SRAM type FPGA loading configuration system based on JTAG, wherein a plurality of SRAM type FPGAs in the system can be loaded and configured through JTAG interfaces under the control of an anti-fuse FPGA, the external high-capacity cache of the anti-fuse FPGA can store software configuration items of all SRAM type FPGAs, the internal JTAG control logic is controlled to be TCK, TMS, TDI, TDO signals of a plurality of SRAM type FPGAs which are connected in a daisy chain by interactively receiving uploading software data or receiving and transmitting other types of data through a bus transceiver, two modes of JTAG signal through and custom control are supported, the JTAG signal through mode can be switched through remote control instructions, TCK, TMS, TDI, TDO signals of the SRAM type FPGAs are directly connected with other systems through the bus transceiver, and the custom control mode is realized by the anti-fuse FPGA according to TCK, TMS, TDI, TDO signals of the SRAM type FPGAs which are controlled by the internal preset logic. The SRAM type FPGA loading configuration method based on JTAG improves the flexibility of the system.
The above is specifically described:
As shown in figures 1-2, in the JTAG-based satellite-borne SRAM type FPGA loading configuration system, JTAG interfaces of a plurality of SRAM type FPGAs in the system are connected in a daisy chain through a bus isolation driving chip, and are connected with JTAG interfaces controlled by anti-fuse FPGA logic through the bus isolation driving chip, the SRAM type FPGA performs loading configuration and readback refreshing through a SelectMAP interface by default, and the JTAG interfaces are used as a redundant loading configuration mode.
The external high-capacity cache of the anti-fuse FPGA is used for storing configuration software of all SRAM type FPGAs, and the anti-fuse FPGAs are communicated with a star computer or ground detection equipment through a bus transceiver and are used for receiving uploading software or performing other data interaction. The internal logic of the anti-fuse FPGA is provided with a mode selection module, an upper data analysis module, a cache read-write control module, a JTAG control module, a measurement and control management module, a read-back refreshing circuit control module and an SRAM type FPGA working state monitoring module.
And the measurement and control management module of the anti-fuse FPGA realizes the remote measurement and control management functions of other systems such as a star computer or ground detection equipment. The read-back refreshing circuit control module realizes the SelectMAP mode loading of the SRAM type FPGA, the read-back refreshing circuit controlled by the anti-fuse FPGA defaults after power-on loads software through a SelectMAP interface, and realizes the read-back refreshing of configuration data, the read-back refreshing circuit judges whether the FPGA has errors or not by comparing a bit file stored in an external memory with the read-back file in the FPGA configuration memory, if so, the corresponding correct data packet is written into the configuration memory of the FPGA to replace the error data packet, and the real-time online configuration refreshing of the FPGA is completed, so that the single event effect resistance of the satellite-borne SRAM type FPGA is improved.
JTAG control module of anti-fuse FPGA controls JTAG interface TCK, TMS, TDI, TDO signal of SRAM type FPGA connected in daisy chain, supports JTAG signal through and autonomous control two modes, and can switch according to remote control instruction through mode selection module. The JTAG signal through mode is that a satellite computer or ground detection equipment directly controls TCK, TMS, TDI, TDO signals of a JTAG interface through a bus transceiver, and an anti-fuse FPGA is only used as a data connection path and does not perform any operation on the signals; the autonomous control mode is to enable the anti-fuse FPGA to realize JTAG control function according to remote control instructions and preset logic, read software configuration items from an external large-capacity cache to load and configure any SRAM type FPGA, and at the moment, TCK, TMS, TDI, TDO signals of the bus transceiver can be used for other data interaction functions such as software uploading and the like, so that interface time-sharing multiplexing is realized.
In the rail reconstruction process, the anti-fuse FPGA works in an autonomous control mode, a satellite ground measurement and control station uploads new SRAM type FPGA configuration software to a satellite through a measurement and control link, and after the anti-fuse FPGA receives uploading software data through a bus transceiver, the anti-fuse FPGA analyzes and sends the effective data to a cache read-write control module through an uploading data analysis module, and the effective data is written into an external high-capacity cache to realize software uploading and data storage. After the uploading is finished, the JTAG control module reads software data from an external high-capacity cache through the cache read-write control module, frames according to a JTAG protocol, and writes the software into a configuration area of the SRAM type FPGA through a JTAG interface of the SRAM type FPGA, so that loading configuration of the SRAM type FPGA is realized.
The SRAM type FPGA working state monitoring module of the antifuse FPGA is used for monitoring the running state of the SRAM type FPGA after loading, and judging whether the SRAM type FPGA needs to be reloaded according to the working state information returned by each SRAM type FPGA.
The system uses the bus isolation driving chip to improve the signal integrity of the JTAG signal daisy chain connection, and the automatic bypass circuit is connected before the TDI and TDO signals of each SRAM type FPGA enter and exit the bus isolation driving chip, and after the automatic bypass circuit detects that the positioned SRAM type FPGA unit is abnormal, the automatic bypass circuit automatically shorts the TDI and TDO signals of the unit, skips the abnormal SRAM type FPGA unit and does not influence the work of other normal SRAM type FPGA units on the JTAG daisy chain.
The foregoing will be described in detail with reference to specific examples and accompanying drawings:
As shown in FIG. 3, a system is composed of 1 anti-fuse FPGA and 5 SRAM type FPGAs, JTAG interfaces of 5 SRAM type FPGAs in the system are connected in a daisy chain through a bus isolation driving chip 162245, and analog JTAG interfaces logically controlled by the anti-fuse FPGA are connected through the bus isolation driving chip 162245. Before TDI and TDO signals of each SRAM type FPGA enter and exit bus isolation driving chip 162245, an automatic bypass circuit is connected, as shown in FIG. 4, the automatic bypass circuit detects a POWERGOOD signal of a power supply DCDC chip of the SRAM type FPGA unit, if the POWERGOOD signal is normal, namely high level, the JTAG interface of the SRAM type FPGA is considered to be normal, a PMOS tube Q2 is in a cut-off state, the TDI signal returns to the TDO signal after entering the JTAG interface of the SRAM type FPGA through bus isolation driving chip 162245, and then enters the next stage JTAG interface through bus isolation driving chip 162245; if the POWERGOOD signal is abnormal, namely low level, the JTAG interface of the SRAM type FPGA is considered to be abnormal, the PMOS tube Q2 is in a conducting state, the TDI signal and the TDO signal are directly short-circuited to skip the abnormal JTAG interface, and the normal operation of other SRAM type FPGA units on the JTAG daisy chain is not affected.
Each SRAM type FPGA in the system is provided with 1 special read-back refreshing chip, the special read-back refreshing chip is controlled by the anti-fuse FPGA, the SRAM type FPGA is powered on by the special read-back refreshing chip through a SelectMAP interface by default, and then loading configuration and read-back refreshing are carried out, and a JTAG interface is used as a redundant loading configuration mode.
The internal logic of the anti-fuse FPGA is provided with a mode selection module, an upper-injection data analysis module, a cache read-write control module, a JTAG control module, a 1553B bus measurement and control management module, a read-back refreshing circuit control module and an SRAM type FPGA working state monitoring module, and the functions of JTAG working mode selection, upper-injection data receiving and analysis, external high-capacity cache read-write, communication with a JTAG interface of the SRAM type FPGA, measurement and control management of the working state of the chip, control of the work of a special read-back refreshing chip and monitoring of the working state of the SRAM type FPGA are respectively realized.
The anti-fuse FPGA performs measurement and control management through a 1553B BUs controller BU65170, receives a remote control instruction and sends telemetry information; when the JTAG interface is used for loading and configuring the SRAM type FPGA, the anti-fuse FPGA supports two modes of JTAG signal direct connection and autonomous control, and can be switched according to a 1553B bus remote control instruction through the mode selection module; the anti-fuse FPGA is communicated with a satellite computer or ground detection equipment through an RS422 bus receiver 26C32 and an RS422 bus transmitter 26C31, and is provided with at least 3 paths of RS422 bus receiving signals and at least 1 path of RS422 bus transmitting signals; in a JTAG signal through mode, 3 paths of RS422 bus receiving signals respectively correspond to TCK, TMS, TDI of JTAG signals, 1 path of RS422 bus sending signals correspond to TDO of the JTAG signals, and internal logic of the FPGA only bridges the signals without any processing, namely other equipment outside the system can directly control JTAG chains of the SRAM type FPGA through an RS422 bus transceiver; in the autonomous control mode, the RS422 bus signal can be used for other functions of the system, such as receiving fast uploading software data, and realizing interface time-sharing multiplexing.
After the anti-fuse FPGA receives the quick uploading software data of the SRAM type FPGA through the RS422 interface, the uploading data is analyzed by the internal uploading data analysis module according to a protocol, and then the uploading data is written into an external large capacity NAND FLASH, NAND FLASH through the cache read-write control module, so that the configuration software of all the SRAM type FPGAs can be stored.
In JTAG autonomous control mode, the analog JTAG interface TCK, TMS, TDI, TDO signal of the antifuse FPGA is controlled by the internal JTAG control logic, and communicates with any SRAM type FPGA on the daisy chain according to JTAG protocol; when any SRAM type FPGA is loaded, the antifuse FPGA reads configuration software of the SRAM type FPGA to be loaded from the external NAND FLASH, and the configuration software is written into a configuration area of the SRAM type FPGA through JTAG signals, so that the quick loading of the configuration software is realized.
The method comprises the steps that state monitoring logic in the SRAM type FPGA regularly sends monitoring signals indicating normal operation of the SRAM type FPGA working state monitoring module of the anti-fuse FPGA, and if the working state of a certain SRAM type FPGA is abnormal and the anti-fuse FPGA cannot receive the normal monitoring signals, the anti-fuse FPGA automatically reloads the abnormal SRAM type FPGA.
One possible automatic bypass circuit is shown in fig. 4. The DCDC is used for supplying power to a 1.8V power supply of the SRAM type FPGA, the POWERGOOD signal of the DCDC is pulled up to 3.3V through a resistor, and the JTAG signal is 3.3V. Under normal conditions, the POWERGOOD signal is at a high level, the Vg of the PMOS tube is smaller than Vs, the PMOS tube is not conducted, and JTAG signals are output from a TDO pin after entering the TDI pin of the SRAM type FPGA through 162245 and then enter the next stage 162245. If the SRAM type FPGA works abnormally, the DCDC of 1.8V is considered to be abnormal, and the POWERGOOD signal is low level; when JTAG signal is "0", vg=Vs of the PMOS tube, the PMOS tube is not conducted, and the D end of the PMOS tube is low level under the action of the pull-down resistor, namely the signal is "0"; when JTAG signal is "1", vg of PMOS tube is less than Vs, PMOS tube is conducted, D end of PMOS is same as S end and is high level, namely signal "1". Thus JTAG signals are transmitted through PMOS, and the fault SRAM type FPGA is automatically bypassed.
The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (6)
1. JTAG-based satellite-borne SRAM type FPGA loading configuration system is characterized by comprising:
an antifuse FPGA and a plurality of SRAM type FPGAs;
The JTAG interface of the SRAM type FPGA is connected in a daisy chain through a first bus isolation driving chip; the JTAG interface of the anti-fuse FPGA is connected in a daisy chain through a second bus isolation driving chip, and the first bus isolation driving chip is connected with the second bus isolation driving chip;
The SRAM type FPGA directly reads configuration software through a SelectMAP interface by default to carry out loading configuration and readback refreshing; or transmitting configuration software to the JTAG interface of the SRAM type FPGA through the JTAG interface of the antifuse type FPGA, and using the JTAG interface of the SRAM type FPGA as a redundant loading configuration mode;
the anti-fuse FPGA is also communicated with a telemetry and remote control platform through a bus transceiver, wherein data interaction between the anti-fuse FPGA and the telemetry and remote control platform is carried out through the bus transceiver, and uploading software data is transmitted to the anti-fuse FPGA, and the telemetry and remote control platform comprises a star computer and ground detection equipment;
The anti-fuse FPGA comprises a measurement and control management module, wherein the measurement and control management module is communicated with the telemetry and remote control platform, and receives a remote control instruction of a satellite computer or ground detection equipment through the measurement and control management module to remotely measure and control the anti-fuse FPGA;
The anti-fuse FPGA comprises a mode selection module, an upper data analysis module, a cache read-write control module and a JTAG control module;
The system comprises a bus transceiver, a mode selection module, an upper data analysis module, a cache read-write control module and a JTAG control module, wherein the bus transceiver, the mode selection module, the upper data analysis module, the cache read-write control module and the JTAG control module are sequentially connected, the JTAG control module is connected with the mode selection module, and the cache read-write control module is connected with a memory;
The mode selection module is used for selecting a direct mode and an autonomous control mode according to a telemetry and remote control instruction;
In a through mode, the JTAG control module is used as a data connection path to transmit interaction data of the bus transceiver, and the interaction data is directly transmitted to a JTAG interface of the SRAM type FPGA through a JTAG interface of the antifuse type FPGA, so that direct interaction and control of the telemetry and remote control platform on the SRAM type FPGA are realized;
in the autonomous control mode, the data analysis is carried out on the uploading software data transmitted by the bus transceiver through the uploading data analysis module, and the analyzed data is stored into the memory through the cache read-write control module; when loading configuration, the buffer read-write control module is controlled by the JTAG control module to read configuration software from the memory, the configuration software is processed according to JTAG protocol, the configuration software is transmitted to the JTAG interface of the SRAM type FPGA through the JTAG interface of the antifuse type FPGA, and the configuration software is written into the configuration area of the SRAM type FPGA, so that the loading configuration of the SRAM type FPGA is realized.
2. The system according to claim 1, wherein:
The anti-fuse FPGA comprises a working state monitoring module, wherein the working state monitoring module is connected with the SRAM type FPGA, the working state monitoring module is used for monitoring the running state of the SRAM type FPGA after loading configuration, and whether the SRAM type FPGA needs to be reloaded or not is judged according to the working state information returned by the SRAM type FPGA.
3. The system according to claim 1, wherein:
The JTAG interface comprises a TCK interface, a TMS interface, a TDI interface and a TDO interface, wherein the TCK interface, the TMS interface, the TDI interface and the TDO interface are respectively used for transmitting TCK signals, TMS signals, TDI signals and TDO signals;
the first bus isolation driving chip is connected with the second bus isolation driving chip through TCK signals, TMS signals, TDI signals and TDO signals.
4. The system according to claim 1, wherein:
And an automatic bypass circuit is connected to the TDI signal and TDO connecting line between the second bus isolation driving chip and the first bus isolation driving chip, the automatic bypass circuit is used for detecting the abnormality of the SRAM type FPGA unit, and when the abnormality occurs, the TDI pin and the TDO pin are automatically shorted.
5. The system according to claim 4, wherein:
The automatic bypass circuit includes: the grid electrode of the PMOS tube is connected to the POWERGOOD signal of the power supply DCDC chip of the SRAM type FPGA unit, the source electrode of the PMOS tube is connected to the connecting line of the first TDI signal, the drain electrode of the PMOS tube is connected to the connecting line of the first TDO signal, and when the POWERGOOD signal of the power supply DCDC chip is at a high level, namely normal, the PMOS tube is in a cut-off state, otherwise the PMOS tube is in a conducting state.
6. The system according to claim 1, wherein:
The anti-fuse FPGA comprises a read-back refreshing circuit control module, wherein the read-back refreshing circuit control module is connected with a special read-back refreshing chip, the special read-back refreshing chip is respectively connected with a SelectMAP interface of the SRAM type FPGA and a default memory, and the SelectMAP interface reads configuration software from the default memory; and the special read-back refreshing chip is controlled by the read-back refreshing circuit control module to carry out loading configuration and read-back refreshing by using the SelectMAP interface.
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