CN117539757A - Efficient graph generation logic target board test method - Google Patents

Efficient graph generation logic target board test method Download PDF

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Publication number
CN117539757A
CN117539757A CN202311492022.XA CN202311492022A CN117539757A CN 117539757 A CN117539757 A CN 117539757A CN 202311492022 A CN202311492022 A CN 202311492022A CN 117539757 A CN117539757 A CN 117539757A
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CN
China
Prior art keywords
tested
symbol picture
generation logic
target board
symbol
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Pending
Application number
CN202311492022.XA
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Chinese (zh)
Inventor
常宏光
孙智伟
苏霖
赵学娟
韩明智
梁宸宇
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Luoyang Institute of Electro Optical Equipment AVIC
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Luoyang Institute of Electro Optical Equipment AVIC
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Application filed by Luoyang Institute of Electro Optical Equipment AVIC filed Critical Luoyang Institute of Electro Optical Equipment AVIC
Priority to CN202311492022.XA priority Critical patent/CN117539757A/en
Publication of CN117539757A publication Critical patent/CN117539757A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/005—Testing of electric installations on transport means
    • G01R31/008—Testing of electric installations on transport means on air- or spacecraft, railway rolling stock or sea-going vessels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3684—Test management for test design, e.g. generating new test cases
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3692—Test management for test results analysis

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention relates to a method for testing a logic target board for efficient graph generation, belonging to the field of computer graph generation. Comprising the following steps: the PC MATLAB platform is used as test excitation to generate test case codes and sends the test case codes to the graphic generation logic test equipment; the test equipment generates drawing instructions according to the test case codes and sends the drawing instructions to the graphic generation logic target board and the PC; generating a golden model symbol picture by the PC MATLAB platform according to the drawing instruction; generating a symbol picture to be tested by graphic generation logic residing in the target board according to the drawing instruction, sending the symbol picture to be tested to graphic generation logic testing equipment, and then outputting the symbol picture to a display and a PC; the PC MATLAB platform compares the symbol picture to be tested with the golden model symbol picture pixel by pixel, and judges the comparison result of the symbol picture to be tested and the golden model symbol picture; and generating a new test case code by the PC MATLAB platform, and repeatedly executing the steps until all the test cases finish the test of the target board.

Description

Efficient graph generation logic target board test method
Technical Field
The invention relates to the field of computer graphics generation, in particular to a method for testing a logic target board for efficient graphics generation.
Background
The on-board electronic hardware design assurance guidelines DO-254 are one of the airworthiness approval criteria of a civil aircraft, which define in detail the objective and activity requirements of each stage in the hardware development process, wherein chapter six describes the verification process, objective and activity of the hardware. The graphic generation logic is used as high-safety complex electronic hardware of civil aircraft for providing a symbol picture display function for pilots, and a reliable verification method is required to be invented for sufficiently and effectively testing a target board, so that the graphic generation logic can be proved to be capable of correctly realizing the function of generating symbol pictures, and misleading caused by generating wrong pictures to the pilots is avoided, so that catastrophic results are caused.
The symbol picture generated by the graph generating logic has a plurality of kinds of symbols and complex picture content, and in order to fully verify the correctness of the generating function of the graph generating logic symbol, the system in the prior art needs to design a plurality of test cases based on each symbol type during testing, and only one test can be performed at a time by manual testing, so that the number of the test cases and the test pictures is various, the time cost of the testing work is increased, the testing difficulty is increased, and the automatic testing efficiency is lower.
Disclosure of Invention
In view of the above, the method for testing the high-efficiency graphic generation logic target board provided by the invention solves the technical problem of lower testing efficiency in the prior art of system testing.
A high-efficiency pattern generation logic target board test method is suitable for testing a plurality of test cases, and comprises the steps of using a pattern generation logic target board, pattern generation logic test equipment and a PC, wherein each test case corresponds to a test case code,
the PC machine respectively sends the stored multiple test case codes to the graphic generation logic test equipment at preset period or preset time interval to generate drawing instructions, and the drawing instructions are transmitted to a graphic generation logic target board;
when the graphic generation logic target board receives the drawing instruction, generating a symbol picture to be tested, and feeding back to graphic generation logic test equipment;
and the PC receives the drawing instruction and the symbol picture to be tested sent by the graphic generation logic testing equipment, generates a golden model symbol picture according to the drawing instruction, and compares the golden model symbol picture with the symbol picture to be tested.
Advantageous effects
The graphic generation logic is rapidly and automatically tested, a tester can automatically obtain all test results by clicking an operation button on the PC MATLAB platform without executing any other operation, the test working time is greatly shortened, the test working cost is reduced, and the test working efficiency is improved. Meanwhile, the invention adopts a pixel-by-pixel comparison method, can test unqualified pictures with only one pixel point deviation and a plurality of pixel point deviations, and improves the precision and accuracy of test work.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following description will briefly explain the drawings needed in the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a graphics generation logic target board test;
FIG. 2 is a schematic flow chart of a PC portion in a target board test;
FIG. 3 is a schematic flow diagram of a portion of a graphics-generating logic test device in target board testing;
FIG. 4 is a flow chart of a portion of a graphics-generating logical target board in target board testing.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details.
The method for testing the high-efficiency graphic generation logic target board shown in fig. 1 is suitable for testing a plurality of test cases, and comprises the steps of using the graphic generation logic target board, graphic generation logic testing equipment and a PC, wherein each test case corresponds to one test case code,
the PC machine respectively sends the stored test case codes to the graphic generation logic test equipment to generate drawing instructions at preset periods or preset time intervals, and the drawing instructions are transmitted to the graphic generation logic target board;
when the graphic generation logic target board receives the drawing instruction, generating a symbol picture to be tested, and feeding back to the graphic generation logic test equipment;
the PC receives the drawing instruction and the symbol picture to be tested sent by the graphic generation logic testing equipment, generates a golden model symbol picture according to the drawing instruction, and compares the golden model symbol picture with the symbol picture to be tested.
As the specific implementation mode provided by the scheme, the graphic generation logic test equipment is also used for receiving test case codes sent by the MATLAB platform of the PC through the network port, generating drawing instructions according to the test case codes, sending the drawing instructions to the graphic generation logic target board through the LOCARBUS interface, and sending the drawing instructions to the PC through the network port;
the method comprises the steps of receiving a symbol picture to be tested sent by a graphic generation logic target board through a DVI interface, sending the symbol picture to be tested to a MATLAB platform of a PC through a network port, outputting the symbol picture to be tested to a connected display through the DVI interface, and observing the correctness of the picture through the display.
The graphic generation logic is rapidly and automatically tested, a tester can automatically obtain all test results by clicking an operation button on the PC MATLAB platform without executing any other operation, the test working time is greatly shortened, the test working cost is reduced, and the test working efficiency is improved. Meanwhile, the invention adopts a pixel-by-pixel comparison method, can test unqualified pictures with only one pixel point deviation and a plurality of pixel point deviations, and improves the precision and accuracy of test work.
Further, if the display is a man-machine interactive display device and the display is in error display on the symbol picture to be tested displayed on the current display, the display receives an instruction error instruction from an operator in a man-machine interactive mode, and the instruction error instruction is transmitted to the PC through the graphic generation logic test equipment;
the PC receives the instruction of indicating the error, and does not compare the symbol picture to be tested with the golden model symbol picture, or does not generate the golden model symbol picture.
As the specific implementation mode provided by the scheme, the MATLAB platform of the PC receives the symbol picture to be tested through the network port and performs pixel-by-pixel comparison with the golden model symbol picture, wherein:
if the comparison results are consistent, generating a first signal, wherein the first signal is used for representing that the symbol picture to be tested is correctly generated;
if the comparison results are inconsistent, generating a second signal, wherein the second signal is used for representing that the symbol picture to be tested is incorrectly generated.
As the specific implementation mode provided by the scheme, the MATLAB platform of the PC receives the symbol picture to be tested through the network port, and performs pixel-by-pixel comparison with the golden model symbol picture, and if the symbol picture is consistent with the golden model symbol picture, the comparison result is printed through a connected printer.
As the specific implementation mode provided by the scheme, the MATLAB platform of the PC receives the symbol picture to be tested through the network port, and performs pixel-by-pixel comparison with the golden model symbol picture, if the symbol picture is inconsistent with the golden model symbol picture, the golden model symbol picture and the symbol picture to be tested are subjected to superposition fusion, and the pixel values of the corresponding pixel points are subjected to difference processing, and after superposition fusion, a first color mark is adopted, and the difference value is displayed.
As a specific implementation mode provided by the scheme, the graphic generation logic target board receives drawing instructions through a LOCARBUS interface and configures a Zynq7 chip.
Examples
Step S1: as shown in FIG. 2, the PC MATLAB platform is used as a test stimulus to generate test case codes. The test case code is 8-bit byte data, different test case codes represent different test cases, for example, 0xA1 represents a test case for drawing a static line, and 0xC1 represents a test case for drawing a static open circle. The PC sends the test case code to the graphic generation logic test equipment through the network port;
step S2: as shown in FIG. 3, the PS of the Zynq7 chip in the graphic generation logic test equipment completes the network port configuration, receives the test case code sent by the PC, and generates a drawing instruction according to the test case code. The drawing instructions are frame structure data specially designed through test cases, different test case codes correspond to different drawing instructions, for example, when the test case code received by the PS is 0xA1, the drawing instructions for drawing 20 static lines are output, the PS sends the drawing instructions to a DPRAM chip of a graphic generation logic target board through a LOCALLBUS interface of the PL, and then the drawing instructions are sent to the PC through a network port.
Step S3: as shown in fig. 2, the MATLAB platform of the PC receives a drawing command through the internet access, and runs a graphic generation algorithm adopted by the graphic generation logic to generate a golden model symbol picture according to the drawing command. After generating the golden model symbol picture, the MATLAB platform sends a request signal for reading the symbol picture to be tested to the graphic generation logic test equipment through the network port.
Step S4: as shown in fig. 4, the PS of the Zynq7 chip in the graphic generation logic target board reads the drawing instruction in the DPRAM chip through the local bus interface of the PL, the PS sends the drawing instruction to the PL through the AXI interface, graphic generation logic residing in the PL develops drawing of the graphic element according to the drawing instruction, generates a symbol picture to be tested, and sends the symbol picture to be tested to the graphic generation logic test device through the DVI interface.
Step S5: as shown in fig. 3, PL of the Zynq7 chip in the graphic generation logic test apparatus receives a symbol picture to be tested through the DVI interface, and stores the symbol picture into the SRAM chip. After receiving a request sent by the MATLAB platform through the network port, the PS sends a read request signal to the PL, and the PL reads out a symbol picture to be tested from the SRAM chip and sends the symbol picture to the PS. And the PS sends the symbol picture to be tested to the PC through the network port. Meanwhile, the graphic generation logic test equipment outputs the symbol picture to be tested to the display through the DVI interface, and the correctness of the symbol picture is observed through the display.
Step S6: as shown in fig. 2, the PC reads the symbol image to be tested sent by the graphic generation logic test device through the internet access, compares the symbol image to be tested with the golden model symbol image pixel by pixel (compares whether the corresponding pixel gray values are the same one by one), if the two pixel by pixel comparison results are consistent, it indicates that the symbol image to be tested is generated correctly, the graphic generation logic function is realized normally, and the test is passed; if the two pixel-by-pixel comparison results are inconsistent, the symbol picture to be tested is generated in error, the graph generating logic function is realized abnormally, and the test is not passed.
Step S7: as shown in FIG. 2, the PC MATLAB platform generates the next test case code, and repeatedly executes the steps S1-S7 until all the symbol pictures to be tested generated by the test case code complete the target board test.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (8)

1. A high-efficiency graph generation logic target board test method is suitable for testing a plurality of test cases, and is characterized by comprising the steps of using a graph generation logic target board, graph generation logic test equipment and a PC, wherein each test case corresponds to one test case code,
the PC machine respectively sends the stored multiple test case codes to the graphic generation logic test equipment at preset period or preset time interval to generate drawing instructions, and the drawing instructions are transmitted to a graphic generation logic target board;
when the graphic generation logic target board receives the drawing instruction, generating a symbol picture to be tested, and feeding back to graphic generation logic test equipment;
and the PC receives the drawing instruction and the symbol picture to be tested sent by the graphic generation logic testing equipment, generates a golden model symbol picture according to the drawing instruction, and compares the golden model symbol picture with the symbol picture to be tested.
2. A method of testing a high-efficiency graphics-generating logic target board in accordance with claim 1, wherein said graphics-generating logic testing device is further configured to:
receiving the test case code sent by the MATLAB platform of the PC through the network port, generating a drawing instruction according to the test case code, sending the drawing instruction to a graphic generation logic target board through the LOCALDUS interface, and simultaneously sending the drawing instruction to the PC through the network port;
the method comprises the steps of receiving a symbol picture to be tested sent by a graphic generation logic target board through a DVI interface, sending the symbol picture to be tested to a MATLAB platform of a PC through a network port, outputting the symbol picture to be tested to a connected display through the DVI interface, and observing the correctness of the picture through the display.
3. The method for testing a high-efficiency graphic generation logic target board according to claim 2, wherein the display is a human-computer interactive display device, and if the symbol picture to be tested displayed on the current display is wrong, the display receives an instruction of an operator indicating the wrong in a human-computer interactive mode, and the instruction of the wrong is transmitted to the PC through the graphic generation logic test equipment;
and the PC receives the instruction error, and does not compare the symbol picture to be tested with the golden model symbol picture, or does not generate the golden model symbol picture.
4. The method for testing a logical object board for efficient graphics generation according to claim 3, wherein a MATLAB platform of a PC receives a symbol frame to be tested through a portal and performs a pixel-by-pixel comparison with the golden model symbol frame, wherein:
if the comparison results are consistent, generating a first signal, wherein the first signal is used for representing that the symbol picture to be tested is correctly generated;
and if the comparison results are inconsistent, generating a second signal, wherein the second signal is used for representing that the symbol picture to be tested is incorrectly generated.
5. The method for testing a logic target board for efficient graphic generation according to claim 4, wherein a MATLAB platform of the PC receives a symbol frame to be tested through a portal, performs pixel-by-pixel comparison with a golden model symbol frame, and prints a comparison result through a connected printer if the symbol frame is consistent with the golden model symbol frame.
6. The method for testing the high-efficiency graphic generation logic target board according to claim 5, wherein the MATLAB platform of the PC receives the symbol picture to be tested through the Internet access, performs pixel-by-pixel comparison with the golden model symbol picture, if the symbol picture is inconsistent with the golden model symbol picture, performs superposition fusion on the golden model symbol picture and the symbol picture to be tested, performs difference processing on pixel values of corresponding pixel points, adopts a first color mark after superposition fusion, and displays a difference value.
7. A method of testing a high efficiency graphics producing logic target board as recited in claim 1, wherein the graphics producing logic target board receives drawing instructions via a local bus interface.
8. The method of claim 7, wherein the pattern generation logic test device is configured with a Zynq7 chip.
CN202311492022.XA 2023-11-09 2023-11-09 Efficient graph generation logic target board test method Pending CN117539757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311492022.XA CN117539757A (en) 2023-11-09 2023-11-09 Efficient graph generation logic target board test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311492022.XA CN117539757A (en) 2023-11-09 2023-11-09 Efficient graph generation logic target board test method

Publications (1)

Publication Number Publication Date
CN117539757A true CN117539757A (en) 2024-02-09

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Country Status (1)

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