CN117528929A - Design method of 400G self-loop optical module PCB and PCB - Google Patents

Abstract

The application relates to a design method of a 400G self-loop optical module PCB and a PCB board, wherein the gold finger high-speed bonding pad is subjected to disc cutting and ground wrapping treatment, and under the condition that the gold finger high-speed bonding pad cannot be provided with a through hole, a blind buried hole drilling method is adopted to enable the ground of the layer where the gold finger high-speed bonding pad is positioned to be connected to the ground of the bottommost layer; SI simulation results are carried out on the PCB to obtain hollowing data; hollowing out the gold finger high-speed bonding pads of the second layer and the ninth layer according to the hollowing out data; digging three sides of the golden finger high-speed bonding pad, which are close to the right edge of the PCB, without wires; digging four sides of the high-speed bonding pad of the golden finger close to the left edge of the PCB; hollowing the high-speed signal via hole and the AC capacitor according to the hollowing data; and punching reflow ground through holes around the AC capacitor and the high-speed signal through holes to form the shortest reflow path. The problem of the influence that crosstalk problem led to the fact to the performance of ultra-high speed PCB board data transmission among the prior art has been solved, the problem of reduction crosstalk has been realized.

Description

Design method of 400G self-loop optical module PCB and PCB

Technical Field

The application relates to the field of printed circuit board design, in particular to a design method of a 400G self-loop optical module PCB and a PCB.

Background

With the rapid development of the internet and big data, the arrival of the cloud computing age, more and more businesses need to realize graphic processing and data computing by means of a server, and with the increase of traffic, the stability of the server becomes more and more important. The most important part in the server design is the high-speed signal design, if the high-speed signal design is not good, the design function may be affected, and the system may not work normally seriously.

An Optical module (Optical Modules) is an optoelectronic device for realizing photoelectric conversion and electro-Optical conversion functions in the Optical signal transmission process, and is an important component in Optical fiber communication. The optical module operates at the physical layer of the OSI model and is one of the core devices in an optical fiber communication system. The optical fiber optical communication system mainly comprises an optoelectronic device (an optical transmitter, an optical receiver), a functional circuit, an optical interface and the like, and is mainly used for realizing photoelectric conversion and electro-optical conversion functions in optical fiber communication. The transmitting interface inputs an electric signal with a certain code rate, the electric signal is processed by an internal driving chip and then is transmitted by a driving semiconductor Laser (LD) or a Light Emitting Diode (LED) to form a modulated optical signal with a corresponding rate, the receiving interface converts the optical signal into an electric signal by a light detecting diode after the optical signal is transmitted by an optical fiber, and the electric signal with a corresponding code rate is output after the electric signal passes through a preamplifier.

With the rapid development of optical communication technology at present, the demand of ultra-high speed optical network resource is continuously increased, the demand of people on ultra-high speed PCB design is increased day by day, and the line loss and crosstalk problem on the ultra-high speed PCB design in the market at present can influence the performance of data transmission for the signal transmission function of optical module is poor.

Disclosure of Invention

The embodiment of the application provides a design method of a 400G self-loop optical module PCB and a PCB board, which at least solve the problem that crosstalk influences data transmission performance in the design of a super-speed PCB in the related technology.

In a first aspect, an embodiment of the present application provides a method for designing a 400G self-loop optical module PCB, including:

performing coiling and covering treatment on the high-speed gold finger bonding pad, and connecting the ground bonding pad of the layer where the high-speed gold finger bonding pad is positioned to the ground bonding pad of the bottommost layer by adopting a blind buried hole punching method under the condition that the high-speed gold finger bonding pad cannot be punched with a through hole;

digging the reference ground right below the high-speed bonding pads of the golden fingers of the second layer and the ninth layer according to the digging data to realize cross-layer reference; digging three sides of the golden finger high-speed bonding pad, which are close to the edge of one side of the PCB, and which are not out of wires; digging four sides of the high-speed bonding pad of the golden finger close to the edge of the other side of the PCB; the hollowing data are obtained in advance through simulation of a PCB;

hollowing the high-speed signal via hole and the AC capacitor according to the hollowing data;

and punching reflow ground through holes around the AC capacitor and the high-speed signal through holes to form the shortest reflow path.

In one embodiment, the performing the skiving process on the high-speed pad of the golden finger includes:

and cutting the high-speed bonding pad close to the edge of the PCB in the high-speed bonding pad of the golden finger to the middle of the high-speed signal through hole.

In an embodiment, the hollowing out three sides of the golden finger high-speed bonding pad non-outgoing line near to the edge of one side of the PCB includes:

digging the upper side of a high-speed bonding pad of a golden finger close to one side edge of the PCB into 11mil, digging the left side into 14mil and digging the lower side into 9.9mil;

hollowing out four sides of the high-speed bonding pad of the golden finger close to the edge of the other side of the PCB, comprising:

and hollowing out the upper side of the high-speed bonding pad of the golden finger close to the edge of the other side of the PCB by 11mil, hollowing out the left side by 14mil, hollowing out the lower side by 9.9mil and hollowing out the right side by 14mil.

In an embodiment, the hollowing out the high-speed signal via according to the hollowing out data includes:

the size of the hollowed-out area of the high-speed signal VIA hole is set to 58 x 30mil, and the hollowed-out area is hollowed out by using VIA16D8, a VIA hole specification with a distance of 12mil and a line with a distance of 30 mil.

In an embodiment, the hollowing out the AC capacitor according to the hollowing out data includes:

the size of the hollowed-out area of the AC capacitor is set to 38 mm, and the AC capacitor is hollowed out so that each pin of the AC capacitor extends by 3 mm;

and hollowing down two layers from the layer where the AC capacitor is located, wherein the layer where the AC capacitor is located is not included.

In an embodiment, the method further comprises:

when the high-speed signal via hole and the AC capacitor are hollowed, the high-speed signal via Kong Wakong and the AC capacitor are hollowed to form a ground, and the air space between the hollowed AC capacitor and the hollowed high-speed signal via hole is not smaller than 20mil.

In one embodiment, the reflowing the via around the AC capacitor and the high-speed signal via includes:

four reflow ground holes are formed around the AC capacitor or the high-speed signal via hole, wherein the four reflow ground via holes are uniformly and symmetrically arranged on the outer side of the hollowed-out area, and the ground pad does not enter the hollowed-out area.

In an embodiment, the method further comprises:

setting the spacing between different high-speed signal through holes to be not less than 1.5mm;

aiming at two high-speed signal through holes in parallel relation, more than one ground through hole is arranged on the straight line distance of the two high-speed signal through holes;

a ground via is drilled alongside the AC capacitance, the via being connected to at least the ground of the fourth layer.

In an embodiment, the method further comprises:

obtaining an insertion loss value, determining the line length of a high-speed line according to the insertion loss value, and setting the high-speed line in an inner layer;

determining a reference layer according to the wiring condition of the high-speed line, and increasing the PP value of the reference layer and the line width of the high-speed line;

and the PCB surface is treated by adopting low-loss ink, low-roughness browning liquid medicine and a low-loss factor material.

In a second aspect, an embodiment of the present application provides a 400G self-ring optical module PCB board, where the PCB board is designed according to the method for designing a 400G self-ring optical module PCB according to any one of the above embodiments.

The design method of the 400G self-loop optical module PCB and the PCB have at least the following technical effects.

The method comprises the steps of performing disc cutting and land covering treatment on a gold finger high-speed bonding pad, and connecting the land of the layer where the gold finger high-speed bonding pad is positioned to the bottom land by adopting a blind buried hole punching method under the condition that the gold finger high-speed bonding pad cannot be punched with a through hole; SI simulation results are carried out on the PCB to obtain hollowing data; hollowing out the gold finger high-speed bonding pads of the second layer and the ninth layer according to the hollowing out data; digging three sides of the golden finger high-speed bonding pad, which are close to the right edge of the PCB, without wires; digging four sides of the high-speed bonding pad of the golden finger close to the left edge of the PCB; hollowing the high-speed signal via hole and the AC capacitor according to the hollowing data; and punching reflow ground through holes around the AC capacitor and the high-speed signal through holes to form the shortest reflow path. The problem of the influence that crosstalk problem led to the fact to the performance of ultra-high speed PCB board data transmission among the prior art has been solved, the problem of reduction crosstalk has been realized.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:

fig. 1 is a flowchart of a design method of a self-loop optical module PCB according to an embodiment 400G of the present application.

FIG. 2 is a layout of a golden finger high speed bonding pad in a PCB according to one embodiment of the present application;

FIG. 3 is a layout of a ground pad in a PCB according to one embodiment of the present application;

FIG. 4 is a design drawing of a PCB hollowed out for a golden finger high-speed bonding pad according to one embodiment of the present application;

FIG. 5 is a design drawing of a PCB hollowed out for a high speed signal via in an embodiment of the present application;

FIG. 6 is a schematic illustration of a hollowed-out pattern that does not allow for the presence in a PCB according to one embodiment of the present application;

FIG. 7 is a schematic diagram of a PCB with reflow vias according to one embodiment of the present application;

fig. 8 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described and illustrated below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden on the person of ordinary skill in the art based on the embodiments provided herein, are intended to be within the scope of the present application.

It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the embodiments described herein can be combined with other embodiments without conflict.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar terms herein do not denote a limitation of quantity, but rather denote the singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein refers to two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.

In order to reduce the influence of data transmission performance, the invention mainly aims at reducing line loss and crosstalk. The invention takes an optical module QSFP-DD as an example to describe the design method of the 400G self-loop optical module PCB in detail, the invention is mainly designed aiming at the PCB with ten total layers, and the PCB with different total layers can also refer to the design method of the invention, and only partial data (such as the layer number) is required to be modified correspondingly.

Firstly, the embodiment of the invention designs the PCB aiming at the crosstalk problem, and referring to FIG. 1, the design method is realized by the following steps.

Step S1, carrying out disc cutting and ground covering treatment on the high-speed bonding pad of the golden finger, and connecting the ground bonding pad of the high-speed bonding pad of the golden finger to the ground bonding pad at the bottommost layer by adopting a blind buried hole punching method under the condition that the high-speed bonding pad of the golden finger cannot be punched.

Specifically, for the disc cutting process, the design method of the invention cuts the high-speed bonding pad close to the edge of the PCB in the high-speed bonding pad of the golden finger into the middle of the high-speed signal via hole. Referring specifically to fig. 2, in this embodiment, each gold finger high-speed pad 1 near the left edge of the PCB board is cut to a corresponding high-speed signal via hole 2, so that the gold finger high-speed pad 1 is connected with the high-speed signal via hole 2, so that the signal path is shorter, the transmission time and signal loss of the signal are reduced, and the integrity and reliability of the signal are improved. In addition, the embodiment can reduce reflection and crosstalk of signals by directly connecting the high-speed bonding pad of the golden finger with the high-speed signal via hole, improve the quality of the high-speed signals and reduce the error rate.

For the golden finger high-speed bonding pad package processing, reference may be made to fig. 3. As shown in fig. 3, in this embodiment, ground pads (GND areas in the drawing) are disposed on the upper and lower sides of the high-speed pad of the gold finger, the high-speed pad of the gold finger is surrounded, then through holes 4 are drilled in the ground pads beside the high-speed pad of the gold finger, each of the ground pads is perforated with 4 through holes, and these through holes are only partially perforated in the ground pads, and need not be completely disposed in the ground pads. In addition, under the condition that the through holes cannot be drilled, the ground GND of the layer where the high-speed bonding pads of the golden finger are arranged is also connected to the ground GND of the last layer in a blind buried hole mode, and the Stub on the GND is eliminated through the through holes or the blind buried holes.

In some special cases, the PCB may not be able to be perforated, for example: one is particularly high frequency circuits, where vias introduce additional inductance and capacitance that adversely affects signal transmission. Therefore, in a high-frequency circuit, the use of a via hole is generally avoided; secondly, a high density layout, when the layout of the PCB board is very compact, there is not enough space to place the through holes, it may be necessary to avoid the use of through holes; third is the high-speed differential signal: in high-speed differential signal transmission, the via may introduce asymmetric signal delays, resulting in signal distortion, and thus in this case, special designs are often required to avoid the use of vias; fourth, if the PCB is of a non-standard size or shape, if the PCB is of a shape or size that is not suitable for passing through the hole, or is not designed to be connected through the hole, then the through hole may not be drilled.

And S3, hollowing out the reference ground right below the high-speed bonding pads of the golden fingers of the second layer and the ninth layer according to the hollowing out data.

In the embodiment of the invention, the hollowing data is obtained through PCB simulation in advance, and an SI simulation method is generally adopted. After the hollowing data are obtained, extracting data of the high-speed gold finger bonding pad from the hollowing data, and hollowing out the reference ground right below the high-speed gold finger bonding pad to realize cross-layer reference. Referring to fig. 4, only three sides of the golden finger high-speed bonding pad 3, which are close to the right edge of the PCB, and are not out of wires are hollowed, and four sides of the golden finger high-speed bonding pad 1, which are close to the left edge of the PCB, are hollowed.

In this embodiment, an SI simulation method is used when acquiring hollowing data, where SI simulation refers to signal integrity simulation, and is used to evaluate performance of signal transmission in a circuit board, a package, or an entire system. SI emulates the signal clock, data and control signals in the analysis circuit to predict problems that the signal may encounter during transmission, such as signal attenuation, clock skew, crosstalk, etc. In SI simulation, an electromagnetic field simulation tool or a circuit simulation tool is generally used to simulate signal transmission in a circuit, and factors such as layout of a circuit board, characteristic impedance of a signal line, length of a transmission line, and wiring mode are considered. The simulation results may provide information about signal quality, clock jitter, electromagnetic radiation and scattering from the interconnect lines, etc. SI simulation can help designers optimize circuit board layout and routing planning, select appropriate signal line characteristic impedance, termination, attenuation compensation, and the like, to ensure reliable transmission of signals and reduce occurrence of signal integrity problems.

In this embodiment, according to the result of SI simulation, the area to be hollowed out and the corresponding size may be determined. Specifically, when SI simulation is performed on the PCB board, the signal frequency and speed set by the user are input, that is, the characteristic impedance requirement of signal transmission, and the size and shape of the hollows can be obtained, and then the hollows are determined according to the size and shape of the hollows, and in general, the hollows are determined according to the layout of the circuit board and the trend of the signal lines, and for the AC capacitor, if hollows are required around the pins, the hollows should be sized to allow the pins to extend enough space for connection and welding.

As shown in fig. 4, in the embodiment, the size of the gold finger high-speed pad 1 on the left side of the PCB is 61.68×21.26mil, the size of the gold finger high-speed pad 3 on the right side is 70.87×21.26mil, and in the embodiment, the upper side of the gold finger high-speed pad on the right side is hollowed out by 11mil, the left side is hollowed out by 14mil, and the lower side is hollowed out by 9.9mil; the upper side of the high-speed bonding pad of the gold finger on the left is hollowed out by 11mil, the left side is hollowed out by 14mil, the lower side is hollowed out by 9.9mil, and the right side is hollowed out by 14mil. According to the embodiment, the high-speed bonding pad of the golden finger is hollowed, so that better welding performance and reliability are provided in the welding process. The hollowing of the invention is realized by cutting or drilling on the bonding pad to remove a part of metal material, thus reducing the volume of solder, improving the welding quality and reducing the possible welding defects, thereby reducing the influence of signal attenuation and crosstalk.

It should be noted that, the "left and right sides" of the PCB board in this embodiment are described according to the placement direction of the PCB board in fig. 4. However, in other embodiments, if the rotation of fig. 4 is 90 degrees, the description of "upper and lower sides" may be adopted, so that the gold finger pads near the two sides of the board edge with opposite directions may be actually defined, and the direction is not limited here.

And S4, hollowing out the high-speed signal via hole and the AC capacitor according to the hollowing out data.

After the hollowing data is obtained, the data of the high-speed signal via hole and the AC capacitor are extracted from the hollowing data, and hollowing processing is carried out on the high-speed signal via hole or the AC capacitor.

In a preferred embodiment of the present invention, referring to fig. 5, the size of the hollowed-out area of the high-speed signal VIA is set to 58 x 30mil, and the hollowed-out area is hollowed out by using VIA16D8, a VIA rule with a pitch of 12mil and a line with a pitch of 30mil, so that the impedance can be raised by about 5ohm by setting the hollowed-out area with a pitch of 58 x 30mil, thereby reducing the fluctuation of the impedance. That is, in this embodiment, the spacing between each high speed signal via is 58 mils, and each via has a diameter of 16 mils and 8 holes, and then the process of digging is typically accomplished by cutting or drilling using a 30mil wire. Finally, ensuring that the size and the spacing of the hollows meet the design requirements, and carrying out proper inspection and test after finishing so as to ensure the performance and the reliability of high-speed signal transmission.

In a preferred embodiment of the invention, the hollowed-out area of the AC capacitor is set to 38 x 38mil, and the AC capacitor is hollowed out so that each pin of the AC capacitor extends by 3mil; in addition, two layers need to be hollowed down from the layer where the AC capacitor is located, wherein the layer where the AC capacitor is located is not included.

In the embodiment of the present invention, when the high-speed signal via hole and the AC capacitor are hollowed, the high-speed signal via hole Kong Wakong and the AC capacitor are hollowed, and the AC capacitor and the hollowed area of the high-speed signal via hole cannot be contacted, the Air Gap (Air space) between the two is preferably not less than 20mil, that is, the space between the hollowed AC capacitor and the hollowed area of the high-speed signal via hole Kong Wakong is not less than 20mil, for example, the hollowed mode in fig. 6 does not allow the hollowed area of the high-speed signal via hole 4 and the hollowed area 5 of the AC capacitor to be connected.

And S5, punching a reflow ground via hole around the AC capacitor and the high-speed signal via hole to form the shortest reflow path.

Four reflow ground holes are drilled around the AC capacitor or the high-speed signal via hole, wherein the four reflow ground via holes are uniformly and symmetrically drilled outside the hollowed-out area, and the ground pad does not enter the hollowed-out area.

Specifically, because the via hole and the hollowed-out area are crosstalk high-occurrence areas, the embodiment of the invention punches the reflow ground via hole beside the AC capacitor and around the high-speed signal via hole, and provides a shortest reflow path for the signal so as to reduce the signal and reduce the crosstalk. Referring to fig. 7, in this embodiment, four reflow holes are uniformly and symmetrically drilled beside the hollowed-out area, but are not in contact with the hollowed-out area, and the distribution of the reflow vias 6 corresponding to the high-speed signal Kong Wakong area and the distribution of the reflow vias 7 corresponding to the AC capacitor hollowed-out area are all distributed beside the corners of the hollowed-out area as shown in fig. 7. In addition, in the PCB board designed by the invention, the ground pad does not enter the hollowed-out area. According to the embodiment, through punching the reflow ground via holes, when signal crosstalk occurs, the signal needs to search the nearest GND via holes to complete reflow, and the GND via holes are additionally formed around the signal, so that self radiation can be prevented from interfering with other signals, and other radiation can be prevented from interfering with the self.

In another embodiment of the present invention, on the basis of the steps S1 to S5, the design method of the present embodiment further includes: setting the spacing between different high-speed signal through holes to be not less than 1.5mm; aiming at two high-speed signal through holes in parallel relation, more than one GND through hole is arranged on the straight line distance of the two high-speed signal through holes for isolation; and a ground through hole is drilled beside the AC capacitor, and the through hole is at least connected to GND of the fourth layer. According to the invention, GND through holes are drilled on the sides of the AC capacitor so as to separate radiation of an AC capacitor region from other regions, and if the through holes cannot be drilled, holes for connecting the first layer and the 4 th layer are preferably arranged, because from the perspective of three-dimension, reference of the AC capacitor is referred to GND of the fourth layer; in addition, the provision of holes connecting the first layer and the second layer does not play a significant role. According to the embodiment, the distance between different signal through holes is increased, and the GND through holes are arranged as isolation measures, so that the aim of further reducing crosstalk is achieved.

In another embodiment of the present invention, in order to reduce the line loss of the PCB board, the following design method is added on the basis of the steps S1 to S5.

And S6, obtaining an insertion loss value, calculating the line length of the high-speed line according to the insertion loss value, shortening the line length of the high-speed line as much as possible to reduce the line loss, and arranging the high-speed line in the inner layer.

In the embodiment, the insertion loss value of the surface layer of the PCB is set to be 1.2@13.28GHz, and the insertion loss value of the inner layer is set to be 0.55@13.28GHz.

In the present embodiment, the line length is calculated according to the following formula:

L＝(c*t)/(2*sqrt(K))

where L represents the line length, c represents the propagation speed of electromagnetic waves in the medium (typically, the speed of light, about 3x 10-8 m/s), t represents the rise time of the signal (in seconds), and K represents the insertion loss value of the line. It should be noted that this formula applies to both the case of an lossless medium and the case of a non-reflective one, and that other correction factors need to be considered if there is a reflection or loss of medium in the line.

And S7, determining a reference layer according to the wiring condition of the high-speed line, and increasing the PP value of the reference layer and the line width of the high-speed line.

For a ten-layer board, the present embodiment designs high-speed wires to run on the third and eighth layers to reduce wire loss.

The PP value represents the conductivity of the reference layer, and increasing the PP value can improve the conductivity of the reference layer, so that the resistance and the capacitance between the high-speed wire and the reference layer are reduced, and the purpose of reducing the wire loss is achieved. For the determination of the PP value, the embodiment first determines the number of layers of the high-speed wire, and the number of layers can determine the selection of the reference layer and the increase degree of the PP value; then selecting a proper reference layer according to the wiring layer number of the high-speed wire, wherein the reference layer is usually adjacent to the high-speed wire wiring layer as much as possible so as to provide an optimal reference plane; and finally, in PCB design software, finding out related settings or rules, and adjusting the PP value of the reference layer.

And S8, treating the surface of the PCB by adopting low-loss ink, low-roughness brown chemical and low-loss factor materials.

Namely, the PCB is processed by selecting low-loss printing ink, low-roughness brown chemical liquid and low-loss factor materials, so that the purpose of reducing line loss is achieved.

In another embodiment of the present invention, tear drops are also added to the surface layer of the PCB board, and pads are manually added for high speed vias in order to gradually change the impedance.

On the other hand, the invention provides a 400G self-loop optical module PCB board, which is designed by the design method of the 400G self-loop optical module PCB in any embodiment.

For example, in a PCB board according to a preferred embodiment of the present invention, in order to reduce the influence of crosstalk, the present embodiment skips the high speed pads of the golden finger near the edge of the PCB board to the middle of the high speed signal via hole. Digging three sides of the right golden finger high-speed bonding pad, which are not out of wires; hollowing out four sides of the high-speed bonding pad of the gold finger on the left, for example: digging the upper side of the high-speed bonding pad of the right golden finger to be 11mil, digging the left side to be 14mil and digging the lower side to be 9.9mil; the upper side of the high-speed bonding pad of the gold finger on the left is hollowed out by 11mil, the left side is hollowed out by 14mil, the lower side is hollowed out by 9.9mil, and the right side is hollowed out by 14mil. The size of the hollowed-out area of the high-speed signal VIA hole is set to 58 x 30mil, and the hollowed-out area is hollowed out by using VIA16D8, a VIA hole specification with a distance of 12mil and a line with a distance of 30 mil. The hollowed-out area of the AC capacitor was set to 38 x 38mil, and the AC capacitor was hollowed out so that each pin extended 3mil. The high-speed signal via Kong Wakong and the AC capacitor dig the package ground, and the air space between the AC capacitor dig and the high-speed signal via dig is not less than 20mil. Four return ground holes are drilled around the AC capacitor or high speed signal via. Setting the spacing between different high-speed signal through holes to be not less than 1.5mm; aiming at two high-speed signal through holes in parallel relation, more than one GND through hole is arranged on the straight line distance of the two high-speed signal through holes for isolation; and a ground through hole is drilled beside the AC capacitor, and the through hole is at least connected to GND of the fourth layer.

In addition, in order to reduce the influence of line loss, the high-speed line in the PCB board of the present embodiment is shorter and goes on the inner layer (for the ten-layer board, goes on the third layer and the eighth layer); increasing the PP value of the reference layer and the line width of a high-speed line; and finally, the PCB is processed by low-loss printing ink, low-roughness brown chemical and low-loss factor materials.

In a third aspect, embodiments of the present application provide an electronic device, and fig. 8 is a block diagram of the electronic device, which is shown according to an exemplary embodiment. As shown in fig. 8, the electronic device may include a processor 81 and a memory 82 storing computer program instructions.

In particular, the processor 81 may include a Central Processing Unit (CPU), or an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), or may be configured to implement one or more integrated circuits of embodiments of the present application.

Memory 82 may include, among other things, mass storage for data or instructions. By way of example, and not limitation, memory 82 may comprise a Hard Disk Drive (HDD), floppy Disk Drive, solid state Drive (Solid State Drive, SSD), flash memory, optical Disk, magneto-optical Disk, tape, or universal serial bus (Universal Serial Bus, USB) Drive, or a combination of two or more of the foregoing. The memory 82 may include removable or non-removable (or fixed) media, where appropriate. The memory 82 may be internal or external to the data processing apparatus, where appropriate. In a particular embodiment, the memory 82 is a Non-Volatile (Non-Volatile) memory. In a particular embodiment, the Memory 82 includes Read-Only Memory (ROM) and random access Memory (Random Access Memory, RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (Programmable Read-Only Memory, abbreviated PROM), an erasable PROM (Erasable Programmable Read-Only Memory, abbreviated EPROM), an electrically erasable PROM (Electrically Erasable Programmable Read-Only Memory, abbreviated EEPROM), an electrically rewritable ROM (Electrically Alterable Read-Only Memory, abbreviated EAROM), or a FLASH Memory (FLASH), or a combination of two or more of these. The RAM may be Static Random-Access Memory (SRAM) or dynamic Random-Access Memory (Dynamic Random Access Memory DRAM), where the DRAM may be a fast page mode dynamic Random-Access Memory (Fast Page Mode Dynamic Random Access Memory FPMDRAM), extended data output dynamic Random-Access Memory (Extended Date Out Dynamic Random Access Memory EDODRAM), synchronous dynamic Random-Access Memory (Synchronous Dynamic Random-Access Memory SDRAM), or the like, as appropriate.

Memory 82 may be used to store or cache various data files that need to be processed and/or communicated, as well as possible computer program instructions for execution by processor 81.

The processor 81 reads and executes the computer program instructions stored in the memory 82 to implement the method of designing the 400G self-loop optical module PCB according to any of the above embodiments.

In an embodiment, the electronic device may also include a communication interface 83 and a bus 80. As shown in fig. 8, the processor 81, the memory 82, and the communication interface 83 are connected to each other via the bus 80 and perform communication with each other.

The communication interface 83 is used to implement communications between various modules, devices, units, and/or units in embodiments of the present application. Communication port 83 may also enable communication with other components such as: and the external equipment, the image/data acquisition equipment, the database, the external storage, the image/data processing workstation and the like are used for data communication.

Bus 80 includes hardware, software, or both, components of the electronic device coupled to each other. Bus 80 includes, but is not limited to, at least one of: data Bus (Data Bus), address Bus (Address Bus), control Bus (Control Bus), expansion Bus (Expansion Bus), local Bus (Local Bus). By way of example, and not limitation, bus 80 may include a graphics acceleration interface (Accelerated Graphics Port), abbreviated AGP, or other graphics Bus, an enhanced industry standard architecture (Extended Industry Standard Architecture, abbreviated EISA) Bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an industry standard architecture (Industry Standard Architecture, ISA) Bus, a wireless bandwidth (InfiniBand) interconnect, a Low Pin Count (LPC) Bus, a memory Bus, a micro channel architecture (Micro Channel Architecture, abbreviated MCa) Bus, a peripheral component interconnect (Peripheral Component Interconnect, abbreviated PCI) Bus, a PCI-Express (PCI-X) Bus, a serial advanced technology attachment (Serial Advanced Technology Attachment, abbreviated SATA) Bus, a video electronics standards association local (Video Electronics Standards Association Local Bus, abbreviated VLB) Bus, or other suitable Bus, or a combination of two or more of the foregoing. Bus 80 may include one or more buses, where appropriate. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.

In a fourth aspect, embodiments of the present application provide a computer readable storage medium having a program stored thereon, the program, when executed by a processor, implementing the method for designing a seed 400G self-loop optical module PCB provided in the first aspect.

More specifically, among others, readable storage media may be employed including, but not limited to: portable disk, hard disk, random access memory, read only memory, erasable programmable read only memory, optical storage device, magnetic storage device, or any suitable combination of the foregoing.

In a possible implementation manner, the present invention may also be implemented in the form of a program product, which comprises program code for causing a terminal device to carry out the steps of implementing the design method of the self-loop optical module PCB of the kind 400G provided in the first aspect, when said program product is run on the terminal device.

Wherein the program code for carrying out the invention may be written in any combination of one or more programming languages, which program code may execute entirely on the user device, partly on the user device, as a stand-alone software package, partly on the user device and partly on the remote device or entirely on the remote device.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. The design method of the 400G self-loop optical module PCB is characterized by comprising the following steps of:

performing coiling and covering treatment on the high-speed gold finger bonding pad, and connecting the ground bonding pad of the layer where the high-speed gold finger bonding pad is positioned to the ground bonding pad of the bottommost layer by adopting a blind buried hole punching method under the condition that the high-speed gold finger bonding pad cannot be punched with a through hole;

digging the reference ground right below the high-speed bonding pads of the golden fingers of the second layer and the ninth layer according to the digging data to realize cross-layer reference; digging three sides of the golden finger high-speed bonding pad, which are close to the edge of one side of the PCB, without wires; digging four sides of the high-speed bonding pad of the golden finger close to the edge of the other side of the PCB; the hollowing data are obtained in advance through simulation of a PCB;

hollowing the high-speed signal via hole and the AC capacitor according to the hollowing data;

and punching reflow ground through holes around the AC capacitor and the high-speed signal through holes to form the shortest reflow path.

2. The design method according to claim 1, wherein the performing the skiving process on the gold finger high-speed pad includes:

and cutting the high-speed bonding pad close to the edge of the PCB in the high-speed bonding pad of the golden finger to the middle of the high-speed signal through hole.

3. The design method according to claim 1, wherein the hollowing out three sides of the golden finger high-speed bonding pad non-outgoing line near the edge of one side of the PCB comprises:

digging the upper side of a high-speed bonding pad of a golden finger close to one side edge of the PCB into 11mil, digging the left side into 14mil and digging the lower side into 9.9mil;

hollowing out four sides of the high-speed bonding pad of the golden finger close to the edge of the other side of the PCB, comprising:

and hollowing out the upper side of the high-speed bonding pad of the golden finger close to the edge of the other side of the PCB by 11mil, hollowing out the left side by 14mil, hollowing out the lower side by 9.9mil and hollowing out the right side by 14mil.

4. The method of designing according to claim 1, wherein the hollowing out the high-speed signal via according to the hollowing out data includes:

the size of the hollowed-out area of the high-speed signal VIA hole is set to 58 x 30mil, and the hollowed-out area is hollowed out by using VIA16D8, a VIA hole specification with a distance of 12mil and a line with a distance of 30 mil.

5. The method of designing according to claim 1, wherein hollowing out the AC capacitor according to the hollowing out data includes:

the size of the hollowed-out area of the AC capacitor is set to 38 mm, and the AC capacitor is hollowed out so that each pin of the AC capacitor extends by 3 mm;

and hollowing down two layers from the layer where the AC capacitor is located, wherein the layer where the AC capacitor is located is not included.

6. The design method according to claim 5, further comprising:

when the high-speed signal via hole and the AC capacitor are hollowed, the high-speed signal via Kong Wakong and the AC capacitor are hollowed to form a ground, and the air space between the hollowed AC capacitor and the hollowed high-speed signal via hole is not smaller than 20mil.

7. The method of designing according to claim 6, wherein punching the reflowed via around the AC capacitor and the high-speed signal via comprises:

four reflow ground holes are formed around the AC capacitor or the high-speed signal via hole, wherein the four reflow ground via holes are uniformly and symmetrically arranged on the outer side of the hollowed-out area, and the ground pad does not enter the hollowed-out area.

8. The design method according to any one of claims 1-7, further comprising:

setting the spacing between different high-speed signal through holes to be not less than 1.5mm;

aiming at two high-speed signal through holes in parallel relation, more than one ground through hole is arranged on the straight line distance of the two high-speed signal through holes;

a ground via is drilled alongside the AC capacitance, the ground via being connected to at least the ground of the fourth layer.

9. The design method according to any one of claims 1-7, further comprising:

obtaining an insertion loss value, determining the line length of a high-speed line according to the insertion loss value, and setting the high-speed line in an inner layer;

determining a reference layer according to the wiring condition of the high-speed line, and increasing the PP value of the reference layer and the line width of the high-speed line;

and the PCB surface is treated by adopting low-loss ink, low-roughness browning liquid medicine and a low-loss factor material.

10. A 400G self-loop optical module PCB, wherein the PCB is designed according to the method for designing a 400G self-loop optical module PCB according to any one of claims 1-9.