CN117527529B - Ethernet data storage method and device capable of automatically recovering from normal state - Google Patents
Ethernet data storage method and device capable of automatically recovering from normal state Download PDFInfo
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- 230000011218 segmentation Effects 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 5
- 238000004590 computer program Methods 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 6
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- 238000004891 communication Methods 0.000 description 3
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- 208000025274 Lightning injury Diseases 0.000 description 2
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- 230000005012 migration Effects 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
Abstract
The application discloses an Ethernet data storage method and device capable of automatically recovering from normal, wherein the method comprises the following steps: acquiring an Ethernet packet and segmenting the Ethernet packet to obtain a sub Ethernet packet; writing Ethernet packet data into a random cache, and recording index information of the Ethernet packet; when the data of the sub Ethernet packet is written, corresponding index information is written into a memory, and a null signal of the memory is detected; if the null signal is low, any index information in the memory is read, and the index information is analyzed; reading data in a random cache by taking a head address in the analyzed current index information as a cache reading address, and increasing the data cache reading data address of each sub Ethernet packet until the cache reading address is equal to the length of the sub Ethernet packet; if the null signal is high, the reading is stopped. The problem that the buffer memory read-write address is overturned abnormally and cannot be automatically recovered to be normal is solved, and the Ethernet cache can be automatically recovered without external force intervention.
Description
Technical Field
The present disclosure relates to the field of ethernet communications technologies, and in particular, to a method and an apparatus for storing ethernet data capable of automatically recovering from normal.
Background
In the ethernet logic circuit, processing such as switching requires buffering ethernet packet data. However, in the actual operation process of the circuit, the counter is abnormal due to various reasons, such as electromagnetic interference, lightning stroke, even strong radiation single event effect in the space, and the like, so that the system is crashed. In addition, the Ethernet packets, the packet interval packet length and the like are random, when a long packet is mixed in a short packet, if the processing is not performed, if the processing is performed after receiving a packet, the data is sent outwards, the writing speed of a buffer area is high, the data reading speed is low, and the effective communication speed of a circuit is reduced.
In the prior art, a patent with application number CN202211397502.3 divides a buffer memory into a plurality of blocks according to a preset minimum unit or integer multiple of the minimum unit, receives a data packet of an input port, stores the received data in a corresponding buffer memory, and effectively improves the utilization rate and access speed of the buffer memory space. However, the patent has obvious defects that if a certain bit of the cache read-write address is abnormally overturned due to the interference of lightning stroke and the like, the normal state cannot be automatically recovered, and reset or power-off restarting is needed. For the Ethernet packet, the integrity of the packet after the Ethernet packet is buffered cannot be ensured to be accurate. In addition, when the data written into the cache is smaller than the cache space of the preset minimum unit, the waste of cache resources is caused.
Disclosure of Invention
According to the Ethernet data storage method and device capable of automatically recovering the normal state, the problem that in the prior art, a certain bit of a cache read-write address is abnormally overturned and cannot be automatically recovered is solved, and the fact that no external force is needed to intervene after a circuit is instantaneously abnormal due to abnormal interference is achieved, so that the normal Ethernet cache can be automatically recovered.
In a first aspect, an embodiment of the present application provides an ethernet data storage method capable of automatically restoring normal, including: acquiring an Ethernet packet and segmenting the Ethernet packet to obtain a sub Ethernet packet; writing the data of the sub Ethernet packets into a random cache, and recording the index information of the sub Ethernet packets; the index information comprises packet header information, packet tail information, length of the sub Ethernet packet and a head address of the sub Ethernet packet in the random cache; writing the corresponding index information into a memory after the sub Ethernet packet data are written, and detecting an empty signal of the memory; if the empty signal of the memory is detected to be low, reading one index information in the memory, and analyzing the index information; reading the data in the random cache by taking the head address in the analyzed current index information as a cache read address, and adding one cache read data address to each sub-Ethernet packet data read until the cache read address is equal to the length of the sub-Ethernet packet; if the empty signal of the memory is detected to be high, the reading is stopped.
With reference to the first aspect, in a first possible implementation manner, the obtaining and segmenting the ethernet packet to obtain a sub ethernet packet includes: acquiring the length of the Ethernet packet and determining the segmentation number of the Ethernet packet; and determining the length of the divided sub Ethernet packet according to the number of the segments.
With reference to the first aspect, in a second possible implementation manner, the reading any one of the index information in the memory includes: and starting read control, sending a read pulse to the memory and reading one of the index information.
With reference to the first aspect, in a third possible implementation manner, the reading data in the random cache further includes: the read control module detects whether the current empty signal is low or not before the data is read; if the current null signal is low, continuing to read data, and marking the head and tail of the sub Ethernet packet according to the index information of the current sub Ethernet packet; and if the current null signal is high, stopping reading the data.
With reference to the first aspect, in a fourth possible implementation manner, the writing the corresponding index information into the memory further includes: designing a write index for the memory; the write index is used for storing the head address, the length and the packet head identifier or the packet tail identifier of each sub Ethernet packet written into the memory.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner, the detecting the empty signal of the memory includes: acquiring the current writing index; if the current write index is a packet header mark, the null signal corresponding to the sub Ethernet packet is high; and if the current write index is a packet tail mark, the null signal corresponding to the sub Ethernet packet is low.
With reference to the third possible implementation manner of the first aspect, in a sixth possible implementation manner, a read address counter is disposed in the read control module.
In a second aspect, an embodiment of the present application provides an ethernet data storage device capable of automatically recovering from normal, which is characterized in that the device includes: the segmentation module is used for acquiring the Ethernet packet and segmenting the Ethernet packet to obtain a sub Ethernet packet; the writing module is used for writing the data of the sub Ethernet packets into the random cache and recording the index information of the sub Ethernet packets; the index information comprises packet header information, packet tail information, length of the sub Ethernet packet and a head address of the sub Ethernet packet in the random cache; the detection module is used for detecting the position of the object, for each sub Ethernet packet data writing the corresponding index information is then written to memory, and detecting an empty signal of the memory; the first reading module is used for reading one index information in the memory and analyzing the index information if the empty signal of the memory is detected to be low; the second reading module is used for reading the data in the random cache by taking the head address in the analyzed current index information as a cache reading address, and increasing the cache reading data address by one every time when one piece of sub-Ethernet packet data is read until the cache reading address is equal to the length of the sub-Ethernet packet; and the stopping module is used for stopping reading if the empty signal of the memory is detected to be high.
With reference to the second aspect, in a first possible implementation manner, the acquiring and segmenting the ethernet packet to obtain the sub-ethernet packet includes: acquiring the length of the Ethernet packet and determining the segmentation number of the Ethernet packet; and determining the length of the divided sub Ethernet packet according to the number of the segments.
With reference to the second aspect, in a second possible implementation manner, the reading any one of the index information in the memory includes: and starting read control, sending a read pulse to the memory and reading one of the index information.
With reference to the second aspect, in a third possible implementation manner, the reading data in the random cache further includes: the read control module detects whether the current empty signal is low or not before the data is read; if the current null signal is low, continuing to read data, and marking the head and tail of the sub Ethernet packet according to the index information of the current sub Ethernet packet; and if the current null signal is high, stopping reading the data.
With reference to the second aspect, in a fourth possible implementation manner, the writing the index information corresponding to the index information into a memory further includes: designing a write index for the memory; the write index is used for storing the head address, the length and the packet head identifier or the packet tail identifier of each sub Ethernet packet written into the memory.
With reference to the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner, the detecting a null signal of the memory includes: acquiring the current writing index; if the current write index is a packet header mark, the null signal corresponding to the sub Ethernet packet is high; and if the current write index is a packet tail mark, the null signal corresponding to the sub Ethernet packet is low.
With reference to the third possible implementation manner of the second aspect, in a sixth possible implementation manner, a read address counter is disposed in the read control module.
In a third aspect, embodiments of the present application provide an apparatus, including: a processor; a memory for storing processor-executable instructions; the processor, when executing the executable instructions, implements a method as described in the first aspect or any one of the possible implementations of the first aspect.
In a fourth aspect, embodiments of the present application provide a non-transitory computer readable storage medium comprising instructions for storing a computer program or instructions which, when executed, cause a method as described in the first aspect or any one of the possible implementations of the first aspect to be implemented.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
according to the embodiment of the application, the reading efficiency of the data can be improved through the index information; whether the data is read or not is controlled by the high-low level of the memory null signal, so that the integrity of the Ethernet packet can be ensured; by means of the random cache and the memory, the complete Ethernet packet can be automatically recovered after the system is abnormal. The problem that the normal state cannot be automatically recovered after a certain bit of the cache read-write address is overturned abnormally in the prior art is effectively solved, the problem that no external force is needed to intervene after the circuit is instantaneously abnormal due to abnormal interference is realized, the normal Ethernet cache can be automatically recovered, and the integrity of an Ethernet packet is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the embodiments of the present application or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of an ethernet data storage method capable of automatically restoring normal according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an ethernet data storage device capable of automatically recovering from normal according to an embodiment of the present application;
fig. 3 is a schematic block diagram of an ethernet packet according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a read module and a write module read-write process provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Some of the techniques involved in the embodiments of the present application are described below to aid understanding, and they should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, for the sake of clarity and conciseness, descriptions of well-known functions and constructions are omitted in the following description.
Fig. 1 is a flowchart of a method for automatically recovering ethernet data according to an embodiment of the present application, including steps 101 to 108. Wherein fig. 1 is only one execution order shown in the embodiments of the present application, and does not represent a unique execution order of an ethernet data storage method capable of automatically restoring to normal, and the steps shown in fig. 1 may be executed in parallel or in reverse in case that the final result is achieved.
Step 101: and obtaining the Ethernet packet and segmenting the Ethernet packet to obtain the sub Ethernet packet. In the embodiment of the application, the length of the Ethernet packet is obtained, and the number of segments of the Ethernet packet is determined. The ethernet packet is, illustratively, 1518 bytes in length, which is divided into 24 segments by the write control module. The length of the divided sub-ethernet packets is determined according to the number of segments. Illustratively, an ethernet packet with a length of 1518 bytes is divided into 24-segment sub-ethernet packets, the first 23-segment sub-ethernet packets each having a length of 64 bytes, as shown in fig. 3, where n is equal to 64 bytes, and the last segment sub-ethernet packet has a length of 46 bytes, i.e., m is equal to 46 bytes in fig. 3.
Step 102: and writing the sub Ethernet packet data into a random cache, and recording index information of the sub Ethernet packet. In the embodiment of the application, the random cache ram is designed to be 8 bits wide and 4096 bits deep. The index information comprises packet header information, packet tail information, length and head address of the sub Ethernet packet in random cache. And the Ethernet packet data, namely the data of each sub Ethernet packet, is written into the random cache ram through the write control module. The data reading process is shown in fig. 4.
In the embodiment of the application, a write address counter is arranged in the random cache. Illustratively, a 12-bit wide write address counter waddr is designed, which is incremented by 1 for each byte written, and ethernet packets are written to the random cache ram.
Step 103: every time Ethernet packet data writing is completed and writing the corresponding index information into the memory. In the embodiment of the application, after the last byte in the sub ethernet packet is written into the random cache, the index information corresponding to the sub ethernet packet is written into the memory. Illustratively, the memory is a Fifo memory that is 20 bits wide by 128.
Furthermore, the write index is designed for memory and is 20 bits wide. The write index is used for recording the head address, the length and the packet head identifier or the packet tail identifier of each sub Ethernet packet written into the memory.
Step 104: a memory empty signal is detected and a determination is made as to whether it is high. In the embodiment of the application, the level of the null signal of the sub-ethernet packet stored in the memory at the moment is detected and judged. Specifically, the current write index is obtained. If the current write index is the header flag and the current sub-ethernet packet is the ethernet header, the null signal of the corresponding sub-ethernet packet is high. If the current write index is the packet tail flag and the current sub-ethernet packet is the ethernet tail, the null signal of the corresponding sub-ethernet packet is low. If the current empty signal of the memory is not high, steps 105 to 107 are executed, as follows.
Step 105: and reading index information in the memory, and analyzing the index information. In the embodiment of the application, read control is started, and a read pulse is sent to the memory and one of the index information is read. And analyzing the acquired index information, and acquiring the head address of the data read from the random cache ram, the number of the read addresses, the packet head and packet tail information of the sub Ethernet packet corresponding to the current data, and the like.
Step 106: and reading the data in the random cache by taking the head address in the analyzed current index information as a cache reading address, and increasing one address for reading the data in the data cache of one sub Ethernet packet per reading. In this embodiment of the present application, the read control module caches the read address around the first address of the record in the index information of the sub ethernet packet corresponding to the current data, and reads the corresponding data from the random cache ram.
In the embodiment of the application, a read address counter is arranged in the read control module. Each time the read control module reads one data from the random cache ram, the data address raddr is controlled to be increased by 1, and meanwhile, the read address counter is also increased by one value. The read address counter is used to track the data addresses currently in use, and the value by which the address counter is incremented is determined by the memory size of the computer and the number of memory addresses that have been currently in use.
In addition, the read control module detects whether the current empty signal is low before the data is read. If the current null signal is low, continuing to read the data, and marking the head and tail of the sub-Ethernet packet according to the index information of the current sub-Ethernet packet. If the current null signal is high, the reading of data is stopped.
Step 107: it is determined whether the buffered read address is equal to the length of the sub-ethernet packet. Specifically, it is determined whether the address of the currently read sub ethernet packet is equal to the corresponding length recorded in the index information thereof. If the address of the sub Ethernet packet read currently is not equal to the corresponding length recorded in the index information, continuing to read the data. If the address of the sub ethernet packet currently read is equal to the corresponding length recorded in the index information, step 108 is performed.
If the current empty signal of the memory is high, step 108 is performed, as follows.
Step 108: the reading is stopped. Specifically, if the address of the currently read sub ethernet packet is equal to the corresponding length recorded in the index information thereof or if the current empty signal of the memory is low, the data reading is stopped.
Although the present application provides method operational steps as described in the examples or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive labor. The order of steps recited in the present embodiment is only one way of performing the steps in a plurality of steps, and does not represent a unique order of execution. When implemented by an actual device or client product, the method of the present embodiment or the accompanying drawings may be performed sequentially or in parallel (e.g., in a parallel processor or a multithreaded environment).
As shown in fig. 2, the embodiment of the present application further provides an ethernet data storage device 200 that can automatically restore to normal. The device comprises: the segmentation module 201, the writing module 202, the detection module 203, the first reading module 204, the second reading module 205, and the stopping module 206 are specifically as follows.
The segmentation module 201 is configured to obtain an ethernet packet and segment the ethernet packet to obtain a sub-ethernet packet. The segmentation module 201 is specifically configured to obtain the length of the ethernet packet and determine the number of segments of the ethernet packet. The ethernet packet is, illustratively, 1518 bytes in length, which is divided into 24 segments by the write control module. The length of the divided sub-ethernet packets is determined according to the number of segments. Illustratively, an ethernet packet with a length of 1518 bytes is divided into 24-segment sub-ethernet packets, the first 23-segment sub-ethernet packets each having a length of 64 bytes, as shown in fig. 3, where n is equal to 64 bytes, and the last segment sub-ethernet packet has a length of 46 bytes, i.e., m is equal to 46 bytes in fig. 3.
The writing module 202 is configured to write the sub ethernet packet data into the random cache, and record index information of the sub ethernet packet; wherein; the index information comprises packet header information, packet tail information, length and head address of the sub Ethernet packet in random cache. The write module 202 is specifically configured to design a random cache ram 8 bits wide by 4096 bits deep. The index information comprises header information, tail information of the Ethernet packet, a head address of the sub Ethernet packet in random cache and the length of the sub Ethernet packet. And the Ethernet packet data, namely the data of each sub Ethernet packet, is written into the random cache ram through the write control module. The data reading process is shown in fig. 4.
In the embodiment of the application, a write address counter is arranged in the random cache. Illustratively, a 12-bit wide write address counter waddr is designed, which is incremented by 1 for each byte written, and ethernet packets are written to the random cache ram.
The detection module 203 is configured to write the corresponding index information into the memory every time the ethernet packet data is written, and detect a null signal of the memory. The detection module 203 is specifically configured to write index information corresponding to the sub ethernet packet into the memory after writing the last byte in the sub ethernet packet into the random cache. Illustratively, the memory is a Fifo memory that is 20 bits wide by 128.
Furthermore, the write index is designed for memory and is 20 bits wide. The write index is used for recording the head address, the length and the packet head identifier or the packet tail identifier of each sub Ethernet packet written into the memory.
And detecting and judging the empty signal of the sub Ethernet packet stored in the memory at the moment. Specifically, the current write index is obtained. If the current write index is the header flag and the current sub-ethernet packet is the ethernet header, the null signal of the corresponding sub-ethernet packet is high. If the current write index is the packet tail flag and the current sub-ethernet packet is the ethernet tail, the null signal of the corresponding sub-ethernet packet is low. If the current empty signal of the memory is not high, go to the first read module 204 and the second read module 205. If the current empty signal of the memory is high, then it goes to stop block 206.
The first reading module 204 is configured to read one index information in the memory and parse the index information if the empty signal of the memory is detected to be low. The first reading module 204 is specifically configured to perform dynamic reading control, send a reading pulse to the memory, and read one of the index information. And analyzing the acquired index information, and acquiring the head address of the data read from the random cache ram, the number of the read addresses, the packet head and packet tail information of the sub Ethernet packet corresponding to the current data, and the like.
The second reading module 205 is configured to read data in the random cache using the first address in the parsed current index information as a cache read address, and increase the cache read data address of each sub ethernet packet until the cache read address is equal to the length of the sub ethernet packet. The second reading module 205 is specifically configured to cache a reading address around a first address of a record in index information of a sub ethernet packet corresponding to current data, and read the corresponding data from the random cache ram.
In the embodiment of the application, a read address counter is arranged in the read control module. Each time the read control module reads one data from the random cache ram, the data address raddr is controlled to be increased by 1, and meanwhile, the read address counter is also increased by one value. The read address counter is used to track the data addresses currently in use, and the value by which the address counter is incremented is determined by the memory size of the computer and the number of memory addresses that have been currently in use.
In addition, the read control module detects whether the current empty signal is low before the data is read. If the current null signal is low, continuing to read the data, and marking the head and tail of the sub-Ethernet packet according to the index information of the current sub-Ethernet packet. If the current null signal is high, the reading of data is stopped.
And judging whether the address of the sub Ethernet packet read currently is equal to the corresponding length recorded in the index information of the sub Ethernet packet. If the address of the sub Ethernet packet read currently is not equal to the corresponding length recorded in the index information, continuing to read the data. If the address of the currently read sub-ethernet packet is equal to the corresponding length recorded in the index information, the process goes to the stop module 206.
The stop module 206 is configured to stop reading if the empty signal of the memory is detected to be high. The stopping module 206 is specifically configured to stop reading data if the address of the currently read sub-ethernet packet is equal to the corresponding length recorded in the index information thereof or if the current empty signal of the memory is low.
Some of the modules of the apparatus described herein may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, classes, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The apparatus or module set forth in the embodiments of the application may be implemented in particular by a computer chip or entity, or by a product having a certain function. For convenience of description, the above devices are described as being functionally divided into various modules, respectively. The functions of the modules may be implemented in the same piece or pieces of software and/or hardware when implementing the embodiments of the present application. Of course, a module that implements a certain function may be implemented by a plurality of sub-modules or a combination of sub-units.
The methods, apparatus or modules described herein may be implemented in computer readable program code means and in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (english: application Specific Integrated Circuit; abbreviated: ASIC), programmable logic controllers and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller can be regarded as a hardware component, and means for implementing various functions included therein can also be regarded as a structure within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.
The embodiment of the application also provides equipment, which comprises: a processor; a memory for storing processor-executable instructions; the processor, when executing the executable instructions, implements a method as described in embodiments of the present application.
The embodiments also provide a non-transitory computer readable storage medium having stored thereon a computer program or instructions which, when executed, cause a method as described in the embodiments of the present application to be implemented.
In addition, each functional module in the embodiments of the present invention may be integrated into one processing module, each module may exist alone, or two or more modules may be integrated into one module.
The storage medium includes, but is not limited to, a random access Memory (hereinafter referred to as RAM), a Read-Only Memory (hereinafter referred to as ROM), a Cache Memory (hereinafter referred to as Cache), a Hard disk (hereinafter referred to as HDD), or a Memory card (hereinafter referred to as Memory card). The memory may be used to store computer program instructions.
From the description of the embodiments above, it will be apparent to those skilled in the art that the present application may be implemented in software plus necessary hardware. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product, or may be embodied in the implementation of data migration. The computer software product may be stored on a storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., comprising instructions for causing a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to perform the methods described in various embodiments or portions of embodiments herein.
In this specification, each embodiment is described in a progressive manner, and the same or similar parts of each embodiment are referred to each other, and each embodiment is mainly described as a difference from other embodiments. All or portions of the present application can be used in a number of general purpose or special purpose computer system environments or configurations. For example: personal computers, server computers, hand-held or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, distributed computing environments that include any of the above systems or devices, and the like.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the present application; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions.
Claims (10)
1. An ethernet data storage method capable of automatically restoring normal, comprising:
acquiring an Ethernet packet and segmenting the Ethernet packet to obtain a sub Ethernet packet;
writing the data of the sub Ethernet packets into a random cache, and recording the index information of the sub Ethernet packets; the index information comprises packet header information, packet tail information, length of the sub Ethernet packet and a head address of the sub Ethernet packet in the random cache;
writing the corresponding index information into a memory after the sub Ethernet packet data are written, and detecting an empty signal of the memory;
if the empty signal of the memory is detected to be low, reading one index information in the memory, and analyzing the index information;
reading the data in the random cache by taking the head address in the analyzed current index information as a cache read address, and adding one cache read data address to each sub-Ethernet packet data read until the cache read address is equal to the length of the sub-Ethernet packet;
if the empty signal of the memory is detected to be high, the reading is stopped.
2. The method of claim 1, wherein the obtaining and segmenting the ethernet packet into sub-ethernet packets comprises:
acquiring the length of the Ethernet packet and determining the segmentation number of the Ethernet packet;
and determining the length of the divided sub Ethernet packet according to the number of the segments.
3. The method of claim 1, wherein said reading one of said index information in said memory comprises:
and starting read control, sending a read pulse to the memory and reading one of the index information.
4. The method of claim 1, wherein the reading the data in the random cache further comprises:
the read control module detects whether the current empty signal is low or not before the data is read;
if the current null signal is low, continuing to read data, and marking the head and tail of the sub Ethernet packet according to the index information of the current sub Ethernet packet;
and if the current null signal is high, stopping reading the data.
5. The method of claim 1, wherein writing the corresponding index information to a memory further comprises:
designing a write index for the memory;
the write index is used for storing the head address, the length and the packet head identifier or the packet tail identifier of each sub Ethernet packet written into the memory.
6. The method of claim 5, wherein detecting a null signal of the memory comprises:
acquiring the current writing index;
if the current write index is a packet header mark, the null signal corresponding to the sub Ethernet packet is high;
and if the current write index is a packet tail mark, the null signal corresponding to the sub Ethernet packet is low.
7. The method of claim 4, wherein a read address counter is disposed within the read control module.
8. An ethernet data storage device capable of automatically restoring to normal, comprising:
the segmentation module is used for acquiring the Ethernet packet and segmenting the Ethernet packet to obtain a sub Ethernet packet;
the writing module is used for writing the data of the sub Ethernet packets into the random cache and recording the index information of the sub Ethernet packets; the index information comprises packet header information, packet tail information, length of the sub Ethernet packet and a head address of the sub Ethernet packet in the random cache;
the detection module is used for detecting the position of the object, for each sub Ethernet packet data writing the corresponding index information is then written to memory, and detecting an empty signal of the memory;
the first reading module is used for reading one index information in the memory and analyzing the index information if the empty signal of the memory is detected to be low;
the second reading module is used for reading the data in the random cache by taking the head address in the analyzed current index information as a cache reading address, and increasing the cache reading data address by one every time when one piece of sub-Ethernet packet data is read until the cache reading address is equal to the length of the sub-Ethernet packet;
and the stopping module is used for stopping reading if the empty signal of the memory is detected to be high.
9. An apparatus for performing an automatically resettable ethernet data storage method, comprising:
a processor;
a memory for storing processor-executable instructions;
the processor, when executing the executable instructions, implements the method of any one of claims 1 to 7.
10. A non-transitory computer readable storage medium comprising instructions for storing a computer program or instructions which, when executed, cause the method of any one of claims 1 to 7 to be implemented.
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