CN117525120A - Thin film transistor, array substrate and display device - Google Patents

Thin film transistor, array substrate and display device Download PDF

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Publication number
CN117525120A
CN117525120A CN202310570167.0A CN202310570167A CN117525120A CN 117525120 A CN117525120 A CN 117525120A CN 202310570167 A CN202310570167 A CN 202310570167A CN 117525120 A CN117525120 A CN 117525120A
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China
Prior art keywords
substrate
active layer
thin film
film transistor
insulating layer
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CN202310570167.0A
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Chinese (zh)
Inventor
罗成志
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN202310570167.0A priority Critical patent/CN117525120A/en
Publication of CN117525120A publication Critical patent/CN117525120A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention relates to a thin film transistor, an array substrate and a display device. The grid electrode is arranged on one side surface of the channel part of the active layer, which is far away from the substrate, and is also arranged on one side surface of the channel part of the active layer, which is close to the substrate, and on the side surface of the channel part of the active layer, so that the control of carriers on the upper, lower, left and right sides of the active layer is realized, the control capability of the grid electrode on the channel part of the active layer is enhanced, the leakage current of the array substrate is reduced, the stability of the array substrate is improved, and the high PPI and high refresh rate products are developed, and even the functions of part of ICs are realized. And any two adjacent active layers are connected in parallel, so that the on-state current of the array substrate is increased.

Description

Thin film transistor, array substrate and display device
Technical Field
The application relates to the technical field of display, in particular to a thin film transistor, an array substrate and a display device.
Background
With the development of display technology, flat panel display devices such as liquid crystal displays (Liquid Crystal Display, LCDs) and Organic Light-Emitting diodes (OLEDs) have been widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, as they have advantages of high image quality, power saving, thin body, and wide application range.
With the continuous development of the panel industry, the display panel has higher and higher requirements on parameters such as narrow frame, high aperture ratio, high brightness, high resolution and the like, and the panel manufacturing also faces new challenges. Particularly in the emerging display technology field, such as VR/AR display, panel system integration, etc., array substrates with ultra-high PPI and sub-micron device dimensions are required. To meet these requirements, it is desirable that the size and footprint of the array device be as reduced as possible. On the other hand, in order to improve the mobility of a thin film transistor (Thin Film Transistor, abbreviated as TFT) device, it is necessary to reduce the channel length as much as possible. After the channel length of the current TFT device is reduced, small channel effect can occur to cause the increase of the leakage current and the deterioration of the stability of the TFT.
Disclosure of Invention
The invention aims to provide a thin film transistor and an array substrate, which can solve the problems of increased leakage current, poor stability and the like of a TFT (thin film transistor) caused by small channel effect when the channel length of the traditional TFT device is reduced.
In order to solve the above problems, the present invention provides a thin film transistor comprising: a substrate; at least one active layer disposed on the substrate, each of the active layers including a channel portion; at least one first insulating layer disposed on a surface of a side of each active layer close to the substrate, a surface of a side of each active layer away from the substrate, and a side of each active layer; at least one second insulating layer disposed between the substrate and the first insulating layer adjacent to the substrate, and disposed between the two first insulating layers between two adjacent active layers; at least one of the second insulating layers is provided with at least one side hole at a position corresponding to the channel portion; and the grid electrode is arranged on one side surface of the active layer farthest from the substrate, which is far away from the substrate, extends and fills the side holes, and is arranged corresponding to the channel part.
Further, the material of the first insulating layer includes an oxide, and the etching rate of the material of the second insulating layer is greater than the etching rate of the material of the first insulating layer.
Further, the width of the side hole is greater than or equal to 1/4 of the width of the channel portion.
Further, the outer edge of the side hole is flush with the outer edge of the channel portion.
Further, the number of the active layers is two or more, and any two adjacent active layers are connected in parallel.
Further, the thin film transistor further includes: an interlayer insulating layer arranged on one side of the grid electrode far away from the substrate and extending to cover the substrate; and the source-drain electrode layer is arranged on one side of the interlayer insulating layer far away from the substrate and is electrically connected with the conductive part of each active layer through a connecting piece.
Further, the conductive portion of the active layer adjacent to the substrate is electrically connected to the surface of the connecting member on the side close to the substrate through the surface of the side away from the substrate, and the conductive portion of each of the remaining active layers is electrically connected to the side surface of the connecting member.
In order to solve the above problems, the present invention provides an array substrate including the thin film transistor of the present invention.
In order to solve the above problems, the present invention provides a display device, which includes the array substrate of the present invention.
Further, the display device includes one of a liquid crystal display device and an organic light emitting semiconductor display device.
The invention has the advantages that: according to the invention, the second insulating layer is arranged between the substrate and the first insulating layer adjacent to the substrate and between the two first insulating layers adjacent to the two active layers, then the side holes are formed on the second insulating layer, the grid electrode is arranged on the surface of the side of the active layer farthest from the substrate, which is far away from the substrate, and extends and fills the side holes, and is arranged corresponding to the channel part, so that the grid electrode is arranged on the surface of the side of the channel part of the active layer, which is far away from the substrate, and is also arranged on the surface of the side of the channel part of the active layer, which is close to the substrate, and on the side of the channel part of the active layer, thereby realizing the control of carriers on the upper, lower, left and right sides of the active layer, enhancing the control capability of the grid electrode to the channel part of the active layer, reducing the leakage current of the array substrate, improving the stability of the array substrate, being beneficial to developing high PPI, high refresh rate products and even realizing the functions of part of ICs. And increasing the on-state current of the array substrate by connecting any two adjacent active layers in parallel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural view of a thin film transistor according to embodiment 1 of the present invention;
fig. 2 is a schematic cross-sectional view of a thin film transistor according to embodiment 1 of the present invention;
fig. 3 is a schematic cross-sectional view of a thin film transistor according to embodiment 1 of the present invention;
FIG. 4 is a schematic cross-sectional view of a multilayer active layer structure fabricated on a substrate according to example 1 of the present invention;
FIG. 5 is a schematic cross-sectional view of a multilayer active layer structure fabricated on a substrate according to example 1 of the present invention;
FIG. 6 is a schematic cross-sectional view of the treatment of a multi-layer active layer structure with O3 plasma according to example 1 of the present invention;
FIG. 7 is a schematic cross-sectional view of a multilayer active layer structure treated with O3 plasma according to example 1 of the present invention;
FIG. 8 is a schematic cross-sectional view of a side hole made in accordance with example 1 of the present invention;
FIG. 9 is a schematic cross-sectional view of a side hole according to example 1 of the present invention;
FIG. 10 is a schematic cross-sectional view of a gate electrode according to example 1 of the present invention;
FIG. 11 is a schematic diagram of a second cross-section of a gate electrode prepared according to example 1 of the present invention;
fig. 12 is a schematic cross-sectional view of a conductive portion formed by heavily doping P ions in embodiment 1 of the present invention;
fig. 13 is a schematic cross-sectional view of an interlayer insulating layer prepared in example 1 of the present invention;
fig. 14 is a schematic diagram of a cross section of a thin film transistor according to embodiment 2 of the present invention;
fig. 15 is a schematic structural view of a thin film transistor according to embodiment 3 of the present invention;
fig. 16 is a schematic structural view of a thin film transistor according to embodiment 4 of the present invention.
Reference numerals illustrate:
100. a thin film transistor;
1. a substrate; 2. A buffer layer;
3. an active layer; 4. A first insulating layer;
5. a second insulating layer; 6. A gate;
7. an interlayer insulating layer; 8. A source/drain layer;
9. a connecting piece; 10. A Poly-Si layer;
31. a channel portion; 32. A conductive portion;
51. side holes.
Detailed Description
The following detailed description of the preferred embodiments of the invention, taken in conjunction with the accompanying drawings, is provided to fully convey the substance of the invention to those skilled in the art, and to illustrate the invention to practice it, so that the technical disclosure of the invention will be made more clear to those skilled in the art to understand how to practice the invention more easily. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as limited to the set forth herein.
The directional terms used herein, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are used for explaining and describing the present invention only in terms of the directions of the drawings and are not intended to limit the scope of the present invention.
In the drawings, like structural elements are referred to by like reference numerals and components having similar structure or function are referred to by like reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of understanding and description, and the present invention is not limited to the size and thickness of each component.
The invention provides a display device, which comprises an array substrate. The display device includes one of a liquid crystal display device and an organic light emitting semiconductor display device. The array substrate includes a thin film transistor.
Example 1
As shown in fig. 1, 2 and 3, the present embodiment provides a thin film transistor 100. The thin film transistor 100 includes: a substrate 1, a buffer layer 2, at least one active layer 3, at least one first insulating layer 4, at least one second insulating layer 5, a gate electrode 6, an interlayer insulating layer 7, and a source drain electrode layer 8. The present embodiment is described in detail taking three active layers 3 as an example, and in other embodiments, there may be one active layer 3, two active layers 3, or more active layers 3.
Wherein, the material of the substrate 1 is one or more of glass, polyimide, polycarbonate, polyethylene terephthalate and polyethylene naphthalate. In this embodiment, the substrate 1 is made of glass.
Wherein the buffer layer 2 is covered on the substrate 1. The buffer layer 2 mainly plays a role of buffering, and its material may be SiOx or SiNx or a combination structure of SiNx and SiOx.
Wherein at least one active layer 3 is arranged on the surface of the buffer layer 2 on the side remote from the substrate 1. Each of the active layers 3 includes a channel portion 31 and conductive portions 32 provided at both ends of the channel portion 31. In this embodiment, the material of the active layer 3 is low temperature polysilicon (Low Temperature Poly-Silicon, LTPS).
The first insulating layers 4 are disposed on a surface of a side of each active layer 3, which is close to the substrate 1, a surface of a side of each active layer 3, which is far away from the substrate 1, and a side of each active layer 3, so that the first insulating layers 4 surround the active layers 3, and a short circuit phenomenon is prevented from occurring due to contact between the active layers 3 and the gate electrode 6. Wherein, the material of the first insulating layer 4 comprises oxide. For example: silicon oxide, aluminum oxide, palladium oxide, and the like. In this embodiment, the material of the first insulating layer 4 is silicon oxide (SiOx).
Wherein a second insulating layer 5 is disposed between the substrate 1 and the first insulating layers 4 adjacent to the substrate 1, and between two first insulating layers 4 between two adjacent active layers 3.
The etching rate of the material of the second insulating layer 5 is greater than that of the material of the first insulating layer 4, so that the side holes 51 are formed on the second insulating layer 5 on the basis of not damaging the first insulating layer 4. In this embodiment, the material of the second insulating layer 5 is SiNx.
Wherein at least one of the second insulating layers 5 is provided with at least one side hole 51 at a position corresponding to the channel portion 31.
As shown in fig. 3, the outer edge of the side hole 51 is flush with the outer edge of the channel portion 31.
Wherein the width L1 of the side hole 51 is greater than or equal to 1/4 of the width L2 of the channel portion 31. In this embodiment, the width L1 of the side hole 51 is equal to the width L2 of the channel portion 31. This increases the coverage area of the gate electrode 6 on the channel portion 31, and thus the controllability of the gate electrode 6 to the channel portion 31 of the active layer 3.
The gate electrode 6 is disposed on a surface of the active layer 3 farthest from the substrate 1, which is away from the substrate 1, and extends and fills the side hole 51, and is disposed corresponding to the channel portion 31. Through setting up side opening 51 on second insulating layer 5, be convenient for grid 6 fills in the side opening for grid 6 not only sets up in the channel portion 31 of active layer 3 keep away from one side surface of base plate 1, still set up on the channel portion 31 of active layer 3 is close to on one side surface of base plate 1 and the side of channel portion 31 of active layer 3, realize the control to the carrier of the upper and lower left and right sides of active layer 3, strengthen the controllability of grid 6 to channel portion 31 of active layer 3, reduce array substrate's leakage current, promote array substrate's stability, be favorable to developing high PPI, high refresh rate product, even realize partial IC's function.
The material of the gate 6 may be Mo, ti, W, a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, cu and IZO, a combination of IZO, cu and IZO, a combination of Mo, cu and ITO, a combination of Ni, cu and Ni, a combination of MoTiNi, cu and MoTiNi, a combination of NiCr, cu and NiCr, or CuNb.
The interlayer insulating layer 7 is disposed on a side of the gate electrode 6 away from the substrate 1, and extends to cover the buffer layer 2. The interlayer insulating layer 7 may be made of SiOx, siNx, or SiNOx. The interlayer insulating layer 7 can effectively prevent the short circuit phenomenon from occurring in contact between the gate electrode 6 and the source/drain electrode layer 8.
The source-drain electrode layer 8 is disposed on a side of the interlayer insulating layer 7 away from the substrate 1, and is electrically connected to the conductive portion 32 of each active layer 3 through a connection member 9. The source/drain layer 8 may be made of Mo, ti, W, al, cu, a combination of Mo and Al, a combination of Mo, cu and IZO, a combination of IZO, cu and IZO, a combination of Mo, cu and ITO, a combination of Ni, cu and Ni, a combination of MoTiNi, cu and MoTiNi, a combination of NiCr, cu and NiCr, or CuNb.
The number of the active layers 3 is two or more, the number of the active layers 3 in this embodiment is 3, and any two adjacent active layers 3 are connected in parallel. Specifically, the conductive portion 32 of the active layer 3 adjacent to the substrate 1 is electrically connected to the surface of the connection member 9 on the side close to the substrate 1 through the surface of the side away from the substrate 1, and the conductive portion 32 of each of the remaining active layers 3 is electrically connected to the side surface of the connection member 9. In other words, the upper surface of the conductive portion 32 of the lowermost active layer 3 is electrically connected to the lower surface of the connection member 9, and the conductive portions 32 of the remaining active layers 3 are electrically connected to the side surfaces of the connection member. And increasing the on-state current of the array substrate by connecting any two adjacent active layers 3 in parallel.
The embodiment also provides a preparation method of the thin film transistor, which comprises the following steps.
As shown in fig. 4 and 5, S1, a substrate 1 is provided, a second insulating layer, a first insulating layer, an a-Si layer and a first insulating layer are sequentially deposited on the substrate 1, then the a-Si layer is converted into a Poly-Si layer by an excimer laser annealing process, and then the above steps are repeated again to form a multi-layer active layer structure.
As shown in fig. 6 and 7, S2, the aforementioned multi-layer active layer structure is treated with O3 plasma to generate SiOx on the side surface of the active layer 3, so that the first insulating layer 4 is disposed on the surface of each active layer 3 on the side close to the substrate 1, the surface of each active layer 3 on the side far from the substrate 1, and the side surface of each active layer 3, so that the first insulating layer 4 surrounds the active layer 3, and the short circuit phenomenon is prevented from occurring due to the contact between the active layer 3 and the gate electrode 6.
As shown in fig. 8 and 9, S3 exposes only the channel region by exposing the non-channel region (i.e., the region where the conductive portion is formed later) to light and covering the non-channel region with photoresist. And then the second insulating layer 5 uncovered by the photoresist is laterally etched by dry etching to form the side holes 51.
As shown in fig. 10 and 11, S4, a gate material layer is deposited by magnetron sputtering, and the film formation rate is reduced as much as possible, so that the gate material fills the side holes 51 sufficiently. The gate electrode 6 is then formed by exposure and etching.
As shown in fig. 12, S5, P ion heavy doping is performed with the gate electrode 6 as a mask, and Poly-Si without shielding by the gate electrode 6 will form N-type doped Poly-Si (Np-Poly) as the conductive portion 32.
As shown in fig. 13, S6, an interlayer insulating material layer is deposited, then a hydrogen activation process is performed through high temperature treatment, and then exposure and via etching are performed to form an interlayer insulating layer 7. Note that the via hole in the interlayer insulating layer 7 needs to pass through the upper two active layers 3 to reach the upper surface of the lower active layer 3. Therefore, the connecting piece 9 formed by filling the via holes in the later period connects any two adjacent active layers 3 in parallel, and the on-state current of the array substrate is increased.
As shown in fig. 2, S7, a source/drain material layer is deposited, and then the source/drain layer 8 and the connection member 9 are formed through exposure and etching.
According to the method, the second insulating layer 5 is used as a sacrificial layer, the side holes 51 are formed in the second insulating layer 5, then the grid electrode 6 is filled in the side holes 51, the grid electrode 6 is further arranged on one side surface of the channel part 31 of the active layer 3, which is far away from the substrate 1, and is further arranged on one side surface of the channel part 31 of the active layer 3, which is close to the substrate 1, and on the side surface of the channel part 31 of the active layer 3, so that the control of carriers on the upper, lower, left and right sides of the active layer 3 is realized, the control capability of the grid electrode 6 on the channel part 31 of the active layer 3 is enhanced, the leakage current of the array substrate is reduced, the stability of the array substrate is improved, the development of high PPI and high refresh rate products is facilitated, even the function of partial IC is realized, and the steps are finished through film formation, yellow light, etching and doping.
Example 2
As shown in fig. 14, this embodiment includes most of the technical features of embodiment 1, and is different from embodiment 1 in that the width L1 of the side hole 51 in this embodiment is equal to 1/4 of the width L2 of the channel portion. In other words, the portion of the second insulating layer 5 corresponding to the channel portion 31 in the present embodiment is not completely etched, but is partially etched, so that the coverage area of the gate electrode 6 on the channel portion 31 can be increased, and the control capability of the gate electrode 6 on the channel portion 31 of the active layer 3 can be further increased; the leakage current of the array substrate is reduced, the stability of the array substrate is improved, and the array substrate is beneficial to developing products with high PPI and high refresh rate and even realizing the functions of part of ICs.
Example 3
As shown in fig. 15, this embodiment includes most of the technical features of embodiment 1, and is different from embodiment 1 in that the number of active layers 3 in this embodiment is 2. In this embodiment, the width L1 of the side hole 51 is equal to the width L2 of the channel portion 31. This increases the coverage area of the gate electrode 6 on the channel portion 31, and thus the controllability of the gate electrode 6 to the channel portion 31 of the active layer 3. And increasing the on-state current of the array substrate by connecting any two adjacent active layers 3 in parallel.
Example 4
As shown in fig. 16, this embodiment includes most of the technical features of embodiment 1, and is different from embodiment 1 in that the number of active layers 3 in this embodiment is 4. In this embodiment, the width L1 of the side hole 51 is equal to the width L2 of the channel portion 31. This increases the coverage area of the gate electrode 6 on the channel portion 31, and thus the controllability of the gate electrode 6 to the channel portion 31 of the active layer 3. And increasing the on-state current of the array substrate by connecting any two adjacent active layers 3 in parallel.
The above details of a thin film transistor, an array substrate and a display device provided in the present application, and specific examples are applied to illustrate the principles and embodiments of the present application, and the above examples are only used to help understand the method and core ideas of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. A thin film transistor, comprising:
a substrate;
at least one active layer disposed on the substrate, each of the active layers including a channel portion;
at least one first insulating layer disposed on a surface of a side of each active layer close to the substrate, a surface of a side of each active layer away from the substrate, and a side of each active layer;
at least one second insulating layer disposed between the substrate and the first insulating layer adjacent to the substrate, and disposed between the two first insulating layers between two adjacent active layers; at least one of the second insulating layers is provided with at least one side hole at a position corresponding to the channel portion; and
and the grid electrode is arranged on one side surface of the active layer farthest from the substrate, which is far away from the substrate, extends and fills the side holes, and is arranged corresponding to the channel part.
2. The thin film transistor according to claim 1, wherein the material of the first insulating layer comprises an oxide, and the material of the second insulating layer has an etching rate greater than that of the material of the first insulating layer.
3. The thin film transistor according to claim 1, wherein a width of the side hole is greater than or equal to 1/4 of a width of the channel portion.
4. The thin film transistor of claim 1, wherein an outer edge of the side hole is flush with an outer edge of the channel portion.
5. The thin film transistor according to claim 1, wherein the number of the active layers is two or more, and any two adjacent active layers are connected in parallel to each other.
6. The thin film transistor according to claim 5, further comprising:
an interlayer insulating layer arranged on one side of the grid electrode far away from the substrate and extending to cover the substrate; and
the source-drain electrode layer is arranged on one side of the interlayer insulating layer, which is far away from the substrate, and is electrically connected with the conductive part of each active layer through a connecting piece.
7. The thin film transistor according to claim 6, wherein the conductive portion of the active layer adjacent to the substrate is electrically connected to a surface of the connection member on a side close to the substrate through a surface of the active layer on a side away from the substrate, and the conductive portion of each of the remaining active layers is electrically connected to a side surface of the connection member.
8. An array substrate comprising the thin film transistor of any one of claims 1-7.
9. A display device comprising the array substrate of claim 8.
10. The display device according to claim 9, comprising one of a liquid crystal display device and an organic light-emitting semiconductor display device.
CN202310570167.0A 2023-05-19 2023-05-19 Thin film transistor, array substrate and display device Pending CN117525120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310570167.0A CN117525120A (en) 2023-05-19 2023-05-19 Thin film transistor, array substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310570167.0A CN117525120A (en) 2023-05-19 2023-05-19 Thin film transistor, array substrate and display device

Publications (1)

Publication Number Publication Date
CN117525120A true CN117525120A (en) 2024-02-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310570167.0A Pending CN117525120A (en) 2023-05-19 2023-05-19 Thin film transistor, array substrate and display device

Country Status (1)

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CN (1) CN117525120A (en)

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