CN117525064A

CN117525064A - 3D stacked field effect transistor device with PN junction structure

Info

Publication number: CN117525064A
Application number: CN202310974926.XA
Authority: CN
Inventors: 何铭; M·萨雷米; R·朴; M·阿霍桑乌尔卡里姆; H·西姆卡; 朴星一; 姜明一; 金庆好; 崔道永; 朴宰贤
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-08-05
Filing date: 2023-08-03
Publication date: 2024-02-06

Abstract

There is provided a three-dimensional stacked field effect transistor (3 DSFET) device comprising: a lower source/drain region of a first polarity type connected to the lower channel structure; an upper source/drain region of the second polarity type connected to the upper channel structure, over the lower source/drain region; and a PN junction structure between the lower source/drain region and the upper source/drain region configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a first region of a first polarity type and a second region of a second polarity type.

Description

3D stacked field effect transistor device with PN junction structure

Technical Field

Apparatuses and methods consistent with embodiments relate to a standard cell architecture of a three-dimensional (3D) stacked field effect transistor device, which includes a PN junction structure electrically isolating a lower source/drain region and an upper source/drain region from each other.

Background

The increasing demand for integrated circuits with high device density and high performance has introduced 3D stacked field effect transistor (3 DSFET) devices in which two or more field effect transistors, such as fin field effect transistors (FinFET) and nanoflake transistors, are vertically stacked. A FinFET has one or more horizontally aligned vertical fin structures as channel structures with at least three surfaces surrounded by gate structures, and a nanoflake transistor is characterized by one or more nanoflake channel layers as channel structures vertically stacked on a substrate and gate structures surrounding all four surfaces of each nanoflake channel layer. The nanoplate transistor is known as a Gate All Around (GAA) transistor, a multi-bridge channel field effect transistor (MBCFET).

However, it is also known that 3DSFET devices are difficult to manufacture due to the high device density that requires high aspect ratio patterning and isolation.

The information disclosed in this background section is technical information that the inventors have known or inferred before or during the implementation of the embodiments of the present application or that is obtained during the implementation of the embodiments of the present application. It may therefore contain information that does not constitute prior art known to the public.

Disclosure of Invention

According to an embodiment, the present disclosure provides a 3DSFET device in which a PN junction structure is formed to electrically isolate a lower source/drain region and an upper source/drain region.

According to an embodiment, a 3DSFET device is provided, which may include: a lower source/drain region of a first polarity type connected to the lower channel structure; an upper source/drain region of the second polarity type connected to the upper channel structure, over the lower source/drain region; and a PN junction structure between the lower source/drain region and the upper source/drain region configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a first region of a first polarity type and a second region of a second polarity type.

According to one embodiment, a method of fabricating a 3DSFET device is provided. The method may include: (a) Providing an intermediate 3DSFET structure, the intermediate 3DSFET structure comprising a lower channel structure and an upper channel structure above the lower channel structure; (b) Growing a lower epitaxial structure (Epi) of a first polarity type based on the lower channel structure; (c) Growing a first semiconductor layer of a second polarity type opposite to the first polarity type on the lower epitaxial structure based on the lower epitaxial structure; (d) Growing a second semiconductor layer of the first polarity type on the first semiconductor layer based on the first semiconductor layer; and (e) growing an upper epitaxial structure of a second polarity type on the second semiconductor layer based on the upper channel structure and the second semiconductor layer.

According to one embodiment, a method of fabricating a 3DSFET device is provided. The method may include: (a) Providing an intermediate 3DSFET structure comprising a substrate, a lower channel structure over the substrate, and an upper channel structure over the lower channel structure; (b) Growing an upper epitaxial structure (Epi) of a first polarity type based on the upper channel structure; (c) Growing a first semiconductor layer of a second polarity type opposite to the first polarity type on the upper epitaxial structure based on the upper epitaxial structure; (d) Growing a second semiconductor layer of the first polarity type on the first semiconductor layer based on the first semiconductor layer; and (e) growing a lower epitaxial structure of the second polarity type based on the substrate, the lower channel structure, and the second semiconductor layer.

Drawings

Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 shows a simplified structure of a 3DSFET device including a lower field effect transistor and an upper field effect transistor with a dielectric layer therebetween, according to an embodiment;

fig. 2 shows a simplified structure of a 3DSFET including a lower field effect transistor and an upper field effect transistor with a PN junction structure therebetween according to an embodiment;

fig. 3A and 3B illustrate post-simulation diagrams showing formation of a PNPN structure based on a substrate and channel structure in an intermediate 3DSFET structure, according to an embodiment;

fig. 4 illustrates a flowchart of a method of forming the PNPN structure illustrated in fig. 3A and 3B according to an embodiment;

FIGS. 5A and 5B illustrate post-simulation diagrams showing formation of a P (NPN) structure based on a substrate and a channel structure in an intermediate 3DSFET structure, in accordance with an embodiment;

fig. 5C shows a simplified structure of a 3DSFET device including the P (NPN) structure shown in fig. 5A and 5B according to an embodiment;

fig. 6 illustrates a flowchart of a method of forming the P (NPN) structure illustrated in fig. 5A-5C according to an embodiment; and

Fig. 7 is a schematic block diagram illustrating an electronic device including at least one 3d sfet device including a PN junction structure as an isolation structure between a lower source/drain region and an upper source/drain region, according to an embodiment.

Detailed Description

The embodiments of the present disclosure described herein are example embodiments, and thus, the present disclosure is not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description does not preclude the association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with the present disclosure. For example, even if an item described in a specific example or embodiment is not described in a different example or embodiment thereof, the item may be understood to be related to or combined with the different example or embodiment unless mentioned otherwise in the description thereof. Moreover, it is to be understood that all statements of the principles, aspects, examples, and embodiments of the present disclosure are intended to encompass both structural and functional equivalents thereof. Furthermore, it should be understood that such equivalents include not only currently known equivalents but also equivalents developed in the future, i.e., all devices invented to perform the same function, regardless of structure. For example, the channel layer and the sacrificial layer described herein may take different types or forms as long as the present disclosure can be applied thereto.

It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as "an element") of a semiconductor device is referred to as being "on", "over", "upper", "lower", "below", "connected to" or "coupled to" another element of the semiconductor device, it can be directly on, over, upper, lower, below, under, connected to or coupled to the other element or intervening element(s) may be present. In contrast, when an element of a semiconductor device is referred to as being "directly on," "over," "upper," "lower," "below," "beneath," "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements present. Like numbers refer to like elements throughout the disclosure.

For ease of description, spatially relative terms such as "above … …," "above … …," "on … …," "upper," "below … …," "below … …," "below … …," "lower," and the like may be used herein to describe one element's relationship to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as "under" or "beneath" additional elements would then be oriented "over" the additional elements. Thus, the term "under … …" can encompass both an orientation of above and below. The semiconductor device may be otherwise oriented (rotated 90 degrees or at another orientation) and the spatial relationship descriptors used herein interpreted accordingly.

As used herein, a phrase such as "at least one of … …," when located after a column of elements, modifies the entire column of elements without modifying individual elements in the column. For example, the expression "at least one of a, b and c" should be understood to include a only a, b only, c only, both a and b, both a and c, both b and c, or all of a, b and c. Here, when the term "same" is used to compare the dimensions of two or more elements, the term may encompass "substantially the same" dimensions.

It will be understood that, although the terms first, second, third, fourth, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

It will also be understood that even if a certain step or operation of manufacturing an apparatus or structure is described as being performed later than another step or operation, that step or operation may be performed earlier than the other step or operation unless the other step or operation is described as being performed after the step or operation.

Many embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments (and intermediate structures). Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

For brevity, conventional elements, structures, or layers of semiconductor devices, such as FinFETs and nanoflake transistors, may or may not be described in detail herein. For example, when a certain isolation layer or structure of the semiconductor device is irrelevant to various aspects of the embodiment, the layer or structure may be omitted here.

Fig. 1 shows a simplified structure of a 3DSFET device including a lower field effect transistor and an upper field effect transistor with a dielectric layer therebetween, according to an embodiment.

Fig. 1 shows a cross-sectional view of the 3DSFET device 10 in a channel length direction that is perpendicular to the channel width direction.

Referring to fig. 1,3DSFET, the device 10 can include a lower field effect transistor 10L formed on a substrate 105 and an upper field effect transistor 10U formed over the lower field effect transistor 10L. The substrate 105 may be a silicon (Si) substrate, but it may include other materials such as silicon germanium (SiGe), silicon carbide (SiC), but is not limited thereto. The lower field effect transistor 10L may include a lower source/drain region 112 and a lower channel structure 110 connecting the lower source/drain regions 112 to each other, and the upper field effect transistor 10U may include an upper source/drain region 122 and an upper channel structure 120 connecting the upper source/drain regions 122 to each other. Each of the channel structures 110 and 120 may be formed from multiple nanoplate channel layers to form a nanoplate transistor, or may be formed from one or more fin structures to form a FinFET, according to an embodiment. Thus, according to an embodiment, each of the lower field effect transistor 10L and the upper field effect transistor 10U may be a nano-plate transistor or a FinFET, or one of the lower field effect transistor 10L and the upper field effect transistor 10U may be a FinFET, and the other may be a nano-plate transistor.

Channel structures 110 and 120 may comprise Si or SiGe that may be epitaxially grown based on substrate 105. The source/drain regions 112 and 122 may also comprise Si or SiGe that may be epitaxially grown based on the substrate 105 and/or the channel structures 110 and 120.

In addition, the lower field effect transistor 10L and the upper field effect transistor 10U may include a gate structure 115 surrounding the lower channel structure 110 and the upper channel structure 120. Although fig. 1 shows that the two field effect transistors 10L and 10U share the gate structure 115 to receive the same gate input signal, the gate structure 115 may be divided into a lower gate structure and an upper gate structure isolated from each other depending on the type of the 3DSFET device 10. The gate structure 115 may include titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), copper (Cu), and/or combinations thereof. A gate contact plug 116 may be formed on the gate structure 115 to receive a gate input signal.

The lower field effect transistor 10L may be a P-type metal oxide semiconductor field effect transistor (PFET) in which the lower source/drain region 112 is doped with a P-type dopant such As boron (B) or gallium (Ga), and the upper field effect transistor 10U may be an n-type field effect transistor (NFET) in which the upper source/drain region 122 is doped with an n-type dopant such As phosphorus (P), arsenic (As), or antimony (Sb). However, according to an embodiment, the lower field effect transistor 10L may be an NFET and the upper field effect transistor 10U may be a PFET.

Meanwhile, the 3DSFET device 10 may further include a dielectric layer 130 formed of silicon oxide (e.g., siO) or silicon nitride (e.g., siN) to electrically isolate the lower source/drain region 112 from the upper source/drain region 122 vertically above the lower source/drain region 112. Such isolation of the two source/drain regions 112 and 122 may be required, for example, when one of the lower source/drain regions 112 and one of the upper source/drain regions 122 thereabove are connected to a positive voltage source and a negative voltage source through the lower source/drain contact plug 117 and the upper source/drain contact plug 127, respectively. Further, for example, the dielectric layer 130 may also be required when the further lower source/drain region 112 and the further upper source/drain region 122 above it are connected to different output nodes Q1 and Q2 by means of further lower source/drain contact plugs 117 and further upper source/drain contact plugs 127, respectively.

To form the source/drain regions 112 and 122 of the 3DSFET device 10, a lower epitaxial structure (epitaxial structure) for the lower source/drain region 112 may be first grown from the substrate 105 and/or the lower channel structure 110, a dielectric layer 130 for electrical isolation may be formed thereon, and may be etched back to provide a space for growing an upper epitaxial structure for the upper source/drain region 122, and then the upper epitaxial structure is grown in the etched back space from the upper channel structure 120.

However, formation of the dielectric layer 130, including an etch back operation applied to the dielectric layer 130, may expose various challenges in fabricating the 3DSFET device 10. For example, if dielectric layer 130 is etched back too far, lower source/drain regions 112 may form a short with upper source/drain regions 122. On the other hand, if the dielectric layer 130 is not sufficiently etched back, the upper epitaxial structure may be prevented from growing correctly in the etched back space to form upper source/drain regions.

Fig. 2 shows a simplified structure including a lower field effect transistor and an upper field effect transistor 3DSFET with a PN junction structure therebetween according to an embodiment.

Referring to fig. 2,3DSFET, device 20 can include a lower field effect transistor 20L formed on substrate 205 and an upper field effect transistor 20U formed over lower field effect transistor 20L, similar to 3DSFET device 10 shown in fig. 1. The lower field effect transistor 20L may include a lower channel structure 210 connecting lower source/drain regions 212 to each other, and the upper field effect transistor 20U may include an upper channel structure 220 connecting upper source/drain regions 222 to each other. A gate structure 215 common to the two field effect transistors 20L and 20U may surround the channel structures 210 and 220. A plurality of contact plugs 216, 217, and 227 may also be included in the 3DSFET device 20. These structural elements are the same as or similar to those of the 3DSFET device 10, and thus, repeated description of the same or corresponding structural elements is omitted, and only different aspects of the 3DSFET device 20 are described below.

According to an embodiment, the 3DSFET device 20 may include a PN junction structure 211 in place of the dielectric layer 130 between the lower source/drain region 112 and the upper source/drain region 122 in fig. 1.

According to an embodiment, the PN junction structure 211 may be formed between the p-type lower source/drain region 212 and the n-type upper source/drain region 222. The PN junction structure 211 may include a first semiconductor layer and a second semiconductor layer, each of which may be formed of Si, but is not limited thereto. Further, the first semiconductor layer may include n-type dopants similar to those included in the n-type upper source/drain regions 222, and the second semiconductor layer may include p-type dopants similar to those included in the p-type lower source/drain regions 212. Accordingly, the first semiconductor layer may form an n-type region 211-of the PN junction structure 211, and the second semiconductor layer may form a p-type region 211+ of the PN junction structure 211.

According to an embodiment, a PN junction structure 211 including an n-type region 211-and a p-type region 211+ may be formed between a p-type lower source/drain region 212 and an n-type upper source/drain region 222 in a reverse bias manner. For example, an n-type region 211-may be formed on the top surface of the p-type lower source/drain region 212, and a p-type region 211+ above the n-type region 211-may be formed on the bottom surface of the n-type upper source/drain region 222. Thus, each of the two opposite sides of the 3DSFET device 20 relative to the gate structure 215 may include a PNPN structure 200, the PNPN structure 200 being a stack of a p-type lower source/drain region 212, an n-type region 211-and a p-type region 211+ (which are in reverse bias form) of a PN junction structure 211, and an n-type upper source/drain region 222 over the substrate 205 in that order.

The PN junction structure 211 in reverse biased form may electrically isolate the lower source/drain region 212 from the upper source/drain region 222. For example, when the p-type lower source/drain region 212 and the n-type upper source/drain region 222 are connected to a positive voltage source and a negative voltage source, respectively, the PN junction structure 211 may enter a reverse bias state to prevent or minimize current flow between the lower source/drain region 212 and the upper source/drain region 222. In other words, the reverse-biased PN junction structure 211 may serve as an electrical isolation structure between the lower source/drain region 212 and the upper source/drain region 222.

Although the 3DSFET device 20 shown in fig. 2 may be formed of PNPN structure 200 surrounding channel structures 110 and 120 at each side of gate structure 115, according to an embodiment, PNPN structure 200 may be formed at only one side of gate structure 115 in a 3DSFET device. Further, according to an embodiment, the 3DSFET device 20 may be formed of an NPNP structure in which an n-type lower source/drain region, a p-type region of a PN junction structure thereon, an n-type region of a PN junction structure, and a p-type upper source/drain region are stacked in this order. In this case, the 3DSFET device 20 may be formed of an NFET at the lower stack and a PFET at the upper stack, and the PN junction structure may also be used as an isolation structure between the n-type lower source/drain region and the p-type upper source/drain region.

Next, a method of forming a PNPN structure for a 3DSFET device (such as PNPN structure 200 in 3DSFET device 20) is described.

Fig. 3A and 3B illustrate post-simulation diagrams showing formation of PNPN structures based on a substrate and channel structure in an intermediate 3DSFET structure, according to an embodiment. Fig. 4 illustrates a flowchart of a method of forming the PNPN structure illustrated in fig. 3A and 3B according to an embodiment.

Fig. 3A is a perspective view, including a channel width direction view and a channel length direction view, of an intermediate 3DSFET structure 30 'including a PNPN structure 300 before the intermediate 3DSFET structure 30' is completed as a 3DSFET device corresponding to the 3DSFET device 20 shown in fig. 2, and fig. 3B is a cross-sectional view of the intermediate 3DSFET structure 30 'in the channel length direction taken vertically along the line I-I' shown in fig. 3A.

Referring to fig. 3A and 3B, the intermediate 3DSFET structure 30' may include a plurality of structural elements that are the same as or similar to the structural elements included in the 3DSFET device 20 shown in fig. 2. Therefore, repeated descriptions thereof may be omitted here as needed.

The intermediate 3DSFET structure 30' may include a lower channel structure 310 for a lower nanoflake transistor on a substrate 305 and an upper channel structure 320 for an upper nanoflake transistor. The lower channel structure 310 may include a plurality of lower nano-sheet channel layers 310C and lower sacrificial layers 310S alternately stacked on the substrate 305, and the upper channel structure 320 may include a plurality of upper nano-sheet channel layers 320C and upper sacrificial layers 320S alternately stacked on the lower channel structure 310. These semiconductor nanoplatelets of channel structures 310 and 320 may be epitaxially grown based on substrate 305. For example, the nanoplate channel layers 310C and 320C may be formed of Si, and the sacrificial layers 310S and 320S may be formed of SiGe.

An isolation layer 323 may be formed between the lower channel structure and the upper channel structure 320. Isolation layer 323 may also be epitaxially grown on substrate 305 along with channel structures 310 and 320 and may be formed of silicon nitride. According to an embodiment, the isolation layer 323 may be formed of SiGe having a germanium concentration different from that of the sacrificial layers 310S and 320S.

Although the channel structures 310 and 320 shown in fig. 3A and 3B include nanoplatelets as channel layers, at least one of the channel structures 310 and 320 may optionally include one or more fin structures as channel layers to form FinFET(s) in a 3DSFET device obtained from the intermediate 3DSFET structure 30', as described with reference to fig. 1 and 2.

The dummy gate structure 315' may be formed to surround the channel structures 310 and 320. In a subsequent step of fabricating the 3DSFET device, this dummy gate structure 315' will be removed along with the sacrificial layers 310S and 320S to be replaced by a replacement gate structure, corresponding to the gate structure 215 shown in fig. 2. The dummy gate structure 315' may be formed of amorphous silicon (a-Si), but is not limited thereto. Gate spacers 350 may be formed on side surfaces of the dummy gate structure 315'. The gate spacer 350 may include a material such as silicon nitride, silicon carbonitride, or silicon oxycarbonitride, but is not limited thereto.

Lower epitaxial structures (epitaxial structures) 312 may be formed on both ends of the lower channel structure 310, respectively. The lower epitaxial structures 312 may be connected to each other by the lower nanoplate channel layer 310C while they may be isolated from the lower sacrificial layer 310S by the internal spacers 316. Similarly, upper epitaxial structures 322 may be formed on both ends of the upper channel structure 320, respectively. The upper epitaxial structures 322 may be connected to each other by the upper nanoplate channel layer 320C while they may be isolated from the lower sacrificial layer 310S by the internal spacers 316. For example, the inner spacers 316 may be formed of silicon nitride. The lower epitaxial structure 312 and the upper epitaxial structure 322 will form lower source/drain regions for the lower nanoflake transistor and upper source/drain regions for the upper nanoflake transistor in the 3DSFET device completed by the intermediate 3DSFET structure 30'.

Lower epitaxial structure 312 may be formed from a material(s) similar to the material forming substrate 305 and/or lower nanoplatelet channel layer 310C. For example, the material(s) forming the lower epitaxial structure 312 may include SiGe. The lower epitaxial structure 312 may also include p-type dopants such as boron (B), gallium (Ga), etc. to form a lower nanoflake transistor including the lower epitaxial structure 312 as a PFET in a 3DSFET device. Upper epitaxial structure 322 may also be formed from a material(s) similar to the material forming substrate 305 and/or upper nanoplatelet channel layer 320C. For example, the material(s) forming the upper epitaxial structure 322 may include Si. The upper epitaxial structure 322 may also include n-type dopants such As phosphorus (P), arsenic (As), antimony (Sb), etc., to form an upper nanoflake transistor including the upper epitaxial structure 322 As an NFET in a 3DSFET device.

The lower epitaxial structure 312 may be isolated from the upper epitaxial structure 322 formed thereon by a PN junction structure 311 including a first semiconductor layer and a second semiconductor layer, each of which may be formed of Si, but is not limited thereto. The first semiconductor layer may also include n-type dopants similar to those included in the n-type upper epitaxial structure 322, and the second semiconductor layer may further include p-type dopants similar to those included in the p-type lower epitaxial structure 312. Accordingly, the first semiconductor layer may form an n-type region 311-of the PN junction structure 311, and the second semiconductor layer may form a p-type region 311+ of the PN junction structure 311.

According to an embodiment, the n-type upper epitaxial structure 322 and the n-type region 311-may include the same or different n-type dopants, and the lower epitaxial structure 312 and the p-type region 311+ may include the same or different p-type dopants.

As in the 3DSFET device 20 shown in fig. 2, the PN junction structure 311 of the intermediate 3DSFET structure 30' may also take the form of a reverse bias between the p-type lower epitaxial structure 312 and the n-type upper epitaxial structure 322. For example, an n-type region 311-may be formed on the top surface of the p-type lower epitaxial structure 312, and a p-type region 311+ above the n-type region 311-may be formed on the bottom surface of the n-type upper epitaxial structure 322.

When the p-type lower epitaxial structure 312, the n-type region 311-, the p-type region 311+, and the n-type upper epitaxial structure 322 are formed in the above-described manner, the intermediate 3DSFET structure 30 'may include the PNPN structure 300 on at least one side of the dummy gate structure 315'.

Next, a method of forming the PNPN structure 300 according to an embodiment may be described with reference to fig. 4.

In operation S410, a lower epitaxial structure 312 may be epitaxially grown based on the substrate 305 and the lower channel structure 310 including the lower nanoflake channel layer 310C. When growing the lower epitaxial structure 312, p-type dopants may be doped, implanted, or diffused in the lower epitaxial structure 312 to form the p-type lower epitaxial structure 312.

According to an embodiment, when the lower epitaxial structure 312 is grown, an upper region of the middle 3DSFET structure 30', including lateral sides of the upper channel structure 320 in a channel length direction view, may be sealed by a protective layer such as, but not limited to, spin-on glass (SOG), so that the upper epitaxial structure 322 may not be grown together with the lower epitaxial structure 312.

In operation S420, a first semiconductor layer including, for example, si may be epitaxially grown at least from the p-type lower epitaxial structure 312, and an n-type dopant may be doped, implanted, or diffused in the first semiconductor layer. Thus, an n-type region 311-for a PN junction structure may be formed.

Here, the first semiconductor layer may be grown outwardly from the lower epitaxial structure 312 in all directions except the vertically downward direction in the channel width direction view, as shown in fig. 3A, and thus, the outer surface of the lower epitaxial structure 312 (including the top surface and the side surfaces except the bottom surface thereof) on the substrate 305 may be surrounded by the n-type region 311 for the PN junction structure.

In operation S430, for example, a second semiconductor layer including Si may be at least epitaxially grown from the n-type region 311, and a p-type dopant may be doped, implanted, or diffused in the second semiconductor layer. Thus, the p-type region 311+ may be formed to obtain a PN junction structure 311 comprising the p-type region 311+ and the n-type region 311-on the p-type lower epitaxial structure 312.

Here, in the channel width direction view as shown in fig. 3A, the second semiconductor layer for the p-type region 311+ may be grown to surround the n-type region 311-, but may not be grown on the bottom surface of the lower epitaxial structure 312.

In operation S440, the upper epitaxial structure 322 may be epitaxially grown from the p-type region 311+ in addition to the upper channel structure 320 including the upper nanoflake channel layer 320C. When the upper epitaxial structure 322 is grown, n-type dopants may be doped, implanted, or diffused in the upper epitaxial structure 322 to obtain a PNPN structure 300 comprising a p-type lower epitaxial structure 312, an n-type region 311-, a p-type region 311-, and an n-type upper epitaxial structure 322.

According to an embodiment, the sealed upper region of the intermediate 3DSFET structure 30' may be opened by removing the protective layer, for example, by dry and/or wet etching, prior to growth of the upper epitaxial structure 322.

Here, in the channel width direction view as shown in fig. 3A, the upper epitaxial structure 322 may be grown to surround the p-type region 311+ of the PN junction structure 311, but may not be grown on the bottom surface of the lower epitaxial structure 312. Thus, in the cross-sectional view of the intermediate 3DSFET structure 30' shown in fig. 3B, the PN junction structure 311 may be interposed between the p-type lower epitaxial structure 312 and the n-type upper epitaxial structure 322.

Although not shown in the figures for purposes of brevity, additional structural elements may be added to the intermediate 3DSFET structure 30 'by patterning, etching, and/or deposition processes to complete the intermediate 3DSFET structure 30' into a 3DSFET device. For example, the dummy gate structure 315 'and the sacrificial layers 310S and 320S may be replaced with a replacement gate structure corresponding to the gate structure 115, and a plurality of contact plugs may be formed on the intermediate 3DSFET structure 30' to obtain a 3DSFET device corresponding to the 3DSFET device 20 shown in fig. 2.

As described above with reference to fig. 3A and 3B, a PN junction structure 311 including p-type regions 311+ and n-type regions 311 "in reverse bias form may be used as an electrical isolation structure between the lower source/drain regions (lower epitaxial structure 312) and the upper source/drain regions (upper epitaxial structure 322). Thus, the method of fabricating a 3DSFET device based on the intermediate 3DSFET structure 30' may eliminate the complex and difficult process of forming a dielectric layer between the lower and upper epitaxial structures.

In the above embodiment, the PN junction structure in the form of a reverse bias may be formed as an electrical isolation structure between the lower epitaxial structure and the upper epitaxial structure, and thus, at least one of two opposite sides with respect to the gate structure in the 3DSFET device may form lower source/drain regions and upper source/drain regions in the form of PNPN structures. However, the present disclosure is not limited thereto. In the following embodiments, the reverse biased PN junction structure may form a lower source/drain region and an upper source/drain region in the form of a P (NPN) structure together with the lower and upper epitaxial structures.

Fig. 5A and 5B illustrate post-simulation diagrams showing formation of a P (NPN) structure based on a substrate and a channel structure in an intermediate 3DSFET structure in accordance with an embodiment. Fig. 5C illustrates a simplified structure of a 3DSFET device including the P (NPN) structure illustrated in fig. 5A and 5B according to an embodiment. Fig. 6 illustrates a flowchart of a method of forming the P (NPN) structure illustrated in fig. 5A-5C, according to an embodiment.

Fig. 5A is a perspective view, including a channel width direction view and a channel length direction view, of an intermediate 3DSFET structure 50 'including a P (NPN) structure 500A before the intermediate 3DSFET structure 50' is completed into the 3DSFET device 50 shown in fig. 5C, and fig. 5B is a cross-sectional view of the intermediate 3DSFET structure 50 'in the channel length direction taken vertically along line II-II' shown in fig. 5A.

Referring to fig. 5A and 5B, some of the structural elements of the intermediate 3DSFET structure 50 'may be the same as or similar to the structural elements of the intermediate 3DSFET structure 30' shown in fig. 3A and 3B. These same or similar structural elements may include a substrate 505, an isolation layer 523, a lower channel structure 510 including a plurality of lower nanoflake channel layers 510C and lower sacrificial layers 510S, an upper channel structure 520 including a plurality of upper nanoflake channel layers 520C and upper sacrificial layers 520S, an internal spacer 516, a dummy gate structure 515', and a gate spacer 550. Accordingly, repeated descriptions thereof may be omitted herein as needed, and instead, different aspects of the intermediate 3DSFET structure 50' are described below.

In this embodiment, the lower epitaxial structure 512, the upper epitaxial structure 522, and the PN junction structure 511 separating the two epitaxial structures 512 and 522 may have different shapes or forms in the intermediate 3DSFET structure 50 'compared to the corresponding structural elements in the intermediate 3DSFET structure 30' in the previous embodiment. This is because the method of forming the two epitaxial structures 512 and 522 may be different from the method of forming the two epitaxial structures 312 and 322 of the intermediate 3DSFET structure 30', as will be described later.

As shown in fig. 5A and 5B, in a channel width direction view, the n-type upper epitaxial structure 522 may be surrounded by a first semiconductor layer including, for example, si, and the first semiconductor layer may be surrounded by a second semiconductor layer also including, for example, si. The first semiconductor layer may further include a p-type dopant, and the second semiconductor layer may further include an n-type dopant. Thus, the first semiconductor layer may be p-type to form a p-type region 511+ of the PN junction structure 511, and the second semiconductor layer may be n-type to form an n-type region 511-of the PN junction structure 511. According to an embodiment, in a channel width direction view, the p-type region 511+ may completely surround the upper epitaxial structure 522, and the n-type region 511-may completely surround the p-type region 511+.

Further, in the channel width direction view, the PN junction structure 511 including the p-type region 511+ and the n-type region 511-may be surrounded by the p-type lower epitaxial structure 512, and the p-type lower epitaxial structure 512 may extend from the substrate 505. According to an embodiment, the PN junction structure 511 may be completely surrounded by the lower epitaxial structure 512. Thus, a P-type lower epitaxial structure 512, a PN junction structure 511 surrounded by the P-type lower epitaxial structure 512, and an n-type upper epitaxial structure 522 surrounded by the PN junction structure 511 may form a P (NPN) structure 500A at least one side of the dummy gate structure 515'.

According to an embodiment, the upper n-type epitaxial structure 522 and the n-type region 511-may include the same or different n-type dopants, and the lower epitaxial structure 512 and the p-type region 511+ may include the same or different p-type dopants.

Since the PN junction structure 511 including the p-type region 511+ and the n-type region 511-is formed between the p-type lower epitaxial structure 512 and the n-type upper epitaxial structure 522 in this manner, when the lower source/drain region formed by the lower epitaxial structure 512 and the upper source/drain region formed by the upper epitaxial structure 522 are respectively connected to the positive voltage source and the negative voltage source, the PN junction structure 511 can enter a reverse bias state, thereby functioning as an electrical isolation structure, preventing or minimizing the flow of current between the two source/drain regions 512 and 522.

In the intermediate 3DSFET structure 30' shown in fig. 3A and 3B, the PN junction structure 311 of the PNPN structure 300 may be formed below the upper epitaxial structure 322 to surround the lower epitaxial structure 312 except for a bottom surface thereof facing the substrate 305. However, in the intermediate 3DSFET structure 50' shown in fig. 5A and 5B, the PN junction structure 511 of the P (NPN) structure may be formed on all sides of the upper epitaxial structure 522 (including the upper side thereof) to completely surround the upper epitaxial structure 522, and the lower epitaxial structure 512 may also be formed on all sides of the PN junction structure 511 to completely surround the PN junction structure 511, as shown in fig. 5A. That is, the lower epitaxial structure 512 may extend above the upper epitaxial structure 522 such that an upper portion of the lower epitaxial structure 512 may be formed above the upper epitaxial structure 522. Thus, when the intermediate 3DSFET structure 50' is completed as a 3DSFET device 50 including a P (NPN) structure 500A as shown in fig. 5C, a lower source/drain contact plug 517 extending from a back-end-of-line (BEOL) structure (not shown) may be connected to an upper portion of the lower source/drain region 512 formed above the upper source/drain region 522, without necessarily being connected to a lower portion of the lower epitaxial structure 512 formed below the upper epitaxial structure 522. Here, the lower source/drain region 512 and the upper source/drain region 522 may be the same as the lower epitaxial structure 512 and the upper epitaxial structure 522 shown in fig. 5A and 5B, respectively, and the gate structure 515 may replace the dummy gate structure 515 'of the intermediate 3DSFET structure 50' shown in fig. 5A and 5B.

Fig. 5C shows that in the 3DSFET device 50, one side of the gate structure 515 may be formed of the P (NPN) structure 500A described above, and the other side of the gate structure 515 may be formed of the PNPN structure 500B corresponding to the PNPN structure 200 or 300 shown in fig. 2 and 3A-3B, according to an embodiment.

In the embodiment shown in fig. 5C, PNPN structure 500B may include a lower field effect transistor 50L including a p-type lower source/drain region 512 and an upper field effect transistor 50U including an n-type upper source/drain region 522, and further, PN junction structure 511 is interposed between source/drain regions 512 and 522 in a reverse bias fashion. In addition, the p-type lower source/drain region 512 and the n-type upper source/drain region 522 may be connected to positive and negative voltage sources, respectively, through a lower source/drain contact plug 517 and an upper source/drain contact plug 527, such that the PN junction structure 511 may electrically isolate the upper source/drain region 522 from the lower source/drain region 512. At this time, at least one of the lower source/drain region 512 and the upper source/drain region 522 of the P (NPN) structure 500A may be connected to an output node of the 3dsfet 50.

However, the present disclosure may not be limited thereto. According to an embodiment, P (NPN) structure 500A may be formed on both sides of gate structure 515 to form different 3DSFET devices. Further, the present disclosure may not limit the use of P (NPN) structure 500A at 3DSFET device 50 shown in fig. 5C. Various other circuit implementations may be implemented by P (NPN) structure 500 in different 3DSFET devices. For example, the lower source/drain region 512 of the P (NPN) structure 500A may receive a positive voltage through a lower source/drain contact plug 517 connected to an upper portion of the lower source/drain region 512 formed over the upper source/drain region 522 or may be connected to an output node of the 3DSFET device 50.

Furthermore, although the 3DSFET device 50 shown in fig. 5A-5C may include a P (NPN) structure 500A located on at least one side of the gate structure 515, the 3DSFET device 50 may alternatively include an N (PNP) structure in which the P-type upper source/drain region is surrounded by a PN junction structure in reverse biased form surrounded by an N-type lower source/drain region extending upward from the substrate 505. In this case, the 3DSFET device 50 may be formed of an NFET at the lower stack and a PFET at the upper stack, and the PN junction structure may also serve as an electrical isolation structure between the n-type lower source/drain region and the p-type upper source/drain region.

Next, a method of forming the P (NPN) structure 500A shown in fig. 5A-5C may be described with reference to fig. 6.

In operation S610, an upper epitaxial structure 522 may be epitaxially grown based on the upper channel structure 520 including the upper nanoflake channel layer 520C. When growing the upper epitaxial structure 522, n-type dopants may be doped, implanted, or diffused in the upper epitaxial structure 522 to form the n-type upper epitaxial structure 522.

According to an embodiment, when the upper epitaxial structure 522 is grown, a lower region of the middle 3DSFET structure 50' including lateral sides of the lower channel structure 510 in a channel length direction view may be sealed by a protective layer such as spin-on glass (SOG) and then etched back, but is not limited thereto, so that the lower epitaxial structure 512 may not be grown together with the upper epitaxial structure 522.

In operation S620, a first semiconductor layer including, for example, si may be epitaxially grown at least from the n-type upper epitaxial structure 522, and a p-type dopant may be doped, implanted, or diffused in the first semiconductor layer. Thus, a p-type region 511+ for the PN junction structure may be formed.

Here, the first semiconductor layer may be grown outwardly from the upper epitaxial structure 522 in all directions, and thus, in a channel width direction view as shown in fig. 5A, the outer surface of the upper epitaxial structure 522 may be completely surrounded by the p-type region 511+ for the PN junction structure.

In operation S630, a second semiconductor layer including, for example, si may be epitaxially grown at least from the p-type region 511+, and an n-type dopant may be doped, implanted, or diffused in the second semiconductor layer. Thus, an n-type region 511-may be formed to obtain a PN junction structure 511 comprising a p-type region 511+ surrounding the upper epitaxial structure 522 and the n-type region 511-.

Here, the second semiconductor layer for the n-type region 511-may be grown to completely surround the p-type region 511+ in a channel width direction view as shown in fig. 5A.

In operation S640, a lower epitaxial structure 512 may be epitaxially grown from the n-type region 511-in addition to the substrate 505 and the upper channel structure 510 including the lower nanoflake channel layer 510C. When the lower epitaxial structure 512 is grown, P-type dopants may be doped, implanted, or diffused in the lower epitaxial structure 512 to obtain the P (NPN) structure 300.

According to an embodiment, the sealed lower region of the intermediate 3DSFET structure 50' may be opened by removing the protective layer via, for example, dry and/or wet etching prior to growing the lower epitaxial structure 512.

Thus, the lower epitaxial structure 512 may be grown on the substrate 505 and the lower channel structure 510, and may be further grown as an n-type region 511-that completely surrounds the PN junction structure 511 in a channel width direction view. Thus, in the cross-sectional view of the intermediate 3DSFET structure 50' shown in fig. 5A and 5B, the PN junction structure 511 is not only interposed between the lower epitaxial structure 512 and the upper epitaxial structure 522, but is also formed above the upper epitaxial structure 522 and the upper portion of the lower epitaxial structure 512 is located above it.

Although not shown in the figures for simplicity, additional structural elements may be added to the intermediate 3DSFET structure 50 'by patterning, etching, and/or deposition processes to complete the intermediate 3DSFET structure 50' into a 3DSFET device 50. For example, the dummy gate structure 515 'and the sacrificial layers 510S and 520S may be replaced with replacement gate structures corresponding to the gate structure 515, and a plurality of contact plugs may be formed on the intermediate 3DSFET structure 50' to obtain the 3DSFET device 50 shown in fig. 5C.

In the above-described embodiments described with reference to fig. 3A-3B through 5A-5C, each of the lower channel structure and the upper channel structure is described as including a plurality of nanoflake channel layers to form a corresponding field effect transistor as a nanoflake transistor. However, the present disclosure is not limited thereto. According to an embodiment, the present disclosure may also be applied to a 3DSFET device, wherein each of the lower channel structure and the upper channel structure includes one or more fin structures to form a corresponding field effect transistor as a FinFET. Further, according to an embodiment, the present disclosure may be applied to hybrid 3DSFET devices, wherein one of the lower channel structure and the upper channel structure includes a plurality of nanoflake channel layers and the other includes one or more fin structures to form the 3DSFET device as a combination of nanoflake transistors and finfets at different stacks.

Referring to fig. 7, the electronic apparatus 4000 may include at least one application processor 4100, a communication module 4200, a display/touch module 4300, a storage 4400, and a buffer RAM 4500. According to an implementation, the electronic device 4000 may be a mobile device such as a smart phone or tablet computer, but is not limited thereto.

The application processor 4100 may control the operation of the electronic device 4000. The communication module 4200 is implemented to perform wireless or wired communication with external devices. The display/touch module 4300 is implemented to display data processed by the application processor 4100 and/or receive data through a touch panel. The storage 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a Solid State Drive (SSD), a universal flash memory (UFS) device, or the like. The storage 4400 may perform buffering of the mapping data and the user data as described above.

The buffer RAM 4500 may temporarily store data for processing operations of the electronic device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), a low power consumption double data rate (LPDDR) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, rambus Dynamic Random Access Memory (RDRAM), etc.

At least one component in the electronic device 4000 may include at least one of the 3DSFET devices 20, 30, and 50 described above with reference to fig. 2-6.

The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting the present disclosure. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the present disclosure.

Claims

1. A three-dimensional stacked field effect transistor device comprising:

a lower source/drain region of a first polarity type connected to the lower channel structure;

an upper source/drain region of a second polarity type connected to the upper channel structure, above the lower source/drain region; and

a PN junction structure between the lower source/drain region and the upper source/drain region configured to electrically isolate the upper source/drain region from the lower source/drain region,

wherein the PN junction structure includes a first region of the first polarity type and a second region of the second polarity type.

2. The three-dimensional stacked field effect transistor device of claim 1, wherein the second region of the PN junction structure is on a top surface of the lower source/drain region, and

wherein the first region above the second region of the PN junction structure is on a bottom surface of the upper source/drain region.

3. The three-dimensional stacked field effect transistor device of claim 2, wherein the second region of the PN junction structure surrounds the lower source/drain region except for a bottom surface of the lower source/drain region,

wherein the first region is above the second region of the PN junction structure, and

Wherein the upper source/drain region surrounds the first region of the PN junction structure and is not on the bottom surface of the lower source/drain region.

4. The three-dimensional stacked field effect transistor device of claim 2, wherein a portion of the first region of the PN junction structure is on a top surface of the upper source/drain region, and

wherein a portion of the second region is over the portion of the first region of the PN junction structure.

5. The three-dimensional stacked field effect transistor device of claim 4, wherein the upper source/drain region is surrounded by the first region of the PN junction structure, the first region being surrounded by the second region of the PN junction structure.

6. The three-dimensional stacked field effect transistor device of claim 4, wherein a portion of the lower source/drain region is above the portion of the second region of the PN junction structure.

7. The three-dimensional stacked field effect transistor device of claim 6, wherein the upper source/drain region is surrounded by the first region of the PN junction structure, the first region is surrounded by the second region of the PN junction structure, and

wherein the lower source/drain region surrounds the second region of the PN junction structure.

8. The three-dimensional stacked field effect transistor device of claim 6, further comprising a lower source/drain contact plug connected to the portion of the lower source/drain region above the portion of the second region of the PN junction structure.

9. The three-dimensional stacked field effect transistor device of claim 1, further comprising a lower source/drain contact plug connected to the lower source/drain region and configured to provide a voltage having the same polarity as the lower source/drain region.

10. The three-dimensional stacked field effect transistor device of claim 9, further comprising an upper source/drain contact plug connected to the upper source/drain region and providing a voltage having the same polarity as the upper source/drain region.

11. The three-dimensional stacked field effect transistor device of claim 1, further comprising:

another lower source/drain region of the first polarity type connected to the lower source/drain region by the lower channel structure;

another upper source/drain region of the second polarity type connected to the upper source/drain region by the upper channel structure; and

A further PN junction structure between the further lower source/drain region and the further upper source/drain region configured to electrically isolate the further upper source/drain region from the further lower source/drain region,

wherein the further PN junction structure comprises a further first region of the first polarity type and a further second region of the second polarity type.

12. The three-dimensional stacked field effect transistor device of claim 11, wherein the second region of the PN junction structure is on a top surface of the lower source/drain region,

wherein the first region above the second region of the PN junction structure is on a bottom surface of the upper source/drain region,

wherein the second region of the PN junction structure surrounds the lower source/drain region, except for a bottom surface of the lower source/drain region,

wherein the first region is over the second region of the PN junction structure,

wherein the upper source/drain region surrounds the first region of the PN junction structure and is not on the bottom surface of the lower source/drain region,

wherein the further second region of the further PN junction structure is on a top surface of the further lower source/drain region,

wherein the further first region above the further second region of the further PN junction structure is on a bottom surface of the further upper source/drain region,

Wherein the further second region of the further PN junction structure surrounds the further lower source/drain region, except for a bottom surface of the further lower source/drain region,

wherein the further first region is above the further second region of the further PN junction structure,

wherein the further upper source/drain region surrounds the further first region of the further PN junction structure and is not on the bottom surface of the further lower source/drain region.

13. The three-dimensional stacked field effect transistor device of claim 11, wherein the second region of the PN junction structure is on a top surface of the lower source/drain region,

wherein a portion of the further first region of the further PN junction structure is on a top surface of the further upper source/drain region,

Wherein a portion of the further second region is over the portion of the further first region of the further PN junction structure, and

wherein a portion of the further lower source/drain region is above the portion of the further second region of the further PN junction structure.

14. The three-dimensional stacked field effect transistor device of claim 11, wherein a portion of the first region of the PN junction structure is on a top surface of the upper source/drain region,

wherein a portion of the second region is over the portion of the first region of the PN junction structure, an

Wherein a portion of the lower source/drain region is over the portion of the second region of the PN junction structure,

15. A method of fabricating a three-dimensional stacked field effect transistor device, the method comprising the operations of:

(a) Providing an intermediate three-dimensional stacked field effect transistor structure comprising a lower channel structure and an upper channel structure above the lower channel structure;

(b) Growing a lower epitaxial structure of a first polarity type based on the lower channel structure;

(c) Growing a first semiconductor layer of a second polarity type opposite to the first polarity type on the lower epitaxial structure based on the lower epitaxial structure;

(d) Growing a second semiconductor layer of the first polarity type on the first semiconductor layer based on the first semiconductor layer; and

(e) And growing an upper epitaxial structure of the second polarity type on the second semiconductor layer based on the upper channel structure and the second semiconductor layer.

16. The method of claim 15, wherein in operation (c), the first semiconductor layer is grown outwardly from the lower epitaxial structure in all directions except a vertically downward direction in a channel width direction view such that an outer surface of the lower epitaxial structure except a bottom surface thereof is surrounded by the first semiconductor layer.

17. The method of claim 16, wherein in operation (d), in the channel width direction view, the second semiconductor layer is grown to surround the first semiconductor layer but is not grown on a bottom surface of the lower epitaxial structure.

18. The method of claim 17, wherein in operation (e), in the channel width direction view, the upper epitaxial structure is grown outward to surround the second semiconductor layer but is not grown on the bottom surface of the lower epitaxial structure.

19. A method of fabricating a three-dimensional stacked field effect transistor device, the method comprising the operations of:

(a) Providing an intermediate three-dimensional stacked field effect transistor structure comprising a substrate, a lower channel structure over the substrate, and an upper channel structure over the lower channel structure;

(b) Growing an upper epitaxial structure of a first polarity type based on the upper channel structure;

(c) Growing a first semiconductor layer of a second polarity type opposite to the first polarity type on the upper epitaxial structure based on the upper epitaxial structure;

(e) A lower epitaxial structure of the second polarity type is grown based on the substrate, the lower channel structure, and the second semiconductor layer.

20. The method of claim 19, further comprising:

sealing lateral sides of the lower channel structure in a channel length direction view prior to operation (b); and

Before operation (e), opening the sealed lateral side of the lower channel structure.