CN116960164A

CN116960164A - Multi-stack semiconductor device

Info

Publication number: CN116960164A
Application number: CN202310449600.5A
Authority: CN
Inventors: 尹承灿; 白在职; 曹健浩; 洪炳鹤; 徐康一
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-04-26
Filing date: 2023-04-24
Publication date: 2023-10-27

Abstract

Provided is a multi-stack semiconductor device including: a substrate; a lower field effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work function metal layer and a lower gate electrode; and an upper field effect transistor, wherein the upper channel structure is surrounded by an upper gate structure comprising an upper work function metal layer and an upper gate electrode, wherein each of the lower gate electrode and the upper gate electrode comprises a metal or a metal compound, and wherein the lower gate electrode comprises polysilicon (poly-Si) or polysilicon containing a dopant, and the upper gate electrode comprises a metal or a metal compound.

Description

Multi-stack semiconductor device

Technical Field

Apparatuses and methods consistent with embodiments relate to a multi-stack semiconductor device including a lower and an upper nanoflake transistor in which a gate structure for the lower nanoflake transistor includes a polysilicon (poly-Si) structure.

Background

The increasing demand for integrated circuits with high device density has introduced three-dimensional (3D) multi-stack semiconductor devices in which two or more field effect transistors, such as nanoflake transistors, are vertically stacked. A nanoflake transistor is characterized by one or more nanoflake channel layers vertically stacked on a substrate and a gate structure surrounding the nanoflake channel layers. Thus, the nanoplate transistor is referred to as a fully wrap Gate (GAA) transistor, a multi-bridge channel field effect transistor (MBCFET).

In a multi-stack semiconductor device including two vertically stacked nanoflake transistors, one or more nanoflake channel layers of each nanoflake transistor serve as channel structures of the nanoflake transistor, and these channel layers are surrounded by a gate structure. The gate structure may include a gate dielectric layer, a work function metal layer, and a gate metal pattern for each of a lower nanoflake transistor at a lower stack and an upper nanoflake transistor at an upper stack in a multi-stack semiconductor device.

When it is desired to distinguish the gate structures of the lower and upper nanoflake transistors, the functional metal layers may be formed differently for the two nanoflake transistors. For example, when a multi-stack semiconductor device is to be formed into a complementary metal oxide transistor (CMOS) device that includes Field Effect Transistors (FETs) of opposite polarity (i.e., a p-type lower nanoflake transistor and an n-type lower nanoflake transistor), the work function metal layer of the gate structure of the lower nanoflake transistor (i.e., the lower work function metal layer of the lower gate structure) and the work function metal layer of the gate structure of the upper nanoflake transistor (i.e., the upper work function metal layer of the upper gate structure) may be formed to include different materials or material compounds. Thus, the lower gate structure and the upper gate structure may be capable of having different threshold voltages to drive the lower and upper nanoflake transistors.

A gate structure having a lower work function metal layer and an upper work function metal layer different from each other can be obtained by: forming a gate dielectric layer surrounding each of the nanoplate channel layers for the lower and upper nanoplate transistors; forming a work function metal layer surrounding the gate dielectric layer; removing the work function metal layer formed on the nanoplatelet channel layer at the upper stack, leaving the work function metal layer (i.e., lower work function metal layer) only on the nanoplatelet channel layer at the lower stack; forming another work function metal layer (i.e., an upper work function metal layer) to surround the nanoplatelet channel layer at the upper stack; and forming a gate metal pattern (or gate electrode) to surround the two work function metal layers.

However, the above process of forming different work function metal layers exposes various challenges. For example, during a removal operation of a work function metal layer initially formed on an upper stacked nanoflake channel layer by wet etching, a work function metal layer formed on a lower stacked nanoflake channel layer (i.e., a lower work function metal layer) may also be etched or damaged by wet etching. This risk may increase when the lower and upper stacked nanoplatelet channel layers have different channel widths. Thus, a process to protect the lower work function metal layer is necessary for manufacturing multi-stack semiconductor devices, which may require additional complex patterning and deposition steps.

The information disclosed in this background section is already known or deduced by the inventors before or during the implementation of an embodiment of the application or is technical information obtained during the implementation of an embodiment. It may therefore contain information that does not constitute prior art known to the public.

Disclosure of Invention

The present disclosure provides a multi-stack semiconductor device including a lower nanoflake transistor and an upper nanoflake transistor in which a gate structure includes a polysilicon (poly-Si) structure and a method of manufacturing the same.

According to an embodiment, there is provided a multi-stack semiconductor device, which may include: a substrate; a lower field effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work function metal layer and a lower gate electrode; and an upper field effect transistor in which the upper channel structure is surrounded by an upper gate structure, the upper gate structure including an upper work function metal layer and an upper gate electrode, wherein the lower gate electrode includes polysilicon (poly-Si) or polysilicon containing a dopant, and the upper gate electrode includes a metal or a metal compound.

According to an embodiment, the multi-stack semiconductor device may further include an intra-gate spacer formed between the lower work function metal layer and the upper work function metal layer at a selected region where the lower channel structure does not vertically overlap with the upper channel structure.

According to an embodiment, there is provided a multi-stack semiconductor device, which may include: a lower field effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work function metal layer and a lower gate electrode; an upper field effect transistor in which an upper channel structure is surrounded by an upper gate structure, the upper gate structure including an upper work function metal layer and an upper gate electrode; and a polysilicon (poly-Si) layer between the lower work function metal layer and the upper work function metal layer at selected regions on the lower work function metal layer, wherein each of the lower gate electrode and the upper gate electrode comprises a metal or metal compound, where the polysilicon layer comprises polysilicon or polysilicon containing a dopant.

According to an embodiment, a method of manufacturing a multi-stack semiconductor device including a lower field effect transistor and an upper field effect transistor is provided. The method may include: (a) Providing a multi-stack semiconductor device structure comprising a lower channel structure at a lower stack and an upper channel structure at an upper stack, the lower channel structure and the upper channel structure being surrounded by an initial gate structure, the initial gate structure comprising an initial work function metal layer and an initial gate electrode pattern; (b) Removing the initial gate electrode pattern from the upper stack, leaving the initial gate electrode pattern at the lower stack as a lower gate electrode for the lower field effect transistor; (c) Removing the initial work function metal layer from the upper stack, leaving the initial work function metal layer at the lower stack as a lower work function metal layer for the lower field effect transistor; (d) Forming an upper work function metal layer for the upper field effect transistor on the upper channel structure and the lower gate electrode; and (e) forming an upper gate electrode for the upper field effect transistor on the upper work function metal layer, wherein the initial gate electrode pattern comprises polysilicon (poly-Si) or polysilicon containing a dopant, and the upper gate electrode comprises a metal or a metal compound.

According to an embodiment, a method of manufacturing a multi-stack semiconductor device including a lower field effect transistor and an upper field effect transistor is provided. The method may include: (a) Providing a multi-stack semiconductor device structure comprising a lower channel structure at a lower stack and an upper channel structure at an upper stack, the lower channel structure and the upper channel structure being surrounded by an initial gate structure, the initial gate structure comprising an initial work function metal layer and an initial gate electrode pattern; (b) Removing the initial gate electrode pattern and the initial work function metal layer from the upper stack, except between the upper channel layers of the upper channel structure, such that the initial work function metal layer is removed further down than the initial gate electrode pattern at selected regions, thereby forming a plurality of recesses on the initial work function metal layer left at the lower stack at selected regions, and leaving the initial gate electrode pattern at the lower stack as a lower gate electrode for the lower field effect transistor; (c) Forming an intra-gate spacer in the recess and removing the initial work function metal layer between the upper channel layers, thereby leaving the initial work function metal layer at the lower stack as a lower work function metal layer for the lower field effect transistor; (d) Forming an upper work function metal layer for the upper field effect transistor on the upper channel structure, the lower gate electrode and the intra-gate spacer; and (e) forming an upper gate electrode for the upper field effect transistor on the upper work function metal layer, wherein the initial gate electrode pattern comprises polysilicon (poly-Si) or polysilicon containing a dopant, and the upper gate electrode comprises a metal or a metal compound.

According to an embodiment, a method of manufacturing a multi-stack semiconductor device including a lower nanoflake transistor and an upper nanoflake transistor is provided. The method may include: (a) Providing a multi-stack semiconductor device structure comprising a lower channel structure at a lower stack and an upper channel structure at an upper stack, the lower channel structure and the upper channel structure being surrounded by an initial gate structure, the initial gate structure comprising an initial work function metal layer and an initial gate electrode pattern; (b) Removing the initial gate electrode pattern and the initial work function metal layer from the upper stack except between the upper channel layers of the upper channel structure and below the lowermost upper channel layer of the upper channel layer; (c) Forming a polysilicon structure including polysilicon (poly-Si) or polysilicon containing a dopant in the space from which the initial work function metal layer and the initial gate electrode pattern are removed in operation (b), thereby leaving the initial gate electrode pattern under the polysilicon structure at the lower stack as a lower gate electrode for the lower field effect transistor; (d) Removing the polysilicon structure down to a level between the lower channel structure and the upper channel structure to form a polysilicon layer therebetween; (e) Removing the initial work function metal layer between the upper channel layers and below the lowermost upper channel layer in the upper channel layer based on the polysilicon layer, thereby leaving the initial work function metal layer below the polysilicon layer as a lower work function metal layer for the lower field effect transistor; (f) Forming an upper work function metal layer for the upper field effect transistor on the upper channel structure and the polysilicon layer, the upper work function metal layer comprising a different material than the initial work function metal layer; and (g) forming an upper gate electrode for the upper field effect transistor on the upper work function metal layer, wherein each of the initial gate electrode pattern and the upper gate electrode comprises a metal or a metal compound.

Drawings

Example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIGS. 1A-1E illustrate a multi-stack semiconductor device in which a lower gate electrode for a lower nanoflake transistor is formed of polysilicon (poly-Si) and an upper gate electrode for an upper nanoflake transistor is formed of a metal or metal compound, according to one embodiment;

fig. 2 is a flowchart of a method of manufacturing a multi-stack semiconductor device in which a lower gate electrode for a lower nano-sheet transistor is formed of polysilicon and an upper gate electrode for an upper nano-sheet transistor is formed of a metal or a metal compound, according to an embodiment.

Fig. 3-7 illustrate multi-stack semiconductor device structures in a channel width direction view after various steps of the method of fabricating multi-stack semiconductor devices mentioned in the flowchart of fig. 2, in accordance with an embodiment;

8A-8D illustrate a multi-stack semiconductor device in which a lower gate electrode for a lower nanoflake transistor is formed of polysilicon or polysilicon including dopants and includes an intra-gate spacer protecting a lower work function metal layer for a lower gate structure, according to one embodiment;

Fig. 9 is a flowchart of a method of fabricating a multi-stack semiconductor device in which a lower gate electrode for a lower nanoflake transistor is formed of polysilicon and includes an intra-gate spacer protecting a lower work function metal layer for a lower gate structure, according to one embodiment;

fig. 10-14 illustrate multi-stack semiconductor device structures in a channel width direction view after various steps of the method of fabricating multi-stack semiconductor devices mentioned in the flowchart of fig. 9, in accordance with an embodiment;

15A-15D illustrate a multi-stack semiconductor device in which polysilicon is formed between a lower gate structure and an upper gate structure, according to one embodiment;

fig. 16 is a flowchart of a method of manufacturing a multi-stack semiconductor device in which a polysilicon layer is formed between a lower gate structure and an upper gate structure, both of which are formed of a metal or a metal compound, according to an embodiment;

17-22 illustrate multi-stack semiconductor device structures in a channel width direction view after various steps of the method of fabricating multi-stack semiconductor devices mentioned in the flowchart of FIG. 16, in accordance with an embodiment; and

Fig. 23 is a schematic block diagram illustrating an electronic device including a multi-stack semiconductor device that may include a gate structure formed of polysilicon or polysilicon containing dopants, according to an example embodiment.

Detailed Description

The embodiments of the present disclosure described herein are example embodiments, and thus, the present disclosure is not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description is not to be taken in conjunction with one or more features of another example or embodiment, also provided or not provided herein, but consistent with the present disclosure. For example, even if matters described in a specific example or embodiment are not described in a different example or embodiment thereof, the matters may be understood as being related to or combined with the different example or embodiment unless otherwise mentioned in the description thereof. Moreover, it is to be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover structural and functional equivalents thereof. Furthermore, it should be understood that such equivalents include not only currently known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of structure. For example, the channel layer, the sacrificial spacer layer, and the channel spacer layer described herein may take different types or forms as long as the present disclosure can be applied thereto.

It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as "an element") of a semiconductor device is referred to as being "on", "over", "on", "under", "connected to" or "coupled to" another element of the semiconductor device, it can be directly over, directly under, directly connected to, or directly coupled to the other element or elements of the semiconductor device. In contrast, when an element of a semiconductor device is referred to as being "directly above," "directly over," "directly on," "directly under," "directly connected to," or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Like numbers refer to like elements throughout the disclosure.

For ease of description, spatially relative terms such as "above … …," "above … …," "above … …," "above," "below … …," "below … …," "below … …," "below," and the like may be used herein to describe one element's relationship to another element(s) as illustrated. It will be understood that the spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "below … …" can encompass both an orientation of above and below. The semiconductor device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, a phrase such as "at least one of" when following a column of elements modifies the entire column of elements without modifying individual elements in the column. For example, the expression "at least one of a, b and c" should be understood to include a alone, b alone, c alone, a and b both, a and c both, b and c both, or all of a, b and c. Here, when the term "same" is used to compare dimensions of two or more elements, the term may encompass "substantially the same" dimensions.

It will be understood that, although the terms first, second, third, fourth, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Accordingly, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

It will also be understood that, even if a particular step or operation of a manufacturing apparatus or structure is described as being performed later than another step or operation, that step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed later than the step or operation.

Many embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments (and intermediate structures). As such, deviations from the illustrated shapes that result, for example, from manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or gradients of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

For the sake of brevity, conventional elements, structures, or layers of semiconductor devices including nano-sheet transistors may or may not be described in detail herein. For example, when a certain isolation layer or structure of the semiconductor device is not relevant to various aspects of the embodiments, the layer or structure may be omitted herein.

Fig. 1A-1E illustrate a multi-stack semiconductor device in which a lower gate electrode for a lower nanoflake transistor is formed of polysilicon (poly-Si) and an upper gate electrode for an upper nanoflake transistor is formed of a metal or metal compound, according to an embodiment.

Fig. 1E is a top plan view of each of the multi-stack semiconductor devices 10, 20, and 30 shown in fig. 1A-1D, fig. 8A-8D, and fig. 15A-15D, respectively. Fig. 1E is provided herein only to illustrate how channel structures and gate structures surrounding the channel structures are oppositely arranged in each of the multi-stack semiconductor devices 10, 20, and 30. Thus, for brevity, FIG. 1E does not show other structures or elements shown in FIGS. 1A-1D, FIGS. 8A-8D, and FIGS. 15A-15D. FIGS. 1A-1D, 8A-8D, and 15A-15D are cross-sectional views of multi-stack semiconductor devices 10, 20, and 30, respectively, taken along lines I-I ', II-II', III-III ', and IV-IV' indicated in FIG. 1E.

It is understood herein that lines I-I 'and II-II' indicate channel length directions, and lines III-III 'and IV-IV' indicate channel width directions of the multi-stack semiconductor devices 10, 20, and 30. Accordingly, fig. 1A-1B, 8A-8B, and 15A-15B illustrate the length of the channel structure and the source/drain regions connected by the channel structure, respectively, and fig. 1C-1D, 8C-8D, and 15C-15D illustrate the width of the channel structure and the source/drain regions, respectively, in the multi-stack semiconductor devices 10, 20, and 30.

Referring to fig. 1A-1C, a multi-stack semiconductor device 10 may include a lower nanoflake transistor 10L at a lower stack and an upper nanoflake transistor 10U at an upper stack on a substrate 105. The substrate 105 may be a bulk substrate of semiconductor material, such as silicon, or a silicon-on-insulator (SOI) substrate. Shallow Trench Isolation (STI) structures 106 comprising silicon nitride or silicon oxide may be formed on the substrate 105 or around the substrate 105 to isolate the multi-stack semiconductor device 10 from another multi-stack semiconductor device or circuit element in an integrated circuit comprising the multi-stack semiconductor device 10.

The lower nanoflake transistor 10L may include a plurality of lower channel layers 110C as the lower channel structure 110 of the multi-stack semiconductor device 10. The lower channel layer 110C may be a nano-sheet layer vertically stacked and horizontally extending over the substrate 105 and surrounded by the lower gate structure 115. The upper nanoflake transistor 10U may also include a plurality of upper channel layers 120C as the upper channel structure 120 of the multi-stack semiconductor device 10. As with the lower channel layer 110C, the upper channel layer 120C may also be a nano-sheet layer vertically stacked and extending horizontally above the lower channel layer 110C and surrounded by the upper gate structure 125. Each of the lower channel layer 110C and the upper channel layer 120C may include semiconductor material(s), such as silicon, that may be epitaxially grown from the substrate 105.

According to an embodiment, each of the lower channel layer 110C and the upper channel layer 120C may have an equal thickness in the range of about 4-6nm and an equal length in the range of about 18-24nm, but is not limited thereto. However, according to an embodiment, each upper channel layer 120C may have a smaller width than each lower channel layer 110C, as shown in fig. 1C. For example, the upper channel layers 120C may each have a width of about 23-27nm, and the lower channel layers 110C may each have a width of about 43-47 nm. Due to the channel width difference between the lower channel structure 110 and the upper channel structure 120, the lower source/drain region formed on the lower channel structure 110 may also have a different width than the upper source/drain region formed on the upper channel structure 120, as shown in fig. 1D, which will be further described later.

In contrast, according to an embodiment, the upper channel structure 120 may have a greater number of channel layers than the lower channel structure 110. For example, the number of the upper channel layers 120C may be three (3), and the number of the lower channel layers 110C may be two (2), but the numbers are not limited thereto. Thus, although the channel width differs between the lower channel structure 110 and the upper channel structure 120, the two channel structures 110 and 120 may be formed of different numbers of channel layers such that the multi-stack semiconductor device 10 may have equal or similar effective channel widths (W in the lower and upper nanoflake transistors 10L and 10U _eff ). However, according to an embodiment, the two nano-sheet transistors 10L and 10U may not have equal or similar effective channel widths.

Referring to fig. 1A-1C, lower source/drain regions 112 may be formed on both ends of a lower channel structure 110 including a lower channel layer 110C in a channel length direction. The lower source/drain regions 112 may also be epitaxial structures grown from the lower channel layer 110C and/or the substrate 105 and, thus, may comprise the same or similar material(s) of the lower channel layer 110C and the substrate 105. Each lower channel layer 110C may be connected to lower source/drain regions 112 at both ends thereof. Similarly, upper source/drain regions 122 may be formed on both ends of the upper channel structure including the upper channel layer 120C in the channel length direction. The upper source/drain region 122 may be an epitaxial structure grown from the upper channel layer 120C and, thus, may comprise the same or similar material(s) of the upper channel layer 120C. Each upper channel layer 120C may be connected to upper source/drain regions 122 at both ends thereof.

Depending on the type of Field Effect Transistor (FET) to be formed by the lower source/drain region 112 or the upper source/drain region 122, the lower source/drain region 112 and the upper source/drain region 122 may be doped or implanted with a p-type or n-type dopant. For example, the lower source/drain region 112 may be doped or implanted with a P-type dopant such As boron (B), gallium (Ga), etc. to form the lower nano-sheet transistor 10L As a P-type FET (PFET), and the upper source/drain region 122 may be doped or implanted with an n-type dopant such As phosphorus (P), arsenic (As), indium (In), etc. to form the upper nano-sheet transistor 10U As an n-type FET (NFET). However, the embodiment is not limited thereto. The lower source/drain regions 112 may include n-type dopants and the upper source/drain regions 122 may include p-type dopants. In addition, the lower source/drain region 112 and the upper source/drain region 122 may both include n-type dopants or p-type dopants.

As shown in fig. 1A, an interlayer dielectric (ILD) structure 160 may be formed over the upper source/drain region 122 and between the upper source/drain region 122 and the lower source/drain region 112 at regions (hereinafter referred to as "overlapping regions") where the lower channel structure 110 and the lower source/drain region 112 vertically overlap with the upper channel structure 120 and the upper source/drain region 122, respectively. The overlap region includes a cross-section of the multi-stack semiconductor device (fig. 1A) along line I-I' shown in fig. 1E. As shown in fig. 1B, ILD structure 160 may also be formed over lower source/drain region 112 at regions of lower channel structure 110 and lower source/drain region 112 that do not vertically overlap with upper channel structure 120 and upper source/drain region 122, respectively (hereinafter referred to as "non-overlapping regions"). The non-overlapping region includes a cross-section of the multi-stack semiconductor device (fig. 1B) along line II-II' shown in fig. 1E. The multi-stack semiconductor device 10 may have an overlap region and a non-overlap region due to the difference in channel width between the lower channel structure 110 and the upper channel structure 120 as described above. ILD structure 160 may isolate lower source/drain region 112 from upper source/drain region 122 and may also isolate lower source/drain region 112 and upper source/drain region 122 from other circuit elements in multi-stack semiconductor device 10.

Fig. 1A-1C also illustrate that the first isolation structure 150-1 and the second isolation structure 150-2 may be formed on sides of the multi-stack semiconductor device 10. According to an embodiment, the first isolation structure 150-1 may be a diffusion break structure that isolates the lower source/drain regions 112 and the upper source/drain regions 122 from other source/drain regions in an integrated circuit including the multi-stack semiconductor device 10. According to an embodiment, the second isolation structure 150-2 may be a gate cut isolation structure that isolates the lower gate structure 115 and the upper gate structure from other gate structures in the channel width direction. The first isolation structure 150-1 and the second isolation structure 150-2 may each include silicon oxide or silicon nitride, but are not limited thereto.

Fig. 1D shows that the upper source/drain region 122 may have a smaller width than the lower source/drain region 112 in the channel width direction as previously described. This is because the upper source/drain region 122 is grown from the upper channel structure 120 including the upper channel layer 120C, the upper channel structure 120 having a smaller width than the lower channel structure 110 including the lower channel layer 110C, as described above and as shown in fig. 1C. Due to this channel width difference, a portion of the lower channel structure 110 may not vertically overlap with the upper channel structure 120, as shown in fig. 1C, and thus, an overlapping region is distinguished from a non-overlapping region in the multi-stack semiconductor device 10.

The multi-stack semiconductor device 10 may have the channel width differences described above to achieve a lower source/drain region contact structure (not shown) that extends downward from a back-end-of-line (BEOL) structure (not shown) above the multi-stack semiconductor device to rest on the top surface of the lower source/drain region 112 shown in fig. 1D. Otherwise, if the lower channel structure 110 and the upper channel structure 120 have equal channel widths, the lower source/drain region 112 and the upper source/drain region 122 may have equal widths, and thus, the lower source/drain region contact structure may have to be bent and connected to the side surface of the lower source/drain region 112, which is difficult to form and is prone to error.

Although the lower source/drain regions 112 are connected to the lower channel structure 110, they may be isolated from the lower gate structure 115 by lower inner spacers 117, as shown in fig. 1A. Similarly, upper source/drain regions 122 connected to upper channel structure 120 may be isolated from upper gate structure 125 by upper inner spacers 127, as also shown in fig. 1A. The inner spacers 117 and 127 may be formed of one or more materials including silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon borocarbonitride, silicon oxycarbonitride, and the like, but are not limited thereto.

Referring to fig. 1A-1C, the lower gate structure 115 may include a lower portion of a gate dielectric layer 115D, a lower work function metal layer 115F formed on the lower portion of the gate dielectric layer 115D, and a lower gate electrode 115P formed on the lower work function metal layer 115F. Further, the upper gate structure 125 may include an upper portion of the gate dielectric layer 115D, an upper work function metal layer 125F formed on the upper portion of the gate dielectric layer 115D, and an upper gate electrode 125M formed on the upper work function metal layer 125F. The lower and upper portions of gate dielectric layer 115D may be a continuous connected structure that is formed simultaneously in the fabrication of multi-stack semiconductor device 10.

In addition to surrounding channel layers 110C and 120C, gate dielectric layer 115D may also be formed on the top surface of substrate 105 and may extend outward in the channel length direction to first isolation structure 150-1 and outward in the channel width direction to second isolation structure 150-2 on the top surface of STI structure 106. In addition, the gate dielectric layer 115D may extend upward along sidewalls of the first and second isolation structures 150-1 and 150-2, and may also be formed on top surfaces of these isolation structures 150-1 and 150-2. In addition, a gate dielectric layer 115D surrounding the lower channel layer 110C and the upper channel layer 120C may extend along sidewalls of the ILD structure 160 and may be formed on a top surface of the ILD structure 160.

The gate dielectric layers 115D may each include an interface layer and a high-k layer. An interfacial layer may be provided to protect the channel layers 110C and 120C, promote growth of a high-k layer thereon, and provide a necessary characteristic interface with the channel layers 110C and 120C. The interfacial layer may be formed of silicon oxide, silicon oxynitride, but is not limited thereto. A high-k layer may be provided to allow for increased gate capacitance without an associated current leakage at the channel layers 110C and 120C. The high-k layer may be formed of one or more materials of hafnium oxide, hafnium silicate, hafnium oxynitride, hafnium silicon oxynitride, hafnium aluminum oxide, lanthanum aluminum oxide, zirconium silicate, zirconium oxynitride, zirconium silicon oxynitride, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, and/or lead scandium tantalum oxide, but is not limited thereto.

Gate dielectric layer 115D may be surrounded by lower work function metal layer 115F and upper work function metal layer 125F, and lower work function metal layer 115F and upper work function metal layer 125F may define the polarity type of lower nanoflake transistor 10L and upper nanoflake transistor 10U between p-type and n-type and/or control the respective gate threshold voltages for both nanoflake transistors 10L and 10U. According to an embodiment, a lower work function metal layer 115F may also be formed on the substrate 105, the STI structure 106, the lower portion of the first isolation structure 150-1, and the gate dielectric layer 115D on the lower portion of the second isolation structure 150-2, as shown in fig. 1A-1C. According to an embodiment, the upper work function metal layer 125F formed under the lowermost upper channel layer in the upper channel layer 120C may extend laterally outward over the lower gate electrode 115P to the first and second isolation structures 150-1 and 150-2 to connect to the lower work function metal layer 115F. In addition, the upper work function metal layer 125F may also be formed on the sidewalls and top surfaces of the first isolation structure 150-1, the second isolation structure 150-2, and the ILD structure 160, with the gate dielectric layer 115D therebetween.

The lower work function metal layer 115F and the upper work function metal layer 125F controlling the respective threshold voltages for the lower gate structure 115 and the upper gate structure 125 may each be formed of titanium (Ti), tantalum (Ta), or a compound thereof, such as TiN, tiAl, tiAlN, taN, tiC, taC, tiAlC, taCN, taSiN, but are not limited thereto. However, when the lower and upper nanoflake transistors 10L and 10U are to form PFETs and NFETs, respectively, the lower and upper work function metal layers 115F and 125F may be formed of different materials or material compounds to control the lower and upper gate structures 115 and 125. According to an embodiment, to form an NFET, a combination of TiN and TiC may be included in the upper workfunction metal layer 125F, while TiN without TiC or without carbon may be included in the lower workfunction metal layer 115F to form a PFET. However, the embodiment is not limited thereto. The lower work function metal layer 115F may be for an NFET and the upper work function metal layer 125F may be for a PFET, or both work function metal layers 115F and 125F may be for one of an NFET and PFET.

According to an embodiment, the lower gate electrode 115P may be formed of a material(s) including polysilicon, and the upper gate electrode 125M may be formed of tungsten (W), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), copper (Cu), or a compound thereof, but is not limited thereto. Each of the lower gate electrode 115P and the upper gate electrode 125M may be configured to receive an input voltage for the multi-stack semiconductor device 10 or to configure internal routing for the multi-stack semiconductor device 10 to adjacent circuits in an integrated circuit including the multi-stack semiconductor device 10. According to an embodiment, the polysilicon forming the lower gate electrode 115P may be doped or implanted with one or more dopants such As boron (B), gallium (Ga), phosphorous (As), arsenic (Sb), indium (In), etc. to enhance the conductor properties. Depending on the type of FET to be formed from the lower nanowire transistor 10L, the lower gate electrode 115P may include one or more selected dopants.

According to an embodiment, the lower gate electrode 115P and the upper gate electrode 125M may be connected to each other with the upper work function metal layer 125F therebetween as shown in fig. 1C to form, for example, a CMOS device.

According to an embodiment, the lower gate electrode 115P and the upper gate electrode 125M may not be formed between the lower channel layer 110C and between the upper channel layer 120C, and the lower work function metal layer 115F and the upper work function metal layer 125F may be formed therein, respectively. This is because the nanoscale channel spacing between channel layers 110C and/or 120C may not be wide enough to accommodate gate electrodes 115P and/or 125M therein. However, since the work function metal layers 115F and 125F are connected to the gate electrodes 115P and 125M, respectively, it may not be necessary to form the gate electrodes 115P and 125P therein.

Although polysilicon may result in a higher gate resistance than metal or metal compound for the gate electrode, polysilicon may be used as a conductive gate electrode due to its crystalline metallurgical structure. Furthermore, when polysilicon doped or implanted with the above dopants forms a gate electrode, it may be a cost-effective alternative to metals or metal compounds for the gate electrode. In addition, the lower gate electrode 115P including polysilicon provides a clearer visible boundary between the lower gate electrode 115P and the upper gate electrode 125M.

In addition, the lower gate electrode 115P may be formed of polysilicon because the wet etch selectivity of polysilicon to the metal or metal compound forming the lower work function metal layer 115F may be capable of preventing the lower work function metal layer 115F from being etched or damaged in the step of forming the upper work function metal layer 125F in the multi-stack semiconductor device 10, as will be described below.

Hereinafter, a method of manufacturing a multi-stack semiconductor device corresponding to the multi-stack semiconductor device 10 shown in fig. 1A to 1D is described with reference to fig. 2 to 7.

Fig. 2 is a flowchart of a method of manufacturing a multi-stack semiconductor device in which a lower gate electrode for a lower nano-sheet transistor is formed of polysilicon and an upper gate electrode for an upper nano-sheet transistor is formed of a metal or a metal compound, according to an embodiment. Fig. 3-7 illustrate multi-stack semiconductor device structures in a channel width direction view after various steps of the method of fabricating multi-stack semiconductor devices mentioned in the flow chart of fig. 2, according to an embodiment. It is to be understood that for brevity, the method of fabricating a multi-stack semiconductor device is described with reference to a channel width direction view.

The multi-stack semiconductor device structure shown in fig. 3-7 may be the same as or correspond to the multi-stack semiconductor device 10 shown in fig. 1A-1D. Accordingly, repeated descriptions of identical or corresponding structures or elements may be omitted hereinafter. When referring to the same structures or elements, the same reference numerals and reference characters used to describe the multi-stack semiconductor device 10 in fig. 1A-1D may be used hereinafter.

In step S110 of fig. 2, a multi-stack semiconductor device structure may be provided that includes a lower channel structure at a lower stack and an upper channel structure at an upper stack, wherein the lower channel structure and the upper channel structure are surrounded by an initial gate structure that includes a gate dielectric layer, an initial work function metal layer, and an initial gate electrode pattern that includes polysilicon or polysilicon containing dopants.

Referring to fig. 3, a multi-stack semiconductor device structure 10' may be provided on a substrate 105, including a lower channel structure 110 at a lower stack and an upper channel structure 120 at an upper stack. The two channel structures 110 and 120 may be surrounded by an initial gate structure 115'. According to an embodiment, each of the lower channel structure 110 and the upper channel structure 120 may be formed of a plurality of nano-sheet layers as channel layers. The nanoplatelets of channel structures 110 and 120 may be epitaxially grown from substrate 105. Although not shown in fig. 2, lower source/drain regions 112 and upper source/drain regions 122 may be formed at both ends of lower channel structure 110 and both ends of upper channel structure 120, respectively (as shown in fig. 1A-1D).

In the multi-stack semiconductor device structure 10', the upper channel structure 120 at the upper stack may have a smaller channel width than the lower channel structure 110 at the lower stack. Accordingly, the upper source/drain regions 122 grown from the upper channel structure 120 may have a smaller width than the lower source/drain regions 112 grown from the lower channel structure 110 (as shown in fig. 1A-1D). This channel width difference and source/drain region width difference may be provided to facilitate connection of source/drain contact structures on the top surface of the lower source/drain region 112, as described above with reference to fig. 1A-1D.

The initial gate structure 115 'of the multi-stack semiconductor device structure 10' may include a gate dielectric layer 115D, an initial work function metal layer 115F ', and an initial gate electrode pattern 115P'. The gate dielectric layer 115D with the initial work function metal layer 115F' thereon may surround both the lower channel layer 110C of the lower channel structure 110 and the upper channel layer 120C of the upper channel structure 120. The initial gate electrode pattern 115P 'may be patterned to be formed on the initial work function metal layer 115F'. Here, according to an embodiment, the initial gate electrode pattern 115P', which will form the lower gate electrode 115P of the multi-stack semiconductor device 10 shown in fig. 1A-1D in a later step, may be formed of polysilicon or polysilicon including a dopant.

The gate dielectric layer 115D and the initial work function metal layer 115F' thereon may also extend laterally over the substrate 105 and STI structure 106 to the first isolation structure 150-1 (shown in fig. 1A-1B) and the second isolation structure 150-2. The laterally extending gate dielectric layer 115D and the initial work function metal layer 115F' thereon may also extend upward along the sidewalls of the two isolation structures 150-1 and 150-2 and may also be formed on the top surfaces thereof. The gate dielectric layer 115D and the initial work function metal layer 115F' thereon may also be formed on the sidewalls and top surfaces of the ILD structure 160 (as shown in fig. 1A-1D).

In step S120 of fig. 2, the initial gate electrode pattern may be removed from the upper stack, leaving the initial gate electrode pattern at the lower stack as a lower gate electrode for the lower nanoflake transistor comprising polysilicon or polysilicon containing dopants.

Referring to fig. 4, according to an embodiment, the initial gate electrode pattern 115P 'may be removed from the upper stack of the multi-stack semiconductor device structure 10'.

The removing operation in this step may be performed by, for example, photolithography and dry etching such as Reactive Ion Etching (RIE) to selectively remove the initial gate electrode pattern 115P 'formed of polysilicon or polysilicon including a dopant up to a level between the two channel structures 110 and 120 without affecting other semiconductor elements including the gate dielectric layer 115D and the initial work function metal layer 115F'. For example, a hydrogen bromide (HBr) gas plasma mixed with oxygen may be used for the RIE etchant, but is not limited thereto. Although not shown, the upper channel structure 120 having the mask pattern thereon may be used as a mask structure for photolithography and dry etching operations. Thus, after the removal operation in this step, the gate dielectric layer 115D and the initial work function metal layer 115F 'may still remain at the upper stack of the multi-stack semiconductor device structure 10'.

The initial gate electrode pattern 115P' remaining below the level between the two channel structures 110 and 120 after the removal operation in this step becomes the lower gate electrode 115P for the multi-stack semiconductor device 10.

In step S130 of fig. 2, the initial work function metal layer may be removed from the upper stack, leaving the initial work function metal layer at the lower stack as a lower work function metal layer on which a lower gate electrode is formed for the lower nanoflake transistor.

Referring to fig. 5, according to an embodiment, the initial work function metal layer 115F 'in the upper stack of the multi-stack semiconductor device structure 10' may be removed, leaving the gate dielectric layer 115D.

In this step, the initial work function metal layer 115F 'surrounding the upper channel layer 120C and formed between the lowermost upper channel layer in the upper channel layer 120C and the lower gate electrode 115P may be removed by, for example, a wet etch using a wet etchant including hydrogen peroxide, but not limited thereto, which may selectively attack the material(s) forming the initial work function metal layer 115F' such as TiN or TiC with respect to the polysilicon forming the lower gate electrode 115P or the polysilicon including a dopant. The wet etch operation may also remove the initial work function metal layer 115F 'formed on the sidewalls and top surfaces of the first isolation structure 150-1 (not shown in fig. 4), the second isolation structure 150-2, and the ILD structure 160 above the level of the top surface of the initial gate electrode pattern 115P'. However, gate dielectric layer 115D may withstand this wet etch of initial work function metal layer 115F'.

Here, since the lower gate electrode 115P is formed of polysilicon or polysilicon including a dopant, wet etching control of removing the initial work function metal layer 115F' only to a level between the two channel structures 110 and 120 may be better performed than in the case where a metal or a metal compound is used for the lower gate electrode 115P.

By this removal operation, the initial work function metal layer 115F 'above the level of the top surface of the lower gate electrode 115P may be removed, but the initial work function metal layer 115F' remaining below the level becomes the lower work function metal layer 115F for the multi-stack semiconductor device 10 on which the lower gate electrode 115 is formed.

In step S140 of fig. 2, an upper work function metal layer for the upper nanoflake transistor may be formed at the upper stack where the initial work function metal layer was removed in step S130.

Referring to fig. 6, according to an embodiment, an upper workfunction metal layer 125F may be formed at the location where the initial workfunction metal layer 115F' was removed at the upper stack in a previous step. Here, according to an embodiment, the upper work function metal layer 125F may be formed of a material(s) different from the material(s) forming the initial work function metal layer 115F'.

In this step, the upper work function metal layer 125F may be formed by, for example, atomic Layer Deposition (ALD) but is not limited thereto, instead of the initial work function metal layer 115F' removed in the previous step. The upper work function metal layer 125F may be conformally formed to surround the upper channel layer 120C. An upper work function metal layer 125F may also be formed between the lowermost upper channel layer in the upper channel layer 120C and the top surface of the lower gate electrode 115P. The upper work function metal layer 125F may extend outwardly to the first isolation structure 150-1 (shown in fig. 1A-1B) and the second isolation structure 150-2 with the gate dielectric layer 115D therebetween on the top surface of the lower gate electrode 115P and on the top surfaces of the lower work function metal layers on the isolation structures 150-1, 150-2 and the ILD structure 160 (shown in fig. 1A-1C). In addition, an upper work function metal layer 125F may be formed on the sidewalls and top surfaces of the isolation structures 150-1, 150-2 and ILD structure 160 (shown in fig. 1A-1C), with a gate dielectric layer 115D therebetween.

In step S150 of fig. 2, an upper gate electrode including a metal or a metal compound for an upper nanoflake transistor may be formed on the upper work function metal layer to form a gate structure of a multi-stack semiconductor device in which at least the lower gate electrode and the upper gate electrode include different materials.

Referring to fig. 7, according to an embodiment, an upper gate electrode 125M may be formed on the upper work function metal layer 125F and planarized to complete the gate structure of the multi-stack semiconductor device 10 shown in fig. 1A-1D.

The upper gate electrode 125M may be deposited by, for example, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), or a combination thereof, but is not limited thereto. Planarization of the upper gate electrode 125M may be performed by, for example, chemical Mechanical Planarization (CMP) techniques, but is not limited thereto, such that a top surface of the upper gate electrode 125M may be coplanar with the upper work function metal layer 125F formed on the top surfaces of the isolation structures 150-1, 150-2 and ILD structure 160.

Through the above steps, the multi-stack semiconductor device 10 including the lower gate electrode 115P formed of cost-effective polysilicon or polysilicon containing a dopant can be obtained. In addition, the polysilicon or polysilicon containing dopants may also be able to protect the lower work function metal layer 115F from damage or etching based on the etch selectivity of the polysilicon to the metal or metal compound in this step of forming the upper work function metal layer 125F.

However, the above embodiments may still expose the risk of the lower work function metal layer 115F being etched or damaged during the fabrication of the multi-stack semiconductor device 10. For example, when the initial work function metal layer 115F ' in the upper stack of the multi-stack semiconductor device structure 10' is wet etched as shown in fig. 4, the initial work function metal layer 115F ' on the lower gate electrode 115P side may also be etched or damaged. Thus, in the following embodiments, additional isolation structures are introduced to better protect the lower work function metal layer of the multi-stack semiconductor device.

Fig. 8A-8D illustrate a multi-stack semiconductor device in which a lower gate electrode for a lower nanoflake transistor is formed of polysilicon or polysilicon including dopants and includes an intra-gate spacer that protects a lower work function metal layer for a lower gate structure, according to an embodiment.

Referring to fig. 8A-8D, the multi-stack semiconductor device 20 may include a lower nanoflake transistor 20L and an upper nanoflake transistor 20u formed on a substrate 205, and sti structures 206 may also be formed on the substrate 205 or around the substrate 205.

The various structures and elements forming multi-stack semiconductor device 20 may be the same as or similar to those of multi-stack semiconductor device 10 shown in fig. 1A-1D in terms of their structural, functional, and material properties. For example, the lower nanoflake transistor 20L may include a lower channel structure 210 including a lower channel layer 210C, a lower gate structure 215 including a gate dielectric layer 215D and a lower gate electrode 215P, and lower source/drain regions 212, which may be the same as or similar to corresponding structures or elements of the lower nanoflake transistor 10L of the multi-stack semiconductor device 10. In addition, upper nanoflake transistor 20U may include an upper channel structure 220 including an upper channel layer 220C, an upper gate structure 225 including a gate dielectric layer 215D, an upper work function metal layer 225F, and an upper gate electrode 225M, and upper source/drain regions 222, which may be the same as or similar to corresponding structures or elements of upper nanoflake transistor 10U of multi-stack semiconductor device 10. The lower inner spacer 217, the upper inner spacer 227, the first isolation structure 250-1, the second isolation structure 250-2, and the ILD structure 260 in the multi-stack semiconductor device 20 may also be the same as or similar to corresponding structures or elements in the multi-stack semiconductor device 10. Further, as in the multi-stack semiconductor device 10, the upper channel structure 220 may have a shorter channel width than the lower channel structure 210. Therefore, repeated descriptions thereof are omitted, and only different aspects of the multi-stack semiconductor device 20 are described hereinafter.

Fig. 8B shows that at the non-overlapping region, lower workfunction metal layer 215F may not be connected to upper workfunction metal layer 225F, while lower workfunction metal layer 115F may be connected to upper workfunction metal layer 115F as shown in fig. 1B. This is because, as will be described later, according to an embodiment, the first to sixth grooves G1 to G6, in which the intra-gate spacers 200 may be included, may be formed on the lower work function metal layer 215F below the level of the top surface of the lower gate electrode 215P at the non-overlapping region. According to an embodiment, the top surfaces of the intra-gate spacers 200 in the first to sixth grooves G1 to G6 may be coplanar with the top surface of the lower gate electrode 215P. According to an embodiment, the first to sixth grooves G1 to G6 having the intra-gate spacers 200 therein may extend along the first isolation structure 250-1 in the channel width direction.

Fig. 8C also shows that the lower workfunction metal layer 215F may not be connected to the upper workfunction metal layer 225F. This is because, according to an embodiment, seventh and eighth recesses G7-G8, which may also include intra-gate spacers 200, may be formed on lower work function metal layer 215F below the level of the top surface of lower gate electrode 215P at the non-overlapping region. According to an embodiment, as with the intra-gate spacers 200 in the first to sixth grooves G1 to G6, the intra-gate spacers 200 in the seventh and eighth grooves G7 to G8 may have a top surface that may be coplanar with a top surface of the lower gate electrode 215P.

The seventh and eighth grooves G7 to G8 may be formed at both side surfaces of the lower gate electrode 215P opposite to each other in the channel width direction, respectively. According to an embodiment, the seventh and eighth grooves G7-G8 having the intra-gate spacers 200 therein may extend along the second isolation structure 250-2 in the channel length direction. According to an embodiment, among the seventh and eighth grooves G7 to G8, the eighth groove G8 may be connected to the third and fourth grooves G3 to G4 extending in the channel width direction, and thus, the intra-gate spacers 200 therein may also be connected to each other.

According to an embodiment, when the lower channel structure 210 and the upper channel structure 220 have equal channel widths, and thus a non-overlapping region may not exist in the multi-stack semiconductor device 20, the first to sixth grooves G1 to G6 may not be formed in the multi-stack semiconductor device 20, and the seventh and eighth grooves G7 to G8 may still be formed at the same positions shown in fig. 8C.

The intra-gate spacers 200 included in the first through eighth recesses G1-G8 may serve to better protect the lower work function metal layer 215F during the step of forming the upper work function metal layer 225F in the multi-stack semiconductor device 20 and may remain therein after the multi-stack semiconductor device 20 is completed, as will be further described with reference to fig. 10-14. Similar to the lower and upper inner spacers 217 and 227, the gate inner spacer 200 may be formed of one or more materials including silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon borocarbonitride, silicon oxycarbonitride, and the like, but is not limited thereto.

Fig. 8C further illustrates that an intra-gate spacer 200 in each of the seventh and eighth recesses G7-G8, the lower work function metal layer 215F, and the gate dielectric layer 215D on the lower sidewalls of the second isolation structure 250-2 may be laterally interposed between the lower sidewalls of the second isolation structure 250-2 and the lower gate electrode 215P.

Referring back to fig. 8B, the lower gate electrode 215P may also be formed between adjacent first and second grooves G1-G2 having the intra-gate spacer 200 therein, between adjacent third and fourth grooves G3-G4 having the intra-gate spacer 200 therein, and between adjacent fifth and sixth grooves G5-G6 having the intra-gate spacer 200 therein. This is because, as will be further described with reference to fig. 10-14, the first to sixth grooves G1-G6 may be formed on both sides of the lower gate electrode 215P in the non-overlapping region at these positions above the lower work function metal layer 215F due to the difference in etching rate between the lower work function metal layer 215F and the lower gate electrode 215P.

Thus, while the fabrication process may include additional steps for the recess and intra-gate spacer 200, the multi-stack semiconductor device 20 in this embodiment may provide better protection for the lower work function metal layer 215F in the process of fabricating multi-stack semiconductor devices having different work function metal layers for the lower and upper nanoflake transistors.

Hereinafter, a method of manufacturing a multi-stack semiconductor device corresponding to the multi-stack semiconductor device 20 shown in fig. 8A to 8D will be described with reference to fig. 9 to 14.

Fig. 9 is a flowchart of a method of fabricating a multi-stack semiconductor device in which a lower gate electrode for a lower nanoflake transistor is formed of polysilicon and includes an intra-gate spacer that protects a lower work function metal layer for a lower gate structure, according to one embodiment. Fig. 10-14 illustrate multi-stack semiconductor device structures in a channel width direction view after various steps of the method of fabricating multi-stack semiconductor devices mentioned in the flowchart of fig. 9, in accordance with an embodiment. It is to be understood that for brevity, the method of fabricating a multi-stack semiconductor device is described with reference to a channel width direction view.

The multi-stack semiconductor device structure shown in fig. 10-14 may be the same as or correspond to the multi-stack semiconductor device 20 shown in fig. 8A-8D. Accordingly, repeated descriptions of identical or corresponding structures or elements may be omitted hereinafter. When referring to the same structures or elements, the same reference numerals and reference characters used to describe the multi-stack semiconductor device 20 in fig. 8A-8D may be used hereinafter.

In step S210 of fig. 9, a multi-stack semiconductor device structure may be provided that includes a lower channel structure at a lower stack and an upper channel structure at an upper stack, wherein the lower channel structure and the upper channel structure are surrounded by an initial gate structure that includes a gate dielectric layer, an initial work function metal layer, and an initial gate electrode pattern that includes polysilicon or polysilicon containing dopants.

Referring to fig. 10, a multi-stack semiconductor device structure 20' including a lower channel structure 210 at a lower stack and an upper channel structure 220 at an upper stack may be provided on a substrate 205. The two channel structures 210 and 220 may be surrounded by an initial gate structure 215'. Because the multi-stack semiconductor device structure 20 'may be the same as the multi-stack semiconductor device structure 10' shown in fig. 3, the initial gate structure 215 'of fig. 10 including the gate dielectric layer 215D, the initial work function metal layer 215F' and the initial gate electrode pattern 215P 'may be the same as or similar to the initial gate structure 115' of fig. 3 including the gate dielectric layer 115D, the initial work function metal layer 115F 'and the initial gate electrode pattern 115P'. Therefore, duplicate descriptions are omitted herein.

In step S220 of fig. 9, the initial gate electrode pattern and the initial work function metal layer are removed from the upper stack except between the upper channel layers of the upper channel structure such that the initial work function metal layer is removed further down than the initial gate electrode pattern at selected regions, thereby forming a plurality of recesses at selected regions on the initial work function metal layer at the lower stack and leaving the initial gate electrode pattern at the lower stack as a lower gate electrode for the lower nanoflake transistor.

Referring to fig. 11, according to an embodiment, the initial gate electrode pattern 215P 'and the initial work function metal layer 215F' may be removed from the upper stack of the multi-stack semiconductor device structure 20', except between the upper channel layers 220C and between the lowermost upper channel layer in the upper channel layer 220C and the initial gate electrode pattern 215P', based on different etch rates or etch selectivities between the polysilicon or the polysilicon containing dopants and the metal or metal compound.

The removing operation in this step may be performed by, for example, photolithography and dry etching such as Reactive Ion Etching (RIE) to remove the initial gate electrode pattern 215P 'formed of polysilicon or polysilicon containing a dopant and the initial work function metal layer 215F' to a level around between the two channel structures 210 and 220 without affecting other semiconductor elements including the gate dielectric layer 215D. For example, a combination of hydrogen bromide (HBr) gas and a fluorinated gas mixed with oxygen may be used for the RIE etchant, but is not limited thereto. Although not shown, the upper channel structure 220 having the mask pattern thereon may be used as a mask structure for photolithography and dry etching operations. Thus, after the removal operation in this step, the gate dielectric layer 215D may still remain at the upper stack of the multi-stack semiconductor device structure 20'. In addition, due to the dry etching performed in this step, the initial work function metal layer 215F ' formed between the upper channel layers 220C and between the uppermost upper channel layer 220C and the initial gate electrode pattern 215P ' may also remain in the multi-stack semiconductor device structure 20 '.

In addition, when a Reactive Ion Etch (RIE) having a higher etch rate for the material(s) forming the initial work function metal layer 215F 'than for the material(s) forming the initial gate electrode pattern 215P' is applied in this step, the initial work function metal layer 215F 'may be etched further down than the initial gate electrode pattern 215P'. As a result, a plurality of grooves including the first to eighth grooves G1 to G8 (shown in fig. 8A to 8D and fig. 11) may be formed at the sides of the initial gate electrode pattern 215P' at or below the level between the lower channel structure 210 and the upper channel structure 220. Grooves G1-G8 may be formed on initial workfunction metal layer 215F 'at the lower stack, and thus the bottom of each of grooves G1-G8 may be the top surface of initial workfunction metal layer 215F' remaining at that location. The heights of the grooves G1-G8 may correspond to the etch rate difference between the material(s) of the initial gate electrode pattern 215P 'and the material(s) of the initial work function metal layer 215F'. As described above, the initial gate electrode pattern 215P 'may include polysilicon or polysilicon containing a dopant therein, and the initial work function metal layer 215F' may include titanium (Ti), tantalum (Ta), or a compound thereof, such as TiN, tiAl, tiAlN, taN, tiC, taC, tiAlC, taCN, taSiN, but is not limited thereto.

The first through eighth recesses G1-G8 may be formed on the initial workfunction metal layer 215F' that remains at the non-overlapping region after dry etching, as described above with reference to fig. 1A-1D and fig. 8A-8D. Each of the first to sixth grooves G1 to G6 may extend in the channel width direction, wherein a portion of the initial gate electrode pattern 215P' remains after dry etching (fig. 8A to 8B). In addition, seventh and eighth grooves G7-G8, which may extend in the channel length direction, may be formed on the remaining initial work function metal layer 215F 'between the remaining initial gate electrode pattern 215P' and the second isolation structure 250-2 (fig. 8C and 11).

Among the first to eighth grooves G1 to G8, the first to sixth grooves G1 to G6 may be formed due to the difference in channel width between the lower channel structure 210 and the upper channel structure 220 as described above. Accordingly, when the lower channel structure 210 and the upper channel structure 220 have equal channel widths, and thus the multi-stack semiconductor device structure 20' does not have a non-overlapping region, the first to sixth grooves G1 to G6 may not be formed through photolithography and dry etching operations in this step, and the seventh and eighth grooves G7 to G8 may still be formed at the same positions as shown in fig. 11.

The initial gate electrode pattern 215P' remaining after the removing operation in this step may form the lower gate electrode 215P of the multi-stack semiconductor device 20 of fig. 8A-8D.

In step S230 of fig. 9, an intra-gate spacer may be formed in the recess and the initial work function metal layer between the upper channel layers may be removed, leaving the initial work function metal layer at the lower stack as a lower work function metal layer for the lower nanoflake transistor.

Referring to fig. 12, the intra-gate spacers 200 may be formed in the grooves including the first to eighth grooves G1 to G8, and the initial work function metal layer 215F 'remaining between the upper channel layers 220C and between the lowermost upper channel layer 220C and the lower gate electrode 215P after the dry etching in the previous step may be removed while the intra-gate spacers 200 protect the initial work function metal layer 215F' thereunder.

The intra-gate spacers 200 may be formed in the recesses by, for example, a thin film deposition technique such as Atomic Layer Deposition (ALD). The intra-gate spacer 200 may include one or more materials of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon borocarbonitride, silicon oxycarbonitride, and the like, but is not limited thereto. Although not shown in the drawings, the intra-gate spacers 200 may be formed by: the intra-spacer material(s) described above are deposited on the multi-stack semiconductor device structure 20' exposing the recess via ALD and pinch-off the intra-spacer material(s) formed in the recess via, for example, a wet etch using hydrofluoric acid (HF) or a mixture of hydrofluoric acid and nitric acid as a wet etchant, but is not limited thereto. The wet etch may selectively etch the material(s) forming the intra-gate spacers 200. According to one embodiment, through this deposition and etching operation, the intra-gate spacers 200 may be pinched off to remain in the recess. According to an embodiment, when the intra-gate spacer 200 is pinched off, the top surface of the intra-gate spacer 200 in the recess may be coplanar with the top surface of the lower gate electrode 215P.

When the intra-gate spacer 200 in the recess formed in the non-overlapping region covers or protects the initial work function metal layer 215F ' thereunder, the initial work function metal layer 215F ' remaining between the upper channel layers 220C at the upper stack after the previous dry etching operation may be removed by, for example, wet etching using a wet etchant including hydrogen peroxide, but not limited thereto, which may selectively attack the material(s) forming the initial work function metal layer 215F ' with respect to the polysilicon forming the lower gate electrode 215P or the polysilicon including the dopant and the material(s) forming the intra-gate spacer 200, such as silicon nitride, such as TiN or TiC. Thus, the initial workfunction metal layer 215F' may remain only at the lower stack to form the lower workfunction metal layer 215F of the multi-stack semiconductor device 20 shown in fig. 8A-8D.

Unless the recess is formed and the intra-gate spacer 200 is formed therein, there may still be a risk that the wet etchant used to remove the initial work function metal layer 215F ' remaining between the upper channel layer 220C may also attack the initial work function metal layer 215F ' of the initial gate structure 215 '. In other words, by forming the recess and the intra-gate spacer 200 therein, the initial work function metal layer 215F ' of the initial gate structure 215' may be protected when the initial work function metal layer 215F ' remaining between the upper channel layer 220C is removed in this step.

In step S240 of fig. 9, an upper work function metal layer comprising a material different from the initial work function metal layer may be formed on the upper channel structure, the lower gate electrode, and the intra-gate spacer for the upper nanoflake transistor.

Referring to fig. 13, according to an embodiment, an upper workfunction metal layer 225F may be formed at a location above the level between the two channel structures 110 and 120 where the initial workfunction metal layer 215F' was removed. Here, according to an embodiment, the upper work function metal layer 225F may be formed of a material(s) different from the material(s) forming the initial work function metal layer 215F'.

In this step, the upper work function metal layer 225F, which replaces the initial work function metal layer 215F' removed in the previous step, may be formed by, for example, atomic Layer Deposition (ALD), but is not limited thereto. The upper work function metal layer 225F may be conformally formed to surround the upper channel layer 220C. An upper work function metal layer 225F may also be formed on the top surface of the lower gate electrode 215P, extending outward to the first isolation structure 250-1 (shown in fig. 8A-8B) and the second isolation structure 250-2. In addition, an upper work function metal layer 225F may be formed on the sidewalls and top surfaces of the isolation structures 250-1, 250-2 and ILD structure 260 (shown in fig. 8A-8B), with a gate dielectric layer 215D therebetween.

In step S250, an upper gate electrode comprising a metal or metal compound for the upper nanoflake transistor may be formed on the upper work function metal layer to form a gate structure of a multi-stack semiconductor device in which at least the lower gate electrode and the upper gate electrode comprise different materials, and an intra-gate spacer is formed on the upper work function metal layer at a selected region.

Referring to fig. 14, according to an embodiment, an upper gate electrode 225M may be formed on the upper work function metal layer 225F and planarized to complete the gate structure of the multi-stack semiconductor device 20 shown in fig. 8A-8D.

The upper gate electrode 225M may be deposited by, for example, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), or a combination thereof, but is not limited thereto. Planarization of the upper gate electrode 225M may be performed by, for example, chemical Mechanical Planarization (CMP) techniques, but is not limited thereto, such that a top surface of the upper gate electrode 225M may be coplanar with the upper work function metal layer 225F formed on the top surfaces of the isolation structures 250-1, 250-2 and ILD structure 260.

Through the above steps, in the multi-stack semiconductor device 20, the lower gate electrode 215P may be formed of more cost-effective polysilicon or polysilicon containing a dopant, and the upper gate electrode 225M may be formed of a metal or a metal compound. In addition, the multi-stack semiconductor device 20 may include an intra-gate spacer 200 formed at selected regions including sides of the lower gate electrode 215P to better protect the initial work function metal layer 215F' at the lower stack that will become the lower work function metal layer 215F from being etched or damaged during the fabrication of the multi-stack semiconductor device 20.

In the above embodiments of a multi-stack semiconductor device including a lower nanoflake transistor and an upper nanoflake transistor, polysilicon or polysilicon including dopants is used instead of metal or metal compound to form a lower gate electrode for the lower nanoflake transistor for the purposes of cost effectiveness, manufacturing simplicity, and protection of the lower work function metal layer. However, at least because the metal or metal compound has a lower gate resistance than polysilicon or polysilicon containing dopants, the metal or metal compound may still be preferred as the material(s) for the gate electrode. Accordingly, the following embodiments provide a multi-stack semiconductor device in which a polysilicon layer is formed between a lower gate structure and an upper gate structure to protect a lower work function metal layer during the manufacturing of the multi-stack semiconductor device, and both the lower gate electrode and the upper gate electrode are formed of a metal or a metal compound.

Fig. 15A-15D illustrate a multi-stack semiconductor device in which a polysilicon layer is formed between a lower gate structure and an upper gate structure, according to an embodiment.

Referring to fig. 15A-15D, the multi-stack semiconductor device 30 may include a lower nanoflake transistor 30L and an upper nanoflake transistor 30U formed on a substrate 305, and an STI structure 306 may also be formed on the substrate 305.

The various structures and elements forming multi-stack semiconductor device 30 may be the same as or similar to those of multi-stack semiconductor device 10 as shown in fig. 1A-1D in terms of their structural, functional, and material properties. For example, in multi-stack semiconductor device 30, lower channel structure 310 including lower channel layer 310C, lower source/drain region 312, lower inner spacer 317, upper channel structure 320 including upper channel layer 320C, upper gate structure 325 including upper work function metal layer 325F and upper gate electrode 325M, upper source/drain region 322, upper inner spacer 327, first isolation structure 350-1, second isolation structure 350-2, and ILD structure 360 may be the same as or similar to corresponding structures or elements in multi-stack semiconductor device 10. In addition, the upper channel structure 320 may have a shorter channel width than the lower channel structure 310, as in the multi-stack semiconductor device 10. Therefore, repeated descriptions thereof are omitted, and only different aspects of the multi-stack semiconductor device 30 are described hereinafter.

Referring to fig. 15A-15C, in the multi-stack semiconductor device 30, the upper gate structure 325 is separated from the lower gate structure 315 by an isolation layer 330, and the isolation layer 330 may be formed of, for example, silicon nitride, but is not limited thereto. Similar to the lower gate structure 115 of the multi-stack semiconductor device 10, the lower gate structure 315 may include a lower portion of a gate dielectric layer 315D surrounding a lower channel layer 310C, a lower work function metal layer 315F formed thereon, and a lower gate electrode 315M formed on the lower work function metal layer 315F. As with the gate dielectric layer 115D in the multi-stack semiconductor device 10, the gate dielectric layer 315D may also be formed on the sidewalls and top surfaces of the substrate 305, the STI structure 306, and the first, second, and ILD structures 350-1, 350-2, 360.

However, unlike in the multi-stack semiconductor device 10, the gate dielectric layer 315D in the multi-stack semiconductor device 30 may also surround the isolation layer 330, and the lower work function metal layer 315F may also be formed between the uppermost one of the lower channel layers 315C and the isolation layer 330, with the gate dielectric layer 315D therebetween.

Further, according to an embodiment, the lower gate electrode 315M may be formed of a metal such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or a compound thereof, but is not limited thereto.

Further, according to an embodiment, the polysilicon layer 340 may be formed on the top surface of the lower gate electrode 315M and the portion of the lower work function metal layer 315F on the lower gate electrode 315M. Further, according to an embodiment, an upper work function metal layer 325F extending laterally to the first and second isolation structures 350-1 and 350-2 may be formed on a top surface of the polysilicon layer 340 such that the polysilicon layer 340 may electrically connect the lower gate structure 315 with the upper gate structure 325, through which both gate structures 315 and 325 may share a gate input signal.

Because of its crystalline metallurgical structure, polysilicon may still be used as a conductive gate electrode material, and thus, polysilicon layer 340 formed on lower gate electrode 315M may be capable of electrically connecting the two gate structures 315 and 325. Furthermore, according to an embodiment, the polysilicon layer 340 may also be doped or implanted with one or more dopants such As boron (B), gallium (Ga), phosphorus (As), arsenic (Sb), indium (In), etc., to enhance the conductor properties In the polysilicon layer 340.

According to an embodiment, the polysilicon layer 340 may be formed such that its top surface is at the same level as the top surface of the isolation layer 330 or below the level of the top surface of the isolation layer 330 and its bottom surface is at the same level as the bottom surface of the isolation layer 330 or above the level of the bottom surface of the isolation layer 330. In addition, the polysilicon layer 340 formed on the top surface of the lower gate electrode 315M may be laterally interposed between the isolation layer 330 and the first isolation structure 350-1 and between the polysilicon layer 340 and the second isolation structure 350-2.

The polysilicon layer 340 may be used to protect a work function metal layer formed on the underlying stack of the multi-stack semiconductor device structure during the fabrication of the multi-stack semiconductor device 30, as will be described later with reference to fig. 17-22. The polysilicon layer 340 may remain in the completed multi-stack semiconductor device 30 and serve as part of the lower gate electrode of the lower nanoflake transistor 30L.

Hereinafter, a method of manufacturing a multi-stack semiconductor device corresponding to the multi-stack semiconductor device 30 shown in fig. 15A to 15D will be described with reference to fig. 16 to 22.

Fig. 16 is a flowchart of a method of manufacturing a multi-stack semiconductor device in which a polysilicon layer is formed between a lower gate structure and an upper gate structure, and both the lower gate electrode and the upper gate electrode are formed of a metal or a metal compound, according to an embodiment. Fig. 17-22 illustrate multi-stack semiconductor device structures in a channel width direction view after various steps of the method of fabricating multi-stack semiconductor devices mentioned in the flowchart of fig. 16, in accordance with an embodiment. It is to be understood that for brevity, the method of fabricating a multi-stack semiconductor device is described with reference to a channel width direction view.

The multi-stack semiconductor device structure shown in fig. 17-22 may be the same as or correspond to the multi-stack semiconductor device 30 shown in fig. 15A-15D. Accordingly, repeated descriptions of identical or corresponding structures or elements may be omitted hereinafter. When referring to the same structures or elements, the same reference numerals and reference characters used to describe the multi-stack semiconductor device 30 in fig. 15A-15D may be used hereinafter.

In step S310 of fig. 16, a multi-stack semiconductor device structure including a lower channel structure at a lower stack and an upper channel structure at an upper stack may be provided, wherein the lower channel structure and the upper channel structure are surrounded by an initial gate structure including a gate dielectric layer, an initial work function metal layer, and an initial gate electrode pattern including a metal or a metal compound.

Referring to fig. 17, a multi-stack semiconductor device structure 30' including a lower channel structure 310 at a lower stack and an upper channel structure 320 at an upper stack may be provided on a substrate 305. The two channel structures may be surrounded by an initial gate structure 315'. According to an embodiment, each of the lower channel structure 310 and the upper channel structure 320 may be formed of a plurality of nano-sheet layers as channel layers. The nanoplatelets of channel structures 310 and 320 may be epitaxially grown from substrate 305.

As in the multi-stack semiconductor device structure 10' shown in fig. 3, the upper channel structure 320 may have a smaller channel width than the lower channel structure 310. Accordingly, the upper source/drain regions 322 grown from the upper channel structure 320 may have a smaller width than the lower source/drain regions 312 grown from the lower channel structure 310 (as shown in fig. 15A-15D). Such channel width differences and source/drain region width differences may be provided to facilitate connection of source/drain contact structures on the top surface of the lower source/drain region 312, as described in previous embodiments above.

The initial gate structure 315 'of the multi-stack semiconductor device structure 30' may include a gate dielectric layer 315D, an initial work function metal layer 315F ', and an initial gate electrode pattern 315M'. The gate dielectric layer 315 having the initial work function metal layer 315F' thereon may surround both the lower channel layer 310C of the lower channel structure 310 and the upper channel layer 320C of the upper channel structure 320. The initial gate electrode pattern 315M 'may be patterned to be formed on the initial work function metal layer 315F'. Here, according to an embodiment, the initial gate electrode pattern 315M' of the lower gate electrode 315M of the multi-stack semiconductor device 30 shown in fig. 15A to 15D to be formed in a later step may be formed of a metal such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or a compound thereof, but is not limited thereto.

The gate dielectric layer 315D and the initial work function metal layer 315F' thereon may also extend laterally over the substrate 305 and STI structure 306 to the first isolation structure 350-1 (shown in fig. 15A-15B) and the second isolation structure 350-2. The laterally extending gate dielectric layer 315D and the initial work function metal layer 315F' thereon may also extend upward along the sidewalls of the two isolation structures 350-1 and 350-2 and may also be formed on the top surfaces thereof. The gate dielectric layer 315D and the initial work function metal layer 315F' thereon may also be formed on the sidewalls and top surfaces of the ILD structure 360 (as shown in fig. 15A-15D).

According to an embodiment, an isolation layer 330 may be formed between the lower channel structure 310 and the upper channel structure 320 and surrounded by the gate dielectric layer 315D and the initial work function metal layer 315F'. Although not shown, isolation layer 330 may replace a silicon germanium layer interposed between two channel structures 310 and 320 epitaxially grown from substrate 305 with channel layers 310C and 320C.

In step S320 of fig. 16, the initial gate electrode pattern and the initial work function metal layer may be removed from the upper stack, except between the upper channel layers of the upper channel structure and below the lowermost upper channel layer in the upper channel layer.

Referring to fig. 18, according to an embodiment, the initial gate electrode pattern 315M ' and the initial work function metal layer 315F ' may be removed from the upper stack of the multi-stack semiconductor device structure 30', except between the upper channel layers 320C and between the lowermost upper channel layer in the upper channel layers 320C and the isolation layer 330.

According to an embodiment, the removing operation in this step may be performed by, for example, photolithography and dry etching such as Reactive Ion Etching (RIE) to selectively remove the initial gate electrode pattern 315M 'and the initial work function metal layer 315F' down to a level of the bottom surface of the isolation layer 330 or a level below the bottom surface of the isolation layer 330, or to a level between the bottom surface and the top surface of the isolation layer 330. For example, a fluorinated gas plasma mixed with oxygen may be used for the RIE etchant, but is not limited thereto. Although not shown, the upper channel structure 320 having the mask pattern thereon may be used as a mask structure for photolithography and dry etching operations. Accordingly, after the removal operation in this step, the initial work function metal layer 315F 'formed between the upper channel layers 320C and between the lowermost upper channel layer in the upper channel layer 320C and the isolation layer 330 may remain at the upper stack of the multi-stack semiconductor device structure 30'. Gate dielectric layer 315D may also survive the removal operation in this step.

In step S330 of fig. 16, a polysilicon structure may be formed in the space where the initial work function metal layer and the initial gate electrode pattern were removed in step S320, leaving the initial gate electrode pattern at the lower stack under the polysilicon structure as a lower gate electrode for the lower nanoflake transistor.

Referring to fig. 19, according to an embodiment, a polysilicon structure 340 'may be formed in a space where the initial gate electrode pattern 315M' and the initial work function metal layer 315F 'are removed, and the polysilicon structure 340' may be planarized.

In this step, the formation of the polysilicon structure 340' may be performed by, for example, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), or a combination thereof, but is not limited thereto. Planarization of the polysilicon structure 340 'may be performed by, for example, chemical Mechanical Planarization (CMP) techniques, but is not limited thereto, such that the top surface of the polysilicon structure 340' may be coplanar with the top surfaces of the isolation structures 350-1, 350-2 and ILD structure 360.

According to an embodiment, the polysilicon structure 340' may be formed on the top surface of the initial gate electrode 315M, and in addition, the polysilicon structure 340' may cover the top surface of the initial work function metal layer 315F ' that remains and is exposed upward after the removal operation in the previous step.

The initial gate electrode pattern 315M 'remaining under the polysilicon structure 340' in this step forms the lower gate electrode 315M of the multi-stack semiconductor device 30.

In step S340 of fig. 16, the polysilicon structure may be removed down to a predetermined level between the two channel structures to form a polysilicon layer therebetween.

Referring to fig. 20, according to an embodiment, the polysilicon structure 340 'may be removed down to a level of the top surface of the isolation layer 330 or a level below the top surface of the isolation layer 330 to form the polysilicon layer 340 at the lower gate electrode 315M and the initial work function metal layer 315F' at one side of the lower channel structure 310.

Although not shown, the operation of removing the polysilicon structure 340' in this step may be performed by, for example, another photolithography and dry etching, again based on the upper channel structure 320 having the mask pattern thereon.

According to an embodiment, the removing operation may be performed such that a top surface of the polysilicon structure 340' remaining after the removing operation may be at a level of a top surface of the isolation layer 330 or below the top surface of the isolation layer 330 to form the polysilicon layer 340 on the lower gate electrode 315M.

Further, according to an embodiment, in this step, the polysilicon layer 340 may be doped or implanted with one or more dopants, such As boron (B), gallium (Ga), phosphorus (P), arsenic (As), indium (In), and the like. Alternatively, according to an embodiment, the doping or implantation operation may be performed on the polysilicon structure 340 'before removing the polysilicon structure 340' to leave only the polysilicon layer 340 in a previous step.

In step S350 of fig. 16, the initial work function metal layer between the upper channel layers and below the lowermost upper channel layer in the upper channel layer may be removed based on the polysilicon layer, thereby leaving the initial work function metal layer below the polysilicon layer as a lower work function metal layer for the lower nanoflake transistor.

Referring to fig. 21, according to an embodiment, the initial work function metal layer 315F' remaining between the upper channel layers 320C and between the lowermost upper channel layer in the upper channel layer 320C and the isolation layer 330 may be removed.

In this step, the initial work function metal layer 315F 'may be removed by, for example, a wet etch using a wet etchant including hydrogen peroxide, which may selectively attack the material(s) forming the initial work function metal layer 315F', such as TiN or TiC, with respect to the polysilicon included in the polysilicon layer 340 or the polysilicon including a dopant and the gate dielectric layer 315D, but is not limited thereto. Accordingly, the initial work function metal layer 315F' formed under the polysilicon layer 340 may be prevented from being etched or damaged.

After the removal operation of the initial work function metal layer 315F 'in the upper stack of the multi-stack semiconductor device structure 30', the initial work function metal layer 315F 'remaining in the lower stack of the multi-stack semiconductor device structure 30' becomes the lower work function metal layer 315F for the multi-stack semiconductor device 30.

Alternatively and/or additionally, according to an embodiment, polysilicon layer 340 may be further removed by etching only the portion thereof on lower gate electrode 315M prior to removing initial work function metal layer 315F 'in the upper stack of multi-stack semiconductor device structure 30'. According to an embodiment, the further removal operation may leave at least a portion of the polysilicon layer 340 on the initial work function metal layer 315F' that remains and is exposed upward distal of the lower channel structure 310 and the upper channel structure 320 after the removal operation in the previous step of fig. 18. This optional and/or additional step may reduce the higher gate resistance that may be created by polysilicon layer 340 because polysilicon layer 340 may not be formed on the top surface of lower gate electrode 310M, but rather it may be formed on the remaining and exposed initial work function metal layer 315F'.

In step S360 of fig. 16, an upper work function metal layer including a material different from the initial work function metal layer for the upper nanoflake transistor may be formed on the upper channel structure and the polysilicon layer, and an upper gate electrode for the upper nanoflake transistor may be formed on the upper work function metal layer to form a gate structure of the multi-stack semiconductor device, wherein the lower gate structure and the upper gate structure are connected through the polysilicon layer.

Referring to fig. 22, according to an embodiment, an upper work function metal layer 325F may be formed where the initial work function metal layer 315F 'in the upper stack of the multi-stack semiconductor device structure 30' is removed, and an upper gate electrode 325M may be formed on the upper work function metal layer 325F and planarized to complete the gate structure of the multi-stack semiconductor device 30 shown in fig. 15A-15D.

Here, according to an embodiment, the upper work function metal layer 325F may include a material(s) different from the material(s) included in the initial work function metal layer 315F'.

In this step, the upper work function metal layer 325F, which replaces the initial work function metal layer 315F 'removed from the upper stack of the multi-stack semiconductor device structure 30' in the previous step, may be formed by, for example, atomic Layer Deposition (ALD), but is not limited thereto. The upper work function metal layer 325F may be conformally formed around the upper channel layer 320C. An upper work function metal layer 325F may also be formed on the top surface of polysilicon layer 340 and may also be formed on the sidewalls and top surfaces of isolation structures 350-1, 350-2 and ILD structure 360 (shown in fig. 15A-15D), with gate dielectric layer 315D therebetween.

The upper gate electrode 325M may be deposited by, for example, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD), or a combination thereof, but is not limited thereto. Planarization of the upper gate electrode 325M may be performed by, for example, chemical Mechanical Planarization (CMP) techniques, but is not limited thereto, such that a top surface of the upper gate electrode 325M may be coplanar with a top surface of the upper work function metal layer 325F formed on the isolation structures 350-1, 350-2 and ILD structure 360.

Through the above steps, the multi-stack semiconductor device 30 may be obtained in which the polysilicon layer 340 is formed on the lower gate electrode 315M and the lower work function metal layer at one side of the lower channel structure. Due to the polysilicon layer 340, the lower work function metal layer 315F of the multi-stack semiconductor device 30 can be prevented from being damaged or etched during the manufacturing process of the multi-stack semiconductor device 30.

The present disclosure has been presented in the above embodiments in which each of the lower field effect transistor and the upper field effect transistor in the multi-stack semiconductor device is a nano-sheet transistor. However, according to an embodiment, the present disclosure may also be applied to a multi-stack semiconductor device in which at least one of the lower field effect transistor and the upper field effect transistor is a fin field effect transistor (FinFET) in which one or more vertical fin structures as a channel layer are surrounded by a gate structure, and the other is a nano-sheet transistor, and to a multi-stack semiconductor device in which each of the lower field effect transistor and the upper field effect transistor is a FinFET.

Further, the present disclosure has been presented in the above embodiments in which a multi-stack semiconductor device includes a lower channel structure and an upper channel structure having different channel widths. However, the present disclosure may also be applied to a multi-stack semiconductor device in which the lower channel structure and the upper channel structure have equal channel widths.

Further, the present disclosure has been presented in the above embodiments, in which the multi-stack semiconductor device includes a lower channel structure and an upper channel structure, and the upper channel structure has a greater number of channel layers than the lower channel structure. However, the present disclosure may also be applied to a multi-stack semiconductor device in which the lower channel structure has a greater number of channel layers than the upper channel structure, or the lower channel structure has the same number of channel layers as the upper channel structure.

Referring to fig. 23, the electronic apparatus 4000 may include at least one application processor 4100, a communication module 4200, a display/touch module 4300, a storage device 4400, and a buffer RAM 4500. According to an implementation, the electronic device 4000 may be a mobile device such as a smart phone or tablet computer, but is not limited thereto.

The application processor 4100 may control the operation of the electronic device 4000. The communication module 4200 is implemented to perform wireless or wired communication with external devices. The display/touch module 4300 is implemented to display data processed by the application processor 4100 and/or receive data through a touch panel. The storage device 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a Solid State Drive (SSD), a universal flash memory (UFS) device, or the like. The storage device 4400 may perform buffering of user data and map data as described above.

The buffer RAM 4500 may temporarily store data for processing the operation of the electronic device 4000. For example, the buffer RAM 4500 may be a volatile memory such as a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), a low power consumption double data rate (LPDDR) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, rambus Dynamic Random Access Memory (RDRAM), etc.

At least one component in the electronic device 4000 may include at least one of the multi-stack semiconductor devices 10, 20, and 30 described above with reference to fig. 1A-1D through 22.

The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting the present disclosure. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above embodiments without materially departing from the present disclosure.

Claims

1. A multi-stack semiconductor device, comprising:

a substrate;

a lower field effect transistor in which a lower channel structure is surrounded by a lower gate structure, the lower gate structure comprising a lower work function metal layer and a lower gate electrode; and

an upper field effect transistor in which an upper channel structure is surrounded by an upper gate structure, the upper gate structure comprising an upper work function metal layer and an upper gate electrode,

Wherein the lower gate electrode comprises polysilicon or polysilicon containing a dopant and the upper gate electrode comprises a metal or metal compound.

2. The multi-stack semiconductor device of claim 1, wherein the lower work function metal layer and the upper work function metal layer each comprise a different material.

3. The multi-stack semiconductor device of claim 2, wherein the upper channel structure has a channel width that is less than a channel width of the lower channel structure,

wherein each of the lower channel structure and the upper channel structure has one or more nanoplatelet channel layers, and

wherein the upper channel structure has a greater number of the nanoplatelet channel layers than the lower channel structure.

4. The multi-stack semiconductor device of claim 1, further comprising an intra-gate spacer formed between the lower work function metal layer and the upper work function metal layer at a selected region where the lower channel structure does not vertically overlap the upper channel structure.

5. The multi-stack semiconductor device of claim 4, wherein a top surface of the lower work function metal layer under the intra-gate spacer is below a level of a top surface of the lower gate electrode at the selected region.

6. The multi-stack semiconductor device of claim 5, wherein the upper work function metal layer is formed on and connected to the lower gate electrode.

7. The multi-stack semiconductor device of claim 1, wherein the upper channel structure has a channel width that is less than a channel width of the lower channel structure,

8. The multi-stack semiconductor device of claim 1, wherein each of the lower channel structure and the upper channel structure has one or more nanoplatelet channel layers.

9. The multi-stack semiconductor device of claim 1, wherein the lower channel structure has one or more nanoplate channel layers for nanoplate transistors and the upper channel structure has one or more vertical fin structures as channel layers for fin field effect transistors.

10. The multi-stack semiconductor device of claim 1, further comprising an intra-gate spacer formed between the lower work function metal layer and the upper work function metal layer at a selected region.

11. The multi-stack semiconductor device of claim 10, wherein a top surface of the lower work function metal layer under the intra-gate spacer is below a level of a top surface of the lower gate electrode at the selected region.

12. The multi-stack semiconductor device of claim 10, wherein the upper channel structure has a channel width that is less than a channel width of the lower channel structure,

13. The multi-stack semiconductor device of claim 10, wherein the selected region comprises a side of the lower gate electrode at which the intra-gate spacer does not vertically overlap with any of the lower channel structure and the upper channel structure when viewed in a channel width direction.

14. The multi-stack semiconductor device of claim 10, wherein the lower work function metal layer and the upper work function metal layer each comprise a different material.

15. A multi-stack semiconductor device, comprising:

a substrate;

a lower field effect transistor in which a lower channel structure is surrounded by a lower gate structure, the lower gate structure comprising a lower work function metal layer and a lower gate electrode;

an upper field effect transistor in which an upper channel structure is surrounded by an upper gate structure, the upper gate structure comprising an upper work function metal layer and an upper gate electrode; and

a polysilicon layer between the lower work function metal layer and the upper work function metal layer at selected regions on the lower work function metal layer,

wherein each of the lower gate electrode and the upper gate electrode comprises a metal or a metal compound, and

wherein the polysilicon layer comprises polysilicon or polysilicon containing a dopant.

16. The multi-stack semiconductor device of claim 15, wherein the polysilicon layer connects the lower work function metal layer to the upper work function metal layer.

17. The multi-stack semiconductor device of claim 16, wherein the selected region comprises a region on one side of the lower channel structure and the upper channel structure in which the polysilicon layer does not vertically overlap with any of the lower channel structure and the upper channel structure when viewed in a channel width direction.

18. The multi-stack semiconductor device of claim 17, further comprising an isolation layer between the lower channel structure and the upper channel structure.

19. The multi-stack semiconductor device of claim 18, wherein the polysilicon layer is formed on the lower gate electrode on one side of the isolation layer.