CN117524986A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117524986A
CN117524986A CN202210903950.XA CN202210903950A CN117524986A CN 117524986 A CN117524986 A CN 117524986A CN 202210903950 A CN202210903950 A CN 202210903950A CN 117524986 A CN117524986 A CN 117524986A
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dielectric layer
gate structure
fins
metal gate
forming
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于海龙
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210903950.XA priority Critical patent/CN117524986A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises discrete fins and a pseudo gate structure crossing the fins, and the bottoms of the pseudo gate structures on two sides of the fins are provided with protruding parts; forming a first dielectric layer which covers the fins and has the surface flush with the top surface of the pseudo gate structure on the substrate, removing the pseudo gate structure to form a groove, and extending the bottom of the groove into the first dielectric layer; forming a second dielectric layer on the side wall of the groove, wherein the second dielectric layer also fills up the part of the groove extending into the first dielectric layer; and forming a metal gate structure with the surface flush with the top surface of the first dielectric layer in the groove. The semiconductor structure and the forming method thereof can improve the 3D corner problem of the FinFET.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In order to improve the performance of semiconductor devices, logic CMOS devices continue to be studied. During the past few years, MOSFETs have changed from planar structures to fin structures (finfets), improving short channel effects, allowing devices with higher drive currents and lower leakage currents.
However, finfets have the problem of 3D cap of Metal Gate (MG), resulting in finfets with high capacitance that affects the ac performance of the device. Therefore, improving the 3D corner problem is critical to improving Finfet performance.
Disclosure of Invention
The technical problem to be solved by the application is to improve the 3D burner problem of FinFETs.
In order to solve the above technical problems, the present application provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises discrete fins and a pseudo gate structure crossing the fins, and the bottoms of the pseudo gate structures on two sides of the fins are provided with protruding parts; forming a first dielectric layer which covers the fins and has the surface flush with the top surface of the pseudo gate structure on the substrate, removing the pseudo gate structure to form a groove, and extending the bottom of the groove into the first dielectric layer; forming a second dielectric layer on the side wall of the groove, wherein the second dielectric layer also fills up the part of the groove extending into the first dielectric layer; and forming a metal gate structure with the surface flush with the top surface of the first dielectric layer in the groove.
In some embodiments of the present application, the method of forming the second dielectric layer includes: forming a second dielectric material layer on the side wall and the bottom of the groove, wherein the second dielectric material layer also fills the part of the groove extending into the first dielectric layer; and removing the second dielectric material layer in the downward orthographic projection range of the top of the groove to form the second dielectric layer.
In some embodiments of the present application, the second dielectric material layer is formed using an atomic layer deposition process.
In some embodiments of the present application, the atomic layer deposition process is performed at a temperature of 300-400 ℃ and at a power of 100-300W.
In some embodiments of the present application, a dry etching process is used to remove the second dielectric material in a top-down orthographic projection range of the trench.
In some embodiments of the present application, the material of the second dielectric layer includes at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
In some embodiments of the present application, before forming the metal gate structure, the method further includes: and etching the second dielectric layer by adopting an isotropic etching process, so that the side wall of the second dielectric layer and the side wall of the first dielectric layer are coplanar.
In some embodiments of the present application, the critical dimensions of the metal gate structure and the dummy gate structure are the same.
In some embodiments of the present application, the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.
The present application also provides a semiconductor structure comprising: a substrate including discrete fins thereon; a metal gate structure spanning the fins; the first dielectric layer is positioned on the substrate and covers the fins, and the surface of the first dielectric layer is flush with the top surface of the metal gate structure; and the second dielectric layer is positioned between the first dielectric layer and the metal gate structure, and the bottom of the second dielectric layer extends into the first dielectric layer from the side wall of the metal gate structure.
In some embodiments of the present application, the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer includes at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
The present application also provides another semiconductor structure comprising: a substrate including discrete fins thereon; a metal gate structure spanning the fins; the first dielectric layer is positioned on the substrate and covers the fins, and the surface of the first dielectric layer is flush with the top surface of the metal gate structure; and the second dielectric layer extends from the bottom side wall of the metal gate structure into the first dielectric layer.
In some embodiments of the present application, the material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer includes at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
After the groove is formed by removing the pseudo gate structure, a second dielectric layer is formed on the side wall of the groove, the second dielectric layer can fill the part of the groove extending into the first dielectric layer, and the fooling structure at the bottom of the groove is eliminated, so that the problem of 3D (three-dimensional) burner can be effectively avoided when the metal gate structure is formed in the groove, and the alternating current performance of the device is improved.
Further, before forming the metal gate structure, etching the second dielectric layer through an isotropic etching process to enable the side wall of the second dielectric layer to be coplanar with the side wall of the first dielectric layer, and further enabling the CD of the metal gate structure to keep the CD of the dummy gate structure.
Drawings
The following figures describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to like structure throughout the several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and that the drawings are for illustration and description purposes only and are not intended to limit the scope of the present application, other embodiments may equally well accomplish the intent of the invention in this application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a FinFET structure;
fig. 2 to fig. 4 are schematic structural views illustrating steps of a method for forming a FinFET structure;
fig. 5 is a flow chart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 6 to 13 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The following description provides specific applications and requirements to enable any person skilled in the art to make and use the teachings of the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
Referring to fig. 1, a FinFET structure includes a substrate 10, where the substrate 10 includes a discrete fin 11, a dielectric layer 20 is formed on the substrate 10 between adjacent fins 11, and dielectric layers 21 are formed on sidewalls and surfaces of the fins 11, where materials of the dielectric layer 20 and the dielectric layers 21 may be the same or different. The fin 11 is spanned with a metal gate structure 60, the metal gate structures 60 at two sides of the fin 11 are provided with protruding portions 61, and the dielectric layer 20 is further provided with an interlayer dielectric layer which covers the fin 11 and has a surface level with the top surface of the metal gate structure 60. The interlayer dielectric layer is not shown in fig. 1 for clarity of illustration of the protrusion 61 of the metal gate structure 60. Since the metal gate structure 60 has the protrusion 61, the protrusion 61 may generate parasitic capacitance with the source-drain current, and thus may have a great influence on Alternating Current (AC) performance of the device.
The formation process of the metal gate structure 60 is explained with reference to the drawings, and the reason for forming the protrusion 61 is analyzed, and the following fig. 2 to 4 show cross-sectional views at the plane of the dashed frame in fig. 1.
Referring to fig. 2, a dummy gate structure 30 is formed across the fin 11. Due to the deposition process characteristics, the protruding portions 31 are formed at the bottoms of the dummy gate structures 30 at both sides of the fin 11, and the protruding portions 31 are specifically located at corners formed by the dummy gate structures 30 and the fin 11. After the dummy gate structure 30 is formed, an interlayer dielectric layer 40 is formed on the dielectric layer 20 to cover the fins 11 and to have a surface flush with the top surface of the dummy gate structure 30.
Referring to fig. 3, the dummy gate structure 30 is removed to form a trench 50, and the bottom of the trench 50 extends into the interlayer dielectric layer 40 to form a patterning structure.
Referring to fig. 4, the trench 50 is filled with metal to form a metal gate structure 60. Since the metal is deposited, the metal is filled in the fin structure, and thus a protrusion 61, also called "3D com", is formed at the corner formed by the metal gate structure 60 and the fin 11.
Based on the above, the technical scheme of the application provides a method for forming a semiconductor structure, after forming a trench, a film layer is formed to fill a patterning structure, and then a metal gate structure is formed, so that the phenomenon of '3D com' can be effectively avoided.
Referring to fig. 5, a method for forming a semiconductor structure according to an embodiment of the present application includes:
step S1: providing a substrate, wherein the substrate comprises discrete fins and a pseudo gate structure crossing the fins, and the bottoms of the pseudo gate structures on two sides of the fins are provided with protruding parts;
step S2: forming a first dielectric layer which covers the fins and has the surface flush with the top surface of the pseudo gate structure on the substrate, removing the pseudo gate structure to form a groove, and extending the bottom of the groove into the first dielectric layer;
step S3: forming a second dielectric layer on the side wall of the groove, wherein the second dielectric layer also fills up the part of the groove extending into the first dielectric layer;
step S4: and forming a metal gate structure with the surface flush with the top surface of the first dielectric layer in the groove.
Referring to fig. 6, a substrate is provided that includes a discrete fin 110 and a dummy gate structure 200 that spans the fin 110. The substrate may include a semiconductor base 100 and a dielectric layer 200 on the semiconductor base 100 between adjacent fins 110. The surface of the dielectric layer 200 is lower than the top surface of the fin 110, and serves as isolation. The sidewalls and surfaces of the fins 110 may also form a dielectric layer 210.
The semiconductor substrate 100 may include at least one of the following materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In the embodiment of the present application, the constituent material of the semiconductor substrate 100 is monocrystalline silicon or silicon on insulator. The materials of the dielectric layer 200 and the dielectric layer 210 may be the same or different. The materials of the dielectric layer 200 and the dielectric layer 210 may include silicon oxide, silicon nitride, silicon oxynitride, or the like.
The fin 110 may be formed on a starting semiconductor substrate by an etch back process. The formation process of the dummy gate structure 300 may be a deposition process, but due to the nature of the deposition process, a protrusion 310 is formed at the bottom of the dummy gate structure 300 at both sides of the fin 110, and the presence of the protrusion 310 may cause the metal gate structure formed by the subsequent process to have a 3D cap.
Fig. 7 to 13 below show cross-sectional views at the plane of the dashed frame in fig. 6.
Referring to fig. 7, a first dielectric layer 400 is formed on the substrate, and in particular, the first dielectric layer 400 may be located on the dielectric layer 200. The first dielectric layer 400 covers the fins 110, and the surface of the first dielectric layer 400 is flush with the top surface of the dummy gate structure 300. The material of the first dielectric layer 400 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
Referring to fig. 8, the dummy gate structure 300 is removed to form a trench 500, and the bottom of the trench 500 extends into the first dielectric layer 400 to form a patterning structure 510.
Then, a second dielectric layer is formed on the sidewall of the trench 500, and the second dielectric layer also fills the portion of the trench extending into the first dielectric layer.
Referring to fig. 9, a second dielectric material layer 610 is formed on the sidewall and the bottom of the trench 500, and the second dielectric material layer 610 also fills the portion of the trench 500 extending into the first dielectric layer 400, that is, fills the patterning structure 510. Wherein the process of forming the second dielectric material layer 610 may include an atomic layer deposition process (ALD). When the atomic layer deposition process is adopted for deposition, the second dielectric material grows together from the three-dimensional direction at the fooling structure 510, so that the finally formed second dielectric material layer 610 can substantially fill the fooling structure 510 with the increase of the deposition thickness of the second dielectric material. In order to improve the filling effect, it is necessary to control the process parameters of the atomic layer deposition process. In the embodiment of the application, the temperature of the atomic layer deposition process can be 300-400 ℃, the power can be 100-300W, and a general reaction precursor is adopted. For example, the reactive precursor may include the commonly used SM24 and O 2 。
Referring to fig. 10, the second dielectric material layer 610 in the top downward orthographic projection range of the trench 500 is removed, and the second dielectric layer 600 is formed. After etching the portion of the second dielectric material layer 610 at the bottom of the trench 500, the accommodating space of the metal gate structure may be relatively increased. The material of the second dielectric layer 600 may include at least one of silicon oxycarbide, silicon nitride, and silicon oxide. A dry etching process may be used to remove the second dielectric material layer 610 in the top-down orthographic projection range of the trench 500, and parameters of the dry etching process may be controlled to etch the second dielectric material layer 610 in the top-down orthographic projection range of the trench 500 as completely as possible.
Referring to fig. 11, a metal gate structure 700 is formed in the trench 500, and a surface of the metal gate structure 700 is flush with a top surface of the first dielectric layer 400, while also being flush with a top surface of the second dielectric layer 600. Due to the existence of the second dielectric layer 600, the bottom of the formed metal gate structure 700 is not provided with a 3D corner any more, so that the problem of parasitic capacitance generated between the 3D corner and the source leakage current is avoided, and the AC performance of the device is improved.
In some embodiments, before forming the metal gate structure 700, the method further includes a step of making the sidewalls of the second dielectric layer 600 and the sidewalls of the first dielectric layer 400 coplanar. Referring to fig. 12, the second dielectric layer 600 may be etched using an isotropic etching process such that sidewalls of the second dielectric layer 600 and sidewalls of the first dielectric layer 400 are coplanar. Thereby enabling the Critical Dimension (CD) of trench 500 to continue the CD of the dummy gate structure.
Referring to fig. 13, a metal gate structure 700 having a surface flush with the top surface of the first dielectric layer 400 is formed in the trench 500. Since the CD of the trench 500 continues with the CD of the dummy gate structure, the CD of the metal gate structure 700 is the same or substantially the same as the CD of the dummy gate structure.
With reference to fig. 6 and 11, an embodiment of the present application further provides a semiconductor structure, including: a substrate including discrete fins 110 thereon; a metal gate structure 700 spanning the fins 110; a first dielectric layer 400, which is located on the substrate and covers the fins 110, and the surface of the first dielectric layer 400 is flush with the top surface of the metal gate structure 700; the second dielectric layer 600 is located between the first dielectric layer 400 and the metal gate structure 700, and the bottom of the second dielectric layer 600 extends from the sidewall of the metal gate structure 700 into the first dielectric layer 400.
In some embodiments, the material of the first dielectric layer 400 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer 600 includes at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
With reference to fig. 6 and 13, another semiconductor structure according to an embodiment of the present application includes: a substrate including discrete fins 110 thereon; a metal gate structure 700 spanning the fins 110; a first dielectric layer 400, which is located on the substrate and covers the fins 110, and the surface of the first dielectric layer 400 is flush with the top surface of the metal gate structure 700; a second dielectric layer 600 extends from the bottom sidewall of the metal gate structure 700 into the first dielectric layer 400.
In some embodiments, the material of the first dielectric layer 400 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the second dielectric layer 600 includes at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
In view of the foregoing, it will be evident to those skilled in the art after reading this application that the foregoing application may be presented by way of example only and may not be limiting. Although not explicitly described herein, those skilled in the art will appreciate that the present application is intended to embrace a variety of reasonable alterations, improvements and modifications to the embodiments. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the present application.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means without intermediate elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present application. Like reference numerals or like reference numerals designate like elements throughout the specification.
Furthermore, the present specification describes example embodiments by reference to idealized example cross-sectional and/or plan and/or perspective views. Thus, differences from the illustrated shapes, due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

Claims (13)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises discrete fins and a pseudo gate structure crossing the fins, and the bottoms of the pseudo gate structures on two sides of the fins are provided with protruding parts;
forming a first dielectric layer which covers the fins and has the surface flush with the top surface of the pseudo gate structure on the substrate, removing the pseudo gate structure to form a groove, and extending the bottom of the groove into the first dielectric layer;
forming a second dielectric layer on the side wall of the groove, wherein the second dielectric layer also fills up the part of the groove extending into the first dielectric layer;
and forming a metal gate structure with the surface flush with the top surface of the first dielectric layer in the groove.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the second dielectric layer comprises:
forming a second dielectric material layer on the side wall and the bottom of the groove, wherein the second dielectric material layer also fills the part of the groove extending into the first dielectric layer;
and removing the second dielectric material layer in the downward orthographic projection range of the top of the groove to form the second dielectric layer.
3. The method of claim 2, wherein the second dielectric material layer is formed using an atomic layer deposition process.
4. The method of claim 3, wherein the atomic layer deposition process is performed at a temperature of 300-400 ℃ and a power of 100-300W.
5. The method of claim 2, wherein the second dielectric material is removed within a top-down orthographic projection of the trench by a dry etching process.
6. The method of claim 1, wherein the material of the second dielectric layer comprises at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
7. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the metal gate structure: and etching the second dielectric layer by adopting an isotropic etching process, so that the side wall of the second dielectric layer and the side wall of the first dielectric layer are coplanar.
8. The method of claim 7, wherein critical dimensions of the metal gate structure and the dummy gate structure are the same.
9. The method of claim 1, wherein the material of the first dielectric layer comprises at least one of silicon oxide, silicon nitride, and silicon oxynitride.
10. A semiconductor structure, comprising:
a substrate including discrete fins thereon;
a metal gate structure spanning the fins;
the first dielectric layer is positioned on the substrate and covers the fins, and the surface of the first dielectric layer is flush with the top surface of the metal gate structure;
and the second dielectric layer is positioned between the first dielectric layer and the metal gate structure, and the bottom of the second dielectric layer extends into the first dielectric layer from the side wall of the metal gate structure.
11. The semiconductor structure of claim 10, wherein the material of the first dielectric layer comprises at least one of silicon oxide, silicon nitride, and silicon oxynitride and the material of the second dielectric layer comprises at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
12. A semiconductor structure, comprising:
a substrate including discrete fins thereon;
a metal gate structure spanning the fins;
the first dielectric layer is positioned on the substrate and covers the fins, and the surface of the first dielectric layer is flush with the top surface of the metal gate structure;
and the second dielectric layer extends from the bottom side wall of the metal gate structure into the first dielectric layer.
13. The semiconductor structure of claim 12, wherein the material of the first dielectric layer comprises at least one of silicon oxide, silicon nitride, and silicon oxynitride and the material of the second dielectric layer comprises at least one of silicon oxycarbide, silicon nitride, and silicon oxide.
CN202210903950.XA 2022-07-28 2022-07-28 Semiconductor structure and forming method thereof Pending CN117524986A (en)

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