CN117524101A

CN117524101A - Gate driving circuit and display panel

Info

Publication number: CN117524101A
Application number: CN202311650380.9A
Authority: CN
Inventors: 鲁建军; 盖翠丽; 郭恩卿; 潘康观
Original assignee: Yungu Guan Technology Co Ltd; Hefei Visionox Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd; Hefei Visionox Technology Co Ltd
Priority date: 2023-11-29
Filing date: 2023-11-29
Publication date: 2024-02-06

Abstract

The invention discloses a gate driving circuit and a display panel. The grid driving circuit comprises a first input module, a second output module and a coupling control module; the first input module is connected with the second control end of the second output module and is used for transmitting an input signal to the second control end based on a second clock signal; the second output module is used for outputting a second voltage signal when being conducted; the coupling control module is electrically connected with the second control end, and is used for performing coupling control on the potential of the second control end based on the jump from the first level to the second level of the first clock signal according to the second clock signal and the input signal, so that the output end of the grid driving circuit outputs a second voltage signal. The technical scheme of the invention improves the display effect of the display panel.

Description

Gate driving circuit and display panel

Technical Field

The present invention relates to the field of display technologies, and in particular, to a gate driving circuit and a display panel.

Background

Along with the continuous development of display technology, the application range of the display panel is wider and wider, and the requirements of people on the display panel are also higher and higher.

However, the existing organic light-emitting display products have abnormal display conditions, and the display effect of the display products is required to be improved.

Disclosure of Invention

The invention provides a grid driving circuit and a display panel, which are used for solving the problem that display products have abnormal display.

According to an aspect of the present invention, there is provided a gate driving circuit including:

the first input module is connected with a second control end of the second output module, and is used for transmitting an input signal to the second control end based on a second clock signal; the second output module is used for outputting a second voltage signal when being conducted; and the coupling control module is electrically connected with the second control end and is used for carrying out coupling control on the potential of the second control end based on the jump from the first level to the second level of the first clock signal according to the second clock signal and the input signal so as to enable the output end of the grid driving circuit to output a second voltage signal.

Optionally, there is overlap between the second level pulse of the second clock signal and the second level pulse of the input signal; the coupling control module is configured to transmit a second level of the input signal to an internal node of the coupling control module when the second clock signal is at a second level, and couple a potential of the internal node when the first clock signal transitions from the first level to the second level, and transmit the coupled potential to the second control terminal;

Preferably, the second level is the same as the second voltage signal, and the first level is the same as the first voltage signal.

Optionally, the coupling control module includes: the device comprises a first input unit, a first control unit, a first coupling unit and a switch unit;

the control end of the first input unit is connected with the second clock signal, the first end of the first input unit is connected with the input signal, the second end of the first input unit is connected with the internal node of the coupling control module, and the first input unit is used for transmitting the second level of the input signal to the internal node when the second clock signal is at the second level; wherein the internal node is a first end of the first coupling unit;

the control end of the first control unit is connected with the internal node, the first end of the first control unit is connected with the first clock signal, the second end of the first control unit is connected with the second end of the first coupling unit, and the first control unit is used for coupling the potential of the internal node when the first clock signal jumps from a first level to a second level;

The control end of the switch unit and the first end of the switch unit are both connected with the internal node, the second end of the switch unit is connected with the second control end, and the switch unit is used for transmitting the potential after the coupling of the internal node to the second control end when the potential difference between the second control end and the internal node meets the conduction condition of the switch unit.

Optionally, the gate driving circuit further includes:

the first control module is connected with a first control end of the first output module, the first control module is used for controlling the potential of the first control end based on the input signal, the first voltage signal and the first clock signal, and the first output module is used for being conducted when the potential of the first control end is a second level so as to output the first voltage signal when being conducted;

preferably, the coupling control module further comprises: a second control unit;

the control end of the second control unit is connected with the first control end, the first end of the second control unit is connected with the first voltage signal, the second end of the second control unit is connected with the second end of the first coupling unit, and the second control unit is used for transmitting the first voltage signal to the second end of the first coupling unit when the potential of the first control end is at a second level.

Optionally, the first input unit includes a first transistor and a second transistor;

the control electrode of the first transistor is connected with the second clock signal, and the first electrode of the first transistor is connected with the input signal;

the control electrode of the second transistor is connected to the second voltage signal, the first electrode of the second transistor is electrically connected with the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected with the internal node;

and/or the first coupling unit comprises a first capacitor, a first pole of the first capacitor is the internal node, and a second pole of the first capacitor is a second end of the first coupling unit;

and/or the first control unit comprises a third transistor, a control electrode of the third transistor is electrically connected with the internal node, a first electrode of the third transistor is connected with the first clock signal, and a second electrode of the third transistor is electrically connected with a second end of the first coupling unit;

and/or the switch unit comprises a fourth transistor, wherein a control electrode of the fourth transistor and a first electrode of the fourth transistor are electrically connected with the internal node, and a second electrode of the fourth transistor is electrically connected with the second control end;

And/or the second control unit comprises a fifth transistor, wherein the control electrode of the fifth transistor is electrically connected with the first control end, the first electrode of the fifth transistor is connected with the first voltage signal, and the second electrode of the fifth transistor is electrically connected with the second end of the first coupling unit.

Optionally, the gate driving circuit further includes:

and the coupling module is connected between the output end and the second control end and is used for coupling the potential of the second control end according to the potential jump of the output end.

Optionally, the coupling module includes a second capacitor;

the second capacitor is connected between the output end and the second control end.

Optionally, the gate driving circuit further includes:

and the node mutual control module is respectively connected with the first control end and the second control end and is used for responding to the potential of the second control end and transmitting the first voltage signal to the first control end.

Optionally, the first control module includes:

a sixth transistor having a control electrode connected to the input signal and a first electrode connected to the first voltage signal;

A control electrode of the seventh transistor is electrically connected with the second electrode of the sixth transistor, a first electrode of the seventh transistor is connected with the first clock signal, and a second electrode of the seventh transistor is electrically connected with the first control end; the third capacitor is connected between the control electrode of the seventh transistor and the first electrode of the seventh transistor;

and/or, the first output module comprises: a fourth capacitor and an eighth transistor;

the fourth capacitor is connected between the control electrode of the eighth transistor and the first electrode of the eighth transistor;

the control electrode of the eighth transistor is electrically connected with the first control end, and the second electrode of the eighth transistor is connected with the output end;

and/or the second output module comprises a ninth transistor; the control electrode of the ninth transistor is electrically connected with the second control end, the first electrode of the ninth transistor is connected with the second voltage signal, and the second electrode of the ninth transistor is the output end of the gate driving circuit.

According to another aspect of the present invention, there is provided a display panel including the gate driving circuit according to any one of the embodiments of the present invention.

According to the technical scheme, the coupling control module is arranged, and the coupling control module performs coupling control on the potential of the second control end based on the jump from the first level to the second level of the first clock signal according to the second clock signal and the input signal. The second level may be coupled to the second control terminal such that the potential of the second control terminal changes in the direction of the second level. When the input signal is at the second level, that is, the potential of the second control terminal is at the second level, the potential of the second control terminal is further changed to the direction of the second level by the coupling control of the coupling control module, and becomes an electric signal lower than the second level or an electric signal higher than the second level. Therefore, the second output module can be guaranteed to be completely conducted, the second output module can be guaranteed to output a second voltage signal, namely the amplitude of the output voltage of the grid driving circuit is guaranteed to be equal to the amplitude of the second voltage signal, the amplitude of the second voltage signal can meet the requirement that a corresponding transistor in the pixel circuit is completely conducted, and accordingly the conduction and the disconnection of the transistor in the pixel circuit are better controlled, the luminous time sequence or the luminous brightness of a luminous device corresponding to the pixel circuit is accurately controlled, a picture to be displayed can be better displayed by the display panel, and the display effect of the display panel is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a structure of a gate driving circuit according to another embodiment of the present invention;

fig. 3 is a schematic diagram of a structure of a gate driving circuit according to another embodiment of the present invention;

fig. 4 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present invention;

fig. 5 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present invention;

FIG. 7 is a timing diagram corresponding to FIG. 5;

FIG. 8 is a timing diagram corresponding to FIG. 6;

fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The pixel unit of the display product includes a pixel circuit and a light emitting device, the pixel circuit includes a 2T1C pixel circuit and its modifications, or the pixel circuit includes a 7T1C circuit and its modifications. The 7T1C pixel circuit includes, for example, a data writing transistor, a threshold compensation transistor, a driving transistor, a first initialization transistor, a second initialization transistor, a first light emission control transistor, and a second light emission control transistor. The gate driving circuit is provided to output a gate driving signal which drives on and off of a transistor of the pixel circuit. The gate driving signal may be a scan driving signal corresponding to at least one of the data writing transistor, the threshold compensating transistor, the driving transistor, the first initializing transistor, and the second initializing transistor, or may be a light emission control signal corresponding to at least one of the first light emission control transistor and the second light emission control transistor. The gate driving circuit may include two output modules, one for outputting an active level and the other for outputting an inactive level. The active level refers to the signal that controls the transistor to turn on, and the inactive level refers to the signal that controls the transistor to turn off. When the control end of the output module outputting the effective level is the effective level, the output module outputs the effective level. When the transistor (the transistor connected with the control end of the output module outputting the effective level) in the grid driving circuit has the electric leakage condition, the electric potential of the control end of the output module outputting the effective level may change towards the direction of the ineffective level, so that the output module outputting the effective level cannot be completely opened, and the effective level cannot be completely outputted, namely the amplitude of the electric level outputted by the output module is insufficient, the requirement of completely conducting the corresponding transistor in the control pixel circuit cannot be met, the conduction of the transistor in the pixel circuit cannot be accurately controlled, the pixel circuit cannot normally output driving current, and the light emitting device cannot normally emit light, so that the display product is abnormal in display.

In view of the above technical problems, an embodiment of the present invention provides a gate driving circuit. Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, and referring to fig. 1, the gate driving circuit according to an embodiment of the present invention includes: a first input module 130, a second output module 140, and a coupling control module 150; the first input module 130 is connected to the second control end N2 of the second output module 140, and the first input module 130 is configured to transmit the input signal EIN to the second control end N2 based on the second clock signal CK 2; the second output module 140 is configured to output a second voltage signal VG2 when turned on; the coupling control module 150 is electrically connected to the second control terminal N2, and is configured to perform coupling control on the potential of the second control terminal N2 based on the transition from the first level to the second level of the first clock signal CK1 according to the second clock signal CK2 and the input signal EIN, so that the output terminal OUT of the gate driving circuit outputs the second voltage signal VG2.

The output terminal OUT of the gate driving circuit of the output terminal of the second output module 140 outputs a gate driving signal, which is a gate driving signal of a transistor in a pixel circuit of the display panel. The second level is a low level signal, and the first level is a high level signal; alternatively, the second level is a high level signal and the first level is a low level signal. The second level is, for example, a voltage for controlling the first input module to be turned on, and the first level is a voltage for controlling the first input module to be turned off. The first clock signal CK1, the second clock signal CK2, and the input signal EIN are, for example, pulse signals, each including a first level and a second level.

Specifically, when the second clock signal CK2 is at the second level, the first input module 130 is turned on, the first input module 130 transmits the input signal EIN to the second control terminal N2, and when the input signal EIN is at the second level, the potential of the second control terminal N2 is at the second level. When the coupling control module 150 performs coupling control on the potential of the second control terminal N2 based on the transition of the first level of the first clock signal CK1 to the second level according to the second clock signal CK2 and the input signal EIN, the second level may be coupled to the second control terminal N2, so that the potential of the second control terminal N2 changes in the direction of the second level. When the input signal EIN is the fourth signal, that is, the second control terminal N2 is at the second level, the coupling of the coupling control module 150 may enable the potential of the second control terminal N2 to become lower than the electrical signal at the second level or higher than the electrical signal at the second level (when the second level is at the low level, the potential of the second control terminal N2 becomes lower than the electrical signal at the second level, and when the second level is at the high level, the potential of the second control terminal N2 becomes higher than the electrical signal at the second level).

In some embodiments, when the second level is low, the potential of the second control terminal N2 is at the second level when the input signal EIN is at the second level, and then the second control terminal N2 is at the ultra-low level through the coupling of the coupling control module 150. In some embodiments, when the second level is high, the potential of the second control terminal N2 is ultrahigh because the potential of the second control terminal N2 is the second level when the input signal EIN is the second level, and then the second control terminal N2 is coupled by the coupling control module 150. When the potential of the second control end N2 is at the ultra-low level or the ultra-high level, the second output module 140 can be controlled to be turned on more effectively than the second level, so that the second output module 140 can be turned on completely, the second output module 140 can output the second voltage signal VG2, and further the gate driving circuit can output the second voltage signal VG2, that is, the amplitude of the output voltage of the gate driving circuit is equal to the amplitude of the second voltage signal VG2, the output of the complete second voltage signal VG2 is ensured, and the amplitude of the second voltage signal VG2 can meet the requirement that the corresponding transistor in the pixel circuit is turned on completely.

Therefore, the grid driving circuit can be guaranteed to output the second voltage signal VG2, so that the on and off of transistors in the pixel circuit are better controlled, the luminous time sequence or luminous brightness of a luminous device corresponding to the pixel circuit is further controlled, the display panel can better display a picture to be displayed, abnormal display caused by the fact that the grid driving circuit cannot output the second voltage signal VG2 is avoided, and the display effect of the display panel is improved.

According to the technical scheme of the embodiment, the coupling control module is arranged, and the coupling control module performs coupling control on the potential of the second control end based on the jump from the first level to the second level of the first clock signal according to the second clock signal and the input signal. The second level may be coupled to the second control terminal such that the potential of the second control terminal changes in the direction of the second level. When the input signal is at the second level, that is, the potential of the second control terminal is at the second level, the potential of the second control terminal is further changed to the direction of the second level by the coupling control of the coupling control module, and becomes an electric signal lower than the second level or an electric signal higher than the second level. Therefore, the second output module can be guaranteed to be completely conducted, the second output module can be guaranteed to output a second voltage signal, namely the amplitude of the output voltage of the grid driving circuit is guaranteed to be equal to the amplitude of the second voltage signal, the amplitude of the second voltage signal can meet the requirement that a corresponding transistor in the pixel circuit is completely conducted, and accordingly the conduction and the disconnection of the transistor in the pixel circuit are better controlled, the luminous time sequence or the luminous brightness of a luminous device corresponding to the pixel circuit is accurately controlled, a picture to be displayed can be better displayed by the display panel, and the display effect of the display panel is improved.

On the basis of the above technical solution, optionally, there is an overlap between the second level pulse of the second clock signal CK2 and the second level pulse of the input signal EIN; the coupling control module 150 is configured to transmit the second level of the input signal EIN to the internal node N3 of the coupling control module 150 when the second clock signal CK2 is at the second level, and couple the potential of the internal node N3 and transmit the coupled potential to the second control terminal N2 when the first clock signal CK1 transitions from the first level to the second level.

Specifically, when the second clock signal CK2 is at the second level, the first input module 130 is turned on, and the first input module 130 transmits the input signal EIN to the second control terminal N2. Therefore, when the second level pulse of the second clock signal CK2 overlaps the second level pulse of the input signal EIN, the potential of the second control terminal N2 is at the second level.

When the second clock signal CK2 is at the second level, the coupling control module 150 transmits the second level of the input signal EIN to the internal node N3, so that the potential of the internal node N3 is at the second level. When the first clock signal CK1 transitions from the first level to the second level, the coupling control module 150 couples the potential of the internal node N3, so that the potential of the internal node N3 further changes in the direction of the second level, i.e., the potential of the internal node N3 becomes an ultra-low level or an ultra-high level.

The coupled potential of the internal node N3 is transmitted to the second control terminal N2 by the coupling control module 150, so that the potential of the second control terminal N2 is further changed in the direction of the second level, and becomes an ultra-low level or an ultra-high level, that is, becomes a more effective level, thereby ensuring that the second output module 140 can be completely opened, and being beneficial to ensuring that the second output module 140 outputs the second voltage signal VG2.

The gate driving circuit further includes a first voltage signal VG1, and a level state of the first voltage signal VG1 is different from a level state of the second voltage signal VG2. The first voltage signal VG1 is a high level signal, and the second voltage signal VG2 is a low level signal; alternatively, the first voltage signal VG1 is a low level signal, and the second voltage signal VG2 is a high level signal.

Optionally, the second level is the same as the second voltage signal VG2, and the first level is the same as the first voltage signal VG 1. In this way, the second output module 140 outputs the second level when outputting the second voltage signal VG2, and outputs the first level when the first output module 120 outputs the first voltage signal VG1, so that the gate driving signal output by the gate driving circuit outputs the high level and the low level in a time-sharing manner, that is, outputs the inactive level and the active level in a time-sharing manner, thereby realizing the control of the transistors in the pixel circuit.

On the basis of the above technical solution, the following further describes the gate driving circuit in combination with a possible structure of the coupling control module, but is not limited to this application.

Fig. 2 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present invention, optionally, referring to fig. 2, a coupling control module 150 includes: a first input unit 151, a first control unit 152, a first coupling unit 153, and a switching unit 154;

the control end of the first input unit 151 is connected to the second clock signal CK2, the first end of the first input unit 151 is connected to the input signal EIN, the second end of the first input unit 151 is connected to the internal node N3 of the coupling control module 150, and the first input unit 151 is configured to transmit the second level of the input signal EIN to the internal node N3 when the second clock signal CK2 is at the second level; wherein the internal node N3 is a first end of the first coupling unit 153;

the control end of the first control unit 152 is connected to the internal node N3, the first end of the first control unit 152 is connected to the first clock signal CK1, the second end of the first control unit 152 is connected to the second end N4 of the first coupling unit 153, and the first control unit 152 is configured to couple the potential of the internal node N3 when the first clock signal CK1 transitions from the first level to the second level;

The control end of the switch unit 154 and the first end of the switch unit 154 are both connected to the internal node N3, the second end of the switch unit 154 is connected to the second control end N2, and the switch unit 154 is configured to transmit the coupled potential of the internal node N3 to the second control end N2 when the potential difference between the second control end N2 and the internal node N3 satisfies the conduction condition of the switch unit 154.

Specifically, when the second clock signal CK2 is at the second level, the first input unit 151 transmits the second level of the input signal EIN to the internal node N3, i.e., to the first terminal of the first coupling unit 153, and at this time, the first control unit 152 is turned on. When the first clock signal CK1 transitions from the first level to the second level, the first control unit 152 transmits the second level to the second terminal of the first coupling unit 153 such that the potential of the second terminal N4 of the first coupling unit 153 changes. Since the charge stored in the first coupling unit 153 is unchanged, that is, the voltage difference across the first coupling unit 153 is unchanged, when the potential of the second terminal N4 of the first coupling unit 153 changes to the second level, the first terminal of the first coupling unit 153 is changed in a coupling manner, and is further changed in the direction of the second level.

Illustratively, when the second level is a low level, the potential of the second terminal N4 of the first coupling unit 153 is changed to a low level, and thus the first terminal of the first coupling unit 153 is further lowered to an ultra-low level since the voltage difference across the first coupling unit 153 is not changed. When the second level is high, the potential of the second terminal N4 of the first coupling unit 153 changes to a high level, and thus the voltage difference across the first coupling unit 153 does not change, and the first terminal of the first coupling unit 153 further increases to a super high level.

When the potential of the internal node N3 is lower or higher than the second level (the ultra-high level or the ultra-low level), and the potential of the second control terminal N2 is the second level, the potential difference between the second control terminal N2 and the internal node N3 satisfies the conduction condition of the switch unit 154, the switch unit 154 is turned on, and the switch unit 154 transmits the potential (the ultra-high level or the ultra-low level) after the internal node N3 is coupled to the second control terminal N2, so that the potential of the second control terminal N2 becomes a more effective level (the ultra-high level or the ultra-low level), thereby ensuring that the second output module 140 is completely turned on.

Optionally, referring to fig. 2, the gate driving circuit further includes a first control module 110 and a first output module 120, wherein the first control module 110 is configured to control the potential of the first control terminal N1 based on the input signal EIN, the first voltage signal VG1, and the first clock signal CK1, and the first output module 120 is configured to be turned on when the potential of the first control terminal N1 is at the second level, so as to output the first voltage signal VG1 when turned on; the coupling control module 150 further includes: a second control unit 155; the control end of the second control unit 155 is connected to the first control end N1, the first end of the second control unit 155 is connected to the first voltage signal VG1, the second end of the second control unit 155 is connected to the second end N4 of the first coupling unit 153, and the second control unit 155 is configured to transmit the first voltage signal VG1 to the second end N4 of the first coupling unit 153 when the potential of the first control end N1 is at the second level.

The output terminal of the first output module 120 and the output terminal of the second output module 140 are both output terminals OUT of the gate driving circuit. When the first control module 110 controls the potential of the first control terminal N1 to be the second level based on the input signal EIN, the first voltage signal VG1, and the first clock signal CK1, the first output module 120 is turned on, and the first output module 120 outputs the first voltage signal VG1, so that the gate driving signal output by the gate driving circuit is the first voltage signal VG1.

Specifically, when the potential of the first control terminal N1 is at the second level, the first output module 120 is turned on, and the first output module 120 outputs the first voltage signal VG1. When the potential of the first control terminal N1 is at the second level, the first voltage signal VG1 is transmitted to the second terminal N4 of the first coupling unit 153, so that the potential of the second terminal N4 of the first coupling unit 153 is at the first level, the potential of the internal node N3 is not coupled to the ultra-high level or the ultra-low level, and the second control terminal N2 is not coupled and controlled, so that the second output module 140 does not output the second voltage signal VG2. In this way, the first output module 120 and the second output module 140 are prevented from being turned on simultaneously, so that the disorder of the output signals of the gate driving circuit is avoided, and the accuracy of the gate driving signals output by the gate driving circuit is guaranteed.

On the basis of the above technical solution, fig. 3 is a schematic structural diagram of a further gate driving circuit provided by an embodiment of the present invention, and fig. 4 is a schematic structural diagram of a further gate driving circuit provided by an embodiment of the present invention, optionally, referring to fig. 3 and fig. 4, the first input unit 151 includes a first transistor T1 and a second transistor T2; the control electrode of the first transistor T1 is connected with the second clock signal CK2, and the first electrode of the first transistor T1 is connected with the input signal EIN; the control electrode of the second transistor T2 is connected to the second voltage signal VG2, the first electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1, and the second electrode of the second transistor T2 is electrically connected to the internal node N3. By providing the first transistor T1, the input signal EIN may be transmitted to the internal node N3 when the second clock signal CK2 is at the second level. By setting the second transistor T2, the control electrode of the second transistor T2 is connected to the second voltage signal VG2, so that the second transistor T2 is normally open, and when the internal node N3 is at a more effective level (ultra-low level or ultra-high level), the voltage of the internal node N3 is prevented from being transmitted to the first transistor T1, thereby avoiding damaging the first transistor T1.

Alternatively, referring to fig. 3 and 4, the first coupling unit 153 includes a first capacitor C1, a first terminal of the first capacitor C1 is an internal node N2, and a second terminal of the first capacitor C1 is a second terminal N4 of the first coupling unit 153. Since the voltage difference across the first capacitor C1 is unchanged, when the potential of the second pole of the first capacitor C1 changes to the second level, the first pole coupling of the first capacitor C1 changes, and further changes in the direction of the second level.

Alternatively, referring to fig. 3 and 4, the first control unit 152 includes a third transistor T3, a control electrode of the third transistor T3 is electrically connected to the internal node N3, a first electrode of the third transistor T3 is connected to the first clock signal CK1, and a second electrode of the third transistor T3 is electrically connected to the second terminal of the first coupling unit 153. By providing the third transistor T3, when the first clock signal CK1 transitions from the first level to the second level, the third transistor T3 transmits the second level to the second terminal N4 of the first coupling unit 153, so that the first coupling unit 153 can control the potential of the internal node N3 in a coupling manner.

Alternatively, referring to fig. 3 and 4, the switching unit 154 includes a fourth transistor T4, the control electrode of the fourth transistor T4 and the first electrode of the fourth transistor T4 are both electrically connected to the internal node N3, and the second electrode of the fourth transistor T4 is electrically connected to the second control terminal N2. By means of the potential difference between the internal node N3 and the second control terminal N2, it is possible to control whether the fourth transistor T4 is turned on or not, and thus whether the potential coupling is performed to the second control terminal N2 or not.

Optionally, referring to fig. 3 and 4, the second control unit 155 includes a fifth transistor T5, a control electrode of the fifth transistor T5 is electrically connected to the first control terminal N1, a first electrode of the fifth transistor T5 is connected to the first voltage signal VG1, and a second electrode of the fifth transistor T5 is electrically connected to the second terminal N4 of the first coupling unit 153. By setting the fifth transistor T5, when the potential of the first control terminal N1 is at the second level, the fifth transistor T5 transmits the first voltage signal VG1 to the second terminal N4 of the first coupling unit 153, so that the potential of the second terminal N4 of the first coupling unit 153 is at the first level, and the potential of the internal node N3 is not coupled to the ultra-low level or the ultra-high level, and thus the coupling control of the second control terminal N2 is not performed.

Note that, fig. 3 shows a case where the transistors of the coupling control module 150 in the gate driving circuit are P-type transistors, and fig. 4 shows a case where the transistors of the coupling control module 150 in the gate driving circuit are N-type transistors, but the present invention is not limited thereto. In other embodiments, the transistors of the gate driving circuit coupled to the control module 150 may be partially P-type transistors and partially N-type transistors.

On the basis of the above technical solutions, fig. 5 is a schematic structural diagram of another gate driving circuit provided by the embodiment of the present invention, and fig. 6 is a schematic structural diagram of another gate driving circuit provided by the embodiment of the present invention, optionally, referring to fig. 5 and fig. 6, the gate driving circuit further includes a coupling module 160; the coupling module 160 is connected between the output terminal OUT and the second control terminal N2, and is configured to couple the potential of the second control terminal N2 according to the potential jump of the output terminal OUT. The first end of the coupling module 160 is connected to the output terminal OUT, and the second end of the coupling module 160 is connected to the second control terminal N2.

Specifically, when the second clock signal CK2 is at the second level, the first input module 130 is turned on, the first input module 130 transmits the input signal EIN to the second control terminal N2, and when the input signal EIN is at the second level, the potential of the second control terminal N2 is at the second level, and at this time, the second output module 140 is turned on. After the second output module 140 is turned on, the second voltage signal VG2 and the threshold voltage of the second output module 140 are transmitted to the output terminal OUT. The signal at the output terminal OUT approaches the second voltage signal VG2, i.e., approaches the second level, so that the potential at the first terminal of the coupling module 160 jumps. Because the charge stored in the coupling module 160 is unchanged, that is, the voltage difference between two ends of the coupling module 160 is unchanged, when the potential at the first end of the coupling module 160 jumps, the potential at the second control end N2 is coupled, so that the potential at the second control end N2 changes to the second level, that is, to a level higher or lower than the second level, that is, to a more effective level (ultra-low level or ultra-high level), thereby controlling the second output module 140 to be fully turned on and further ensuring that the gate driving circuit can output the second voltage signal VG2. Because the potential of the second control terminal N2 is coupled soon after the potential jump of the first terminal of the coupling module 160, i.e. the time from the conduction to the complete conduction of the second output module 140 is very short. That is, when the second clock signal CK2 and the input signal EIN transition to the second level, the second output module 140 can be quickly turned on, so that the second output module 140 immediately outputs the second voltage signal VG2, and the gate driving signal output by the gate driving circuit is prevented from having steps.

Alternatively, referring to fig. 5 and 6, the coupling module 160 includes a second capacitor C2; the second capacitor C2 is connected between the output terminal OUT and the second control terminal N2. The amount of charge stored in the second capacitor C2 does not change, that is, the voltage difference between two ends of the second capacitor C2 does not change, so when one end (output end OUT) of the second capacitor C2 hops, the electric potential of the other end (second control end N2 of the second capacitor C2) can be coupled, so as to realize the coupling control of the electric potential of the second control end N2.

In summary, according to the technical solution of the present embodiment, the coupling module 160 is provided, so that the second output module 140 immediately outputs the second voltage signal VG2, thereby avoiding the occurrence of steps in the gate driving signal output by the gate driving circuit; by setting the coupling control module 150, a more effective level (ultra-low level or ultra-high level) of the second control terminal N2 can be maintained, so as to avoid the influence of leakage current in the circuit on the second output module 140, maintain the second output module 140 to output the second voltage signal VG2, and ensure the output of the gate driving circuit.

Optionally, referring to fig. 5 and 6, the gate driving circuit further includes: the node mutual control module 170 is connected to the first control terminal N1 and the second control terminal N2, and the node mutual control module 170 is configured to respond to the potential of the second control terminal N2 and transmit the first voltage signal VG1 to the first control terminal N1.

Specifically, when the potential of the second control terminal N2 is at the second level, the node mutual control module 170 is turned on to transmit the first voltage signal VG1 to the first control terminal N1, so that the potential of the first control terminal N1 is at the first level. Thus, mutual control of the node potentials of the first control end N1 and the second control end N2 is achieved, the possibility that an intermediate potential between the high potential and the low potential appears on the potential of the first control end N1 and the potential of the second control end N2 is reduced, the potentials of the two control ends are ensured to be clear, the first output module 120 and the second output module 140 are prevented from being conducted simultaneously, and the output state of the gate driving circuit is further ensured to be accurate.

Alternatively, referring to fig. 5 and 6, the first control module 110 includes: a control electrode of the sixth transistor T6 is connected to the input signal EIN, and a first electrode of the sixth transistor T6 is connected to the first voltage signal VG1; the control electrode N5 of the seventh transistor T7 is electrically connected with the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7 is connected with the first clock signal CK1, and the second electrode of the seventh transistor T7 is electrically connected with the first control end N1; the third capacitor C3 is connected between the control electrode N5 of the seventh transistor T7 and the first electrode of the seventh transistor T7. When the input signal EIN is at an inactive level (first level), the sixth transistor T6 is turned off; when the first clock signal CK1 is at an active level (second level), the control electrode N5 of the seventh transistor T7 is at an active level (second level), and the seventh transistor T7 is turned on and outputs the active level (second level), i.e., the first control terminal N1 is at an active level (second level), thereby controlling the first output module 120 to be turned on, and the first output module 120 outputs the first voltage signal VG1. When the input signal EIN is at an active level (second level) and the first clock signal CK1 is at an active level (second level), the sixth transistor T6 and the seventh transistor T7 are turned on, and the first output module 120 outputs the first voltage signal VG1 as well.

Alternatively, referring to fig. 5 and 6, the first output module 120 includes: a fourth capacitor C4 and an eighth transistor T8; the fourth capacitor C4 is connected between the control electrode of the eighth transistor T8 and the first electrode of the eighth transistor T8; the control electrode of the eighth transistor T8 is electrically connected to the first control terminal N1, and the second electrode of the eighth transistor T8 is connected to the output terminal. When the potential of the first control terminal N1 is at the active level (the second level), the eighth transistor T8 may be controlled to be turned on, such that the eighth transistor T8 outputs the first voltage signal VG1.

Alternatively, referring to fig. 5 and 6, the second output module 140 includes a ninth transistor T9; the control electrode of the ninth transistor T9 is electrically connected to the second control terminal N2, the first electrode of the ninth transistor T9 is connected to the second voltage signal VG2, and the second electrode of the ninth transistor T9 is the output terminal OUT of the gate driving circuit. When the second control terminal N2 is at an active level (second level), the ninth transistor T9 may be controlled to be turned on, and the ninth transistor T9 outputs the second voltage signal VG2. When the second control terminal N2 is at a more effective level (ultra-low level or ultra-high level), the ninth transistor T9 can be controlled to be fully turned on, and the ninth transistor T9 outputs the second voltage signal VG2 better.

Optionally, referring to fig. 5 and 6, the node mutual control module 170 includes a tenth transistor T10, a control electrode of the tenth transistor T10 is electrically connected to the second control terminal N2, a first electrode of the tenth transistor T10 is connected to the first voltage signal VG1, and a second electrode of the tenth transistor T10 is electrically connected to the first control terminal N1. The tenth transistor T10 is controlled to be turned on and off by the second control terminal N2, so that when the potential of the second control terminal N2 is an active level (a second level), the potential of the first control terminal N1 is a first voltage signal VG1, that is, an inactive level (a first level), thereby realizing the mutual control of the potentials of the first control terminal N1 and the second control terminal N2.

Alternatively, referring to fig. 5 and 6, the first input module 130 includes an eleventh transistor T11, a control electrode of the eleventh transistor T11 is connected to the second clock signal CK2, a first electrode of the eleventh transistor T11 is connected to the input signal EIN, and a second electrode of the eleventh transistor T11 is electrically connected to the second control terminal N2. When the second clock signal CK2 is at an active level (second level), the eleventh transistor T11 is turned on to transmit the input signal EIN to the second control terminal N2. When the second clock signal CK2 and the input signal EIN are both valid signals (second level), the second control terminal N2 may be enabled to be both valid signals (second level), so that the second output module 140 outputs the second voltage signal VG2, i.e. the valid level (second level), so as to facilitate the implementation of shifting and outputting the input signal EIN by the gate driving circuit.

Optionally, referring to fig. 5 and 6, the gate driving circuit further includes a twelfth transistor T12, a control electrode of the twelfth transistor T12 is connected to the second clock signal CK2, a first electrode N6 of the twelfth transistor T12 is electrically connected to the first input module 130, and a second electrode of the twelfth transistor T12 is electrically connected to the second control terminal N2. The second clock signal CK2 is at an active level (second level), i.e., the twelfth transistor T12 is normally on, so that the second control terminal N2 can be prevented from affecting the potential of the first input module 130 when the second control terminal N2 is at a more active level (ultra-low level or ultra-high level), and damage to the first input module 130 can be prevented.

Note that fig. 5 shows a case where all transistors in the gate driving circuit are P-type transistors, and fig. 6 shows a case where all transistors in the gate driving circuit are N-type transistors, but the present invention is not limited thereto. In other embodiments, the transistors in the gate drive circuit may be partially P-type transistors and partially N-type transistors.

The operation of the gate driving circuit will be described with reference to specific timings. In one embodiment, the first voltage signal VG1 in fig. 5 is a high level signal VGH, and the second voltage signal VG2 is a low level signal VGL. Fig. 7 is a timing diagram corresponding to fig. 5, and optionally, referring to fig. 5 and 7, the operation of the gate driving circuit includes the following stages.

In the first stage T1, the input signal EIN is the high level signal VGH, and the sixth transistor T6 is turned off; the first clock signal CK1 is the high level signal VGH, the potential VN5 of the gate N5 of the seventh transistor T7 is the high level signal VGH, the seventh transistor T7 is turned off, the potential VN1 of the first control terminal N1 is the high level signal VGH, and the eighth transistor T8 is turned off. The second clock signal CK2 is a low level signal VGL, the eleventh transistor T11 is turned on, the input signal EIN is transmitted to the second control terminal N2, the potential VN2 of the second control terminal N2 is a high level signal VGH, the potential VN6 of the first pole N6 of the twelfth transistor T12 is also a high level signal VGH, and the ninth transistor T9 is turned off. The potential VN1 of the first control terminal N1 is the high level signal VGH, so the fifth transistor T5 is turned off. The second clock signal CK2 is a low level signal VGL, the first transistor T1 is turned on, the input signal EIN is transmitted to the internal node N3, the potential VN3 of the internal node N3 is a high level signal VGH, and the third transistor T3 and the fourth transistor T4 are turned off, and the potential VN4 of the second pole N4 of the first capacitor C1 is a high level signal VGH. Therefore, in the first stage T1, the potential of each important node is vn1=vn2=vn3=vn4=vn5=vn6=vgh, and both the eighth transistor T8 and the ninth transistor T9 are turned off, and the output terminal OUT maintains the voltage at the previous time and continues to output the low-level signal VGL.

In the second phase T2, the input signal EIN is still the high level signal VGH, and the sixth transistor T6 is still turned off. The second clock signal CK2 transitions to the high-level signal VGH, the eleventh transistor T11 is turned off, and the potential VN2 of the second control terminal N2 and the potential VN6 of the first pole N6 of the twelfth transistor T12 maintain the high-level signal VGH. The first transistor T1 is turned off, and the potential VN3 of the internal node N3 maintains the high-level signal VGH. The first clock signal CK1 jumps to the low level signal VGL, and the low level signal VGL is coupled to the control electrode N5 of the seventh transistor T7 through the third capacitor C3 until the potential of the control electrode N5 of the seventh transistor T7 becomes VGL-Vth, the seventh transistor T7 is turned on and VGL-Vth is outputted, that is, the potential VN1 of the first control terminal N1 is VGL-Vth. The eighth transistor T8 is turned on to output the high-level signal VGH, i.e., the potential VOUT of the output terminal OUT jumps to the high-level signal VGH. And, the second clock signal CK2 jumps to the high level signal VGH, and the first transistor T1 is turned off; when the potential VN1 of the first control terminal N1 is VGL-Vth, the fifth transistor T5 is turned on, the potential VN4 of the second pole N4 of the first capacitor C1 is still the high level signal VGH, and the potential VN3 of the internal node N3 is unchanged and still VGH. Therefore, in the second phase t2, the potentials of the respective important nodes are vn2=vn3=vn4=vn6=vgh, vn1=vn5=vgl-Vth, and vout=vgh. Where Vth is the threshold voltage of the transistor.

In the third stage T3, the input signal EIN is still the high level signal VGH, and the sixth transistor T6 is still turned off. The second clock signal CK2 transitions to the low-level signal VGL, and the potential VN6 of the first pole N6 and the potential VN2 of the second control terminal N2 of the twelfth transistor T12 are the high-level signal VGH. The first clock signal CK1 transitions to the high level signal VGH, the potential of the gate N5 of the seventh transistor T7 changes to the high level signal VGH, and the seventh transistor T7 is turned off. Due to the fourth capacitor C4, the potential VN1 of the first control terminal N1 is maintained, such that the potential VN1 of the first control terminal N1 is still VGL-Vth, the eighth transistor T8 is turned on, and the high level signal VGH is output, i.e. the potential VOUT of the output terminal OUT maintains the high level signal VGH output. The second clock signal CK2 is a low level signal VGL, the first transistor T1 is turned on, the input signal EIN is transmitted to the internal node N3, the potential VN3 of the internal node N3 is a high level signal VGH, and the third transistor T3 and the fourth transistor T4 are turned off. When the potential VN1 of the first control terminal N1 is VGL-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second pole N4 of the first capacitor C1 is still the high level signal VGH. Therefore, in the third stage t3, the potentials of the respective important nodes are vn2=vn3=vn4=vn5=vn6=vgh, vn1=vgl-Vth, and vout=vgh.

The fourth stage t4 to the seventh stage t7 are cycles of the second stage t2 and the third stage t3, that is, the potentials of the nodes in the fourth stage t4 and the sixth stage t6 are the same as the potentials of the nodes in the second stage t2, the conduction states of the transistors in the fourth stage t4 and the sixth stage t6 are the same as the conduction states of the nodes in the second stage t2, and the outputs of the gate driving circuits in the fourth stage t4, the sixth stage t6 and the second stage t2 are the same. The potential of each node in the fifth stage t5 and the seventh stage t7 is the same as the potential of each node in the third stage t3, the conducting state of each transistor in the fifth stage t5 and the seventh stage t7 is the same as the conducting state of each node in the third stage t3, and the output of the gate driving circuit in the fifth stage t5, the seventh stage t7 and the third stage t3 is the same.

In the eighth stage T8, the input signal EIN transitions to the low level signal VGL, the sixth transistor T6 is turned on, the sixth transistor T6 transmits the high level signal VGH to the gate N5 of the seventh transistor T7, the seventh transistor T7 is turned off, the fourth capacitor C4 maintains the potential VN1 of the first control terminal N1, vn1=vgl-Vth, the eighth transistor T8 is turned on, and the eighth transistor T8 outputs the high level signal VGH, vout=vgh. The second clock signal CK2 transitions to the high-level signal VGH, the eleventh transistor T11 is turned off, and the potential VN6 of the first pole N6 and the potential VN2 of the second control terminal N2 of the twelfth transistor T12 remain at the high-level signal VGH. The second clock signal CK2 transitions to the high-level signal VGH, the first transistor T1 is turned off, the potential VN3 of the internal node N3 is the high-level signal VGH, and the third transistor T3 and the fourth transistor T4 are turned off. When the potential VN1 of the first control terminal N1 is VGL-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second pole N4 of the first capacitor C1 is still the high level signal VGH. Therefore, in the eighth stage t8, the potentials of the respective important nodes are vn2=vn3=vn4=vn5=vn6=vgh, vn1=vgl-Vth, and vout=vgh.

In the ninth stage T9, the first clock signal CK1 transitions to the high level signal VGH, the input signal EIN is the low level signal VGL, the sixth transistor T6 is turned on, the sixth transistor T6 transmits the high level signal VGH to the gate N5 of the seventh transistor T7, and the seventh transistor T7 is turned off. The second clock signal CK2 transitions to the low level signal VGL, the eleventh transistor T11 is turned on, and the eleventh transistor T11 transmits the input signal EIN to the first pole N6 of the twelfth transistor T12. The potential VN6 of the first pole N6 of the twelfth transistor T12 is the low level signal VGL-Vth, the tenth transistor T10 is turned on, the tenth transistor T10 transmits the high level signal VGH to the first control terminal N1, the potential VN1 of the first control terminal N1 is the high level signal VGH, the eighth transistor T8 is turned off, and the fifth transistor T5 is turned off. The potential VN6 of the first pole N6 of the twelfth transistor T12 is a low level signal VGL, the twelfth transistor T12 transmits the low level signal VGL-Vth to the second control terminal N2, the potential VN2 of the second control terminal N2 is VGL-Vth, and the ninth transistor T9 is turned on. After the ninth transistor T9 is turned on, a lower level is output, the potential of the output terminal OUT is pulled down, the charge stored in the second capacitor C2 is unchanged due to the coupling effect of the second capacitor C2, and the second capacitor C2 pulls down the second control terminal N2 in a coupling manner, so that the potential of the second control terminal N2 is at an ultra-low level (more effective level). The second clock signal CK2 transitions to the low-level signal VGL, the first transistor T1 is turned on, and the first transistor T1 and the second transistor T2 transmit the low-level signal VGL of the input signal EIN to the internal node N3, and the potential VN3 of the internal node N3 becomes VGL-Vth. The potential of the control electrode of the third transistor T3 is VGL-Vth, the third transistor T3 is conducted, the potential of the second electrode of the third transistor T3 is VGH, the second electrode N4 of the first capacitor C1 maintains the high level signal VGH, and then the voltage difference between two ends of the first capacitor C1 is VGL-Vth-VGH. The potential of the control electrode of the fourth transistor T4 is VGL-Vth, the second electrode N2 of the fourth transistor T4 is at an ultra-low level (more effective level), the fourth transistor T4 does not satisfy the on condition, the fourth transistor T4 is turned off, and the potential of the internal node N3 is not transmitted to the second control terminal N2. The potential of the second control terminal N2 is at an ultra-low level (more effective level), so that the ninth transistor T9 is fully turned on, and the ninth transistor T9 can immediately output the low-level signal VGL, i.e. the gate driving circuit can immediately output the low-level signal VGL, so as to avoid the output gate driving signal from generating steps. Therefore, in the ninth stage t9, the potential of each important node is vn1=vn4=vn5=vgh, VN2 is an ultra-low level, vn3=vn6=vgl-Vth, and vout=vgl.

In the tenth stage T10, the first clock signal CK1 transitions to the low level signal VGL, the third transistor T3 transmits the low level signal VGL to the second pole N4 of the first capacitor C1, the voltage VN4 of the second pole N4 of the first capacitor C1 is VGL-Vth, the voltage difference across the first capacitor C1 is VGL-Vth-VGH, and the voltage VN3 of the internal node N3 becomes VGL-Vth-vgh+vgl, that is, v3=2vgl-Vth-VGH, and becomes an ultra-low level. The potential VN3 of the internal node N3 is at an ultra-low level, and if the potential of the second control terminal N2 increases due to the leakage of the twelfth transistor T12, the fourth transistor T4 is turned on, so that the ultra-low level of the internal node N3 is transmitted to the second control terminal N2, thereby maintaining the ultra-low level of the second control terminal N2, ensuring that the ninth transistor T9 can be completely turned on, and ensuring that the gate driving circuit outputs the low level signal VGL. The input signal EIN is a low level signal VGL, the sixth transistor T6 is turned on, the sixth transistor T6 transmits a high level signal VGH to the gate N5 of the seventh transistor T7, and the seventh transistor T7 is turned off. The second clock signal CK2 transitions to the high level signal VGH, and the eleventh transistor T11 is turned off. Since the second control terminal N2 maintains the low level signal VGL and the eleventh transistor T11 is turned off, the first pole N6 of the twelfth transistor T12 maintains the level signal VGL-Vth. The tenth transistor T10 is turned on, the tenth transistor T10 transmits the high-level signal VGH to the first control terminal N1, the potential VN1 of the first control terminal N1 is the high-level signal VGH, the eighth transistor T8 is turned off, and the fifth transistor T5 is turned off. Therefore, at the tenth stage t10, the potentials of the important nodes are vn1=vn5=vgh, vn4=vn6=vgl-Vth, vn3=2×vgl-Vth-VGH, and VN2 is at the ultra-low level, and VN2 approaches VN3.

The subsequent stages are the loop of the ninth stage t9 and the tenth stage t10, and will not be described here.

In another embodiment, the first voltage signal VG1 in fig. 6 is a low level signal VGL, and the second voltage signal VG2 is a high level signal VGH. Fig. 8 is a timing diagram corresponding to fig. 6, and optionally, referring to fig. 6 and 8, the operation of the gate driving circuit includes the following stages.

In the first stage T1', the input signal EIN is the low level signal VGL, and the sixth transistor T6 is turned off; the first clock signal CK1 is the low level signal VGL, the potential VN5 of the gate N5 of the seventh transistor T7 is the low level signal VGL, the seventh transistor T7 is turned off, the potential VN1 of the first control terminal N1 is the low level signal VGL, and the eighth transistor T8 is turned off. The second clock signal CK2 is a high level signal VGH, the eleventh transistor T11 is turned on, the input signal EIN is transmitted to the second control terminal N2, the potential VN2 of the second control terminal N2 is a low level signal VGL, the potential VN6 of the first pole N6 of the twelfth transistor T12 is also a low level signal VGL, and the ninth transistor T9 is turned off. The potential VN1 of the first control terminal N1 is the low-level signal VGL, so the fifth transistor T5 is turned off. The second clock signal CK2 is a high level signal VGH, the first transistor T1 is turned on, the input signal EIN is transmitted to the internal node N3, the potential VN3 of the internal node N3 is a low level signal VGL, and the third transistor T3 and the fourth transistor T4 are turned off, and the potential VN4 of the second pole N4 of the first capacitor C1 is a low level signal VGL. Therefore, in the first phase T1', the potential of each node is vn1=vn2=vn3=vn4=vn5=vn6=vgl, both the eighth transistor T8 and the ninth transistor T9 are turned off, the output terminal OUT maintains the voltage at the previous time, and the high-level signal VGH is continuously output.

In the second phase T2', the input signal EIN is still the low level signal VGL, and the sixth transistor T6 is still turned off. The second clock signal CK2 transitions to the low level signal VGL, the eleventh transistor T11 is turned off, and the potential VN2 of the second control terminal N2 and the potential VN6 of the first pole N6 of the twelfth transistor T12 maintain the low level signal VGL. The first transistor T1 is turned off, and the potential VN3 of the internal node N3 maintains the low-level signal VGL. The first clock signal CK1 jumps to the high level signal VGH, and the high level signal VGH is coupled to the control electrode N5 of the seventh transistor T7 through the third capacitor C3, until the potential of the control electrode N5 of the seventh transistor T7 becomes VGH-Vth, the seventh transistor T7 is turned on, and VGH-Vth is outputted, that is, the potential VN1 of the first control terminal N1 is VGH-Vth. The eighth transistor T8 is turned on to output the low level signal VGL, i.e., the potential VOUT of the output terminal OUT jumps to the low level signal VGL. And, the second clock signal CK2 jumps to the low level signal VGL, and the first transistor T1 is turned off; when the potential VN1 of the first control terminal N1 is VGH-Vth, the fifth transistor T5 is turned on, the potential VN4 of the second pole N4 of the first capacitor C1 is still the low level signal VGL, the potential VN3 of the internal node N3 is unchanged, and VGL is still obtained. Therefore, in the second phase t2', the potentials of the respective important nodes are vn2=vn3=vn4=vn6=vgl, vn1=vn5=vgh-Vth, and vout=vgl. Where Vth is the threshold voltage of the transistor.

In the third stage T3', the input signal EIN is still the low level signal VGL, and the sixth transistor T6 is still turned off. The second clock signal CK2 transitions to the high-level signal VGH, and the potential VN6 of the first electrode N6 and the potential VN2 of the second control terminal N2 of the twelfth transistor T12 are the low-level signal VGL. The first clock signal CK1 transitions to the low level signal VGL, the potential of the gate N5 of the seventh transistor T7 becomes the low level signal VGL, and the seventh transistor T7 is turned off. Due to the fourth capacitor C4, the potential VN1 of the first control terminal N1 is maintained, such that the potential VN1 of the first control terminal N1 is still VGH-Vth, the eighth transistor T8 is turned on, and the low level signal VGL is output, i.e. the potential VOUT of the output terminal OUT maintains the low level signal VGL. The second clock signal CK2 is a high level signal VGH, the first transistor T1 is turned on, the input signal EIN is transmitted to the internal node N3, the potential VN3 of the internal node N3 is a low level signal VGL, and the third transistor T3 and the fourth transistor T4 are turned off. When the potential VN1 of the first control terminal N1 is VGH-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second pole N4 of the first capacitor C1 is still the low level signal VGL. Therefore, in the third stage t3', the potentials of the respective important nodes are vn2=vn3=vn4=vn5=vn6=vgl, vn1=vgh-Vth, and vout=vgl.

The fourth stage t4 'to the seventh stage t7' are cycles of the second stage t2 'and the third stage t3', and are not described herein.

In the eighth stage T8', the input signal EIN transitions to the high level signal VGH, the sixth transistor T6 is turned on, the sixth transistor T6 transmits the low level signal VGL to the gate N5 of the seventh transistor T7, the seventh transistor T7 is turned off, the fourth capacitor C4 maintains the potential VN1 of the first control terminal N1, vn1=vgh-Vth, the eighth transistor T8 is turned on, and the eighth transistor T8 outputs the low level signal VGL, vout=vgl. The second clock signal CK2 transitions to the low level signal VGL, the eleventh transistor T11 is turned off, and the potential VN6 of the first pole N6 and the potential VN2 of the second control terminal N2 of the twelfth transistor T12 remain at the low level signal VGL. The second clock signal CK2 transitions to the low level signal VGL, the first transistor T1 is turned off, the potential VN3 of the internal node N3 is the low level signal VGL, and the third transistor T3 and the fourth transistor T4 are turned off. When the potential VN1 of the first control terminal N1 is VGH-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second pole N4 of the first capacitor C1 is still the low level signal VGL. Therefore, in the eighth stage t8', the potentials of the respective important nodes are vn2=vn3=vn4=vn5=vn6=vgl, vn1=vgh-Vth, and vout=vgl.

In the ninth stage T9', the first clock signal CK1 transitions to the low level signal VGL, the input signal EIN is the high level signal VGH, the sixth transistor T6 is turned on, the sixth transistor T6 transmits the low level signal VGL to the gate N5 of the seventh transistor T7, and the seventh transistor T7 is turned off. The second clock signal CK2 transitions to the high level signal VGH, the eleventh transistor T11 is turned on, and the eleventh transistor T11 transmits the input signal EIN to the first pole N6 of the twelfth transistor T12. The potential VN6 of the first pole N6 of the twelfth transistor T12 is the high level signal VGH-Vth, the tenth transistor T10 is turned on, the tenth transistor T10 transmits the low level signal VGL to the first control terminal N1, the potential VN1 of the first control terminal N1 is the low level signal VGL, the eighth transistor T8 is turned off, and the fifth transistor T5 is turned off. The potential VN6 of the first pole N6 of the twelfth transistor T12 is a high level signal VGH, the twelfth transistor T12 transmits the high level signal VGH-Vth to the second control terminal N2, the potential VN2 of the second control terminal N2 is VGH-Vth, and the ninth transistor T9 is turned on. After the ninth transistor T9 is turned on, a lower level is output, the potential of the output terminal OUT is pulled down, the charge stored in the second capacitor C2 is unchanged due to the coupling effect of the second capacitor C2, and the second capacitor C2 pulls down the second control terminal N2 in a coupling manner, so that the potential of the second control terminal N2 is at an ultra-high level (more effective level). The second clock signal CK2 transitions to the high-level signal VGH, the first transistor T1 is turned on, and the first transistor T1 and the second transistor T2 transmit the high-level signal VGH of the input signal EIN to the internal node N3, and the potential VN3 of the internal node N3 becomes VGH-Vth. The potential of the control electrode of the third transistor T3 is VGH-Vth, the third transistor T3 is turned on, the potential of the second electrode of the third transistor T3 is VGL, the second electrode N4 of the first capacitor C1 maintains the low level signal VGL, and the voltage difference across the first capacitor C1 is VGH-Vth-VGL. The potential of the control electrode of the fourth transistor T4 is VGH-Vth, the second electrode N2 of the fourth transistor T4 is at an ultra-high level (more effective level), the fourth transistor T4 does not satisfy the on condition, the fourth transistor T4 is turned off, and the potential of the internal node N3 is not transmitted to the second control terminal N2. The potential of the second control terminal N2 is in an ultra-high level (more effective level), so that the ninth transistor T9 is fully turned on, and the ninth transistor T9 can immediately output the high-level signal VGH, i.e., the gate driving circuit can immediately output the high-level signal VGH, so as to avoid the output gate driving signal from generating steps. Therefore, in the ninth stage t9', the potential of each important node is vn1=vn4=vn5=vgl, VN2 is the high level, vn3=vn6=vgh-Vth, and vout=vgh.

In the tenth stage T10', the first clock signal CK1 transitions to the high level signal VGH, the third transistor T3 transmits the high level signal VGH to the second pole N4 of the first capacitor C1, the voltage VN4 of the second pole N4 of the first capacitor C1 is VGH-Vth, the voltage difference across the first capacitor C1 is VGH-Vth-VGL, and the voltage VN3 of the internal node N3 becomes VGH-Vth-vgl+vgh, that is, v3=2vgh-Vth-VGL, and becomes the super high level. The potential VN3 of the internal node N3 is at a super high level, and if the potential of the second control terminal N2 increases due to the leakage of the twelfth transistor T12, the fourth transistor T4 is turned on, so that the super high level of the internal node N3 is transferred to the second control terminal N2, thereby maintaining the super high level of the second control terminal N2, ensuring that the ninth transistor T9 can be completely turned on, and ensuring that the gate driving circuit outputs the high level signal VGH. The input signal EIN is a high level signal VGH, the sixth transistor T6 is turned on, the sixth transistor T6 transmits a low level signal VGL to the gate N5 of the seventh transistor T7, and the seventh transistor T7 is turned off. The second clock signal CK2 transitions to the low level signal VGL, and the eleventh transistor T11 is turned off. Since the second control terminal N2 maintains the high level signal VGH and the eleventh transistor T11 is turned off, the first pole N6 of the twelfth transistor T12 maintains the level signal VGH-Vth. The tenth transistor T10 is turned on, the tenth transistor T10 transmits the low level signal VGL to the first control terminal N1, the potential VN1 of the first control terminal N1 is the low level signal VGL, the eighth transistor T8 is turned off, and the fifth transistor T5 is turned off. Therefore, in the tenth stage t10', the potentials of the important nodes are v1=v5=vgl, v4=v6=vgh-Vth, and v3=2×vgh-Vth-VGL, and VN2 is at the high level, and VN2 approaches VN3.

The subsequent stages are the cycle of the ninth stage t9 'and the tenth stage t10', and will not be described here again.

The embodiment also provides a display panel. Fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 9, the display panel includes a plurality of gate driving circuits 10 according to any of the above embodiments, the plurality of gate driving circuits 10 are connected in cascade, and an input signal EIN of the n-th stage gate driving circuit 10 is provided by an output signal of an output terminal OUT of the n-1-th stage gate driving circuit 10, where n is a positive integer greater than or equal to 2. The input signal EIN of the first stage gate driving circuit 10 may be provided by an external device. The display panel may be, for example, a display panel on a mobile phone, a tablet, an MP3, an MP4, a smart watch, an intelligent helmet, or other wearable devices, and the display panel of this embodiment includes the gate driving circuit provided in any of the foregoing embodiments, so that the display panel of this embodiment has the same beneficial effects as the gate driving circuit provided in any of the foregoing embodiments, and will not be described herein again.

As illustrated in fig. 9, the display panel further includes a first clock signal line CLK1 for supplying the first clock signal CK1 to the mth stage gate driving circuit 10 and a second clock signal line CLK2 for supplying the second clock signal CK2 to the mth stage gate driving circuit 10; the first clock signal line CLK1 is used to supply the second clock signal CK2 to the m+1th stage gate driving circuit 10, and the second clock signal line CLK2 is used to supply the first clock signal CK1 to the m+1th stage gate driving circuit 10. Wherein m is a positive integer greater than or equal to 1, and m is an odd number.

As shown in fig. 9, the display panel further includes a plurality of pixel circuits 20 arranged in an array, and the output terminal OUT of each stage of gate driving circuit is correspondingly connected to one row of pixel circuits 20 to control the transistors in the pixel circuits 20, thereby controlling the light emitting time sequence or the light emitting duration of the light emitting device corresponding to the pixel circuits 20.

Fig. 10 is a schematic diagram of a pixel circuit according to an embodiment of the present invention, and as shown in fig. 10, the pixel circuit 20 includes a data writing transistor M1, a threshold compensation transistor M2, a driving transistor M3, a first initialization transistor M4, a second initialization transistor M5, a first light emitting control transistor M6, a second light emitting control transistor M7, and a storage capacitor Cst. The pixel circuit 20 is connected to the light emitting device 30. The light emitting device 30 includes a light emitting diode OLED. As shown in fig. 10, the control electrode of the Data writing transistor M1 is connected to the first scan line S1, the first electrode of the Data writing transistor M1 is connected to the Data line Data, and the second electrode of the Data writing transistor M1 is electrically connected to the first electrode of the driving transistor M3. The first pole of the threshold compensation transistor M2 is electrically connected to the second pole of the driving transistor M3, the second pole of the threshold compensation transistor M2 is electrically connected to the control pole of the driving transistor M3, and the control pole of the threshold compensation transistor M2 is connected to the first scanning line S1. The control electrode of the first initialization transistor M4 is connected to the second scan line S2, the first electrode of the first initialization transistor M4 is connected to the initialization line Vref, and the second electrode of the first initialization transistor M4 is electrically connected to the control electrode of the driving transistor M3. The control electrode of the second initialization transistor M5 is connected to the second scan line S2, the first electrode of the second initialization transistor M5 is connected to the initialization line Vref, and the second electrode of the second initialization transistor M5 is electrically connected to the anode of the light emitting diode OLED. The control electrode of the first light emitting control transistor M6 is connected to the light emitting control line EM, the first electrode of the first light emitting control transistor M6 is connected to the first power supply VDD, and the second electrode of the first light emitting control transistor M6 is electrically connected to the first electrode of the driving transistor M3. The control electrode of the second light emitting control transistor M7 is connected to the light emitting control line EM, the first electrode of the second light emitting control transistor M7 is electrically connected to the second electrode of the driving transistor M3, and the second electrode of the second light emitting control transistor M7 is electrically connected to the anode of the light emitting diode OLED. The cathode of the light emitting diode OLED is connected to the second power source VSS. The storage capacitor Cst is connected between the first power supply VDD and the control electrode of the driving transistor M3. The driving process of the pixel circuit 20 includes the following stages:

In the initialization stage, the second scan line S2 supplies an active level (second level) to the first initialization transistor M4 and the second initialization transistor M5, and the first initialization transistor M4 and the second initialization transistor M5 are turned on. The first scan line S1 supplies an inactive level (first level) to the data writing transistor M1 and the threshold compensating transistor M2, and the data writing transistor M1 and the threshold compensating transistor M2 are turned off. The emission control line EM supplies an inactive level (first level) to the first and second emission control transistors M6 and M7, and the first and second emission control transistors M6 and M7 are turned off. The first initializing transistor M4 transmits an initializing signal on the initializing line Vref to the control electrode of the driving transistor M3, and initializes the control electrode of the driving transistor M3. The second initialization transistor M5 transmits an initialization signal on the initialization line Vref to the anode of the light emitting diode OLED, and initializes the anode of the light emitting diode OLED.

In the data writing and threshold compensation stage, the first scan line S1 supplies an active level (second level) to the data writing transistor M1 and the threshold compensation transistor M2, and the data writing transistor M1 and the threshold compensation transistor M2 are turned on. The second scan line S2 supplies an inactive level (first level) to the first and second initialization transistors M4 and M5, and the first and second initialization transistors M4 and M5 are turned off. The emission control line EM supplies an inactive level (first level) to the first and second emission control transistors M6 and M7, and the first and second emission control transistors M6 and M7 are turned off. The Data writing transistor M1 writes the Data voltage on the Data line Data to the control electrode of the driving transistor M3 through the driving transistor M3 and the threshold compensating transistor M2, and the threshold compensating transistor M2 performs threshold compensation on the driving transistor M3.

In the light emitting stage, the first scan line S1 supplies an inactive level (first level) to the data writing transistor M1 and the threshold compensating transistor M2, and the data writing transistor M1 and the threshold compensating transistor M2 are turned off. The second scan line S2 supplies an inactive level (first level) to the first and second initialization transistors M4 and M5, and the first and second initialization transistors M4 and M5 are turned off. The emission control line EM supplies an active level (second level) to the first and second emission control transistors M6 and M7, and the first and second emission control transistors M6 and M7 are turned on. The first power supply VDD, the first light emitting control transistor M6, the driving transistor M3, the second light emitting control transistor M7, the light emitting diode OLED, and the second power supply VSS form a current loop, and the light emitting diode OLED emits light in response to the driving current generated by the driving transistor M3.

In the above-described pixel circuit driving process, the active level (second level) and the inactive level (first level) supplied from the first scan line S1, the second scan line S2, and the emission control line EM may be supplied from the gate driving circuit provided in any of the above-described embodiments. Since the timings of the first scan line S1, the second scan line S2, and the emission control line EM are different, the first scan line S1, the second scan line S2, and the emission control line EM corresponding to the same pixel circuit may be connected to different gate driving circuits. The gate driving circuit provided by any embodiment can ensure that an effective level (second level) is output, and the effective level (second level) is the same as the second voltage signal.

Note that fig. 10 shows only a case where all transistors in the pixel circuit are P-type transistors, but the present invention is not limited thereto. All transistors in the pixel circuit may be N-type transistors. The transistors in the pixel circuit may be partly P-type transistors and partly N-type transistors. It is known that the active level of the P-type transistor is the low level signal VGL, and the gate driving signal of the P-type transistor is provided by the gate driving circuit of which the active level of the output is the low level signal VGL. The active level of the N-type transistor is the high level signal VGH, and the gate driving signal of the N-type transistor is provided by the gate driving circuit of which the active level of the output is the high level signal VGH.

In the transistors according to the above embodiments, the first pole may be a source or a drain, and the second pole may be a drain or a source.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A gate driving circuit, comprising:

the first input module is connected with a second control end of the second output module, and is used for transmitting an input signal to the second control end based on a second clock signal; the second output module is used for outputting a second voltage signal when being conducted;

and the coupling control module is electrically connected with the second control end and is used for carrying out coupling control on the potential of the second control end based on the jump from the first level to the second level of the first clock signal according to the second clock signal and the input signal so as to enable the output end of the grid driving circuit to output a second voltage signal.

2. The gate driving circuit according to claim 1, wherein,

the second level pulse of the second clock signal overlaps the second level pulse of the input signal; the coupling control module is configured to transmit a second level of the input signal to an internal node of the coupling control module when the second clock signal is at a second level, and couple a potential of the internal node when the first clock signal transitions from the first level to the second level, and transmit the coupled potential to the second control terminal;

3. The gate drive circuit of claim 1, wherein the coupling control module comprises: the device comprises a first input unit, a first control unit, a first coupling unit and a switch unit;

4. A gate drive circuit as recited in claim 3, further comprising:

5. The gate driving circuit of claim 4, wherein the gate driving circuit comprises a gate driver circuit,

the first input unit includes a first transistor and a second transistor;

6. The gate drive circuit of claim 1, further comprising:

7. The gate drive circuit of claim 6, wherein the coupling module comprises a second capacitor;

8. The gate drive circuit of claim 4, further comprising:

9. The gate drive circuit of claim 8, wherein the first control module comprises:

10. A display panel, comprising: the gate drive circuit of any one of claims 1-9.