CN117520260A

CN117520260A - FPGA-based template securities trading quotation analysis system

Info

Publication number: CN117520260A
Application number: CN202311550952.6A
Authority: CN
Inventors: 王嘉晨
Original assignee: East China Normal University
Current assignee: East China Normal University
Priority date: 2023-11-20
Filing date: 2023-11-20
Publication date: 2024-02-06

Abstract

The invention discloses an analysis system of templated securities trade quotation based on FPGA, which is characterized in that the system comprises: the system comprises an FPGA acceleration card, a server and a DDR memory chip, wherein the FPGA acceleration card is connected with the DDR memory chip; the FPGA acceleration card comprises network communication, FAST decoding and PCIE DPRK communication; the network communication support is realized through a UDP/IP protocol analysis circuit; performing hardware decoding by the FAST decoding through a template; and the PCIE DPRK operates the receiving and sending of the network card. Compared with the prior art, the invention flexibly adapts to different market data analysis requirements, meets the requirements of high-frequency transaction and large-scale data processing, better solves the problem of insufficient flexibility of redesigning and firing the FPGA acceleration card due to market information transformation when based on the FPGA decoding system, and has good application scenes and prospects.

Description

FPGA-based template securities trading quotation analysis system

Technical Field

The invention relates to the technical field of FPGA development, in particular to an analysis system for templated securities trading quotations based on an FPGA.

Background

Since the transaction of the certificate was established in 1613, the development of technology is certainly one of the biggest factors affecting the quotation system. The high-speed development of information technology improves the speed of information transmission and improves the quality and depth of stock exchange quotation data. The securities exchange promotes the Level-2 quotation in 2006, uses the latest international FAST technical standard for the first time, optimizes the data transmission efficiency, provides ten-grade deeper price information, and simultaneously provides the gradual success quotation. In 2021, the Level-2 quotation was continuously optimized, and a per-stroke delegated quotation was introduced. Thus, the full-open of the entrusting market information and the success market information makes the information available to the high-frequency trade participators more complete. The high-frequency trading participants can restore the market information from a large amount of data by entrusting market information and trading information.

The market data distribution system is the fundamental part of the complete high frequency transaction system, responsible for receiving encoded market data from the transaction center, decoding, and then transmitting the data to the host for further analysis. As more complex algorithms are introduced into algorithm transactions, such as artificial intelligence and data mining models, the time for data exchange is further reduced, placing more stringent demands on the efficiency and latency of the market data distribution system. Market data distribution systems need to provide ultra low latency data distribution through optimized market data parsing and communication while providing a degree of flexibility to support dynamic changes in template switching and financial protocol updating.

The FAST protocol is developed on the FIX (Financial Information exchange protocol) protocol, and is specially optimized for stream data compression, so that low-delay transmission of financial information is realized. FAST is a template-based compression mechanism for streaming data that shares some common field attributes or operations.

The stock exchange quotation analysis in the prior art is based on the problem that the flexibility of redesigning and firing the FPGA acceleration card is insufficient due to the fact that quotation information is transformed in the FPGA decoding system.

Disclosure of Invention

The invention aims to provide a template stock exchange quotation analysis system based on an FPGA, which aims at the defects of the prior art, adopts the template quotation analysis system constructed by an FPGA acceleration card, a server and a DDR memory chip, applies FPGA hardware processing to quotation decoding, carries out hardware decoding processing on frequently-transformed quotation templates, simultaneously carries out pipeline processing and parallel optimization to reduce delay, enhances the overall flexibility of the system of the template, and can flexibly adapt to different quotation data analysis requirements through template design without complex hardware design and development. Meanwhile, hardware acceleration based on the FPGA can provide high-speed data processing and resolving capability, and the requirements of high-frequency transaction and large-scale data processing are met. The invention optimizes the network communication and encoding process in delay, well solves the problem of insufficient flexibility of redesigning and firing the FPGA acceleration card caused by market information transformation in the traditional FPGA-based decoding system, breaks through the performance bottleneck of software, greatly enhances the system efficiency and the overall flexibility, has simple structure, convenient operation and good application scene and prospect.

The specific technical scheme for realizing the aim of the invention is as follows: an FPGA-based template securities trading quotation analysis system is characterized by comprising: the FPGA acceleration card, the server and the DDR memory chip, the FPGA acceleration card comprises: the system comprises a network communication unit, a FAST decoding unit and a PCIE DPRK (Data Plane Development Kit) communication unit; the network communication support is realized through a UDP/IP protocol analysis circuit; the FAST decoding module is responsible for carrying out hardware decoding through a template; the PCIE DPRK is responsible for directly operating the receiving and sending of the network card;

the network communication unit includes: a physical layer and a MAC layer, the physical layer comprising: protocol decoding and receiving and transmitting processing; the MAC layer includes: receiving transmitted decoding processing, UDP hardware data processing, UDP bus interface and control processing. The data flow analog circuit signal realizes operations such as clock recovery/transmission pre-emphasis, encoding and decoding, channel binding, data caching and the like of a receiving end of an electric signal through a high-speed serial interface and by matching with PHY IP.

The network communication unit supports preamble filtering and addition of teraethernet data, and filling and verification of CRC check codes.

The FAST decoding unit includes: a STEP parser and a FAST parser; the STEP parser adopts verilog custom design to provide quotation information and service session information, and the quotation information and the service session information are segmented through characters and transferred into a cache.

The FAST parser reads data from the cache, the fields are segmented through the segmentation principle of the template file, and decoding operation is completed under parallel control of the microprogram.

The DPDK module is used for solving frequent data interaction between the FPGA accelerator card and the host CPU.

Compared with the prior art, the invention flexibly adapts to different market data analysis requirements, and does not need to carry out complicated hardware design and development. Meanwhile, the hardware acceleration based on the FPGA can provide high-speed data processing and analysis capability, meets the requirements of high-frequency transaction and large-scale data processing, better solves the problem of insufficient flexibility of the FPGA acceleration card caused by market information transformation and firing when the FPGA decoding system is based, performs optimization processing on network communication and encoding processes in delay, breaks through the performance bottleneck of software, greatly enhances the system efficiency and the overall flexibility, has a simple structure, is convenient to operate, and has good application scenes and prospects.

Drawings

FIG. 1 is a schematic diagram of the structure of the present invention;

FIG. 2 is a schematic diagram of the structure of a FAST decoding unit;

FIG. 3 is a schematic diagram of a DPDK module structure;

FIG. 4 is a diagram of an embodiment of the present invention.

Description of the embodiments

The invention designs a hardware system for analyzing templated market data based on FPGA, a STEP analyzer divides each field in the data stream, judges the position and attribute of the field in the template, and a FAST decoder analyzes the template by XML analysis to reconstruct data, so that the FPGA card decodes the hardware in parallel. The FPGA provides an integrated programmable hardware development platform integrating network processing, encoding and decoding, intelligent algorithm acceleration and the like. The FPGA acceleration card comprises low-delay Ethernet communication and PCIE DPRK communication, supports hardware analysis of UDP/IP protocol, reduces square interaction with CPU, and has certain acceleration in a network layer.

Referring to fig. 1, the invention is constructed by an FPGA accelerator card, a server and a DDR memory chip, wherein the DDR memory chip is connected with the FPGA accelerator card; the FPGA acceleration card comprises: the FPGA acceleration card acquires a market data stream from the DDR memory chip and sends the market data stream to the server through decoding; the network communication unit analyzes the circuit through UDP/IP protocol; the FAST decoding unit performs hardware decoding through a template, divides and classifies the original market data stream, decodes and reconstructs the original market data stream for storage; and the PCIE DPRK communication unit operates the receiving and transmitting of the network card and transmits the data after the stock exchange quotation decoding to the server.

The present invention will now be described in detail with reference to the exemplary trading of securities, and the embodiments described are only some, but not all, of the embodiments of the present invention. Embodiments of the present invention are intended to be within the scope of the present invention as defined by the appended claims.

Examples

The data stream analog circuit signal is used for analyzing the digital signal data through the high-speed serial interface, transmitting the data through the XGMII interface and the MAC module, encoding the transmitted data frame and decoding the received data frame. And a tera Ethernet data filtering and cyclic redundancy check code verification function is supported. The MAC controller firstly transmits 7-bit synchronous codes and 1-bit delimiters, fills in 4-bit cyclic redundancy verification codes after transmission is finished, supplements 0 when the data length is smaller than 46 bits, and the transmitting end retransmits the data. After removing the lead code and the delimiter, the MAC of the receiving end performs cyclic redundancy check code verification, and then performs decoding processing to obtain real market information.

The STEP parser encapsulates additional information added to the data stream encoded by the FAST, acquires 64-bit data segments transmitted through the network port from the bus in each period, divides the data segments by 8 bits, automatically judges the field name or the field attribute to which the current data segment belongs by detecting ASCII codes of "=" and < SOH >, and transmits the field name or the field attribute to the designated cache space.

Referring to fig. 2, the fast decoding unit reads the content of the template, analyzes the template by xml analysis, reconstructs data according to the field sequence and meaning defined by the template, uses 1 byte as stop bit detection, and analyzes pipeline processing under the control of micro instructions.

Referring to fig. 3, dpdk is a function library and a driver set for fast packet processing, bypasses a Linux kernel mode protocol stack, and cooperates with a high-speed QDMA module on an FPGA to replace an interrupt trigger-based data interaction mechanism of an original Linux operating system by adopting a polling mode PMD (Poll Mode Drivers) driver, and directly operates a receiving and transmitting queue of a network card by using an interrupt-free mode, so that the analysis of market data and service processing delay of a system scheme can be greatly reduced.

Referring to fig. 4, in order to test the time delay effect of the present invention, the market data intercepted in the market source VDE of a certain stock exchange is read, and the market data is simultaneously sent to the tera ethernet card of the receiving end high-performance workstation and the special acceleration card of the FPGA through the Intel high-performance tera ethernet card via the optical module.

Selecting 100 FAST data test time delays randomly of different templates in a data stream, testing in Level-1 market data of a certain securities exchange, wherein the overall time delay of the template market analysis system based on the FPGA is 840ns on average; the invention tests in the Level-2 market snapshot market data of the stock exchange, and the whole time delay of the template market analysis system based on the FPGA is 708ns on average; the method is tested in the stock exchange transaction data, and the overall time delay of the template quotation analysis system based on the FPGA is 223ns on average; the method is tested in the entrusted data of the stock exchange, and the overall time delay of the template quotation analysis system based on the FPGA is 178ns on average; the method is tested in the quotation snapshot of the stock exchange index, and the overall time delay of the template analysis system based on the FPGA is 241ns on average.

According to the invention, through the templated design, a user can flexibly adapt to different market data analysis requirements, and complex hardware design and development are not required. Meanwhile, hardware acceleration based on the FPGA can provide high-speed data processing and resolving capability, and the requirements of high-frequency transaction and large-scale data processing are met.

It will be apparent to those skilled in the art that the above-described embodiments are not limited to the details of the above-described exemplary embodiments, but that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. The system is characterized in that an analytic system constructed by an FPGA acceleration card, a server and a DDR (double data rate) memory chip is adopted to meet the requirements of high-frequency transaction and large-scale data processing, and the DDR memory chip is connected with the FPGA acceleration card; the FPGA acceleration card comprises: the FPGA acceleration card acquires a stock exchange quotation data stream from the DDR memory chip and sends the stock exchange quotation data stream to the server through decoding; the network communication unit analyzes the circuit through UDP/IP protocol; the FAST decoding unit performs hardware decoding through a template, divides and classifies the original market data stream, decodes and reconstructs the original market data stream for storage; and the PCIE DPRK communication unit operates the receiving and transmitting of the network card and transmits the data after the stock exchange quotation decoding to the server.

2. The FPGA-based templated stock exchange ticker parsing system of claim 1, wherein the network communication unit includes: a physical layer and a MAC layer, the physical layer comprising: protocol decoding and receiving and transmitting processing; the MAC layer includes: receiving transmitted decoding processing, UDP hardware data processing, UDP bus interface and control processing.

3. The FPGA-based templated stock exchange resolution system of claim 1, wherein the FAST decoding unit includes: decoding segmentation of STEP analyzer and decoding reconstruction of FAST analyzer; the STEP parser reads data from the cache, and performs character segmentation and transfer to the cache, and decoding operation is completed under parallel control of the microprogram.

4. The system for analyzing the template securities trading market based on the FPGA according to claim 1, wherein a DPDK module in the PCIE DPRK communication unit is used for solving frequent data interaction between an FPGA accelerator card and a host CPU, the DPRK module is matched with a high-speed QDMA module on the FPGA, is driven in a polling mode, uses a non-interrupt mode to operate a receiving and transmitting queue of the network card, and transmits data after securities trading market decoding to a server.

5. The FPGA-based templated stock exchange quotation analysis system according to claim 3, wherein the decoding division of the STEP resolver uses each 8 bits as the division processing, and automatically determines the field name or field attribute to which the current data segment belongs by detecting the ASCII codes of "=" and < SOH >, and sends the field name or field attribute to the designated buffer space; the decoding reconstruction of the FAST parser includes a sequence mapping table control word; the sequence mapping control word is used as a special domain architecture of FAST decoding; and when all the control words of the switching template are executed, the decoder jumps back to the initial control word to start processing the next FAST data message.

6. The FPGA-based templated securities trade quotation resolution system according to claim 5, wherein said sequence map control word comprises: an attribute group and a position group; the attribute group represents the relevant attribute of the field in the AST template; the position group sequentially reconstructs a nested structure of the template; the nested structure embeds the sequence mapping table control field of the deeper sequence field into the sequence field of the shallower sequence mapping table control field, and the nested sequence field is recursively processed.