CN117518646A

CN117518646A - Array substrate, display panel and display device

Info

Publication number: CN117518646A
Application number: CN202310728602.8A
Authority: CN
Inventors: 张伟伟
Original assignee: Suzhou China Star Optoelectronics Technology Co Ltd
Current assignee: Suzhou China Star Optoelectronics Technology Co Ltd
Priority date: 2023-06-19
Filing date: 2023-06-19
Publication date: 2024-02-06

Abstract

The application provides an array substrate, a display panel and a display device, wherein the array substrate comprises a substrate; a first metal layer on the substrate, the first metal layer including a plurality of first scan lines; a second metal layer on the first metal layer, the second metal layer including a plurality of common electrode lines; a third metal layer on the second metal layer, the third metal layer including a plurality of pixel electrodes; wherein, the orthographic projection of the common electrode line on the substrate covers the orthographic projection of the first scanning line on the substrate. The array substrate, the display panel and the display device provided by the application can effectively reduce the capacitance between the pixel electrode and the first scanning line (Vgate), and improve the problem of uneven display (mura) of the display panel.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

Along with the gradual development of display panels, the existing products are continuously developed towards the directions of high resolution, narrow frames, light thinning and the like, and the ultra-narrow frame technology is developed accordingly, wherein the scanning line data line driving same-side design is used in the existing ultra-narrow frame technology, a driving signal of a horizontal scanning line (Hgate) is output from a driving circuit at a Source (Source) side through a vertical scanning line (Vgate), and the vertical scanning line (Vgate) is connected with the horizontal scanning line (Hgate) through a connecting hole (GI via) so as to transmit the signal to the horizontal scanning line (Hgate). However, at the connection hole (GI via), there is a strong coupling (coupling) capacitance between the vertical scanning line (Vgate) and the pixel electrode, which affects the pixels near the connection hole, resulting in a problem of display unevenness (mura) of the display panel.

Disclosure of Invention

The application provides an array substrate, a display panel and a display device, which can effectively reduce the capacitance between a pixel electrode and a first scanning line (Vgate) and improve the problem of uneven display (mura) of the display panel.

The application provides an array substrate, including:

a substrate;

a first metal layer on the substrate, the first metal layer including a plurality of first scan lines;

a second metal layer on the first metal layer, the second metal layer including a plurality of common electrode lines;

a third metal layer on the second metal layer, the third metal layer including a plurality of pixel electrodes;

wherein, the orthographic projection of the common electrode line on the substrate covers the orthographic projection of the first scanning line on the substrate.

In an embodiment, at least part of the common electrode lines are provided with hollowed-out parts, and orthographic projection of the hollowed-out parts on the substrate covers orthographic projection of at least part of the first scanning lines on the substrate.

In an embodiment, the array substrate includes a plurality of sub-pixels, the plurality of sub-pixels are arranged on the substrate in an array manner, and the first scan line and the common electrode line are located between adjacent sub-pixels.

In an embodiment, the array substrate further includes a plurality of second scan lines, the second scan lines being located on the substrate; the first scanning lines are arranged along a first direction, the second scanning lines are arranged along a second direction perpendicular to the first direction, and the first scanning lines are connected with the second scanning lines; the first scanning lines and the second scanning lines are arranged in a staggered mode to define a plurality of pixel areas, and the sub-pixels are located in the pixel areas.

In an embodiment, a first insulating layer is disposed between the first scan line and the second scan line, a connection hole is disposed on the first insulating layer, and the first scan line and the second scan line are electrically connected through the connection hole.

In an embodiment, along an extending direction of the first scan line, the first scan line includes multiple segments, and each segment of the first scan line corresponds to one of the sub-pixels; on at least one section of the first scanning line close to the connecting hole, the orthographic projection of the corresponding common electrode line on the substrate covers the orthographic projection of the first scanning line on the substrate; and on the other sections of the first scanning lines, the corresponding common electrode lines are provided with hollowed-out parts, and the orthographic projection of the hollowed-out parts on the substrate covers the orthographic projection of at least part of the first scanning lines on the substrate.

In an embodiment, the array substrate further includes a thin film transistor disposed on the substrate and connected to the pixel electrode.

In an embodiment, the array substrate further includes a driving circuit, the driving circuit is disposed on the substrate, and the first scan line is connected to the driving circuit.

The application also provides a display panel comprising the array substrate according to any one of the embodiments.

The application also provides a display device comprising the display panel according to any of the embodiments.

The beneficial effects of this application lie in: according to the display device, the common electrode is arranged between the first scanning line and the pixel electrode, and covers the first scanning line, so that the capacitance between the pixel electrode and the first scanning line is greatly reduced, the coupling capacitance between the pixel electrode and the first scanning line is effectively reduced, and the display non-uniformity (mura) problem of the display panel is improved.

Drawings

In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a driving structure of an array substrate in the prior art.

Fig. 2 is a schematic diagram of a pixel structure of an array substrate according to an embodiment of the present application.

FIG. 3 is a schematic A-A cross-sectional view of an array substrate according to the embodiment of FIG. 2.

Fig. 4 is a schematic B-B cross-sectional view of an array substrate according to the embodiment of fig. 2.

Fig. 5 is a schematic view of another pixel structure of an array substrate according to an embodiment of the present application.

Fig. 6 is a schematic diagram of a driving architecture of an array substrate according to an embodiment of the present application.

Fig. 7 is a schematic C-C cross-sectional view of an array substrate according to the embodiment of fig. 5.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be understood that the azimuth or positional relationship indicated by the terms "upper", "lower", etc. are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless specifically defined otherwise.

The present application may repeat reference numerals and/or letters in the various examples, and such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Fig. 1 is a schematic diagram of a driving structure of an array substrate in the prior art. The array substrate includes a plurality of first scan lines 200 (Vgate), a plurality of second scan lines 600 (Hgate), and a driving circuit 800, wherein the plurality of first scan lines 200 are arranged along a first direction (X direction), the plurality of second scan lines 600 are arranged along a second direction (Y direction), the first scan lines 200 and the second scan lines 600 are staggered to define a plurality of pixel regions, each pixel region includes one sub-pixel 500, and the sub-pixel 500 includes a pixel electrode 400. The first scan line 200 is connected to the driving circuit 800, the first scan line 200 is electrically connected to the second scan line 600 through the connection hole 210, and a driving signal sent by the driving circuit 800 is transmitted to the second scan line 600 correspondingly connected via the first scan line 200, so as to drive the second scan line 600. At the connection between the first scan line 200 and the second scan line 600, a stronger coupling (coupling) capacitance exists between the first scan line 200 and the pixel electrode 400, which affects the sub-pixels, resulting in a problem of uneven display (mura) of the display panel.

In order to solve the above-mentioned problems, the present application proposes an array substrate capable of effectively reducing the coupling (coupling) capacitance between the pixel electrode 400 and the first scan line 200 (Vgate) and improving the display non-uniformity (mura) problem of the display panel.

The array substrate provided in the present application will be described in detail with reference to specific embodiments and drawings.

As shown in fig. 2-3, the present application provides an array substrate, including:

a substrate 100;

a first metal layer on the substrate 100, the first metal layer including a plurality of first scan lines 200;

a second metal layer on the first metal layer, the second metal layer including a plurality of common electrode lines 300;

a third metal layer on the second metal layer, the third metal layer including a plurality of pixel electrodes 400;

wherein the front projection of the common electrode line 300 on the substrate 100 covers the front projection of the first scan line 200 on the substrate 100.

Further, as shown in fig. 3, the array substrate further includes a first insulating layer 110, a second insulating layer 120, a filter layer 130, and a planarization layer 140. The first insulating layer 110 is located between the first metal layer and the second metal layer, the second insulating layer 120 is located at a side of the second metal layer away from the first insulating layer 110, the filter layer 130 is located at a side of the second insulating layer 120 away from the second metal layer, and the planarization layer 140 is located between the pixel electrode 400 and the filter layer 130.

The common electrode 300 is disposed between the first scan line 200 and the pixel electrode 400, and the common electrode 300 covers the first scan line 200, so that the capacitance between the pixel electrode 400 and the first scan line 200 is greatly reduced, and the coupling (coupling) capacitance between the pixel electrode 400 and the first scan line 200 is effectively reduced, thereby improving the display non-uniformity (mura) problem of the display panel.

Since the load (loading) of the first scan line 200 is large after all the first scan line 200 is completely covered with the common electrode 300, the charging rate is low. Therefore, the hollowed-out portion 310 may be formed on a part of the common electrode 300, so as to reduce the load (loading) of the first scan line 200, and effectively improve the charging rate.

In an embodiment, as shown in fig. 4 to 5, at least a part of the common electrode line 300 is provided with a hollowed-out portion 310, and an orthographic projection of the hollowed-out portion 310 on the substrate 100 covers an orthographic projection of at least a part of the first scan line 200 on the substrate 100.

Specifically, the portion of the common electrode line 300 may be opened to form a hollowed portion 310, where the hollowed portions 310 may be disposed at intervals or may be disposed continuously. For example, in the extending direction of the common electrode 300, a plurality of hollow portions 310 may be disposed on the common electrode 300 at intervals, and the intervals between adjacent hollow portions 310 may be equal or unequal; the hollow portion 310 may be continuously disposed at a middle section or both ends of the common electrode 300. The position of the hollowed-out portion 310 on the common electrode 300 is not particularly limited herein.

At the first scan line corresponding to the hollowed portion 310, the hollowed portion 310 exposes a portion of the first scan line 200 (i.e., the orthographic projection of the hollowed portion 310 on the substrate 100 covers a portion of the orthographic projection of the first scan line 200 on the substrate 100), and the hollowed portion 310 may also expose all of the first scan line 200 (i.e., the orthographic projection of the hollowed portion 310 on the substrate 100 completely covers the orthographic projection of the first scan line 200 on the substrate 100). Since the overlapping area between the common electrode 300 and the first scan line 200 is reduced, the capacitance between the common electrode 300 and the first scan line 200 is reduced, and thus the influence of crosstalk is reduced, and thus the load (loading) of the first scan line 200 is greatly reduced, so that the charging rate can be effectively increased.

In an embodiment, as shown in fig. 4 and 6, the array substrate includes a plurality of sub-pixels 500, the plurality of sub-pixels 500 are arranged on the substrate 100 in an array, and the first scan line 200 and the common electrode line 300 are located between two adjacent columns of sub-pixels 500.

Further, as shown in fig. 6, the array substrate further includes a plurality of second scan lines 600, where the second scan lines 600 are located on the substrate 100; a plurality of the first scan lines 200 are arranged along a first direction (X direction), a plurality of the second scan lines 600 are arranged along a second direction (Y direction) perpendicular to the first direction, and the first scan lines 200 are connected to the second scan lines 600; the first scan lines 200 and the second scan lines 600 are staggered to define a plurality of pixel regions, and the sub-pixels 500 are located in the pixel regions.

Further, the first scan line 200 and the second scan line 600 are electrically connected through a connection hole 210, specifically, as shown in fig. 7, a first insulating layer 110 is disposed between the first scan line 200 and the second scan line 600, a connection hole 210 is disposed on the first insulating layer 110, and the first scan line 200 and the second scan line 600 are electrically connected through the connection hole 210.

In this embodiment, one of the first scan lines 200 and the corresponding one of the second scan lines 600 are electrically connected through the connection hole 210, for example, as shown in fig. 6, the array substrate includes a plurality of columns (Y direction) of first scan lines 200 (Vgate) and a plurality of rows (X direction) of second scan lines 600 (Hgate), the nth column Vgate and the nth row Hgate are electrically connected through the connection hole 210 at the point P, the n+1th column Vgate and the n+1th row Hgate are electrically connected through the connection hole 210 at the point P1, the n+2th column Vgate and the n+2th row Hgate are electrically connected through the connection hole 210 at the point P2, and so on.

Since the region where the mura problem occurs is mainly near the position where the first scan line 200 and the second scan line 600 are electrically connected (i.e., at the connection hole 210), since the first scan line 200 and the second scan line 600 need to be electrically connected through the connection hole 210, there is a strong coupling capacitance between the first scan line 200 and the pixel electrode 400 at the connection hole 210, resulting in that the capacitive coupling states of the pixel electrode 400 near the connection hole 210 and the pixel electrode 400 far from the connection hole 210 are not uniform when the first scan line 200 is turned off, and thus the pixel electrode 400 near the connection hole 210 becomes darker than the pixel electrode 400 far from the connection hole 210, so that the mura of the sub-pixel 500 near the connection hole 210 is more obvious.

In order to solve the above problem, the present application sets the first scan line 200 corresponding to the sub-pixel 500 near the connection hole 210 to be the common electrode 300 to completely cover the first scan line 200, and sets the first scan line 200 corresponding to the sub-pixel 500 far from the connection hole 210 to be the common electrode 300 to cover a part of the first scan line 200 (i.e. the common electrode 300 is hollowed out). The load of the first scan line 200 is further reduced while reducing the coupling capacitance between the first scan line 200 and the pixel electrode 400, so as to effectively increase the charging rate.

In one embodiment, as shown in fig. 6, along the extending direction (Y direction) of the first scan line 200, the first scan line 200 includes multiple segments, and each segment of the first scan line 200 corresponds to one of the sub-pixels 500; on at least one section of the first scan line 200 near the connection hole 210, the orthographic projection of the corresponding common electrode line 300 on the substrate 100 covers the orthographic projection of the first scan line 200 on the substrate 100; on the remaining segments of the first scan line 200, the corresponding common electrode line 300 is provided with a hollowed-out portion 310, and the orthographic projection of the hollowed-out portion 310 on the substrate 100 covers the orthographic projection of at least part of the first scan line 200 on the substrate 100.

Specifically, as shown in fig. 6, taking the nth column Vgate as an example, along the signal transmission direction (Y direction) of the Vgate, the N-th, n+1-th, n+2-th, n+3-th, n+4-th, n+5-th segment of the common electrode 300 corresponding to the 6 th sub-pixel 500 near the connection point P is set to completely cover the Vgate, and the hollow portions 310 are disposed on the common electrode 300 corresponding to the other segments except the N-th, n+1-th, n+2-th, n+3-th, n+4-th, n+5-th segments on the nth column Vgate, so as to reduce the coupling capacitance between the pixel electrode 400 of the 6 th sub-pixel 500 near the connection point P and the nth column Vgate, and reduce the overall load of the nth column Vgate.

In this embodiment, the mura affected area is mainly 6 sub-pixels 500 near the connection hole 210, so that each segment of the first scan line 200 corresponding to the 6 sub-pixels 500 near the connection hole 210 is disposed to be completely covered by the common electrode 300. It should be noted that, in other embodiments, the main area affected by mura may be 1 sub-pixel 500, 2 sub-pixels 500, 3 sub-pixels 500, etc. near the connection hole 210 according to different product designs, which is not limited herein. When the main area affected by mura is 1 sub-pixel 500 near the connection hole 210, 1 segment of the first scan line 200 corresponding to 1 sub-pixel 500 near the connection hole 210 may be set to be completely covered by the common electrode 300, and the common electrodes 300 on the remaining segments of the first scan line 200 are all provided with the hollowed-out portions 310; when the main area affected by mura is 2 sub-pixels 500 near the connection hole 210, 2 segments of the first scan line 200 corresponding to 2 sub-pixels 500 near the connection hole 210 may be set to be completely covered by the common electrode 300, and the common electrode 300 on the remaining segments of the first scan line 200 is provided with the hollowed-out portion 310, and so on.

In an embodiment, as shown in fig. 2 and fig. 4, the array substrate further includes a data line 700 (Date), where the data line 700 is parallel to the first scan line 200 and is led out from the middle of the sub-pixel 500, and the data signal input end of the data line 700 and the scan signal input end of the first scan line 200 may be located on the same side of the array substrate, so that the screen duty ratio may be improved, and a narrow frame design may be implemented.

In an embodiment, the array substrate further includes a thin film transistor 510, and the thin film transistor 510 is disposed on the substrate 100 and connected to the pixel electrode 400.

Specifically, the thin film transistor 510 includes a gate electrode on the substrate 100, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, a passivation layer on the active layer, a source electrode and a drain electrode on the passivation layer, and a planarization layer 140 on the source electrode and the drain electrode, and the source electrode or the drain electrode of the thin film transistor 510 is electrically connected to the pixel electrode 400.

In an embodiment, as shown in fig. 6, the array substrate further includes a driving circuit 800, the driving circuit 800 is disposed on the substrate 100, and the first scan line 200 is connected to the driving circuit 800.

Specifically, the driving circuit 800 may be a gate driving circuit GOA, the array substrate includes a display area 101 and a non-display area 102, the GOA is integrated on the substrate 100 and is located in the non-display area 102, the first scan line 200 is electrically connected to the GOA, and the GOA transmits a gate driving signal to the second scan line 600 through the first scan line 200 to drive the second scan line 600. Furthermore, the GOA is disposed at one side of the array substrate and is located at one side of the source electrode of the array substrate, so that the frame width of other sides of the array substrate can be reduced, and a narrow frame design can be realized.

In some embodiments, the driving circuit 800 may be a COF, and the first scan line 200 may be directly connected to the COF, and the COF may transmit a driving signal to the second scan line 600 through the first scan line 200 to drive the second scan line 600, so that GOA may be omitted in this embodiment to make the frame narrower.

The application also provides a display panel comprising the array substrate according to any one of the embodiments. For example, the display panel may be a liquid crystal display panel, which illustratively includes the array substrate, a liquid crystal layer, an ITO electrode layer, a black matrix layer, cover glass, and the like, which are sequentially stacked.

It should be noted that the display panel may be any other type of display panel, and is not particularly limited herein.

The application also provides a display device comprising the display panel according to any of the embodiments. The display device may be any product or component with a display function, such as a television, a notebook computer, a tablet computer, a wearable display device (e.g., a smart bracelet, a smart watch, etc.), a mobile phone, a virtual reality device, an augmented reality device, a vehicle-mounted display, an advertisement lamp box, etc., which is not particularly limited herein.

In summary, the present application provides an array substrate, a display panel and a display device, where a common electrode is disposed between a first scan line and a pixel electrode, and the common electrode covers the first scan line, so that a capacitance between the pixel electrode and the first scan line is greatly reduced, a coupling (coupling) capacitance between the pixel electrode and the first scan line is effectively reduced, and a display non-uniformity (mura) problem of the display panel is improved.

In summary, although the present application has been described with reference to the preferred embodiments, the preferred embodiments are not intended to limit the application, and those skilled in the art can make various modifications and adaptations without departing from the spirit and scope of the application, and the scope of the application is therefore defined by the claims.

Claims

1. An array substrate, characterized by comprising:

a substrate;

2. The array substrate according to claim 1, wherein at least part of the common electrode lines are provided with hollowed-out portions, and orthographic projections of the hollowed-out portions on the substrate cover orthographic projections of at least part of the first scanning lines on the substrate.

3. The array substrate according to claim 2, wherein the array substrate includes a plurality of sub-pixels arranged in an array on the substrate, the first scan line and the common electrode line being located between adjacent sub-pixels.

4. The array substrate of claim 3, further comprising a plurality of second scan lines, the second scan lines being located on the substrate;

the first scanning lines are arranged along a first direction, the second scanning lines are arranged along a second direction perpendicular to the first direction, and the first scanning lines are connected with the second scanning lines;

the first scanning lines and the second scanning lines are arranged in a staggered mode to define a plurality of pixel areas, and the sub-pixels are located in the pixel areas.

5. The array substrate of claim 4, wherein a first insulating layer is disposed between the first scan line and the second scan line, a connection hole is disposed on the first insulating layer, and the first scan line and the second scan line are electrically connected through the connection hole.

6. The array substrate of claim 5, wherein the first scan line includes a plurality of segments along an extension direction of the first scan line, each segment of the first scan line corresponding to one of the sub-pixels;

on at least one section of the first scanning line close to the connecting hole, the orthographic projection of the corresponding common electrode line on the substrate covers the orthographic projection of the first scanning line on the substrate;

and on the other sections of the first scanning lines, the corresponding common electrode lines are provided with hollowed-out parts, and the orthographic projection of the hollowed-out parts on the substrate covers the orthographic projection of at least part of the first scanning lines on the substrate.

7. The array substrate according to any one of claims 1 to 6, further comprising a thin film transistor disposed on the substrate and connected to the pixel electrode.

8. The array substrate of any one of claims 1-6, further comprising a driving circuit disposed on the substrate, the first scan line being connected to the driving circuit.

9. A display panel comprising an array substrate according to any one of claims 1-8.

10. A display device comprising the display panel according to claim 9.